JP4608880B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP4608880B2
JP4608880B2 JP2003412115A JP2003412115A JP4608880B2 JP 4608880 B2 JP4608880 B2 JP 4608880B2 JP 2003412115 A JP2003412115 A JP 2003412115A JP 2003412115 A JP2003412115 A JP 2003412115A JP 4608880 B2 JP4608880 B2 JP 4608880B2
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insulating film
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interlayer insulating
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semiconductor device
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将伸 岩谷
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Fuji Electric Co Ltd
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Fuji Electric Systems Co Ltd
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Description

この発明は、化学機械研磨およびエッチングにより作製される集積回路装置などの半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device such as an integrated circuit device manufactured by chemical mechanical polishing and etching, and a manufacturing method thereof.

化学機械研磨（Ｃｈｅｍｉｃａｌ Ｍｅｃｈａｎｉｃａｌ Ｐｏｌｉｓｈｉｎｇ：以下ＣＭＰと称す）は、近年の半導体集積回路の平坦化に幅広く用いられており、その応用の一つに層間絶縁膜であるメタル下層絶縁膜（ＩｎｔｅｒＬａｙｅｒ Ｄｉｅｌｅｃｔｒｉｃ：以下ＩＬＤと称す）の平坦化がある。以下に例として、ｐ型シリコン基板を用いて、ポリシリコンを二層積層して電極としたキャパシタとＣＭＯＳ（Ｃｏｍｐｌｉｍｅｎｔａｒｙ ＭＯＳＦＥＴ）とを含む半導体装置の製造方法について説明する。
図１２は、従来の半導体装置の要部構成図であり、同図（ａ）は平面図、同図（ｂ）は同図（ａ）のＸ１−Ｘ１線で切断した断面図である。
図１２（ａ）は、例えばＣＭＯＳとキャパシタ６９が形成される回路形成領域８４とそれを取り囲むチップ２００の外周部に配置されたパッド用電極８３を示す。 Chemical mechanical polishing (hereinafter referred to as CMP) has been widely used for planarization of recent semiconductor integrated circuits, and one of its applications is a metal underlayer dielectric film (InterLayer Dielectric: hereinafter). (Referred to as ILD). As an example, a method for manufacturing a semiconductor device including a capacitor using two layers of polysilicon as an electrode and a CMOS (Complementary MOSFET) using a p-type silicon substrate will be described.
12A and 12B are main part configuration diagrams of a conventional semiconductor device, where FIG. 12A is a plan view and FIG. 12B is a cross-sectional view taken along line X1-X1 in FIG.
FIG. 12A shows a circuit forming region 84 in which, for example, a CMOS and a capacitor 69 are formed and a pad electrode 83 disposed on the outer periphery of the chip 200 surrounding the circuit forming region 84.

図１２（ｂ）において、ＣＭＯＳはＮＭＯＳとＰＭＯＳで構成され、ＮＭＯＳはｐ基板５１の表面層に形成されたｐウェル領域５３に形成され、ＰＭＯＳはｐ基板５１の表面層に形成されたｎウェル領域５２に形成され、キャパシタ６９とパッド用電極８３はｐウェル領域５３上のＬＯＣＯＳ酸化膜５５上に形成される。
ＮＭＯＳはｐウェル領域５３の表面層に形成されるｎソース領域５６、ｎドレイン領域５７とこれらの領域と接続するプラグ７７とゲート酸化膜６０とゲート電極６２で構成される。また、ＰＭＯＳはｎウェル領域５２の表面層に形成されるｐソース領域５８、ｐドレイン領域５９とこれらの領域と接続するプラグ７８とゲート酸化膜６１とゲート電極６３で構成される。これらのプラグ７７、７８は配線８０、８１と接続する。
キャパシタ６９はＬＯＣＯＳ酸化膜５５上に形成された第１電極６４、酸化膜６６、第２電極６７で構成され、キャパシタ用配線８２はプラグ７９で第２電極６７と接続しＩＬＤ７２上に形成される。また、パッド用電極８３はＩＬＤ７２上に形成される。 In FIG. 12B, the CMOS is composed of NMOS and PMOS, the NMOS is formed in the p-well region 53 formed in the surface layer of the p substrate 51, and the PMOS is the n-well formed in the surface layer of the p substrate 51. Capacitor 69 and pad electrode 83 formed in region 52 are formed on LOCOS oxide film 55 on p well region 53.
The NMOS includes an n source region 56 and an n drain region 57 formed on the surface layer of the p well region 53, a plug 77 connected to these regions, a gate oxide film 60, and a gate electrode 62. The PMOS includes a p source region 58 and a p drain region 59 formed in the surface layer of the n well region 52, a plug 78 connected to these regions, a gate oxide film 61, and a gate electrode 63. These plugs 77 and 78 are connected to the wirings 80 and 81.
The capacitor 69 includes a first electrode 64, an oxide film 66, and a second electrode 67 formed on the LOCOS oxide film 55, and the capacitor wiring 82 is connected to the second electrode 67 with a plug 79 and formed on the ILD 72. . The pad electrode 83 is formed on the ILD 72.

図１３から図１８は、図１２の半導体装置の製造方法を示す図であり、工程順に示した要部製造工程断面図である。
図１３に示すように、ｐ基板５１の表面層に、図示しないフォトレジストをマスクにｎウェル領域５２を形成し、このときｎウエル領域５２上に形成された図示しない酸化膜をマスクにｐウェル領域５３を形成し、酸化膜を除去する。この酸化膜除去により、ｐウェル領域５３の表面の高さよりｎウェル領域５２の表面の高さが低くなり、段差５４が生じる。
つぎに、図１４に示すように、素子分離のために、ｐウェル領域５３上、ｐウェル領域５３とｎウェル領域５２の境界付近に選択酸化膜（以下、ＬＯＣＯＳ酸化膜５５と称す。ＬＯＣＯＳとはＬｏｃａｌ Ｏｘｉｄａｔｉｏｎ ｏｆ Ｓｉｌｉｃｏｎである）を形成する。その後、図示しない犠牲酸化膜を形成し、ｎウェル領域５２とｐウェル領域５３にそれぞれにイオン注入などによりゲート電極形成箇所下に図示しないチャネル領域を形成する。 13 to 18 are views showing a method for manufacturing the semiconductor device of FIG. 12, and are cross-sectional views of main part manufacturing steps shown in the order of steps.
As shown in FIG. 13, an n-well region 52 is formed on the surface layer of a p-substrate 51 using a photoresist (not shown) as a mask. At this time, an p-well is formed using an oxide film (not shown) formed on the n-well region 52 as a mask. Region 53 is formed and the oxide film is removed. By removing the oxide film, the height of the surface of the n-well region 52 becomes lower than the height of the surface of the p-well region 53, and a step 54 is generated.
Next, as shown in FIG. 14, for element isolation, a selective oxide film (hereinafter referred to as LOCOS oxide film 55) is formed on the p well region 53 and in the vicinity of the boundary between the p well region 53 and the n well region 52. Is a Local Oxidation of Silicon). Thereafter, a sacrificial oxide film (not shown) is formed, and a channel region (not shown) is formed in each of the n well region 52 and the p well region 53 by ion implantation or the like under the gate electrode formation portion.

つぎに、図１５に示すように、犠牲酸化膜を除去した後、ゲート酸化膜６０、６１を例えば１０ｎｍ形成する。その後、ポリシリコンでゲート電極６２、６３と、ＬＯＣＯＳ酸化膜５５上にキャパシタ６９の第１電極６４とを形成する。そして、通常のＭＯＳＦＥＴ形成工程にしたがって、ｐウェル領域５３にはｎチャネルＭＯＳＦＥＴ（ＮＭＯＳ）のｎソース領域５６、ｎドレイン領域５７を形成し、ｎウェル領域５２にはｐチャネルＭＯＳＦＥＴ（ＰＭＯＳ）のｐソース領域５８、ｐドレイン領域５９を形成する。
つぎに、図１６に示すように、キャパシタ６９の誘電膜となる酸化膜６６をＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）により形成し、その上にポリシリコンでキャパシタ６９の第２電極６７を形成する。
つぎに、図１７に示すように、表面にＩＬＤ７２となる酸化膜をＣＶＤで堆積し、例えば、数１０秒程度のＣＭＰ処理をして、０．６μｍ程度表面を削って平坦化を行う。 Next, as shown in FIG. 15, after removing the sacrificial oxide film, gate oxide films 60 and 61 are formed to a thickness of 10 nm, for example. Thereafter, the gate electrodes 62 and 63 and the first electrode 64 of the capacitor 69 are formed on the LOCOS oxide film 55 with polysilicon. Then, in accordance with a normal MOSFET formation process, an n source region 56 and an n drain region 57 of an n channel MOSFET (NMOS) are formed in the p well region 53, and a p channel MOSFET (PMOS) p is formed in the n well region 52. A source region 58 and a p drain region 59 are formed.
Next, as shown in FIG. 16, an oxide film 66 serving as a dielectric film of the capacitor 69 is formed by CVD (Chemical Vapor Deposition), and a second electrode 67 of the capacitor 69 is formed thereon using polysilicon.
Next, as shown in FIG. 17, an oxide film that becomes ILD 72 is deposited on the surface by CVD, and, for example, CMP is performed for about several tens of seconds, and the surface is flattened by cutting the surface by about 0.6 μm.

つぎに、図１８に示すように、第２電極６７上と、ｎソース領域５６上、ｎドレイン領域５７上、ｐソース領域５８上およびｐドレイン領域５９上のＩＬＤ７２に開口部７４、７５、７６をそれぞれ形成し、これらの開口部７４、７５、７６をアルミニウムなどで充填してプラグ７７、７８、７９を形成し、このプラグ７７、７８、７９と接続する配線８０、８１とキャパシタ配線８２およびパッド用電極８３をアルミニウムで同時に形成する。この図１８は、図１２の従来の半導体装置の要部断面図となる。
上記プロセスにより集積回路を作製した場合、ＩＬＤ７２をＣＭＰ処理により平坦化すると、コンタクトを取る箇所のＩＬＤ７２の厚さが場所によって変わってくる。ソース領域５６、５８およびドレイン領域５７、５９などシリコン層とコンタクトする箇所のＩＬＤ７２の厚さは厚く、キャパシタ６９を構成する第２電極６７とコンタクトする箇所のＩＬＤ７２の厚さは薄い。そのため、ＩＬＤ７２の薄い第２電極６７とのコンタクトは、オーバーエッチして、図１９のＡ部で示すように、第２電極６７が削れて取られると、第２電極６７とプラグ７９とのコンタクトは第２電極６７の側面から取るようになり接触抵抗が増大してコンタクト不良となる。また、図示しないが誘電膜である酸化膜６６を突き抜けて第１電極６４に達してキャパシタ６９が短絡することもある。 Next, as shown in FIG. 18, openings 74, 75, 76 are formed in the ILD 72 on the second electrode 67, the n source region 56, the n drain region 57, the p source region 58, and the p drain region 59. These openings 74, 75, 76 are filled with aluminum or the like to form plugs 77, 78, 79, wirings 80, 81 connected to the plugs 77, 78, 79, capacitor wirings 82 and The pad electrode 83 is simultaneously formed of aluminum. FIG. 18 is a fragmentary cross-sectional view of the conventional semiconductor device of FIG.
In the case where an integrated circuit is manufactured by the above process, when the ILD 72 is planarized by CMP, the thickness of the ILD 72 where the contact is made varies depending on the location. The thickness of the ILD 72 where the source regions 56 and 58 and the drain regions 57 and 59 are in contact with the silicon layer is large, and the thickness of the ILD 72 where the second region 67 is in contact with the second electrode 67 constituting the capacitor 69 is thin. Therefore, when the contact with the thin second electrode 67 of the ILD 72 is over-etched and the second electrode 67 is cut away and removed as shown in part A of FIG. 19, the contact between the second electrode 67 and the plug 79 Is taken from the side surface of the second electrode 67 and the contact resistance increases, resulting in a contact failure. Although not shown, the capacitor 69 may be short-circuited through the oxide film 66 that is a dielectric film to reach the first electrode 64.

また、ＩＬＤ７２をＣＭＰ処理する際に平坦化は良好に行われるが、ＣＭＰ処理は枚葉式で行われるために、研磨量がウェハ間でばらつく場合がある。また、ウェハがゴミなどの介在で傾いたり、ウェハに反りがある場合には、研磨量がウェハ面内でばらつく。このように研磨量にばらつきがあると、研磨量が少ないとＩＬＤ７２の厚さが厚くなり、コンタクトする箇所にＩＬＤ７２が残りコンタクト不良になる。一方、研磨量が多いとオーバーエッチが多すぎて前記のように第２電極６７が削れ取られてしまい、コンタクト不良となる。
これらを解決するために、ＣＭＰ処理でストッパ膜を用いると、ストッパ膜のパターンを形成するためにフォトマスクを追加しなければならず製造コストが増大する。
このストッパ膜を回路形成領域に設けた場合について説明する。 Further, although flattening is performed satisfactorily when the ILD 72 is subjected to the CMP process, the polishing amount may vary between wafers because the CMP process is performed in a single wafer mode. Further, when the wafer is tilted due to the presence of dust or the like, or the wafer is warped, the polishing amount varies within the wafer surface. When the polishing amount varies as described above, the ILD 72 becomes thick when the polishing amount is small, and the ILD 72 remains at the contact point, resulting in poor contact. On the other hand, when the polishing amount is large, the over-etching is excessive and the second electrode 67 is scraped off as described above, resulting in contact failure.
In order to solve these problems, if a stopper film is used in the CMP process, a photomask must be added to form the pattern of the stopper film, and the manufacturing cost increases.
The case where this stopper film is provided in the circuit formation region will be described.

図２０は、ストッパ膜を回路形成領域に設けた半導体装置の要部構成図であり、同図（ａ）は平面図、同図（ｂ）は同図（ａ）のＸ−Ｘ線で切断した断面図である。
回路形成領域８４には、キャパシタ６９とストッパ膜６５が４箇所に形成されている。同図（ｂ）は図１２（ｂ）に相当する図であるが、Ｘ−Ｘ線上にはキャパシタ６９が形成されていない場合の図である。
ストッパ膜６５の表面の高さをキャパシタ６９の第２電極６７より高くするために、ストッパ膜６５を形成する箇所のＩＬＤ７２内には高さ調整用の第１ポリシリコン膜６４、第２ポリシリコン膜６７がキャパシタ６９の第１電極６４、第２電極６７と同時に形成されている。このストッパ膜６５を設けることで、ＩＬＤ７２の研磨量を所定量にすることができる（例えば、特許文献１）。 20A and 20B are main part configuration diagrams of a semiconductor device in which a stopper film is provided in a circuit formation region. FIG. 20A is a plan view, and FIG. 20B is cut along line XX in FIG. FIG.
In the circuit formation region 84, capacitors 69 and stopper films 65 are formed at four locations. FIG. 12B is a diagram corresponding to FIG. 12B, but is a diagram in the case where the capacitor 69 is not formed on the XX line.
In order to make the height of the surface of the stopper film 65 higher than that of the second electrode 67 of the capacitor 69, the first polysilicon film 64 and the second polysilicon for height adjustment are formed in the ILD 72 where the stopper film 65 is formed. The film 67 is formed simultaneously with the first electrode 64 and the second electrode 67 of the capacitor 69. By providing the stopper film 65, the polishing amount of the ILD 72 can be set to a predetermined amount (for example, Patent Document 1).

しかし、ストッパ膜６５として昨日するためには面積や数が必要となるためて、ストッパ膜６５を形成する部分を回路形成領域８４内に設けると回路形成領域８４の面積が減少する。
この回路形成領域の面積を減少させないために、層間絶縁膜の膜厚を管理するモニターパターンをスクライブラインに設けて、層間絶縁膜の膜厚を測定して管理する方法が報告されている（例えば、特許文献２）。
特開２００２−３５３２２０号公報 図１５ 特開２００２−８３７９２号公報 図１ However, since the area and the number of the stopper film 65 are required to be used yesterday, the area of the circuit formation region 84 is reduced when the portion for forming the stopper film 65 is provided in the circuit formation region 84.
In order not to reduce the area of this circuit formation region, a method of measuring and managing the thickness of the interlayer insulating film by providing a monitor pattern for controlling the thickness of the interlayer insulating film on the scribe line has been reported (for example, Patent Document 2).
Japanese Patent Laid-Open No. 2002-353220 FIG. Japanese Patent Laid-Open No. 2002-83792 FIG.

しかし、回路形成領域８４の面積が減少しないように、ストッパ膜６５をスクライブラインに設ける場合、スクライブラインには、ＰＣＭ（Ｐｒｏｃｅｓｓ Ｃｏｎｔｒｏｌ Ｍｏｎｉｔｏｒ）等のモニタを多数形成することが多く、ストッパ膜６５を形成する面積が十分に得られないことがある。このストッパ膜６５の面積が小さいと、ＣＭＰ処理でストッパ膜６５が削られて前記のＩＬＤ７２の研磨量がばらつき、コンタクト不良を起こす。
この発明の目的は、前記の課題を解決してコンタクト不良を防止できる半導体装置およびその製造方法を提供することにある。 However, when the stopper film 65 is provided on the scribe line so that the area of the circuit formation region 84 is not reduced, many monitors such as PCM (Process Control Monitor) are often formed on the scribe line. A sufficient area may not be obtained. If the area of the stopper film 65 is small, the stopper film 65 is scraped by the CMP process, the amount of polishing of the ILD 72 varies, and contact failure occurs.
An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can solve the above-described problems and prevent contact failure.

前記の目的を達成するために、半導体基板上の層間絶縁膜上に形成されたパッド用電極を有する半導体装置の製造方法において、
前記半導体基板上に第１層間絶縁膜を形成する工程と、前記パッド用電極を形成する箇所の真下で前記第１層間絶縁膜上に研磨停止層を形成する工程と、前記第１層間絶縁膜上と前記研磨停止層上に第２層間絶縁膜を形成する工程と、該第２層間絶縁膜を前記研磨停止層が露出するまで研磨し平坦化する工程と、前記第１層間絶縁膜及び前記第２層間絶縁膜にコンタクト孔を形成する工程と、前記研磨停止層の真上にパッド用電極を形成する工程とを含み、前記研磨停止層を形成する工程では回路形成領域には前記研磨停止層を形成しない製造方法とする。 In order to achieve the above object, in a method of manufacturing a semiconductor device having a pad electrode formed on an interlayer insulating film on a semiconductor substrate,
Forming a first interlayer insulating film on the semiconductor substrate; forming a polishing stopper layer on the first interlayer insulating film directly below a portion where the pad electrode is formed; and the first interlayer insulating film. Forming a second interlayer insulating film on the top and the polishing stopper layer; polishing and planarizing the second interlayer insulating film until the polishing stopper layer is exposed; and the first interlayer insulating film and the Forming a contact hole in the second interlayer insulating film; and forming a pad electrode immediately above the polishing stopper layer; in the step of forming the polishing stopper layer, stop the polishing in the circuit formation region. The manufacturing method does not form a layer .

また、半導体基板上の層間絶縁膜上に形成されたパッド用電極と、該層間絶縁膜内に形成した上下二層の電極を有するキャパシタとを有する半導体装置の製造方法において、
前記半導体基板上に選択的に素子分離絶縁膜を形成する工程と、
第１導電材料を前記素子分離絶縁膜上に形成し、前記キャパシタを形成する箇所および前記パッド用電極を形成する箇所の真下の前記第１導電材料を残し他を除去する工程と、
前記半導体基板上全面に誘電膜を形成する工程と、
第２電極材料を前記第１導電材料の真上の前記誘電膜上に形成する工程と、
前記半導体基板上全面に第１層間絶縁膜を形成する工程と、
前記パッド用電極を形成する箇所の真下の前記第２導電材料の真上の前記第１層間絶縁膜上、及び前記キャパシタを形成する箇所の前記第２導電材料の真上の前記第１層間絶縁膜上に研磨停止層を形成する工程と、
前記半導体基板上全面に第２層間絶縁膜を形成する工程と、
前記第２層間絶縁膜を前記研磨停止層が露出するまで平坦化する工程と、
前記第２層間絶縁膜、前記第１層間絶縁膜及び前記誘電膜に前記半導体基板に達するコンタクト孔を形成するとともに、前記キャパシタ形成箇所の前記研磨停止層及び前記第１層間絶縁膜に前記第２導電材料に達するコンタクト孔を形成する工程と、
前記研磨停止層の真上に前記パッド電極を形成する工程とを含み、前記研磨停止層を形成する工程では前記キャパシタ形成箇所以外の回路形成領域には前記研磨停止層を形成しない製造方法とする。 Further, in a method of manufacturing a semiconductor device having a pad electrode formed on an interlayer insulating film on a semiconductor substrate and a capacitor having two upper and lower electrodes formed in the interlayer insulating film,
Forming an element isolation insulating film selectively on the semiconductor substrate;
Forming a first conductive material on the element isolation insulating film , leaving the first conductive material directly under a portion where the capacitor is formed and a portion where the pad electrode is formed;
Forming a dielectric film on the entire surface of the semiconductor substrate;
Forming a second electrode material on the dielectric film directly above the first conductive material;
Forming a first interlayer insulating film on the entire surface of the semiconductor substrate;
The first interlayer insulating film on the first interlayer insulating film directly above the second conductive material immediately below the portion where the pad electrode is to be formed, and on the first interlayer insulating film directly above the second conductive material where the capacitor is to be formed. Forming a polishing stopper layer on the film;
Forming a second interlayer insulating film on the entire surface of the semiconductor substrate;
Planarizing the second interlayer insulating film until the polishing stopper layer is exposed;
Contact holes reaching the semiconductor substrate are formed in the second interlayer insulating film, the first interlayer insulating film, and the dielectric film, and the second stopper is formed in the polishing stopper layer and the first interlayer insulating film at the capacitor formation location. Forming a contact hole reaching the conductive material;
Look including the step of forming the pad electrode directly above the polishing stop layer, wherein the circuit forming region other than the capacitor formation portion, in the process of forming a polish stop layer and a manufacturing method which does not form the polishing stop layer To do.

また、前記平坦化する工程の後でコンタクト孔を形成する工程の前に前記半導体基板全面に第３層間絶縁膜を形成する工程を含むとよい。
また、前記素子分離絶縁膜が前記半導体基板を選択酸化した選択酸化膜であるとよい。
また、前記コンタクト孔を形成する工程は、前記半導体基板に達するコンタクト孔を形成する工程と同時に、前記研磨停止層のエッチングレートが前記誘電膜、及び前記第１から第２または第１から第３層間絶縁膜のエッチングレートより小さい条件で行うとよい。 Further, a step of forming a third interlayer insulating film on the entire surface of the semiconductor substrate may be included before the step of forming the contact hole after the step of planarization.
The element isolation insulating film may be a selective oxide film obtained by selectively oxidizing the semiconductor substrate.
In the step of forming the contact hole, simultaneously with the step of forming the contact hole reaching the semiconductor substrate, the etching rate of the polishing stopper layer is the dielectric film and the first to second or first to third. The etching may be performed under conditions lower than the etching rate of the interlayer insulating film.

また、前記研磨停止層がシリコン窒化膜からなり、前記素子分離絶縁膜、前記誘電膜、及び前記第１から第２または第１から第３層間絶縁膜がシリコン酸化膜からなるとよい。
また、前記平坦化する工程をＣＭＰ処理で行うとよい。

The polishing stopper layer may be made of a silicon nitride film, and the element isolation insulating film, the dielectric film, and the first to second or first to third interlayer insulating films may be made of a silicon oxide film.
Further, the planarization step may be performed by a CMP process.

この発明によれば、ストッパ膜を設けることで、ＣＭＰ処理によるＩＬＤの膜厚のばらつきを抑えることができる。
また、このストッパ膜をパッド用電極形成箇所に設けることで、回路形成領域の面積の減少を防止できる。
また、キャパシタの第２電極に達する開口部と同時に半導体基板に達する開口部を形成する場合、キャパシタ上に形成されるストッパ膜のエッチングレートがＩＬＤのエッチングレートより小さい条件でエッチングを行うことで、キャパシタの第２電極が過度に削れることを防止することができて、コンタクト不良を防止できる。
また、このストッパ膜をパッド用電極形成箇所に設けることで、回路形成領域の面積の減少を防止できる。 According to the present invention, by providing the stopper film, variations in the ILD film thickness due to the CMP process can be suppressed.
Further, by providing this stopper film at the pad electrode formation site, it is possible to prevent the area of the circuit formation region from being reduced.
Further, when forming the opening reaching the semiconductor substrate at the same time as the opening reaching the second electrode of the capacitor, etching is performed under the condition that the etching rate of the stopper film formed on the capacitor is smaller than the etching rate of the ILD, It is possible to prevent the second electrode of the capacitor from being excessively shaved and to prevent contact failure.
Further, by providing this stopper film at the pad electrode formation site, it is possible to prevent the area of the circuit formation region from being reduced.

この発明の実施の最良の形態は、集積回路を形成する場合などで、標高の最も高いパッド用電極形成箇所にＣＭＰ処理で平坦化した層間絶縁膜上にストッパ膜（研磨停止層）を設けることで、回路形成領域の面積を減少させることがなくなる。また、キャパシタの第２電極に達する開口部と同時に半導体基板に達する開口部を形成する場合、層間絶縁膜よりストッパ膜の方がエッチングレートが小さい条件でエッチングを行うと、層間絶縁膜内で標高の高い箇所に形成したキャパシタの電極とのコンタクト不良を防止することができることである。つぎに、具体的な実施例について図を用いて説明する。   The best mode for carrying out the present invention is, for example, in the case of forming an integrated circuit. A stopper film (polishing stop layer) is provided on an interlayer insulating film flattened by CMP at a pad electrode forming portion having the highest altitude. Thus, the area of the circuit formation region is not reduced. Further, when the opening reaching the semiconductor substrate is formed simultaneously with the opening reaching the second electrode of the capacitor, if the etching is performed under the condition that the stopper film has a lower etching rate than the interlayer insulating film, the altitude is increased in the interlayer insulating film. It is possible to prevent contact failure with the electrode of the capacitor formed at a high point. Next, specific examples will be described with reference to the drawings.

図１は、この発明の第１実施例の半導体装置の要部構成図であり、同図（ａ）は平面図、同図（ｂ）は同図（ａ）のＸ１−Ｘ１線で切断した断面図である。
図１（ａ）は、例えばＣＭＯＳとキャパシタ１９が形成される回路形成領域３４とそれを取り囲むチップ１００の外周部に配置されたパッド用電極３３を示す。
図１（ｂ）において、ＣＭＯＳはＮＭＯＳとＰＭＯＳで構成され、ＮＭＯＳはｐ基板１の表面層に形成されたｐウェル領域３に形成され、ＰＭＯＳはｐ基板１の表面層に形成されたｎウェル領域２に形成され、キャパシタ１９とパッド用電極３３はｐウェル領域３上のＬＯＣＯＳ酸化膜５上に形成される。
ＮＭＯＳはｐウェル領域３の表面層に形成されるｎソース領域６、ｎドレイン領域７とこれらの領域と接続するプラグ２７とゲート酸化膜１０とゲート電極１２で構成される。また、ＰＭＯＳはｎウェル領域２の表面層に形成されるｐソース領域８、ｐドレイン領域９とこれらの領域と接続するプラグ２８とゲート酸化膜１１とゲート電極１３で構成される。これらのプラグ２７、２８は配線３０、３１と接続する。 1A and 1B are main part configuration diagrams of a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a plan view, and FIG. 1B is cut along a line X1-X1 in FIG. It is sectional drawing.
FIG. 1A shows a circuit forming region 34 in which, for example, a CMOS and a capacitor 19 are formed, and pad electrodes 33 arranged on the outer periphery of the chip 100 surrounding the circuit forming region 34.
In FIG. 1B, the CMOS is composed of NMOS and PMOS, the NMOS is formed in the p well region 3 formed in the surface layer of the p substrate 1, and the PMOS is the n well formed in the surface layer of the p substrate 1. Capacitor 19 and pad electrode 33 formed in region 2 are formed on LOCOS oxide film 5 on p well region 3.
The NMOS is composed of an n source region 6 and an n drain region 7 formed in the surface layer of the p well region 3, a plug 27 connected to these regions, a gate oxide film 10, and a gate electrode 12. The PMOS includes a p source region 8 and a p drain region 9 formed in the surface layer of the n well region 2, a plug 28 connected to these regions, a gate oxide film 11, and a gate electrode 13. These plugs 27 and 28 are connected to the wirings 30 and 31.

キャパシタ１９はＬＯＣＯＳ酸化膜５上に形成された第１電極１４、酸化膜１６、第２電極１７で構成され、キャパシタ用配線３２はプラグ２９で第２電極１７と接続しＩＬＤ２２から露出したストッパ膜２０上に形成される。
また、パッド用電極３３はＬＯＣＯＳ酸化膜５上のＩＬＤ２２内部に形成された第１ポリシリコン膜１５、第２ポリシリコン膜１８とＩＬＤ２２から露出したストッパ膜２１上に形成される。
パッド用電極３３下のストッパ膜２１の表面の高さがキャパシタ１９の第２電極１７の表面の高さやソース領域／ドレイン領域の表面の高さより高くなるようにする。尚、表面の高さとは、ここでは半導体基板表面で最も低い表面からの高さをいう。 The capacitor 19 is composed of the first electrode 14, the oxide film 16 and the second electrode 17 formed on the LOCOS oxide film 5, and the capacitor wiring 32 is connected to the second electrode 17 by the plug 29 and is exposed from the ILD 22. 20 is formed.
The pad electrode 33 is formed on the first polysilicon film 15 and the second polysilicon film 18 formed in the ILD 22 on the LOCOS oxide film 5 and the stopper film 21 exposed from the ILD 22.
The height of the surface of the stopper film 21 under the pad electrode 33 is set higher than the height of the surface of the second electrode 17 of the capacitor 19 and the height of the surface of the source region / drain region. Here, the surface height refers to the height from the lowest surface of the semiconductor substrate surface.

図２から図７は、この発明の第２実施例の半導体装置の製造方法を示す図であり、工程順に示した要部製造工程断面図である。この半導体装置の製造方法は、図１の半導体装置の製造方法を示すものである。また、これらの工程断面図は、図１（ｂ）に相当する断面図である。
図２に示すように、ｐ基板１の表面層に、図示しないフォトレジストをマスクにｎウェル領域２を形成し、このときｎウエル領域２上に形成された図示しない酸化膜をマスクにｐウェル領域３を形成し、酸化膜を除去する。この酸化膜除去により、ｐウェル領域３の表面の高さよりｎウェル領域１の表面の高さが低くなり、段差４が生じる。
つぎに、図３に示すように、素子分離のために、ｐウェル領域３上、ｐウェル領域３とｎウェル領域１の境界付近にＬＯＣＯＳ酸化膜５を形成する。その後、図示しない犠牲酸化膜を形成し、ｎウェル領域１とｐウェル領域３のそれぞれにイオン注入などによりゲート電極形成箇所下に図示しないチャネル領域を形成する。 2 to 7 are views showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention, and are cross-sectional views showing main part manufacturing steps shown in the order of steps. This method of manufacturing a semiconductor device shows the method of manufacturing the semiconductor device of FIG. Moreover, these process sectional views are sectional views corresponding to FIG.
As shown in FIG. 2, an n-well region 2 is formed on a surface layer of a p-substrate 1 using a photoresist (not shown) as a mask. At this time, an oxide film (not shown) formed on the n-well region 2 is used as a mask. Region 3 is formed and the oxide film is removed. By removing the oxide film, the height of the surface of the n-well region 1 becomes lower than the height of the surface of the p-well region 3, and a step 4 is generated.
Next, as shown in FIG. 3, a LOCOS oxide film 5 is formed on the p-well region 3 in the vicinity of the boundary between the p-well region 3 and the n-well region 1 for element isolation. Thereafter, a sacrificial oxide film (not shown) is formed, and a channel region (not shown) is formed in each of the n well region 1 and the p well region 3 by ion implantation or the like under the gate electrode formation portion.

つぎに、図４に示すように、犠牲酸化膜を除去した後、ゲート酸化膜１０、１１を例えば１０ｎｍ形成する。その後、ポリシリコンでゲート電極１２、１３と、ＬＯＣＯＳ酸化膜５上にキャパシタ１９の第１電極１４とパッド用電極３３形成箇所に高さ調整用の第１ポリシリコン膜１５とを同時に形成する。この第１ポリシリコン膜１５を形成するのは、後で形成するパッド用電極３３形成箇所のストッパ膜２１の表面の高さをキャパシタ１９形成箇所のストッパ膜２０の表面の高さと同一とするために必要である。そして、通常のＭＯＳＦＥＴ形成工程にしたがって、ｐウェル領域３にはｎチャネルＭＯＳＦＥＴ（ＮＭＯＳ）のｎソース領域６、ｎドレイン領域７を形成し、ｎウェル領域２にはｐチャネルＭＯＳＦＥＴ（ＰＭＯＳ）のｐソース領域８、ｐドレイン領域９を形成する。
つぎに、図５に示すように、キャパシタ１９の誘電膜となる酸化膜１６をＣＶＤにより形成し、その上にポリシリコンでキャパシタ１９の第２電極１７と、高さ調整用の第２ポリシリコン膜１８を同時に形成する。この第２ポリシリコン膜１８を形成するのは、後で形成するパッド用電極３３形成箇所に形成されるストッパ膜２１の表面の高さをキャパシタ１９形成箇所のストッパ膜２０の表面の高さと同一にして、キャパシタ１９の第２電極１７がＣＭＰ処理で削られることを防止する。 Next, as shown in FIG. 4, after removing the sacrificial oxide film, gate oxide films 10 and 11 are formed to a thickness of 10 nm, for example. Thereafter, the gate electrodes 12 and 13, and the first electrode 14 of the capacitor 19 and the first polysilicon film 15 for height adjustment are simultaneously formed on the LOCOS oxide film 5 at the position where the pad electrode 33 is formed. The first polysilicon film 15 is formed in order to make the height of the surface of the stopper film 21 where the pad electrode 33 is formed later the same as the height of the surface of the stopper film 20 where the capacitor 19 is formed. Is necessary. Then, in accordance with a normal MOSFET formation process, an n source region 6 and an n drain region 7 of an n channel MOSFET (NMOS) are formed in the p well region 3, and a p channel MOSFET (PMOS) p is formed in the n well region 2. A source region 8 and a p drain region 9 are formed.
Next, as shown in FIG. 5, an oxide film 16 serving as a dielectric film of the capacitor 19 is formed by CVD, on which a second electrode 17 of the capacitor 19 and a second polysilicon for height adjustment are formed with polysilicon. The film 18 is formed simultaneously. The second polysilicon film 18 is formed because the height of the surface of the stopper film 21 formed at the place where the pad electrode 33 is formed later is the same as the height of the surface of the stopper film 20 where the capacitor 19 is formed. Thus, the second electrode 17 of the capacitor 19 is prevented from being scraped by the CMP process.

また、これらのストッパ膜２０、２１の表面の高さは、回路形成領域３４内に形成されるゲート電極１２、１３やソース領域／ドレイン領域など他の箇所の表面の高さよりも高くすることで、ＣＭＰ処理で表面が削られるのを防止する。
つぎに、図６に示すように、第２電極１７上と第２ポリシリコン膜１８上にＩＬＤ２２となる酸化膜を形成し、この酸化膜上のキャパシタ１９形成箇所とパッド用電極３３形成箇所に窒化膜でストッパ膜２０、２１を形成する。その後、さらにその表面にＩＬＤ２２となる酸化膜をＣＶＤで堆積させた後、このＩＬＤ２２となる酸化膜をパッド用電極３３形成箇所のストッパ膜２１が露出するまでＣＭＰ処理をして平坦化する。このとき、第２電極１７上のストッパ膜２０も露出する。尚、ＣＰＭ処理した後はストッパ膜２０、２１は役目を終えるので削除しても構わない。 Further, the heights of the surfaces of these stopper films 20 and 21 are made higher than the heights of the surfaces of other portions such as the gate electrodes 12 and 13 and the source / drain regions formed in the circuit formation region 34. The surface is prevented from being scraped by the CMP process.
Next, as shown in FIG. 6, an oxide film to be ILD 22 is formed on the second electrode 17 and the second polysilicon film 18, and the capacitor 19 and the pad electrode 33 are formed on the oxide film. Stopper films 20 and 21 are formed of a nitride film. Thereafter, an oxide film to be ILD 22 is further deposited on the surface by CVD, and then the oxide film to be ILD 22 is planarized by CMP until the stopper film 21 at the position where the pad electrode 33 is formed is exposed. At this time, the stopper film 20 on the second electrode 17 is also exposed. Note that after the CPM treatment, the stopper films 20 and 21 finish their roles and may be deleted.

つぎに、図７に示すように、第２電極１７上のストッパ膜２０と、ｎソース領域６上、ｎドレイン領域７上、ｐソース領域８上およびｐドレイン領域９上のＩＬＤ２２に開口部２４、２５、２６をそれぞれ形成し、これらの開口部２４、２５、２６をアルミニウムなどで充填してプラグ２７、２８、２９を形成し、これらのプラグ２７、２８、２９と接続する配線３０、３１とキャパシタ配線３２と、ストッパ膜２１上にパッド用電極３３をアルミニウムで同時に形成する。前記したように、このパッド用電極３３下のストッパ膜２１の表面の高さが他の箇所より高くなるようにストッパ膜２１は形成される。
パッド用電極３３形成箇所にストッパ膜２１を形成することで、回路形成領域３４の面積を小さくすることがない。
また、開口部２４、２５、２６を同時にエッチングにより形成する際、第２電極２０上に形成されるストッパ膜２０のエッチングレートをＩＬＤ２２のエッチングレートより小さい条件で行うことで、第２電極１７のオーバーエッチングを減少できるので、コンタクト不良を防止できる。 Next, as shown in FIG. 7, the opening 24 is formed in the stopper film 20 on the second electrode 17 and the ILD 22 on the n source region 6, the n drain region 7, the p source region 8 and the p drain region 9. 25, 26 are formed, and the openings 24, 25, 26 are filled with aluminum or the like to form plugs 27, 28, 29, and wirings 30, 31 connected to these plugs 27, 28, 29 are formed. The pad electrode 33 is simultaneously formed of aluminum on the capacitor wiring 32 and the stopper film 21. As described above, the stopper film 21 is formed so that the height of the surface of the stopper film 21 under the pad electrode 33 is higher than that of other portions.
By forming the stopper film 21 at the position where the pad electrode 33 is formed, the area of the circuit formation region 34 is not reduced.
Further, when the openings 24, 25, and 26 are simultaneously formed by etching, the etching rate of the stopper film 20 formed on the second electrode 20 is performed under a condition that is lower than the etching rate of the ILD 22, thereby Since over-etching can be reduced, contact failure can be prevented.

図８は、この発明の第３実施例の半導体装置の製造方法を示す図であり、同図（ａ）から同図（ｂ）は工程順に示した要部製造工程断面図である。これら図は図６、図７に相当する図であり、図８（ｂ）はこの発明の半導体装置の要部断面図でもある。
第２実施例との違いは、図６の工程で、ＩＬＤ２２となる酸化膜を第２電極１７上および第２ポリシリコン膜１８上に形成しないで、窒化膜のストッパ膜２０、２１を形成した点である。こうすることで、ストッパ膜２０、２１の形成と、第２電極１７、第２ポリシリコン膜１８の形成を１枚のマスクで同時にできるため、工程の短縮とフォトマスク枚数の削減ができる。
尚、パッド用電極３３下のストッパ膜２１はｐウェル領域３上のＬＯＣＯＳ酸化膜５上に形成されており、その表面の高さはチップ１００内で一番高くなる。 FIG. 8 is a view showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention. FIGS. 8A to 8B are sectional views showing the main part manufacturing steps shown in the order of steps. These drawings correspond to FIGS. 6 and 7, and FIG. 8B is a cross-sectional view of the main part of the semiconductor device of the present invention.
The difference from the second embodiment is that the nitride stopper films 20 and 21 are formed without forming the oxide film to be the ILD 22 on the second electrode 17 and the second polysilicon film 18 in the step of FIG. Is a point. By doing so, the formation of the stopper films 20 and 21 and the formation of the second electrode 17 and the second polysilicon film 18 can be performed simultaneously with one mask, so that the process can be shortened and the number of photomasks can be reduced.
The stopper film 21 under the pad electrode 33 is formed on the LOCOS oxide film 5 on the p-well region 3, and the height of the surface thereof is the highest in the chip 100.

図９は、この発明の第４実施例の半導体装置の製造方法を示す図であり、同図（ａ）から同図（ｂ）は工程順に示した要部製造工程断面図である。これらの図は図６、図７に相当する図であり、図９（ｂ）はこの発明の半導体装置の要部断面図でもある。これらの要部製造工程断面図は、図１（ａ）のＸ２−Ｘ２で切断した要部断面図に相当する。
第３実施例との違いは、キャパシタ１９がｎウェル領域２上のＬＯＣＯＳ酸化膜５上にに形成されている点である。こうすることで、キャパシタ１９となる部分の第２電極１７上のＢ部にはｎウエル領域２とｐウェル領域３の段差分のＩＬＤ２２が形成される。
第２電極２０と隣接してＩＬＤ２２上に配線３５が形成された場合、このＩＬＤ２２が層間絶縁膜となって、配線３５と第２電極１７との間の絶縁を確保できる。
尚、パッド用電極３３下のストッパ膜２１はｐウェル領域３上のＬＯＣＯＳ酸化膜５上に形成されており、その表面の高さはチップ１００内で一番高くなる。 FIG. 9 is a view showing a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention, and FIGS. 9A to 9B are sectional views showing the principal part manufacturing steps shown in the order of steps. These drawings correspond to FIGS. 6 and 7, and FIG. 9B is a cross-sectional view of the main part of the semiconductor device of the present invention. These principal part manufacturing process sectional views correspond to principal part sectional views cut along X2-X2 in FIG.
The difference from the third embodiment is that the capacitor 19 is formed on the LOCOS oxide film 5 on the n-well region 2. As a result, an ILD 22 corresponding to the level difference between the n-well region 2 and the p-well region 3 is formed in the portion B on the second electrode 17 in the portion that becomes the capacitor 19.
When the wiring 35 is formed on the ILD 22 adjacent to the second electrode 20, the ILD 22 serves as an interlayer insulating film, and insulation between the wiring 35 and the second electrode 17 can be ensured.
The stopper film 21 under the pad electrode 33 is formed on the LOCOS oxide film 5 on the p-well region 3, and the height of the surface thereof is the highest in the chip 100.

図１０は、この発明の第５実施例の半導体装置の製造方法を示す図であり、同図（ａ）から同図（ｂ）は工程順に示した要部製造工程断面図である。これらの図は図６、図７に相当する図であり、図１０（ｂ）はこの発明の半導体装置の要部断面図でもある。
第３実施例との違いは、ＣＭＰ処理での平坦化した後の図８（ａ）のＩＬＤ２２の表面３６（スパッタ膜２０、２２の表面でもある）にさらにＩＬＤとなる酸化膜３７を形成した点である。こうすることにより、窒化膜のストッパ膜２０、２１が多少ＣＭＰ処理で削られても、ＩＬＤ２２の膜厚を十分厚く確保することができる。この場合も第４実施例と同様にＩＬＤ２２上に形成される配線３５と第２電極１７との間の絶縁を確保できる。 10A and 10B are views showing a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention. FIGS. 10A to 10B are cross-sectional views showing the main part manufacturing steps shown in the order of steps. These drawings correspond to FIGS. 6 and 7, and FIG. 10B is a cross-sectional view of the main part of the semiconductor device of the present invention.
The difference from the third embodiment is that an oxide film 37 to be an ILD is further formed on the surface 36 of the ILD 22 (also the surface of the sputtered films 20 and 22) of FIG. 8A after planarization by CMP processing. Is a point. By doing so, the ILD 22 can be sufficiently thick even if the stopper films 20 and 21 of the nitride film are slightly cut by the CMP process. In this case as well, insulation between the wiring 35 formed on the ILD 22 and the second electrode 17 can be ensured as in the fourth embodiment.

図１１は、この発明の第６実施例の半導体装置の要部断面図である。これはキャパシタ１９が無い場合である。この半導体装置の製造方法は第２実施例において、キャパシタ１９を削除すればよい。キャパシタ１９がないために、図４の第１ポリシリコン膜１５および図５の第２ポリシリコン膜１８などを形成する必要がない。この場合も、パッド用電極３３形成箇所にストッパ膜２１を形成することで、回路形成領域３４の面積は減少しない。   FIG. 11 is a sectional view showing the principal part of a semiconductor device according to the sixth embodiment of the present invention. This is the case where there is no capacitor 19. In this semiconductor device manufacturing method, the capacitor 19 may be eliminated in the second embodiment. Since there is no capacitor 19, it is not necessary to form the first polysilicon film 15 of FIG. 4, the second polysilicon film 18 of FIG. Also in this case, the area of the circuit formation region 34 is not reduced by forming the stopper film 21 at the position where the pad electrode 33 is formed.

この発明の第１実施例の半導体装置の要部構成図であり、（ａ）は平面図、（ｂ）は（ａ）のＸ１−Ｘ１線で切断した断面図BRIEF DESCRIPTION OF THE DRAWINGS It is a principal part block diagram of the semiconductor device of 1st Example of this invention, (a) is a top view, (b) is sectional drawing cut | disconnected by the X1-X1 line | wire of (a) この発明の第２実施例の半導体装置の要部製造工程断面図Sectional view of manufacturing process of main part of semiconductor device according to second embodiment of this invention. 図２に続く、この発明の第２実施例の半導体装置の要部製造工程断面図FIG. 2 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the second embodiment of the present invention continued from FIG. 図３に続く、この発明の第２実施例の半導体装置の要部製造工程断面図FIG. 3 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the second embodiment of the present invention continued from FIG. 図４に続く、この発明の第２実施例の半導体装置の要部製造工程断面図FIG. 4 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the second embodiment of the present invention continued from FIG. 図５に続く、この発明の第２実施例の半導体装置の要部製造工程断面図FIG. 5 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the second embodiment of the present invention continued from FIG. 図６に続く、この発明の第２実施例の半導体装置の要部製造工程断面図FIG. 6 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the second embodiment of the present invention continued from FIG. この発明の第３実施例の半導体装置の製造方法を示す図であり、（ａ）から（ｂ）は工程順に示した要部製造工程断面図It is a figure which shows the manufacturing method of the semiconductor device of 3rd Example of this invention, (a) to (b) is principal part manufacturing process sectional drawing shown to process order この発明の第４実施例の半導体装置の製造方法を示す図であり、（ａ）から（ｂ）は工程順に示した要部製造工程断面図It is a figure which shows the manufacturing method of the semiconductor device of 4th Example of this invention, (a) to (b) is principal part manufacturing process sectional drawing shown to process order この発明の第５実施例の半導体装置の製造方法を示す図であり、（ａ）から（ｂ）は工程順に示した要部製造工程断面図It is a figure which shows the manufacturing method of the semiconductor device of 5th Example of this invention, (a) to (b) is principal part manufacturing process sectional drawing shown to process order この発明の第６実施例の半導体装置の要部断面図Sectional drawing of the principal part of the semiconductor device of 6th Example of this invention 従来の半導体装置の要部構成図であり、（ａ）は平面図、（ｂ）は（ａ）のＸ１−Ｘ１線で切断した断面図It is a principal part block diagram of the conventional semiconductor device, (a) is a top view, (b) is sectional drawing cut | disconnected by the X1-X1 line | wire of (a) 図１２の半導体装置の要部製造工程断面図FIG. 12 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. 図１３に続く、図１２の半導体装置の要部製造工程断面図FIG. 13 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. 図１４に続く、図１２の半導体装置の要部製造工程断面図FIG. 14 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. 図１５に続く、図１２の半導体装置の要部製造工程断面図FIG. 15 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. 図１６に続く、図１２の半導体装置の要部製造工程断面図FIG. 16 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. 図１７に続く、図１２の半導体装置の要部製造工程断面図FIG. 17 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. キャパシタの第２電極がエッチングで削れ取られた様子を示す図The figure which shows a mode that the 2nd electrode of the capacitor was shaved off by the etching ストッパ膜を回路形成領域に設けた半導体装置の要部構成図であり、（ａ）は平面図、（ｂ）は（ａ）のＸ−Ｘ線で切断した断面図4A and 4B are main part configuration diagrams of a semiconductor device in which a stopper film is provided in a circuit formation region, where FIG. 5A is a plan view, and FIG.

符号の説明Explanation of symbols

１ ｐ基板
２ ｎウェル領域
３ ｐウェル領域
４ 段差
５ ＬＯＣＯＳ酸化膜
６ ｎソース領域
７ ｎドレイン領域
８ ｐソース領域
９ ｐドレイン領域
１０、１１ ゲート酸化膜
１２、１３ ゲート電極
１４ 第１電極
１５ 第１ポリシリコン膜
１６ 酸化膜
１７ 第２電極
１８ 第２ポリシリコン膜
１９ キャパシタ
２０、２１ ストッパ膜
２２ ＩＬＤ
２４、２５、２６ 開口部
２７、２８、２９ プラグ
３０、３１ 配線
３２ キャパシタ配線
３３ パッド用電極
３４ 回路形成領域
３５ 配線
１００ チップ 1 p substrate 2 n well region 3 p well region 4 step 5 LOCOS oxide film 6 n source region 7 n drain region 8 p source region 9 p drain region 10, 11 gate oxide film 12, 13 gate electrode 14 first electrode 15 first electrode 15 1 Polysilicon film 16 Oxide film 17 Second electrode 18 Second polysilicon film 19 Capacitor 20, 21 Stopper film 22 ILD
24, 25, 26 Opening 27, 28, 29 Plug 30, 31 Wiring 32 Capacitor Wiring 33 Pad Electrode 34 Circuit Forming Area 35 Wiring 100 Chip

Claims (7)

半導体基板上の層間絶縁膜上に形成されたパッド用電極を有する半導体装置の製造方法において、
前記半導体基板上に第１層間絶縁膜を形成する工程と、前記パッド用電極を形成する箇所の真下で前記第１層間絶縁膜上に研磨停止層を形成する工程と、前記第１層間絶縁膜上と前記研磨停止層上に第２層間絶縁膜を形成する工程と、該第２層間絶縁膜を前記研磨停止層が露出するまで研磨し平坦化する工程と、前記第１層間絶縁膜及び前記第２層間絶縁膜にコンタクト孔を形成する工程と、前記研磨停止層の真上にパッド用電極を形成する工程とを含み、前記研磨停止層を形成する工程では回路形成領域には前記研磨停止層を形成しないことを特徴とする半導体装置の製造方法。 In a method for manufacturing a semiconductor device having a pad electrode formed on an interlayer insulating film on a semiconductor substrate,
Forming a first interlayer insulating film on the semiconductor substrate; forming a polishing stopper layer on the first interlayer insulating film directly below a portion where the pad electrode is formed; and the first interlayer insulating film. Forming a second interlayer insulating film on the top and the polishing stopper layer; polishing and planarizing the second interlayer insulating film until the polishing stopper layer is exposed; and the first interlayer insulating film and the forming a contact hole in the second interlayer insulating film, seen including a step of forming a pad electrode directly above the polishing stop layer, the abrasive in the circuit formation region in the step of forming a polish stop layer A method of manufacturing a semiconductor device, wherein no stop layer is formed . 半導体基板上の層間絶縁膜上に形成されたパッド用電極と、該層間絶縁膜内に形成した上下二層の電極を有するキャパシタとを有する半導体装置の製造方法において、
前記半導体基板上に選択的に素子分離絶縁膜を形成する工程と、
第１導電材料を前記素子分離絶縁膜上に形成し、前記キャパシタを形成する箇所および前記パッド用電極を形成する箇所の真下の前記第１導電材料を残し他を除去する工程と、
前記半導体基板上全面に誘電膜を形成する工程と、
第２電極材料を前記第１導電材料の真上の前記誘電膜上に形成する工程と、
前記半導体基板上全面に第１層間絶縁膜を形成する工程と、
前記パッド用電極を形成する箇所の真下の前記第２導電材料の真上の前記第１層間絶縁膜上、及び前記キャパシタを形成する箇所の前記第２導電材料の真上の前記第１層間絶縁膜上に研磨停止層を形成する工程と、
前記半導体基板上全面に第２層間絶縁膜を形成する工程と、
前記第２層間絶縁膜を前記研磨停止層が露出するまで平坦化する工程と、
前記第２層間絶縁膜、前記第１層間絶縁膜及び前記誘電膜に前記半導体基板に達するコンタクト孔を形成するとともに、前記キャパシタ形成箇所の前記研磨停止層及び前記第１層間絶縁膜に前記第２導電材料に達するコンタクト孔を形成する工程と、
前記研磨停止層の真上に前記パッド電極を形成する工程とを含み、前記研磨停止層を形成する工程では前記キャパシタ形成箇所以外の回路形成領域には前記研磨停止層を形成しないことを特徴とする半導体装置の製造方法。 In a method for manufacturing a semiconductor device comprising a pad electrode formed on an interlayer insulating film on a semiconductor substrate and a capacitor having two upper and lower electrodes formed in the interlayer insulating film,
Forming an element isolation insulating film selectively on the semiconductor substrate;
Forming a first conductive material on the element isolation insulating film , leaving the first conductive material directly under a portion where the capacitor is formed and a portion where the pad electrode is formed;
Forming a dielectric film on the entire surface of the semiconductor substrate;
Forming a second electrode material on the dielectric film directly above the first conductive material;
Forming a first interlayer insulating film on the entire surface of the semiconductor substrate;
The first interlayer insulating film on the first interlayer insulating film directly above the second conductive material immediately below the portion where the pad electrode is to be formed, and on the first interlayer insulating film directly above the second conductive material where the capacitor is to be formed. Forming a polishing stopper layer on the film;
Forming a second interlayer insulating film on the entire surface of the semiconductor substrate;
Planarizing the second interlayer insulating film until the polishing stopper layer is exposed;
A contact hole reaching the semiconductor substrate is formed in the second interlayer insulating film, the first interlayer insulating film, and the dielectric film, and the second stopper is formed in the polishing stopper layer and the first interlayer insulating film at the capacitor formation location. Forming a contact hole reaching the conductive material;
Characterized in that said saw including a step of forming the pad electrode directly above the polishing stop layer, wherein the the circuit forming region other than the capacitor formation portion, in the process of forming the polishing layer does not form the polish stop layer A method for manufacturing a semiconductor device. 前記平坦化する工程の後でコンタクト孔を形成する工程の前に前記半導体基板全面に第３層間絶縁膜を形成する工程を含むことを特徴とする請求項２に記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 2 , further comprising a step of forming a third interlayer insulating film on the entire surface of the semiconductor substrate before the step of forming the contact hole after the step of flattening. 前記素子分離絶縁膜が前記半導体基板を選択酸化した選択酸化膜であることを特徴とする請求項２または３のいずれかに記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 2 or 3, wherein the element isolation insulating film is a selective oxide film selected oxidizing the semiconductor substrate. 前記コンタクト孔を形成する工程は、前記半導体基板に達するコンタクト孔を形成する工程と同時に、前記研磨停止層のエッチングレートが前記誘電膜、及び前記第１から第２または第１から第３層間絶縁膜のエッチングレートより小さい条件で行うことを特徴とする請求項２または３のいずれかに記載の半導体装置の製造方法。 The step of forming the contact hole is the same as the step of forming the contact hole reaching the semiconductor substrate, and the etching rate of the polishing stopper layer is the dielectric film and the first to second or first to third interlayer insulation. 4. The method of manufacturing a semiconductor device according to claim 2 , wherein the method is performed under a condition lower than the etching rate of the film. 前記研磨停止層がシリコン窒化膜からなり、前記素子分離絶縁膜、前記誘電膜、及び前記第１から第２または第１から第３層間絶縁膜がシリコン酸化膜からなることを特徴とする請求項２〜５のいずれか一項に記載の半導体装置の製造方法。 The polishing stop layer is made of a silicon nitride film, and the element isolation insulating film, the dielectric film, and the first to second or first to third interlayer insulating films are made of a silicon oxide film. The manufacturing method of the semiconductor device as described in any one of 2-5 . 前記平坦化する工程をＣＭＰ処理で行うことを特徴とする請求項２〜６のいずれか一項に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 2 , wherein the planarizing step is performed by a CMP process.
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