JP2002305197A - Semiconductor device and manufacturing method therefor - Google Patents
Semiconductor device and manufacturing method thereforInfo
- Publication number
- JP2002305197A JP2002305197A JP2001106765A JP2001106765A JP2002305197A JP 2002305197 A JP2002305197 A JP 2002305197A JP 2001106765 A JP2001106765 A JP 2001106765A JP 2001106765 A JP2001106765 A JP 2001106765A JP 2002305197 A JP2002305197 A JP 2002305197A
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- Prior art keywords
- insulating film
- film
- semiconductor device
- grooves
- manufacturing
- Prior art date
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法に係り、特に絶縁膜に形成した溝又は接続孔
に化学機械研磨（ＣＭＰ）法によって金属膜が埋め込ま
れた配線またはプラグを有する半導体装置及びその製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a wiring or a plug in which a metal film is embedded in a groove or a connection hole formed in an insulating film by a chemical mechanical polishing (CMP) method. The present invention relates to a semiconductor device and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来、配線やプラグなどを形成する方法
として、ＣＭＰ法を用いて絶縁膜に設けられた溝や接続
孔などの凹部内に金属膜を埋め込んで形成する方法があ
る。2. Description of the Related Art Conventionally, as a method for forming a wiring or a plug, there is a method in which a metal film is buried in a concave portion such as a groove or a connection hole provided in an insulating film by using a CMP method.
【０００３】以下、従来の半導体装置の製造方法につい
て説明する。図５（ａ）〜図５（ｃ）は、ＣＭＰ法を用
いて配線を形成する従来の半導体装置の製造工程を示す
断面図である。Hereinafter, a conventional method for manufacturing a semiconductor device will be described. FIGS. 5A to 5C are cross-sectional views illustrating a process of manufacturing a conventional semiconductor device in which a wiring is formed by using a CMP method.
【０００４】まず、図５（ａ）に示す工程で、基板５１
上に膜厚１０００ｎｍの酸化膜からなる絶縁膜５２を形
成する。その後、フォトリソグラフィー技術及びドライ
エッチング技術を用いて、絶縁膜５２における埋め込み
配線形成領域に深さ６００ｎｍの溝５３を形成する。こ
のとき、溝５３ａは孤立して形成されているのに対し
て、溝５３ｂ、５３ｃ、５３ｄは密集して形成されてい
る。First, in a step shown in FIG.
An insulating film 52 made of an oxide film having a thickness of 1000 nm is formed thereon. Thereafter, a groove 53 having a depth of 600 nm is formed in the buried wiring formation region in the insulating film 52 by using a photolithography technique and a dry etching technique. At this time, the grooves 53a are formed in isolation, whereas the grooves 53b, 53c, 53d are formed densely.
【０００５】次に、図５（ｂ）に示す工程で、溝５３を
含む絶縁膜５２上の全面に厚み３０ｎｍのＴａ及びＴａ
Ｎからなるバリア膜５４を形成した後、銅または銅合金
を主成分とする銅膜からなる金属膜５５を９００ｎｍ程
度の厚みで堆積する。Next, in the step shown in FIG. 5B, a 30 nm thick Ta and Ta film are formed on the entire surface of the insulating film 52 including the groove 53.
After forming the barrier film 54 made of N, a metal film 55 made of a copper film containing copper or a copper alloy as a main component is deposited with a thickness of about 900 nm.
【０００６】次に、図５（ｃ）に示す工程で、絶縁膜５
２上の金属膜５５及びバリア膜５４をＣＭＰ法を用いて
研磨除去する。これによって、溝５３ａ内にはバリア膜
５４ａと金属膜５５ａからなる配線５６ａ、溝５３ｂ内
にはバリア膜５４ｂと金属膜５５ｂからなる配線５６
ｂ、溝５３ｃ内にはバリア膜５４ｃと金属膜５５ｃから
なる配線５６ｃ、溝５３ｄ内にはバリア膜５４ｄと金属
膜５５ｄからなる配線５６ｄがそれぞれ形成される。Next, in the step shown in FIG.
The metal film 55 and the barrier film 54 on 2 are polished and removed by using the CMP method. Thus, the wiring 56a formed of the barrier film 54a and the metal film 55a is formed in the groove 53a, and the wiring 56 formed of the barrier film 54b and the metal film 55b is formed in the groove 53b.
b, a wiring 56c composed of a barrier film 54c and a metal film 55c is formed in the groove 53c, and a wiring 56d composed of the barrier film 54d and the metal film 55d is formed in the groove 53d.
【０００７】[0007]
【発明が解決しようとする課題】上述した従来の半導体
装置の製造方法では、図５（ｃ）に示すように、配線５
６ａのように単独配線だけが形成されている、あるい
は、配線が形成されていない低密度配線領域５７に比べ
て、配線５６ｂ、５６ｃ、５６ｄのように複数の配線が
密集して形成されている高密度配線領域５８にへこみが
生じる、いわゆるエロージョンによって凹部５９が形成
され平坦化できないという問題がある。In the above-described conventional method for manufacturing a semiconductor device, as shown in FIG.
Only a single wiring is formed as in 6a, or a plurality of wirings are formed densely as in the wirings 56b, 56c and 56d as compared with the low-density wiring region 57 in which no wiring is formed. The high-density wiring region 58 has a problem that a recess 59 is formed by so-called erosion due to erosion, and it cannot be flattened.
【０００８】これは、ＣＭＰ法によって研磨する際に、
金属膜５５に対する研磨速度が、バリア膜５４や絶縁膜
５２に対する研磨速度よりも大きいため、低密度配線領
域５７と高密度配線領域５８とでは、その絶縁膜５２表
面に加わる研磨圧力が異なり、高密度配線領域５８の方
が圧力が高くなる。このため、高密度配線領域５８で過
剰にＣＭＰが進行し、高密度配線領域５８の絶縁膜５２
は、低密度配線領域５７の絶縁膜５２よりも多く研磨さ
れるため、凹部５９が形成されてしまうという問題が生
じる。This is because when polishing by the CMP method,
Since the polishing rate for the metal film 55 is higher than the polishing rate for the barrier film 54 and the insulating film 52, the polishing pressure applied to the surface of the insulating film 52 differs between the low-density wiring region 57 and the high-density wiring region 58. The pressure is higher in the density wiring region 58. For this reason, excessive CMP progresses in the high-density wiring region 58 and the insulating film 52 in the high-density wiring region 58
Is polished more than the insulating film 52 in the low-density wiring region 57, so that there is a problem that a concave portion 59 is formed.
【０００９】本発明の目的は、ＣＭＰ法におけるエロー
ジョンを抑制し、複数の配線あるいはプラグが密集して
形成されている絶縁膜の表面が平坦化されている半導体
装置及びその製造方法を提供することにある。An object of the present invention is to provide a semiconductor device in which erosion in a CMP method is suppressed, and a surface of an insulating film in which a plurality of wirings or plugs are densely formed is planarized, and a method of manufacturing the same. It is in.
【００１０】[0010]
【課題を解決するための手段】本発明の第１の半導体装
置は、基板上に形成された第１の絶縁膜と、第１の絶縁
膜を所定の深さまで除去して形成された凹部と、凹部内
に埋め込まれた第２の絶縁膜と、少なくとも第２の絶縁
膜をエッチングして形成された複数の溝または接続孔
と、複数の溝または接続孔に埋め込まれた少なくとも金
属膜からなる複数の配線またはプラグとを備え、第２の
絶縁膜は、第１の絶縁膜に比べてＣＭＰ法による研磨速
度が遅く、ＣＭＰ法によって第１の絶縁膜の表面と複数
の配線またはプラグが形成された第２の絶縁膜の表面と
が平坦化されている。According to a first semiconductor device of the present invention, there is provided a first insulating film formed on a substrate, and a concave portion formed by removing the first insulating film to a predetermined depth. A second insulating film embedded in the recess, a plurality of grooves or connection holes formed by etching at least the second insulating film, and at least a metal film embedded in the plurality of grooves or connection holes. A plurality of wirings or plugs, the second insulating film has a lower polishing rate by the CMP method than the first insulating film, and the surface of the first insulating film and the plurality of wirings or plugs are formed by the CMP method; The surface of the formed second insulating film is flattened.
【００１１】上記第１の半導体装置において、複数の溝
または接続孔は、第２の絶縁膜を貫通し、下地の第１の
絶縁膜を所定の深さまでエッチングして設けられてい
る。In the first semiconductor device, the plurality of grooves or connection holes penetrate the second insulating film and are provided by etching the underlying first insulating film to a predetermined depth.
【００１２】また、上記第１の半導体装置において、金
属膜が、銅または銅合金を主成分とする銅膜、あるい
は、タングステンまたはタングステン合金を主成分とす
るタングステン膜からなる。Further, in the first semiconductor device, the metal film is made of a copper film mainly containing copper or a copper alloy, or a tungsten film mainly containing tungsten or a tungsten alloy.
【００１３】この第１の実施形態の半導体装置によれ
ば、複数の配線またはプラグが密集して形成される領域
には、第１の絶縁膜に比べて研磨速度の遅い第２の絶縁
膜が形成されているため、ＣＭＰ法によるエロージョン
が抑制され、配線またはプラグの密集度合いに依存しな
い平坦な表面を有する構造を得ることができる。従っ
て、配線またはプラグのエロージョンによる膜厚減少や
段差に起因した信頼性や歩留まりの低下を防止すること
ができ、半導体装置の信頼性や歩留まりの向上を図るこ
とができる。According to the semiconductor device of the first embodiment, in the region where a plurality of wirings or plugs are densely formed, the second insulating film whose polishing rate is lower than that of the first insulating film is formed. Since it is formed, erosion due to the CMP method is suppressed, and a structure having a flat surface independent of the density of wirings or plugs can be obtained. Accordingly, it is possible to prevent a decrease in reliability and yield due to a reduction in film thickness or a step due to erosion of the wiring or plug, and to improve the reliability and yield of the semiconductor device.
【００１４】本発明の第２の半導体装置は、基板上に形
成された第１の絶縁膜と、第１の絶縁膜上の一部領域に
形成された第２の絶縁膜と、第１の絶縁膜上の他部領域
に第２の絶縁膜に接して形成された第３の絶縁膜と、少
なくとも第２の絶縁膜をエッチングして形成された複数
の溝または接続孔と、複数の溝または接続孔に埋め込ま
れた少なくとも金属膜からなる複数の配線またはプラグ
とを備え、第２の絶縁膜は、第３の絶縁膜に比べてＣＭ
Ｐ法による研磨速度が遅く、ＣＭＰ法によって第３の絶
縁膜の表面と複数の配線またはプラグが形成された第２
の絶縁膜の表面とが平坦化されている。According to a second semiconductor device of the present invention, a first insulating film formed on a substrate, a second insulating film formed in a partial region on the first insulating film, A third insulating film formed in contact with the second insulating film in another region on the insulating film, a plurality of grooves or connection holes formed by etching at least the second insulating film, and a plurality of grooves Or a plurality of wirings or plugs made of at least a metal film embedded in the connection hole, and the second insulating film has a higher CM than the third insulating film.
The polishing rate by the P method is low, and the surface of the third insulating film and the second wiring having a plurality of wirings or plugs formed by the CMP method are formed.
Of the insulating film is flattened.
【００１５】また、上記第２の半導体装置において、複
数の溝または接続孔は、第２の絶縁膜を貫通し、下地の
第１の絶縁膜を所定の深さまでエッチングして設けられ
ている。In the second semiconductor device, the plurality of grooves or connection holes penetrate the second insulating film and are provided by etching the underlying first insulating film to a predetermined depth.
【００１６】また、上記第２の半導体装置において、金
属膜が、銅または銅合金を主成分とする銅膜、あるい
は、タングステンまたはタングステン合金を主成分とす
るタングステン膜からなる。In the second semiconductor device, the metal film is made of a copper film mainly containing copper or a copper alloy, or a tungsten film mainly containing tungsten or a tungsten alloy.
【００１７】この第２の実施形態の半導体装置によれ
ば、複数の配線またはプラグが密集して形成される領域
には、第３の絶縁膜に比べて研磨速度の遅い第２の絶縁
膜が形成されているため、ＣＭＰ法によるエロージョン
が抑制され、配線またはプラグの密集度合いに依存しな
い平坦な表面を有する構造を得ることができる。従っ
て、配線またはプラグのエロージョンによる膜厚減少や
段差に起因した信頼性や歩留まりの低下を防止すること
ができ、半導体装置の信頼性や歩留まりの向上を図るこ
とができる。According to the semiconductor device of the second embodiment, in the region where a plurality of wirings or plugs are densely formed, the second insulating film whose polishing rate is lower than that of the third insulating film is formed. Since it is formed, erosion due to the CMP method is suppressed, and a structure having a flat surface independent of the density of wirings or plugs can be obtained. Accordingly, it is possible to prevent a decrease in reliability and yield due to a reduction in film thickness or a step due to erosion of the wiring or plug, and to improve the reliability and yield of the semiconductor device.
【００１８】本発明の第１の半導体装置の製造方法は、
基板上に第１の絶縁膜を形成する工程（ａ）と、第１の
絶縁膜を所定の深さまで除去して凹部を形成する工程
（ｂ）と、凹部を含む第１の絶縁膜上の全面に、第１の
絶縁膜よりもＣＭＰ法における研磨速度の遅い第２の絶
縁膜を形成する工程（ｃ）と、第１の絶縁膜上の第２の
絶縁膜をＣＭＰ法によって研磨除去して、凹部内のみに
第２の絶縁膜を残存させる工程（ｄ）と、工程（ｄ）の
後に、少なくとも第２の絶縁膜をエッチングして複数の
溝または接続孔を形成する工程（ｅ）と、工程（ｅ）の
後に、基板上の全面に、少なくとも金属膜を形成する工
程（ｆ）と、金属膜をＣＭＰ法によって研磨し、複数の
溝または接続孔に金属膜を選択的に埋め込み、複数の配
線またはプラグを形成する工程（ｇ）と、工程（ｇ）の
後に、基板上の全面をＣＭＰ法によって研磨して、少な
くとも第１及び第２の絶縁膜の一部を除去する工程
（ｈ）とを備えている。According to the first method of manufacturing a semiconductor device of the present invention,
(A) forming a first insulating film on a substrate, (b) removing the first insulating film to a predetermined depth to form a concave portion, and (b) forming a concave portion on the first insulating film including the concave portion. (C) forming a second insulating film having a lower polishing rate in the CMP method than the first insulating film over the entire surface, and polishing and removing the second insulating film on the first insulating film by the CMP method; (D) leaving the second insulating film only in the recess, and (e) forming a plurality of grooves or connection holes by etching at least the second insulating film after the step (d). And (f) forming at least a metal film on the entire surface of the substrate after the step (e). Polishing the metal film by a CMP method to selectively bury the metal film in a plurality of grooves or connection holes. Forming a plurality of wirings or plugs, and after the step (g), the entire surface on the substrate is formed. Polished by CMP, and a step (h) removing a portion of the at least first and second insulating films.
【００１９】上記第１の半導体装置の製造方法におい
て、工程（ｈ）では、第２の絶縁膜を全て除去しても良
い。In the first method for manufacturing a semiconductor device, in the step (h), the second insulating film may be entirely removed.
【００２０】また、上記第１の半導体装置の製造方法に
おいて、工程（ｅ）における複数の溝または接続孔は、
第２の絶縁膜を貫通し、下地の第１の絶縁膜を所定の深
さまでエッチングして形成されている。In the first method for manufacturing a semiconductor device, the plurality of grooves or connection holes in the step (e) may be
It is formed by etching the underlying first insulating film to a predetermined depth, penetrating the second insulating film.
【００２１】また、上記第１の半導体装置の製造方法に
おいて、金属膜として、銅または銅合金を主成分とする
銅膜、あるいは、タングステンまたはタングステン合金
を主成分とするタングステン膜からなる。In the first method of manufacturing a semiconductor device, the metal film may be a copper film containing copper or a copper alloy as a main component, or a tungsten film containing tungsten or a tungsten alloy as a main component.
【００２２】この第１の実施形態の半導体装置の製造方
法によれば、複数の配線が密集して形成される領域に
は、研磨速度の遅い第２の絶縁膜が形成されているた
め、ＣＭＰ法により金属膜及びバリア膜を研磨除去した
際に、エロージョンによって生じる第２の絶縁膜の凹み
の深さを低減することができる。さらに、露出した第１
の絶縁膜及び第２の絶縁膜をＣＭＰ法により所定の厚み
分だけ全面研磨することによって、第１の絶縁膜に比べ
て第２の絶縁膜の方が研磨速度が遅いため、エロージョ
ンによって生じた第２の絶縁膜の凹みを無くし、第１の
絶縁膜の表面と第２の絶縁膜の表面とを平坦化すること
ができる。According to the method of manufacturing a semiconductor device of the first embodiment, the second insulating film having a low polishing rate is formed in a region where a plurality of wirings are densely formed. When the metal film and the barrier film are polished and removed by the method, the depth of the depression of the second insulating film caused by erosion can be reduced. In addition, the first exposed
By polishing the entire surface of the insulating film and the second insulating film by a predetermined thickness by a CMP method, the polishing rate of the second insulating film is lower than that of the first insulating film. The depression of the second insulating film can be eliminated, and the surface of the first insulating film and the surface of the second insulating film can be planarized.
【００２３】本発明の第２の半導体装置の製造方法は、
基板上に第１の絶縁膜を形成する工程（ａ）と、第１の
絶縁膜上の一部領域に第２の絶縁膜を形成する工程
（ｂ）と、第１の絶縁膜上の他部領域に、第２の絶縁膜
よりもＣＭＰ法における研磨速度の速い第３の絶縁膜を
形成する工程（ｃ）と、工程（ｂ）及び（ｃ）の後に、
少なくとも第２の絶縁膜をエッチングして複数の溝また
は接続孔を形成する工程（ｄ）と、工程（ｄ）の後に、
基板上の全面に、少なくとも金属膜を形成する工程
（ｅ）と、金属膜をＣＭＰ法によって研磨し、複数の溝
または接続孔に金属膜を選択的に埋め込み、複数の配線
またはプラグを形成する工程（ｆ）と、工程（ｆ）の後
に、基板上の全面をＣＭＰ法によって研磨して、少なく
とも第２及び第３の絶縁膜の一部を除去する工程（ｇ）
とを備えている。According to a second method of manufacturing a semiconductor device of the present invention,
(A) forming a first insulating film on a substrate, (b) forming a second insulating film in a partial region on the first insulating film, and (b) forming a second insulating film on the first insulating film. (C) forming a third insulating film having a higher polishing rate in the CMP method than the second insulating film in the partial region; and (b) and (c),
(D) forming at least a second insulating film to form a plurality of grooves or connection holes by etching, and after the step (d),
Step (e) of forming at least a metal film on the entire surface of the substrate, polishing the metal film by a CMP method, and selectively embedding the metal film in a plurality of grooves or connection holes to form a plurality of wirings or plugs. Step (f) and, after step (f), polishing the entire surface of the substrate by a CMP method to remove at least a part of the second and third insulating films (g).
And
【００２４】上記第２の半導体装置の製造方法におい
て、工程（ｇ）では、第２の絶縁膜を全て除去しても良
い。In the second method of manufacturing a semiconductor device, in the step (g), the second insulating film may be entirely removed.
【００２５】また、上記第２の半導体装置の製造方法に
おいて、工程（ｄ）における複数の溝または接続孔は、
第２の絶縁膜を貫通し、下地の第１の絶縁膜を所定の深
さまでエッチングして形成されている。In the second method of manufacturing a semiconductor device, the plurality of grooves or connection holes in the step (d) may be:
It is formed by etching the underlying first insulating film to a predetermined depth, penetrating the second insulating film.
【００２６】また、上記第２の半導体装置の製造方法に
おいて、金属膜として、銅または銅合金を主成分とする
銅膜、あるいは、タングステンまたはタングステン合金
を主成分とするタングステン膜からなる。In the second method of manufacturing a semiconductor device, the metal film is made of a copper film mainly containing copper or a copper alloy, or a tungsten film mainly containing tungsten or a tungsten alloy.
【００２７】この第２の実施形態の半導体装置の製造方
法によれば、複数の配線が密集して形成される領域に
は、研磨速度の遅い第２の絶縁膜が形成されているた
め、ＣＭＰ法により金属膜及びバリア膜を研磨除去した
際に、エロージョンによって生じる第２の絶縁膜の凹み
の深さを低減することができる。さらに、露出した第３
の絶縁膜及び第２の絶縁膜をＣＭＰ法により所定の厚み
分だけ全面研磨することによって、第３の絶縁膜に比べ
て第２の絶縁膜の方が研磨速度が遅いため、エロージョ
ンによって生じた第２の絶縁膜の凹みを無くし、第３の
絶縁膜の表面と第２の絶縁膜の表面とを平坦化すること
ができる。According to the method of manufacturing a semiconductor device of the second embodiment, the second insulating film having a low polishing rate is formed in a region where a plurality of wirings are densely formed. When the metal film and the barrier film are polished and removed by the method, the depth of the depression of the second insulating film caused by erosion can be reduced. In addition, the third exposed
By polishing the entire surface of the insulating film and the second insulating film by a predetermined thickness by a CMP method, the polishing rate of the second insulating film is lower than that of the third insulating film. The depression of the second insulating film can be eliminated, and the surface of the third insulating film and the surface of the second insulating film can be planarized.
【００２８】[0028]
【発明の実施の形態】（第１の実施形態）本発明の第１
の実施形態に係る半導体装置およびその製造方法につい
て説明する。図１は、本発明の第１の実施形態に係るＣ
ＭＰ法によって形成された複数の配線を有する半導体装
置の断面図である。(First Embodiment) A first embodiment of the present invention.
A semiconductor device according to the embodiment and a method for manufacturing the same will be described. FIG. 1 is a diagram showing a C according to the first embodiment of the present invention.
FIG. 4 is a cross-sectional view of a semiconductor device having a plurality of wirings formed by an MP method.
【００２９】図１に示すように、第１の実施形態に係る
半導体装置は、半導体基板からなる基板１と、基板１上
に形成されたシリコン酸化膜からなる第１の絶縁膜２
と、第１の絶縁膜２を所定の深さまで除去して形成され
た凹部３と、表面が第１の絶縁膜２の表面と平坦になる
ように凹部３内に形成されたシリコン窒化膜からなる第
２の絶縁膜４と、第１の絶縁膜２を所定の深さまでエッ
チングして形成された溝５ａと、第２の絶縁膜４を貫通
し第１の絶縁膜２を所定の深さまでエッチングして形成
された複数の溝５ｂ、５ｃ、５ｄと、溝５ａ内に埋め込
まれたバリア膜６ａと金属膜７ａからなる配線８ａ、複
数の溝５ｂ、５ｃ、５ｄ内にそれぞれ埋め込まれたバリ
ア膜６ｂ、６ｃ、６ｄと金属膜７ｂ、７ｃ、７ｄからな
る配線８ｂ、８ｃ、８ｄとを備えている。本実施の形態
において、バリア膜６ａ、６ｂ、６ｃ、６ｄはＴａ／Ｔ
ａＮの積層膜からなり、金属膜７ａ、７ｂ、７ｃ、７ｄ
は銅または銅合金を主成分とする銅膜からなる。As shown in FIG. 1, a semiconductor device according to the first embodiment includes a substrate 1 made of a semiconductor substrate and a first insulating film 2 made of a silicon oxide film formed on the substrate 1.
And a concave portion 3 formed by removing the first insulating film 2 to a predetermined depth, and a silicon nitride film formed in the concave portion 3 so that the surface is flat with the surface of the first insulating film 2. A second insulating film 4, a groove 5a formed by etching the first insulating film 2 to a predetermined depth, and a first insulating film 2 penetrating through the second insulating film 4 to a predetermined depth. A plurality of trenches 5b, 5c, 5d formed by etching, a wiring 8a composed of a barrier film 6a and a metal film 7a embedded in the trench 5a, a barrier embedded in the plurality of trenches 5b, 5c, 5d, respectively. It has wirings 8b, 8c, 8d composed of films 6b, 6c, 6d and metal films 7b, 7c, 7d. In the present embodiment, the barrier films 6a, 6b, 6c, 6d are made of Ta / T
aN laminated film, metal films 7a, 7b, 7c, 7d
Is made of a copper film containing copper or a copper alloy as a main component.
【００３０】そして、シリコン窒化膜からなる第２の絶
縁膜４は、シリコン酸化膜からなる第１の絶縁膜２に比
べてＣＭＰ法による研磨速度が遅く、ＣＭＰ法によって
第１の絶縁膜２の表面と複数の配線８ｂ、８ｃ、８ｄが
形成された第２の絶縁膜４の表面が平坦化されている。The polishing rate of the second insulating film 4 made of a silicon nitride film is lower than that of the first insulating film 2 made of a silicon oxide film by the CMP method. The surface of the second insulating film 4 on which the surface and the plurality of wirings 8b, 8c, 8d are formed is flattened.
【００３１】図２（ａ）〜図２（ｅ）は、本発明の第１
の実施形態に係るＣＭＰ法を用いて形成された複数の配
線を有する半導体装置の製造工程を示す断面図である。FIGS. 2A to 2E show the first embodiment of the present invention.
FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device having a plurality of wirings formed by using the CMP method according to the embodiment.
【００３２】まず、図２（ａ）に示す工程で、半導体基
板からなる基板１上に膜厚１０００ｎｍのシリコン酸化
膜からなる第１の絶縁膜２を形成する。その後、フォト
リソグラフィー技術及びドライエッチング技術を用い
て、複数の配線を密集して形成する高密度配線領域１０
の第１の絶縁膜２を所定の深さまでエッチングして、例
えば深さ２００ｎｍ程度の凹部３を形成する。このと
き、凹部３は、密集して形成される複数の配線を包含で
きるように形成する。なお、凹部３領域以外の低密度配
線領域１１には、配線を形成しないか、あるいは、配線
を形成しても単独で形成し複数の配線を密集させないこ
とが望ましい。First, in the step shown in FIG. 2A, a first insulating film 2 made of a silicon oxide film having a thickness of 1000 nm is formed on a substrate 1 made of a semiconductor substrate. Thereafter, a high-density wiring region 10 in which a plurality of wirings are densely formed using photolithography technology and dry etching technology.
The first insulating film 2 is etched to a predetermined depth to form a concave portion 3 having a depth of, for example, about 200 nm. At this time, the recess 3 is formed so as to include a plurality of wirings formed densely. It is desirable that no wiring is formed in the low-density wiring region 11 other than the concave portion 3 region, or that even if the wiring is formed, it is formed independently and the plurality of wirings are not densely packed.
【００３３】次に、図２（ｂ）に示す工程で、凹部３を
含む第１の絶縁膜２上の全面に、第１の絶縁膜２よりも
ＣＭＰ法における研磨速度の遅いシリコン窒化膜からな
る第２の絶縁膜を膜厚４００ｎｍ程度で形成する。その
後、ＣＭＰ法によって第１の絶縁膜２上の第２の絶縁膜
を研磨除去して、凹部３内に厚さ２００ｎｍ程度の第２
の絶縁膜４を埋め込み形成する。このとき、第１の絶縁
膜２の表面と第２の絶縁膜４の表面とが平坦になるよう
に形成する。Next, in the step shown in FIG. 2B, a silicon nitride film having a lower polishing rate than the first insulating film 2 by the CMP method is formed on the entire surface of the first insulating film 2 including the concave portion 3. A second insulating film having a thickness of about 400 nm is formed. After that, the second insulating film on the first insulating film 2 is polished and removed by the CMP method, and the second insulating film having a thickness of about 200 nm is formed in the concave portion 3.
Is buried. At this time, the surface of the first insulating film 2 and the surface of the second insulating film 4 are formed to be flat.
【００３４】次に、図２（ｃ）に示す工程で、第１の絶
縁膜２及び第２の絶縁膜４をエッチングして所定の深さ
例えば深さ６００ｎｍ程度の溝５を形成する。このと
き、密集していない単独の配線を形成するための溝５ａ
は、低密度配線領域１１の第１の絶縁膜２を６００ｎｍ
程度エッチングして形成する。また、密集した複数の配
線を形成するための溝５ｂ、５ｃ、５ｄは、高密度配線
領域１０の第２の絶縁膜４を貫通し、下地の第１の絶縁
膜２を４００ｎｍ程度エッチングして形成する。Next, in the step shown in FIG. 2C, the first insulating film 2 and the second insulating film 4 are etched to form a groove 5 having a predetermined depth, for example, a depth of about 600 nm. At this time, the groove 5a for forming a single wiring that is not dense
Sets the first insulating film 2 in the low-density wiring region 11 to 600 nm.
It is formed by etching to a certain degree. The grooves 5b, 5c, and 5d for forming a plurality of dense wirings penetrate the second insulating film 4 in the high-density wiring region 10, and etch the underlying first insulating film 2 by about 400 nm. Form.
【００３５】次に、図２（ｄ）に示す工程で、溝５を含
む第１の絶縁膜２及び第２の絶縁膜４上の全面に厚み３
０ｎｍのＴａ及びＴａＮからなるバリア膜６を形成した
後、バリア膜６上に銅または銅合金を主成分とする銅膜
からなる金属膜７を９００ｎｍ程度の厚みで堆積する。Next, in the step shown in FIG. 2D, the entire surface of the first insulating film 2 and the second
After forming the barrier film 6 made of Ta and TaN with a thickness of 0 nm, a metal film 7 made of a copper film containing copper or a copper alloy as a main component is deposited on the barrier film 6 to a thickness of about 900 nm.
【００３６】次に、図２（ｅ）に示す工程で、ＣＭＰ法
によって第１の絶縁膜２及び第２の絶縁膜４上の金属膜
７及びバリア膜６を研磨除去する。さらに、ＣＭＰ法に
より露出した第１の絶縁膜２及び第２の絶縁膜４を所定
の厚み分、例えば第２の絶縁膜４の厚みで５０ｎｍ程度
だけ全面研磨して、第１の絶縁膜２の表面と第２の絶縁
膜４の表面を平坦化する。これによって、溝５ａ内には
バリア膜６ａと金属膜７ａからなる配線８ａ、溝５ｂ内
にはバリア膜６ｂと金属膜７ｂからなる配線８ｂ、溝５
ｃ内にはバリア膜６ｃと金属膜７ｃからなる配線８ｃ、
溝５ｄ内にはバリア膜６ｄと金属膜７ｄからなる配線８
ｄがそれぞれ形成される。Next, in the step shown in FIG. 2E, the metal film 7 and the barrier film 6 on the first insulating film 2 and the second insulating film 4 are polished and removed by the CMP method. Further, the first insulating film 2 and the second insulating film 4 exposed by the CMP method are entirely polished by a predetermined thickness, for example, about 50 nm with a thickness of the second insulating film 4, so that the first insulating film 2 is formed. And the surface of the second insulating film 4 are flattened. Thus, the wiring 8a formed of the barrier film 6a and the metal film 7a in the groove 5a, the wiring 8b formed of the barrier film 6b and the metal film 7b in the groove 5b, and the groove 5
c, a wiring 8c composed of a barrier film 6c and a metal film 7c;
A wiring 8 composed of a barrier film 6d and a metal film 7d is provided in the groove 5d.
d are respectively formed.
【００３７】なお、上記第１の実施形態では、第１の絶
縁膜２としてシリコン酸化膜を用い、第２の絶縁膜４と
してシリコン窒化膜を用いて説明したが、第１の絶縁膜
２に対して第２の絶縁膜の研磨速度が遅ければ良い。例
えば、第１の絶縁膜２がＢＰＳＧ膜の場合、第２の絶縁
膜としてＢＰＳＧ膜よりも研磨速度の遅いＮＳＧ膜、ま
たは、シリコン窒化膜を用いれば良い。In the first embodiment, a silicon oxide film is used as the first insulating film 2 and a silicon nitride film is used as the second insulating film 4. On the other hand, it is sufficient that the polishing rate of the second insulating film is low. For example, when the first insulating film 2 is a BPSG film, an NSG film or a silicon nitride film having a lower polishing rate than the BPSG film may be used as the second insulating film.
【００３８】また、溝５の深さに比べ凹部３の深さを浅
く形成したが、凹部３の深さを溝５の深さよりも深く形
成してもよい。これによって、凹部３内には、溝５の深
さよりも膜厚の厚い第２の絶縁膜４が形成されるため、
配線８ｂ、８ｃ、８ｄの側面及び底面を第２の絶縁膜４
で取り囲むことができる。Although the depth of the concave portion 3 is formed shallower than the depth of the groove 5, the depth of the concave portion 3 may be formed to be deeper than the depth of the groove 5. As a result, the second insulating film 4 having a thickness larger than the depth of the groove 5 is formed in the concave portion 3,
The side surfaces and the bottom surfaces of the wirings 8b, 8c, 8d are
Can be surrounded by
【００３９】また、図２（ｅ）に示す工程では、第２の
絶縁膜４のうち一部厚み分だけ研磨除去したが、第２の
絶縁膜４の全厚み分を除去してもよい。この場合の第２
の絶縁膜４の膜厚としては、ＣＭＰ法によって金属膜７
及びバリア膜６を研磨除去した際に第２の絶縁膜に生じ
た凹みを、その後の全面研磨によって平坦化できる程度
の膜厚があればよく、例えば凹部３の深さを５０ｎｍに
して厚み５０ｎｍの第２の絶縁膜４を形成しておけばよ
い。In the step shown in FIG. 2E, a part of the second insulating film 4 is polished and removed. However, the entire thickness of the second insulating film 4 may be removed. The second in this case
The thickness of the insulating film 4 is determined by the CMP method.
Further, it is sufficient that the recess formed in the second insulating film when the barrier film 6 is polished and removed has a film thickness that can be flattened by subsequent overall polishing. The second insulating film 4 may be formed beforehand.
【００４０】この第１の実施形態の半導体装置及びその
製造方法によれば、複数の配線８ｂ、８ｃ、８ｄが密集
して形成される高密度配線領域１０には、研磨速度の遅
い第２の絶縁膜４が形成されている。そのため、ＣＭＰ
法により金属膜７及びバリア膜６を研磨除去した際に、
エロージョンによって生じる第２の絶縁膜４の凹みの深
さが低減される。さらに、露出した第１の絶縁膜２及び
第２の絶縁膜４をＣＭＰ法により全面研磨することによ
って、第１の絶縁膜２に比べて第２の絶縁膜４の方が研
磨速度が遅いため、エロージョンによって生じた第２の
絶縁膜４の凹みが解消され、第１の絶縁膜２の表面と第
２の絶縁膜４の表面とを平坦化することができる。According to the semiconductor device of the first embodiment and the method of manufacturing the same, the high-density wiring region 10 in which the plurality of wirings 8b, 8c and 8d are formed densely has the second polishing rate of low An insulating film 4 is formed. Therefore, CMP
When the metal film 7 and the barrier film 6 are polished and removed by the method,
The depth of the depression of the second insulating film 4 caused by the erosion is reduced. Furthermore, since the exposed first insulating film 2 and the second insulating film 4 are entirely polished by the CMP method, the polishing rate of the second insulating film 4 is lower than that of the first insulating film 2. In addition, the depression of the second insulating film 4 caused by the erosion is eliminated, and the surface of the first insulating film 2 and the surface of the second insulating film 4 can be flattened.
【００４１】（第２の実施形態）本発明の第２の実施形
態に係る半導体装置およびその製造方法について説明す
る。図３は、本発明の第２の実施形態に係るＣＭＰ法に
よって形成された複数の配線を有する半導体装置の断面
図である。(Second Embodiment) A semiconductor device according to a second embodiment of the present invention and a method for manufacturing the same will be described. FIG. 3 is a cross-sectional view of a semiconductor device having a plurality of wirings formed by the CMP method according to the second embodiment of the present invention.
【００４２】図３に示すように、第２の実施形態に係る
半導体装置は、半導体基板からなる基板１と、基板１上
に形成されたシリコン酸化膜からなる第１の絶縁膜２
と、第１の絶縁膜上の一部領域上に形成されたシリコン
窒化膜からなる第２の絶縁膜４と、第１の絶縁膜上の他
部領域上に第２の絶縁膜４に接して形成されたシリコン
酸化膜からなる第３の絶縁膜９と、第３の絶縁膜９を貫
通し第１の絶縁膜２を所定の深さまでエッチングして形
成された溝５ａと、第２の絶縁膜４を貫通し第１の絶縁
膜２を所定の深さまでエッチングして形成された複数の
溝５ｂ、５ｃ、５ｄと、溝５ａ内に埋め込まれたバリア
膜６ａと金属膜７ａからなる配線８ａと、複数の溝５
ｂ、５ｃ、５ｄ内にそれぞれ埋め込まれたバリア膜６
ｂ、６ｃ、６ｄと金属膜７ｂ、７ｃ、７ｄからなる配線
８ｂ、８ｃ、８ｄとを備えている。本実施の形態におい
て、バリア膜６ａ、６ｂ、６ｃ、６ｄはＴａ／ＴａＮの
積層膜からなり、金属膜７ａ、７ｂ、７ｃ、７ｄは銅ま
たは銅合金を主成分とする銅膜からなる。As shown in FIG. 3, a semiconductor device according to the second embodiment includes a substrate 1 made of a semiconductor substrate and a first insulating film 2 made of a silicon oxide film formed on the substrate 1.
And a second insulating film 4 made of a silicon nitride film formed on a partial region on the first insulating film, and a second insulating film 4 on another region on the first insulating film. A third insulating film 9 made of a silicon oxide film formed by etching, a groove 5a penetrating the third insulating film 9 and etching the first insulating film 2 to a predetermined depth, and a second A plurality of trenches 5b, 5c, and 5d formed by penetrating the insulating film 4 and etching the first insulating film 2 to a predetermined depth, and a wiring including a barrier film 6a and a metal film 7a embedded in the trench 5a. 8a and a plurality of grooves 5
barrier film 6 embedded in each of b, 5c and 5d
b, 6c, 6d and wirings 8b, 8c, 8d composed of metal films 7b, 7c, 7d. In the present embodiment, the barrier films 6a, 6b, 6c, and 6d are made of a laminated film of Ta / TaN, and the metal films 7a, 7b, 7c, and 7d are made of a copper film containing copper or a copper alloy as a main component.
【００４３】そして、シリコン窒化膜からなる第２の絶
縁膜４は、シリコン酸化膜からなる第３の絶縁膜９に比
べてＣＭＰ法による研磨速度が遅く、ＣＭＰ法によって
第３の絶縁膜９の表面と複数の配線８ｂ、８ｃ、８ｄが
形成された第２の絶縁膜４の表面が平坦化されている。The polishing rate of the second insulating film 4 made of a silicon nitride film is lower than that of the third insulating film 9 made of a silicon oxide film by the CMP method. The surface of the second insulating film 4 on which the surface and the plurality of wirings 8b, 8c, 8d are formed is flattened.
【００４４】図４（ａ）〜図４（ｅ）は、本発明の第２
の実施形態に係るＣＭＰ法を用いて形成された複数の配
線を有する半導体装置の製造工程を示す断面図である。FIGS. 4A to 4E show the second embodiment of the present invention.
FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device having a plurality of wirings formed by using the CMP method according to the embodiment.
【００４５】まず、図４（ａ）に示す工程で、半導体基
板からなる基板１上に膜厚８００ｎｍのシリコン酸化膜
からなる第１の絶縁膜２を形成する。その後、第１の絶
縁膜２上に膜厚２００ｎｍのシリコン窒化膜からなる第
２の絶縁膜を形成した後、フォトリソグラフィー技術及
びドライエッチング技術を用いてパターニングを行い、
複数の配線を密集して形成する高密度配線領域１０に第
２の絶縁膜４を形成する。このとき、第２の絶縁膜４
は、密集して形成される複数の配線を包含できるように
形成することが望ましい。First, in a step shown in FIG. 4A, a first insulating film 2 made of a silicon oxide film having a thickness of 800 nm is formed on a substrate 1 made of a semiconductor substrate. After that, a second insulating film made of a silicon nitride film having a thickness of 200 nm is formed on the first insulating film 2 and then patterned by using a photolithography technique and a dry etching technique.
The second insulating film 4 is formed in the high-density wiring region 10 where a plurality of wirings are densely formed. At this time, the second insulating film 4
Is desirably formed so as to include a plurality of wirings formed densely.
【００４６】次に、図４（ｂ）に示す工程で、第２の絶
縁膜４を含む第１の絶縁膜２上の全面に、第２の絶縁膜
４よりもＣＭＰ法における研磨速度の速いシリコン酸化
膜からなる第３の絶縁膜を膜厚５００ｎｍ程度で形成す
る。その後、ＣＭＰ法によって第２の絶縁膜４上の第３
の絶縁膜を研磨除去して、第２の絶縁膜４が形成されて
いない第１の絶縁膜２上の全面に第２の絶縁膜４に接す
る厚さ２００ｎｍ程度の第３の絶縁膜９を形成する。こ
のとき、第２の絶縁膜４の表面と第３の絶縁膜９の表面
とが平坦になるように形成する。なお、第２の絶縁膜４
が形成された領域以外の低密度配線領域１１には、配線
を形成しないか、あるいは、配線を形成しても単独で形
成し複数の配線を密集させないことが望ましい。Next, in the step shown in FIG. 4B, the polishing rate in the CMP method is higher than that of the second insulating film 4 over the entire surface of the first insulating film 2 including the second insulating film 4. A third insulating film made of a silicon oxide film is formed with a thickness of about 500 nm. After that, the third insulating film 4
Is removed by polishing, and a third insulating film 9 having a thickness of about 200 nm in contact with the second insulating film 4 is formed on the entire surface of the first insulating film 2 on which the second insulating film 4 is not formed. Form. At this time, the surface of the second insulating film 4 and the surface of the third insulating film 9 are formed to be flat. The second insulating film 4
It is desirable that no wiring is formed in the low-density wiring area 11 other than the area where the wiring is formed, or that even if the wiring is formed, it is formed independently and the plurality of wirings are not densely packed.
【００４７】次に、図４（ｃ）に示す工程で、第１の絶
縁膜２、第２の絶縁膜４及び第３の絶縁膜９をエッチン
グして所定の深さ例えば深さ６００ｎｍ程度の溝５を形
成する。このとき、密集していない単独の配線を形成す
るための溝５ａは、低密度配線領域１１の第３の絶縁膜
９を貫通し、下地の第１の絶縁膜２を４００ｎｍ程度エ
ッチングして形成する。また、密集した複数の配線を形
成するための溝５ｂ、５ｃ、５ｄは、高密度配線領域１
０の第２の絶縁膜４を貫通し、下地の第１の絶縁膜２を
４００ｎｍ程度エッチングして形成する。Next, in the step shown in FIG. 4C, the first insulating film 2, the second insulating film 4 and the third insulating film 9 are etched to have a predetermined depth, for example, a depth of about 600 nm. A groove 5 is formed. At this time, the groove 5a for forming a single wiring that is not densely formed penetrates through the third insulating film 9 in the low-density wiring region 11, and is formed by etching the underlying first insulating film 2 by about 400 nm. I do. The grooves 5b, 5c, and 5d for forming a plurality of dense wirings are formed in the high-density wiring region 1
The second insulating film 4 is formed by etching the underlying first insulating film 2 by about 400 nm.
【００４８】次に、図４（ｄ）に示す工程で、溝５を含
む第２の絶縁膜４及び第３の絶縁膜９上の全面に厚み３
０ｎｍのＴａ及びＴａＮからなるバリア膜６を形成した
後、バリア膜６上に銅または銅合金を主成分とする銅膜
からなる金属膜７を９００ｎｍ程度の厚みで堆積する。Next, in the step shown in FIG. 4D, the entire surface of the second insulating film 4 and the third
After forming the barrier film 6 made of Ta and TaN with a thickness of 0 nm, a metal film 7 made of a copper film containing copper or a copper alloy as a main component is deposited on the barrier film 6 to a thickness of about 900 nm.
【００４９】次に、図４（ｅ）に示す工程で、ＣＭＰ法
によって第２の絶縁膜４及び第３の絶縁膜９上の金属膜
７及びバリア膜６を研磨除去する。さらに、ＣＭＰ法に
より露出した第２の絶縁膜４及び第３の絶縁膜９を所定
の厚み分、例えば第２の絶縁膜４の厚みで５０ｎｍ程度
だけ全面研磨して、第２の絶縁膜４の表面と第３の絶縁
膜９の表面を平坦化する。これによって、溝５ａ内には
バリア膜６ａと金属膜７ａからなる配線８ａ、溝５ｂ内
にはバリア膜６ｂと金属膜７ｂからなる配線８ｂ、溝５
ｃ内にはバリア膜６ｃと金属膜７ｃからなる配線８ｃ、
溝５ｄ内にはバリア膜６ｄと金属膜７ｄからなる配線８
ｄがそれぞれ形成される。Next, in the step shown in FIG. 4E, the metal film 7 and the barrier film 6 on the second insulating film 4 and the third insulating film 9 are polished and removed by the CMP method. Further, the second insulating film 4 and the third insulating film 9 exposed by the CMP method are entirely polished by a predetermined thickness, for example, about 50 nm in thickness of the second insulating film 4, and the second insulating film 4 is polished. And the surface of the third insulating film 9 are flattened. Thus, the wiring 8a formed of the barrier film 6a and the metal film 7a in the groove 5a, the wiring 8b formed of the barrier film 6b and the metal film 7b in the groove 5b, and the groove 5
c, a wiring 8c composed of a barrier film 6c and a metal film 7c;
A wiring 8 composed of a barrier film 6d and a metal film 7d is provided in the groove 5d.
d are respectively formed.
【００５０】なお、上記第２の実施形態では、第３の絶
縁膜９としてシリコン酸化膜を用い、第２の絶縁膜４と
してシリコン窒化膜を用いて説明したが、第３の絶縁膜
９に対して第２の絶縁膜の研磨速度が遅ければ良い。例
えば、第３の絶縁膜９がＢＰＳＧ膜の場合、第２の絶縁
膜としてＢＰＳＧ膜よりも研磨速度の遅いＮＳＧ膜、ま
たは、シリコン窒化膜を用いれば良い。In the second embodiment, the silicon oxide film is used as the third insulating film 9 and the silicon nitride film is used as the second insulating film 4. On the other hand, it is sufficient that the polishing rate of the second insulating film is low. For example, when the third insulating film 9 is a BPSG film, an NSG film or a silicon nitride film having a lower polishing rate than the BPSG film may be used as the second insulating film.
【００５１】また、図４（ｅ）に示す工程では、第２の
絶縁膜４のうち一部厚み分だけ研磨除去したが、第２の
絶縁膜４の全厚み分を除去し、第２の絶縁膜４及び第３
の絶縁膜９を完全に除去してもよい。この場合の第２の
絶縁膜４の膜厚としては、ＣＭＰ法によって金属膜７及
びバリア膜６を研磨除去した際に第２の絶縁膜に生じた
凹みを、その後の全面研磨によって平坦化できる程度の
膜厚があればよく、例えば厚み５０ｎｍの第２の絶縁膜
４を形成しておけばよい。In the step shown in FIG. 4E, the second insulating film 4 is polished and removed by a part of the thickness. However, the entire thickness of the second insulating film 4 is removed and the second insulating film 4 is removed. Insulating film 4 and third
May be completely removed. In this case, the thickness of the second insulating film 4 can be reduced by polishing the metal film 7 and the barrier film 6 by the CMP method and flattening the recess formed in the second insulating film by subsequent overall polishing. It is sufficient that the second insulating film 4 has a thickness of about 50 nm, for example.
【００５２】この第２の実施形態の半導体装置及びその
製造方法によれば、複数の配線８ｂ、８ｃ、８ｄが密集
して形成される高密度配線領域１０には、研磨速度の遅
い第２の絶縁膜４が形成されている。そのため、ＣＭＰ
法により金属膜７及びバリア膜６を研磨除去した際に、
エロージョンによって生じる第２の絶縁膜４の凹みの深
さが低減される。さらに、露出した第２の絶縁膜４及び
第３の絶縁膜９をＣＭＰ法により全面研磨することによ
って、第３の絶縁膜９に比べて第２の絶縁膜４の方が研
磨速度が遅いため、エロージョンによって生じた第２の
絶縁膜４の凹みが解消され、第３の絶縁膜９の表面と第
２の絶縁膜４の表面とを平坦化することができる。According to the semiconductor device of the second embodiment and the method of manufacturing the same, the high-density wiring region 10 in which the plurality of wirings 8b, 8c and 8d are formed densely has the second polishing rate slower. An insulating film 4 is formed. Therefore, CMP
When the metal film 7 and the barrier film 6 are polished and removed by the method,
The depth of the depression of the second insulating film 4 caused by the erosion is reduced. Further, the entire surface of the exposed second insulating film 4 and the third insulating film 9 is polished by the CMP method, so that the polishing rate of the second insulating film 4 is lower than that of the third insulating film 9. In addition, the dent of the second insulating film 4 caused by the erosion is eliminated, and the surface of the third insulating film 9 and the surface of the second insulating film 4 can be flattened.
【００５３】なお、上記第１及び第２の実施形態では、
密集した複数の配線を有する半導体装置及びその製造方
法について説明したが、密集した複数のプラグを有する
半導体装置及びその製造方法にも適用することができ
る。この場合、溝５の変わりに下層の配線に到達する接
続孔を形成すればよい。In the first and second embodiments,
Although the semiconductor device having a plurality of densely arranged wirings and the method of manufacturing the same have been described, the present invention can also be applied to a semiconductor device having a plurality of densely arranged plugs and a method of manufacturing the same. In this case, a connection hole reaching the lower wiring may be formed instead of the groove 5.
【００５４】また、上記第１及び第２の実施形態では、
金属膜７として銅膜を用いて説明したが、タングステン
またはタングステン合金を主成分とするタングステン
膜、あるいは、アルミニウムまたはアルミニウム合金を
主成分とするアルミニウム膜などの金属材料を用いて良
い。また、バリア膜６としてＴａ／ＴａＮの積層膜を用
いて説明したが、金属膜７に対してバリア性があればよ
く、例えばＴａＮ単層、ＴｉＮ単層、Ｔｉ／ＴｉＮの積
層膜であってもよい。In the first and second embodiments,
Although the description has been made using the copper film as the metal film 7, a metal material such as a tungsten film mainly containing tungsten or a tungsten alloy, or an aluminum film mainly containing aluminum or an aluminum alloy may be used. In addition, although the description has been given using the Ta / TaN laminated film as the barrier film 6, it is sufficient that the metal film 7 has a barrier property. Is also good.
【００５５】[0055]
【発明の効果】以上述べてきたように、本発明の半導体
装置及びその製造方法によれば、複数の配線またはプラ
グが密集して形成される高密度配線領域には、配線が密
集して形成されない低密度配線領域に比べて研磨速度の
遅い絶縁膜を形成する。これによって、ＣＭＰ法におけ
るエロージョンを抑制することができ、複数の配線ある
いはプラグが密集して形成されている絶縁膜の表面が平
坦化されている半導体装置を形成することができる。As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, in the high-density wiring region where a plurality of wirings or plugs are densely formed, the wirings are densely formed. An insulating film having a lower polishing rate than a low-density wiring region not formed is formed. Thus, erosion in the CMP method can be suppressed, and a semiconductor device in which a surface of an insulating film in which a plurality of wirings or plugs are densely formed is planarized can be formed.
【図１】本発明の第１の実施形態に係る半導体装置の断
面図FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention;
【図２】（ａ）〜（ｅ）は、本発明の第１の実施形態に
係る半導体装置の製造工程を示す断面図FIGS. 2A to 2E are cross-sectional views illustrating manufacturing steps of the semiconductor device according to the first embodiment of the present invention;
【図３】本発明の第２の実施形態に係る半導体装置の断
面図FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention;
【図４】（ａ）〜（ｅ）は、本発明の第２の実施形態に
係る半導体装置の製造工程を示す断面図FIGS. 4A to 4E are cross-sectional views illustrating manufacturing steps of a semiconductor device according to a second embodiment of the present invention.
【図５】（ａ）〜（ｃ）は、従来の半導体装置の製造工
程を示す断面図FIGS. 5A to 5C are cross-sectional views showing a process for manufacturing a conventional semiconductor device.
１ 基板 ２ 第１の絶縁膜 ３ 凹部 ４ 第２の絶縁膜 ５、５ａ、５ｂ、５ｃ、５ｄ 溝 ６、６ａ、６ｂ、６ｃ、６ｄ バリア膜 ７、７ａ、７ｂ、７ｃ、７ｄ 金属膜 ８ａ、８ｂ、８ｃ、８ｄ 配線 ９ 第３の絶縁膜 １０ 高密度配線領域 １１ 低密度配線領域 Reference Signs List 1 substrate 2 first insulating film 3 concave portion 4 second insulating film 5, 5a, 5b, 5c, 5d groove 6, 6a, 6b, 6c, 6d barrier film 7, 7a, 7b, 7c, 7d metal film 8a, 8b, 8c, 8d Wiring 9 Third insulating film 10 High density wiring area 11 Low density wiring area
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5F033 HH08 HH09 HH11 HH12 HH18 HH19 HH21 HH32 HH33 MM12 MM13 QQ09 QQ10 QQ48 QQ49 RR04 RR06 XX01 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F033 HH08 HH09 HH11 HH12 HH18 HH19 HH21 HH32 HH33 MM12 MM13 QQ09 QQ10 QQ48 QQ49 RR04 RR06 XX01
Claims (14)
凹部と、 前記凹部内に埋め込まれた第２の絶縁膜と、 少なくとも前記第２の絶縁膜をエッチングして形成され
た複数の溝または接続孔と、 前記複数の溝または接続孔に埋め込まれた少なくとも金
属膜からなる複数の配線またはプラグとを備え、 前記第２の絶縁膜は、前記第１の絶縁膜に比べてＣＭＰ
法による研磨速度が遅く、ＣＭＰ法によって前記第１の
絶縁膜の表面と前記複数の配線またはプラグが形成され
た前記第２の絶縁膜の表面とが平坦化されていることを
特徴とする半導体装置。A first insulating film formed on a substrate; a concave portion formed by removing the first insulating film to a predetermined depth; and a second insulating film embedded in the concave portion. And at least a plurality of grooves or connection holes formed by etching the second insulating film; and a plurality of wirings or plugs made of at least a metal film embedded in the plurality of grooves or connection holes, The second insulating film has a higher CMP than the first insulating film.
A semiconductor, wherein a polishing rate by a polishing method is low, and a surface of the first insulating film and a surface of the second insulating film on which the plurality of wirings or plugs are formed are planarized by a CMP method. apparatus.
し、下地の前記第１の絶縁膜を所定の深さまでエッチン
グして設けられていることを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein the plurality of grooves or connection holes penetrate the second insulating film and are provided by etching the underlying first insulating film to a predetermined depth. A semiconductor device characterized in that:
いて、 前記金属膜が、銅または銅合金を主成分とする銅膜、あ
るいは、タングステンまたはタングステン合金を主成分
とするタングステン膜からなることを特徴とする半導体
装置。3. The semiconductor device according to claim 1, wherein the metal film is made of a copper film mainly containing copper or a copper alloy, or a tungsten film mainly containing tungsten or a tungsten alloy. Characteristic semiconductor device.
膜と、 前記第１の絶縁膜上の他部領域に前記第２の絶縁膜に接
して形成された第３の絶縁膜と、 少なくとも前記第２の絶縁膜をエッチングして形成され
た複数の溝または接続孔と、 前記複数の溝または接続孔に埋め込まれた少なくとも金
属膜からなる複数の配線またはプラグとを備え、 前記第２の絶縁膜は、前記第３の絶縁膜に比べてＣＭＰ
法による研磨速度が遅く、ＣＭＰ法によって前記第３の
絶縁膜の表面と前記複数の配線またはプラグが形成され
た前記第２の絶縁膜の表面とが平坦化されていることを
特徴とする半導体装置。4. A first insulating film formed on a substrate, a second insulating film formed in a partial region on the first insulating film, and another part on the first insulating film. A third insulating film formed in a region in contact with the second insulating film; a plurality of grooves or connection holes formed by etching at least the second insulating film; and the plurality of grooves or connection holes And a plurality of wirings or plugs made of at least a metal film embedded in the second insulating film, wherein the second insulating film has a higher CMP than the third insulating film.
A semiconductor, characterized in that the polishing rate by the method is low, and the surface of the third insulating film and the surface of the second insulating film on which the plurality of wirings or plugs are formed are planarized by a CMP method. apparatus.
し、下地の前記第１の絶縁膜を所定の深さまでエッチン
グして設けられていることを特徴とする半導体装置。5. The semiconductor device according to claim 4, wherein the plurality of grooves or connection holes penetrate the second insulating film and are provided by etching the underlying first insulating film to a predetermined depth. A semiconductor device characterized in that:
いて、 前記金属膜が、銅または銅合金を主成分とする銅膜、あ
るいは、タングステンまたはタングステン合金を主成分
とするタングステン膜からなることを特徴とする半導体
装置。6. The semiconductor device according to claim 4, wherein the metal film is made of a copper film mainly containing copper or a copper alloy, or a tungsten film mainly containing tungsten or a tungsten alloy. Characteristic semiconductor device.
（ａ）と、 前記第１の絶縁膜を所定の深さまで除去して凹部を形成
する工程（ｂ）と、 前記凹部を含む前記第１の絶縁膜上の全面に、前記第１
の絶縁膜よりもＣＭＰ法における研磨速度の遅い第２の
絶縁膜を形成する工程（ｃ）と、 前記第１の絶縁膜上の前記第２の絶縁膜をＣＭＰ法によ
って研磨除去して、前記凹部内のみに前記第２の絶縁膜
を残存させる工程（ｄ）と、 前記工程（ｄ）の後に、少なくとも前記第２の絶縁膜を
エッチングして複数の溝または接続孔を形成する工程
（ｅ）と、 前記工程（ｅ）の後に、前記基板上の全面に、少なくと
も金属膜を形成する工程（ｆ）と、 前記金属膜をＣＭＰ法によって研磨し、前記複数の溝ま
たは接続孔に前記金属膜を選択的に埋め込み、複数の配
線またはプラグを形成する工程（ｇ）と、 前記工程（ｇ）の後に、前記基板上の全面をＣＭＰ法に
よって研磨して、少なくとも前記第１及び第２の絶縁膜
の一部を除去する工程（ｈ）とを備えていることを特徴
とする半導体装置の製造方法。7. A step (a) of forming a first insulating film on a substrate, a step (b) of forming a concave by removing the first insulating film to a predetermined depth, and including the concave The first insulating film is formed on the entire surface of the first insulating film.
(C) forming a second insulating film having a lower polishing rate in the CMP method than the insulating film of (c), and polishing and removing the second insulating film on the first insulating film by a CMP method; (D) leaving the second insulating film only in the recess; and (e) etching at least the second insulating film to form a plurality of grooves or connection holes after the step (d). And (f) forming at least a metal film on the entire surface of the substrate after the step (e). Polishing the metal film by a CMP method to fill the plurality of grooves or connection holes with the metal. (G) selectively embedding a film to form a plurality of wirings or plugs; and, after the step (g), polishing the entire surface of the substrate by a CMP method to form at least the first and second layers. (H) removing a part of the insulating film; Method of manufacturing a semiconductor device characterized in that it comprises.
おいて、 前記工程（ｈ）では、前記第２の絶縁膜を全て除去する
ことを特徴とする半導体装置の製造方法。8. The method for manufacturing a semiconductor device according to claim 7, wherein in the step (h), the second insulating film is entirely removed.
造方法において、 前記工程（ｅ）において、前記複数の溝または接続孔
は、前記第２の絶縁膜を貫通し、下地の前記第１の絶縁
膜を所定の深さまでエッチングして形成することを特徴
とする半導体装置の製造方法。9. The method for manufacturing a semiconductor device according to claim 7, wherein, in the step (e), the plurality of grooves or connection holes penetrate the second insulating film, and the first underlayer is formed. And etching the insulating film to a predetermined depth.
載の半導体装置の製造方法において、 前記金属膜が、銅または銅合金を主成分とする銅膜、あ
るいは、タングステンまたはタングステン合金を主成分
とするタングステン膜からなることを特徴とする半導体
装置の製造方法。10. The method for manufacturing a semiconductor device according to claim 7, wherein the metal film is a copper film containing copper or a copper alloy as a main component, or tungsten or a tungsten alloy. A method for manufacturing a semiconductor device, comprising a tungsten film as a main component.
（ａ）と、 前記第１の絶縁膜上の一部領域に第２の絶縁膜を形成す
る工程（ｂ）と、 前記第１の絶縁膜上の他部領域に、前記第２の絶縁膜よ
りもＣＭＰ法における研磨速度の速い第３の絶縁膜を形
成する工程（ｃ）と、 前記工程（ｂ）及び（ｃ）の後に、少なくとも前記第２
の絶縁膜をエッチングして複数の溝または接続孔を形成
する工程（ｄ）と、 前記工程（ｄ）の後に、前記基板上の全面に、少なくと
も金属膜を形成する工程（ｅ）と、 前記金属膜をＣＭＰ法によって研磨し、前記複数の溝ま
たは接続孔に前記金属膜を選択的に埋め込み、複数の配
線またはプラグを形成する工程（ｆ）と、 前記工程（ｆ）の後に、前記基板上の全面をＣＭＰ法に
よって研磨して、少なくとも前記第２及び第３の絶縁膜
の一部を除去する工程（ｇ）とを備えていることを特徴
とする半導体装置の製造方法。11. A step (a) of forming a first insulating film on a substrate; a step (b) of forming a second insulating film in a partial region on the first insulating film; A step (c) of forming a third insulating film having a higher polishing rate in the CMP method than the second insulating film in the other region on the first insulating film, and the steps (b) and (c) Later, at least the second
(D) forming a plurality of grooves or connection holes by etching the insulating film, and (e) forming at least a metal film on the entire surface of the substrate after the step (d); (F) polishing the metal film by a CMP method, selectively embedding the metal film in the plurality of grooves or connection holes, and forming a plurality of wirings or plugs; and Polishing the entire upper surface by a CMP method to remove at least a part of the second and third insulating films (g).
法において、 前記工程（ｇ）では、前記第２の絶縁膜を全て除去する
ことを特徴とする半導体装置の製造方法。12. The method of manufacturing a semiconductor device according to claim 11, wherein in said step (g), said second insulating film is entirely removed.
置の製造方法において、 前記工程（ｄ）において、前記複数の溝または接続孔
は、前記第２の絶縁膜を貫通し、下地の前記第１の絶縁
膜を所定の深さまでエッチングして形成することを特徴
とする半導体装置の製造方法。13. The method for manufacturing a semiconductor device according to claim 11, wherein, in the step (d), the plurality of grooves or connection holes penetrate the second insulating film, and the first underlayer is formed. And etching the insulating film to a predetermined depth.
に記載の半導体装置の製造方法において、 前記金属膜が、銅または銅合金を主成分とする銅膜、あ
るいは、タングステンまたはタングステン合金を主成分
とするタングステン膜からなることを特徴とする半導体
装置の製造方法。14. The method for manufacturing a semiconductor device according to claim 11, wherein the metal film is a copper film containing copper or a copper alloy as a main component, or tungsten or a tungsten alloy. A method for manufacturing a semiconductor device, comprising a tungsten film as a main component.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005175152A (en) * | 2003-12-10 | 2005-06-30 | Fuji Electric Holdings Co Ltd | Semiconductor device and manufacturing method thereof |
| US7282451B2 (en) | 2005-08-31 | 2007-10-16 | Samsung Electronics Co., Ltd. | Methods of forming integrated circuit devices having metal interconnect layers therein |
-
2001
- 2001-04-05 JP JP2001106765A patent/JP4483116B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005175152A (en) * | 2003-12-10 | 2005-06-30 | Fuji Electric Holdings Co Ltd | Semiconductor device and manufacturing method thereof |
| JP4608880B2 (en) * | 2003-12-10 | 2011-01-12 | 富士電機システムズ株式会社 | Manufacturing method of semiconductor device |
| US7282451B2 (en) | 2005-08-31 | 2007-10-16 | Samsung Electronics Co., Ltd. | Methods of forming integrated circuit devices having metal interconnect layers therein |
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| Publication number | Publication date |
|---|---|
| JP4483116B2 (en) | 2010-06-16 |
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