JP2017126796A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve performance of a semiconductor device.SOLUTION: A semiconductor device has: an electrode 16 and a dummy electrode DE which are formed away from each other on a semiconductor substrate; an electrode 23 formed between the electrode 16 and the dummy electrode DE and on a peripheral side surface of the electrode 16 and on a peripheral side surface of the dummy electrode DE; and a capacitive insulation film 27 formed between the electrode 16 and the electrode 23. The electrode 16, electrode 23 and capacitive insulation film 27 form a capacitive element. The semiconductor device further has: a plug PG1 which pierces an interlayer insulation film 34 and is electrically connected with the electrode 16; and a plug PG2 which pierces the interlayer insulation film 34 to be electrically connected with a part formed on a side face of the dummy electrode DE out of the electrode 23 on the side opposite to the electrode 16 side.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor device, and can be suitably used for a semiconductor device having a capacitor, for example.

  Some semiconductor devices have a microcomputer formed on one semiconductor chip. A semiconductor chip on which the microcomputer is formed is formed with a central processing unit (CPU) including a logic circuit such as a CMISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor), a memory or an analog circuit.

  As the memory formed in the semiconductor chip, for example, an electrically rewritable nonvolatile memory is used. As an electrically writable / erasable nonvolatile memory (nonvolatile semiconductor memory device), an EEPROM (Electrically Erasable and Programmable Read Only Memory) and a flash memory are widely used.

  In order to operate the nonvolatile memory as described above, a drive circuit such as a booster circuit is formed in the semiconductor chip. This drive circuit requires a highly accurate capacitive element. In addition, an analog circuit is formed on the semiconductor chip on which the microcomputer is formed, and a high-accuracy capacitive element is required for this analog circuit. Therefore, a capacitor element is formed on the semiconductor chip in addition to the above-described nonvolatile memory and MISFET.

  As such a capacitive element, there is one that is formed at the same time as the nonvolatile memory cell by using a process for manufacturing the nonvolatile memory cell. Specifically, in the process of forming the control gate electrode of the nonvolatile memory cell, the lower electrode of the capacitor element is formed, and in the process of forming the laminated film including the charge storage film of the nonvolatile memory, the capacitor insulating film of the capacitor element Is formed. Then, the upper electrode of the capacitive element is formed in the step of forming the memory gate electrode of the nonvolatile memory cell. This capacitive element is called a PIP (Polysilicon Insulator Polysilicon) capacitive element because a polysilicon film is used for the upper electrode and the lower electrode.

  JP 2009-99640 A (Patent Document 1) and JP 2011-40621 A (Patent Document 2) describe a lower electrode and an upper electrode made of a polysilicon film formed on a semiconductor substrate, and a lower electrode. A PIP capacitive element having a capacitive insulating film made of, for example, a silicon oxide film formed between the electrode and the upper electrode is disclosed.

  In the above-mentioned Patent Document 1, the upper electrode has an overlapping region in which the lower electrode is present in the lower layer and a non-overlapping region in which the lower electrode is not present in the lower layer, and the plug connected to the upper electrode is not connected to the upper electrode. It is disclosed that they are formed in overlapping areas. Patent Document 2 discloses that a lower electrode, a capacitive film, and an upper electrode are stacked in this order, and a via is connected to the upper electrode on the lower electrode.

JP 2009-99640 A JP 2011-40621 A

  For example, in the PIP capacitor element described in Patent Document 1, the upper electrode has a step region between the overlapping region and the non-overlapping region, and the plug connected to the upper electrode is connected to the upper electrode in the non-overlapping region. The In addition, a metal silicide film is formed on the surface of the upper electrode. In this step region, a sidewall made of an insulating film is formed on the side wall of the upper electrode, and on the surface of the upper electrode in the step region. A metal silicide film is not formed. Therefore, the upper electrode in the step region has a high resistance, and the plug connected to the upper electrode in the non-overlapping region cannot be electrically connected to the portion of the upper electrode located in the overlapping region with a low resistance. And the upper electrode cannot be electrically connected with low resistance.

  On the other hand, for example, in the PIP capacitor element described in Patent Document 2, the plug connected to the upper electrode is connected to the upper electrode in the overlapping region. A metal silicide film is formed on the entire surface of the upper electrode. Therefore, the plug and the upper electrode can be electrically connected with low resistance.

  However, in such a PIP capacitive element, the thickness of the capacitive element is the sum of the thickness of the upper electrode, the thickness of the capacitive insulating film, and the thickness of the lower electrode. Therefore, the height position of the upper surface of the capacitive element is higher than the height position of the upper surface of the source region or the drain region in the nonvolatile memory cell, for example. That is, the distance in the thickness direction from the lower surface of the wiring on the capacitive element to the upper surface of the upper electrode of the capacitive element is the distance in the thickness direction from the lower surface of the wiring on the nonvolatile memory cell to the upper surface of the source region or drain region. Shorter than

  Therefore, when forming a contact hole that penetrates the interlayer insulating film and reaches the source electrode or the drain electrode and a contact hole that penetrates the interlayer insulating film and reaches the upper surface of the upper electrode of the capacitive element, the contact hole is formed. A hole may penetrate the interlayer insulating film, the upper electrode, and the capacitor insulating film to reach the lower electrode. In such a case, the upper electrode and the lower electrode may be short-circuited by the plug made of the conductive film embedded in the contact hole, which degrades the performance of the semiconductor device.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a semiconductor device includes a first electrode and a dummy electrode formed on a semiconductor substrate and spaced apart from each other, a first electrode and a dummy electrode, a peripheral side surface of the first electrode, and a first electrode A second electrode formed on the peripheral side surface of the first dummy electrode; and a capacitive insulating film formed between the first electrode and the second electrode. A capacitor element is formed by the first electrode, the second electrode, and the capacitor insulating film. The semiconductor device also includes a first plug that penetrates the interlayer insulating film and is electrically connected to the first electrode, and a first electrode side of the dummy electrode of the second electrode that penetrates the interlayer insulating film. It has the part formed in the opposite side surface, and the 2nd plug electrically connected.

  According to another embodiment, a semiconductor device includes a first electrode formed on a semiconductor substrate, an opening that penetrates the first electrode, an inside of the opening, and a peripheral side surface of the first electrode. A second electrode formed between the first electrode and the second electrode, and a capacitor insulating film formed between the first electrode and the second electrode. A capacitor element is formed by the first electrode, the second electrode, and the capacitor insulating film. Further, the semiconductor device includes a first plug that penetrates the interlayer insulating film and is electrically connected to the first electrode, and a second plug that penetrates the interlayer insulating film and is electrically connected to the second electrode. Have

  Furthermore, according to another embodiment, a semiconductor device includes a first electrode formed on a semiconductor substrate, a second electrode formed on a peripheral side surface of the first electrode, a first electrode, a second electrode, And a capacitor insulating film formed between the two. The first electrode includes a plurality of line portions extending in the first direction and arranged in a second direction intersecting the first direction in plan view, and capacitively insulated from the first electrode and the second electrode. A capacitive element is formed by the film. Further, the semiconductor device includes a first plug that penetrates the interlayer insulating film and is electrically connected to the first electrode, and a second plug that penetrates the interlayer insulating film and is electrically connected to the second electrode. Have

  According to one embodiment, the performance of a semiconductor device can be improved.

1 is a plan view showing a semiconductor chip as a semiconductor device according to a first embodiment. 4 is a plan view showing a capacitor element in Embodiment 1. FIG. 4 is a cross-sectional view illustrating a capacitor element in Embodiment 1. FIG. FIG. 9 is a plan view showing a capacitive element in a first modification example of the first embodiment. FIG. 6 is a cross-sectional view showing a capacitive element in a first modification of the first embodiment. It is sectional drawing which shows the capacitive element in another example. FIG. 10 is a plan view showing a capacitive element in a second modification example of the first embodiment. FIG. 10 is a cross-sectional view showing a capacitive element in a second modification of the first embodiment. FIG. 10 is a cross-sectional view showing a capacitive element in a second modification of the first embodiment. FIG. 10 is a plan view showing a capacitive element in a third modification of the first embodiment. FIG. 11 is a cross-sectional view showing a capacitive element in a third modification of the first embodiment. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. FIG. 10 is a cross sectional view of the semiconductor device during a manufacturing step in First Embodiment; FIG. 10 is a cross sectional view of the semiconductor device during a manufacturing step in First Embodiment; FIG. 10 is a cross sectional view of the semiconductor device during a manufacturing step in First Embodiment; FIG. 10 is a cross sectional view of the semiconductor device during a manufacturing step in First Embodiment; FIG. 10 is a cross sectional view of the semiconductor device during a manufacturing step in First Embodiment; FIG. 10 is a cross sectional view of the semiconductor device during a manufacturing step in First Embodiment; FIG. 10 is a cross sectional view of the semiconductor device during a manufacturing step in First Embodiment; FIG. 10 is a cross sectional view of the semiconductor device during a manufacturing step in First Embodiment; FIG. 10 is a cross sectional view of the semiconductor device during a manufacturing step in First Embodiment; FIG. 10 is a cross sectional view of the semiconductor device during a manufacturing step in First Embodiment; FIG. 10 is a cross sectional view of the semiconductor device during a manufacturing step in First Embodiment; FIG. 10 is a cross sectional view of the semiconductor device during a manufacturing step in First Embodiment; FIG. 10 is a cross sectional view of the semiconductor device during a manufacturing step in First Embodiment; FIG. 10 is a cross sectional view of the semiconductor device during a manufacturing step in First Embodiment; FIG. 10 is a cross sectional view of the semiconductor device during a manufacturing step in First Embodiment; FIG. 10 is a cross sectional view of the semiconductor device during a manufacturing step in First Embodiment; FIG. 10 is a cross sectional view of the semiconductor device during a manufacturing step in First Embodiment; FIG. 10 is a cross sectional view of the semiconductor device during a manufacturing step in First Embodiment; 7 is a cross-sectional view showing a semiconductor device of Comparative Example 1. FIG. 10 is a cross-sectional view showing a semiconductor device of Comparative Example 2. FIG. FIG. 6 is a plan view showing a capacitive element in a second embodiment. FIG. 6 is a cross-sectional view illustrating a capacitor element in a second embodiment. FIG. 10 is a plan view showing a capacitive element in a first modification example of the second embodiment. FIG. 10 is a cross-sectional view showing a capacitive element in a first modification example of the second embodiment. It is a top view which shows the capacitive element in another example. It is sectional drawing which shows the capacitive element in another example. It is sectional drawing which shows the capacitive element in another example. FIG. 10 is a plan view showing a capacitive element in a second modification example of the second embodiment. FIG. 10 is a cross-sectional view showing a capacitive element in a second modification example of the second embodiment. FIG. 10 is a plan view showing a capacitor element in a third embodiment. FIG. 25 is a plan view showing a capacitive element in a first modification example of the third embodiment. FIG. 25 is a plan view showing a capacitive element in a second modification example of the third embodiment. FIG. 10 is a cross-sectional view showing a capacitive element in a second modification example of the third embodiment. FIG. 10 is a cross-sectional view of a capacitive element in a fourth embodiment.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, typical embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view for easy viewing of the drawings. Further, even a plan view may be hatched to make the drawing easy to see.

  In the cross-sectional view and the plan view, the size of each part does not correspond to the actual device, and a specific part may be displayed relatively large for easy understanding of the drawing. Even when the plan view and the cross-sectional view correspond to each other, the size of each part may be changed and displayed.

(Embodiment 1)
<Configuration of semiconductor device>
FIG. 1 is a plan view showing a semiconductor chip as a semiconductor device according to the first embodiment. FIG. 1 shows a layout configuration of each element formed in a semiconductor chip CHP as a semiconductor device in which a microcomputer is formed, for example.

  In FIG. 1, a semiconductor chip CHP as a semiconductor device includes a CPU 1, a RAM (Random Access Memory) 2, an analog circuit 3, and a flash memory 4. A pad PD, which is an input / output external terminal for connecting these circuits and external circuits, is formed in the periphery of the semiconductor chip.

  The CPU 1 is also called a central processing unit and is the heart of a computer or the like. The CPU 1 reads and decodes instructions from the storage device, and performs a variety of calculations and controls based on the instructions, and requires high processing speed. Therefore, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) constituting the CPU 1 requires a relatively large current driving force among elements formed on the semiconductor chip CHP. That is, the MISFET constituting the CPU 1 is formed of a low withstand voltage MISFET.

  The RAM 2 is a memory that can read stored information at random, that is, read stored information at any time, or write new stored information, and is also called a memory that can be written and read at any time. There are two types of RAM as IC (Integrated Circuit) memory: DRAM (Dynamic RAM) using a dynamic circuit and SRAM (Static RAM) using a static circuit. DRAM is an occasional writing / reading memory that requires a memory holding operation, and SRAM is an occasional writing / reading memory that does not require a memory holding operation. Since these RAMs 2 are required to have high-speed operation, the MISFET constituting the RAM 2 requires a relatively large current driving force among the elements formed on the semiconductor chip CHP. That is, a low breakdown voltage MISFET is used as the MISFET constituting the RAM 2.

  The analog circuit 3 is a circuit that handles a voltage or current signal that changes continuously in time, that is, an analog signal, and includes, for example, an amplifier circuit, a conversion circuit, a modulation circuit, an oscillation circuit, or a power supply circuit. As the MISFET constituting the analog circuit 3, a MISFET having a relatively high breakdown voltage is used among the elements formed in the semiconductor chip CHP.

  The flash memory 4 is a kind of non-volatile memory that can be electrically rewritten in both writing and erasing operations, and is also referred to as an electrically erasable programmable read-only memory. The memory cell of the flash memory 4 includes a MISFET for selecting a memory cell and a MONOS (Metal Oxide Nitride Oxide Semiconductor) type FET (Field Effect Transistor) for storage. For example, hot electron injection or Fowler-Nordheim tunneling is used for the writing operation of the flash memory, and Fowler-Nordheim tunneling or hot hole injection is used for the erasing operation.

  In order to operate the flash memory 4 as described above, a drive circuit such as a booster circuit is formed in the semiconductor chip CHP. This drive circuit requires a highly accurate capacitive element. The analog circuit 3 described above also requires a highly accurate capacitive element. Therefore, in addition to the memory cell and MISFET of the flash memory 4 described above, a capacitor element is also formed in the semiconductor chip CHP. The first embodiment has one feature in the structure of a capacitive element as a PIP capacitive element formed in the semiconductor chip CHP. Hereinafter, a configuration of a capacitive element as a PIP capacitive element formed in the semiconductor chip CHP will be described. Hereinafter, the PIP capacitive element is simply referred to as a capacitive element.

<Configuration of capacitive element>
FIG. 2 is a plan view showing the capacitive element in the first embodiment, and FIG. 3 is a cross-sectional view showing the capacitive element in the first embodiment. 3 is a cross-sectional view taken along line AA in FIG.

  2 is a perspective plan view of the capacitive element in a state where the wirings HL1 and HL2, the interlayer insulating film 34, and the side wall 29b (see FIG. 3) are seen through, and the semiconductor substrate 10 and the element isolation region. 11 is also omitted (the same applies to the following plan views). Further, in the plan view of FIG. 2, for the sake of easy understanding, the portions other than the electrode 23 are hatched, but the electrode 23 is not hatched (the same applies to the following plan views). ).

  As shown in FIGS. 2 and 3, the semiconductor device has a semiconductor substrate 10 and an element isolation region 11. The element isolation region 11 is formed on the surface (first main surface) 10 a of the semiconductor substrate 10. The semiconductor substrate 10 is made of, for example, silicon (Si) single crystal, and the element isolation region 11 is made of, for example, a silicon oxide film.

  The semiconductor device has an electrode 16 made of a conductive film CF <b> 1 formed on the element isolation region 11. Preferably, the electrode 16 includes a conductive film CF1 formed on the element isolation region 11 and a metal silicide film 33 formed on the surface of the conductive film CF1. The conductive film CF1 is made of, for example, a polysilicon film, and the metal silicide film 33 is made of, for example, a cobalt silicide film. As shown in FIG. 3, the electrode 16 may be formed on the element isolation region 11 via an insulating film IF1.

  As shown in FIG. 2, the electrode 16 includes a plurality of line portions LP1 and line portions LP2. The plurality of line portions LP1 extend in the Y-axis direction and are arranged in the X-axis direction when two directions intersecting with each other are taken as an X-axis direction and a Y-axis direction in plan view. The line portion LP2 extends in the X-axis direction in a plan view, and is connected to the end portions on one side of the plurality of line portions LP1 in the Y-axis direction. With such a configuration, the plurality of line portions LP1 are electrically connected to each other via the line portion LP2, and the electrode 16 including the plurality of line portions LP1 and the line portion LP2 has a comb-like shape in plan view. Has a shape.

  In the specification of the present application, in a plan view, the term “viewed from a direction perpendicular to the surface 10 a of the semiconductor substrate 10” is meant.

  Further, the semiconductor device has a dummy electrode DE made of the conductive film CF1 formed on the element isolation region 11 apart from the electrode 16. Preferably, the dummy electrode DE includes a conductive film CF1 in the same layer as the conductive film CF1 constituting the electrode 16, and a metal silicide film 33 formed on the surface of the conductive film CF1. As described above, the conductive film CF1 is made of, for example, a polysilicon film, and the metal silicide film 33 is made of, for example, a cobalt silicide film. Further, as shown in FIG. 3, the dummy electrode DE may be formed on the element isolation region 11 via an insulating film IF1.

  As shown in FIG. 2, the dummy electrode DE extends in the X-axis direction in a plan view and is opposite to the line part LP2 across the plurality of line parts LP1, that is, the plurality of line parts LP1. It arrange | positions on the opposite side to the line part LP2 side. In other words, the dummy electrode DE is disposed on one side in the X-axis direction of the plurality of line portions LP1, and the line portion LP2 is connected to the other end portion in the X-axis direction of the plurality of line portions LP1. ing.

  The semiconductor device also includes an electrode 23 made of the conductive film CF2 formed integrally between the electrode 16 and the dummy electrode DE, on the peripheral side surface of the electrode 16, and on the peripheral side surface of the dummy electrode DE. Preferably, the electrode 23 is formed between the electrode 16 and the dummy electrode DE, on the peripheral side surface of the electrode 16 and on the peripheral side surface of the dummy electrode DE, and on the surface of the conductive film CF2. The metal silicide film 33 is formed. The conductive film CF2 is made of, for example, a polysilicon film, and the metal silicide film 33 is made of, for example, a cobalt silicide film.

  Further, the semiconductor device has a capacitive insulating film 27 made of an insulating film IF2 formed between the electrode 16 and the electrode 23 and between the electrode 23 and the semiconductor substrate 10. Therefore, the electrode 23 is formed on the peripheral side surface of the electrode 16 and the peripheral side surface of the dummy electrode DE via the capacitive insulating film 27. A capacitor element is formed by the electrode 16, the electrode 23, and the capacitor insulating film 27. Note that a sidewall 29 b made of an insulating film is formed on the peripheral side surface of the electrode 23 in the outer peripheral portion of the capacitive element. The metal silicide film 33 is formed on the entire surface of the electrode 23 except for the region where the sidewall 29b is formed.

  As shown in FIG. 3, an interlayer insulating film 34 is formed on the element isolation region 11 so as to cover the capacitive element formed by the electrode 16, the electrode 23, and the capacitive insulating film 27. In the interlayer insulating film 34, contact holes CH1 and contact holes CH2 are formed as connection holes. The contact hole CH1 penetrates the interlayer insulating film 34 and reaches the electrode 16. The contact hole CH2 passes through the interlayer insulating film 34 and reaches the electrode 23.

  In the contact hole CH1, a plug PG1 is formed as a connection electrode made of a conductive film embedded in the contact hole CH1 and electrically connected to the electrode 16. The contact hole CH2 is formed with a plug PG2 as a connection electrode made of a conductive film embedded in the contact hole CH2 and electrically connected to the electrode 23. A wiring HL1 electrically connected to the plug PG1 is formed on the plug PG1, and a wiring HL2 electrically connected to the plug PG2 is formed on the plug PG2. Since the metal silicide film 33 is formed on the surface of the electrode 16, the plug PG1 is electrically connected to the electrode 16 by being in contact with the metal silicide film 33 exposed at the bottom of the contact hole CH1. Further, since the metal silicide film 33 is formed on the surface of the electrode 23, the plug PG2 is electrically connected to the electrode 23 by contacting the metal silicide film 33 exposed at the bottom of the contact hole CH2. The

  The contact hole CH1 penetrates the interlayer insulating film 34 and reaches the line portion LP2 of the electrode 16. The plug PG1 is made of a conductive film embedded in the contact hole CH1, and is electrically connected directly to the line portion LP2 of the electrode 16.

  The contact hole CH2 penetrates the interlayer insulating film 34 and reaches a portion of the electrode 23 formed on the side surface opposite to the electrode 16 side of the dummy electrode DE. With such a configuration, the plug PG2 can be electrically connected to any part of the electrode 23 via the metal silicide film 33 formed on the surface of the electrode 23 and having a relatively small electrical resistance. A metal silicide film 33 is formed on the entire surface of the electrode 23. Therefore, the plug PG2 can be electrically connected to any part of the electrode 23 with a low resistance.

  Moreover, the electrode 16 and the electrode 23 are formed in different regions in plan view. That is, there is no overlapping region where the electrode 16 and the electrode 23 overlap in plan view. With such a configuration, there is no possibility that the contact hole CH2 penetrates the electrode 23 and reaches the electrode 16, and it is possible to prevent the electrode 16 and the electrode 23 from being electrically short-circuited through the plug PG2.

  Further, since the electrode 16 has the plurality of line portions LP1, the area of the side surface of the electrode 23 facing the side surface of the electrode 16 is increased, so that the capacitance of the capacitive element can be easily increased.

  On the other hand, as shown in FIG. 3, since the dummy electrode DE is electrically insulated from the electrode 16, the contact hole CH2 may reach the dummy electrode DE. That is, the contact hole CH2 may have a portion that overlaps the dummy electrode DE in plan view. Thereby, even when the film thickness of the conductive film CF2 constituting the electrode 23 is small and the width of the electrode 23 formed on the side surface of the electrode 16 is small, the contact hole CH2 may be shifted to the dummy electrode DE side. The hole CH2 can be easily aligned.

<First Modification of Capacitance Element>
FIG. 4 is a plan view showing a capacitive element in the first modification of the first embodiment, and FIG. 5 is a cross-sectional view showing the capacitive element in the first modification of the first embodiment. FIG. 5 is a cross-sectional view taken along line AA in FIG.

  The capacitive element in the first modified example is not provided with the line portion LP2 (see FIG. 2), and the plurality of plugs PG1 are electrically directly connected to each of the plurality of line portions LP1, In addition to the plug PG2, a plurality of plugs PG3 are electrically connected directly to the electrode 23, which is different from the capacitive element in the first embodiment described with reference to FIGS. Other points are the same as those of the capacitor in the first embodiment.

  As shown in FIG. 4, the electrode 16 includes a plurality of line portions LP1, but does not include the line portions LP2. Similarly to the first embodiment, the plurality of line portions LP1 extend in the Y-axis direction and are arranged in the X-axis direction in plan view. Therefore, the plurality of line portions LP1 are formed apart from each other.

  The contact hole CH1 passes through the interlayer insulating film 34 and reaches the line portion LP1 of the electrode 16. The plug PG1 is made of a conductive film embedded in the contact hole CH1, and is electrically connected directly to the line portion LP1 of the electrode 16.

  In the interlayer insulating film 34, in addition to the contact holes CH1 and CH2, a contact hole CH3 as an opening is formed. The contact hole CH3 penetrates the interlayer insulating film 34 and reaches a portion of the electrode 23 located between the adjacent line portions LP1. The contact hole CH3 is formed of a conductive film embedded in the contact hole CH3, and a plug PG3 is formed as a connection electrode electrically connected to a portion of the electrode 23 located between adjacent line portions LP1. Yes. A wiring HL3 electrically connected to the plug PG3 is formed on the plug PG3.

  Also in the first modification, the plug PG2 can be electrically connected to any part of the electrode 23 with a low resistance, and the electrode 16 and the electrode 23 are electrically short-circuited, as in the first embodiment. Can be prevented, the capacitance of the capacitive element can be easily increased, and the contact hole CH2 can be easily aligned.

  On the other hand, in the first modification, the width of the line portion LP1 in the X-axis direction is larger than that of the first embodiment, but the plug PG1 can be electrically connected directly to the line portion LP1, so the plug PG1 Can be electrically connected to the electrode 16 with a lower resistance.

  Note that a cross-sectional view of FIG. 6 shows a capacitor element in still another example. As shown in FIG. 6, when the conductive film CF1 is patterned to form the line portion LP1, the opening OP1 formed between the adjacent line portions LP1 is prevented from penetrating the conductive film CF1, and a plurality of lines are formed. The bottoms of the parts LP1 can be connected to each other through the conductive film CF1. That is, the electrode 16 includes a connection portion CN1 that connects the bottom portions of the adjacent line portions LP1.

  In the example shown in FIG. 6, when the height position of the upper surface of the electrode 23 is made equal to the example shown in FIG. 5, the height position of the lower surface of the electrode 23 increases and the thickness of the electrode 23 decreases. However, since the line portions LP1 are connected at the bottom, the electrical resistance of the electrode 16 can be reduced. However, since it is preferable that the electrode 16 and the dummy electrode DE are electrically insulated from each other, the bottom portions of the adjacent line portions LP1 may be connected to each other, but the bottom portion of the electrode 16 and the bottom portion of the dummy electrode DE Are preferably not connected to each other.

  In addition to the first modification of the first embodiment, the first embodiment described above also prevents the opening OP1 from penetrating the conductive film CF1 when patterning the conductive film CF1. In addition, the present invention can be applied to each embodiment and each modification of the embodiment.

<Second Modification of Capacitance Element>
FIG. 7 is a plan view showing a capacitive element in the second modification of the first embodiment, and FIGS. 8 and 9 are cross-sectional views showing the capacitive element in the second modification of the first embodiment. 8 is a cross-sectional view taken along line AA in FIG. 7, and FIG. 9 is a cross-sectional view taken along line BB in FIG.

  In the capacitive element of the second modified example, the electrode 23 is not only between the electrode 16 and the dummy electrode DE, the peripheral side surface of the electrode 16 and the peripheral side surface of the dummy electrode DE, but also a part of the upper surface of the electrode 16. It differs from the capacitor of the first embodiment described with reference to FIGS. 2 and 3 in that it is also formed in the region. Other points are the same as those of the capacitor in the first embodiment.

  As shown in FIG. 7, the electrode 16 does not include a line portion, has a rectangular shape in plan view, and is integrally formed. In the second modification, the dummy electrode DE extends in the Y-axis direction and is formed away from the electrode 16 in the X-axis direction.

  The electrode 23 is also formed between the electrode 16 and the dummy electrode DE, the peripheral side surface of the electrode 16, the peripheral side surface of the dummy electrode DE, and a part of the upper surface of the electrode 16. Moreover, the electrode 23 may be formed integrally. Further, a side wall 29c made of an insulating film is formed on the side surface of the portion of the electrode 23 formed on the upper surface of the electrode 16. FIG. 7 shows a state seen through the side wall 29c.

  The metal silicide film 33 is formed in a region where neither the electrode 23 nor the sidewall 29 c is formed on the upper surface of the electrode 16. Further, the contact hole CH1 penetrates through the interlayer insulating film 34 and reaches a region of the upper surface of the electrode 16 where neither the electrode 23 nor the sidewall 29c is formed. The plug PG1 is made of a conductive film embedded in the contact hole CH1, and is directly electrically connected to the electrode 16. Contact hole CH2 and plug PG2 are the same as in the first embodiment.

  Also in the second modification, as in the first embodiment, the plug PG2 can be electrically connected to any part of the electrode 23 with a low resistance, and the electrode 16 and the electrode 23 are electrically short-circuited. And the contact hole CH2 can be easily aligned.

  On the other hand, in the second modification, the area of the side surface of the electrode 23 facing the side surface of the electrode 16 may be smaller than that in the first embodiment, but the upper surface of the electrode 16 and the lower surface of the electrode 23 are opposed. Therefore, the capacity of the capacitive element can be easily increased.

<Third Modification of Capacitance Element>
FIG. 10 is a plan view showing the capacitive element in the third modification of the first embodiment, and FIG. 11 is a cross-sectional view showing the capacitive element in the third modification of the first embodiment. 11 is a cross-sectional view taken along line AA in FIG.

  The capacitive element according to the third modification is that the cap insulating film CP1 is formed in a partial region of the upper surface of the electrode 16, and the semiconductor device according to the first embodiment described with reference to FIGS. And different. Other points are the same as those of the capacitor in the first embodiment.

  As shown in FIG. 10 and FIG. 11, on the line portion LP1 and on a part of the line portion LP2, that is, on a part of the electrode 16, at least in a plan view, through a capacitive insulating film 27. A cap insulating film CP <b> 1 is formed in a region in contact with the electrode 23. The cap insulating film CP1 is made of an insulating film IF3 such as a silicon nitride film.

  Note that the metal silicide film 33 is not formed in the region where the cap insulating film CP1 is formed in the upper surface of the line portion LP1. On the other hand, in the region near the plug PG1 in the upper surface of the line portion LP2 and the upper surface of the dummy electrode DE, the metal silicide film 33 is formed, but the cap insulating film CP1 is not formed.

  Also in the third modification, the plug PG2 can be electrically connected to any part of the electrode 23 with a low resistance similarly to the first embodiment, and the electrode 16 and the electrode 23 are electrically connected by the plug PG2. Short circuit can be prevented, the capacity of the capacitor can be easily increased, and the contact hole CH2 can be easily aligned.

  On the other hand, in the third modification, a region of the electrode 16 that is in contact with the electrode 23 via the capacitive insulating film 27 in plan view is covered with the cap insulating film CP1. Therefore, in the third modification, it is possible to more reliably prevent the adjacent electrode 16 and the electrode 23 from being electrically short-circuited as compared with the first embodiment.

<Configuration of memory cell>
Next, a memory cell of the flash memory 4 (see FIG. 1) formed in the semiconductor chip CHP (see FIG. 1), and a capacitor element used in the analog circuit 3 (see FIG. 1) and the drive circuit of the flash memory 4 Will be described with reference to FIG.

  12 and 13 are cross-sectional views showing the semiconductor device of the first embodiment. 12 is a cross-sectional view showing the structure of a memory cell of a flash memory and the structure of a capacitor element formed in an analog circuit or the like. FIG. 13 is an enlarged view of the periphery of the insulating film 27a in the memory cell. It is sectional drawing.

  As shown in FIG. 12, the memory cell is formed in the memory cell formation area AR1 of the semiconductor chip, and the capacitive element is formed in the capacitive element formation area AR2 of the semiconductor chip. In other words, the semiconductor device includes a memory cell formed in the memory cell region AR1 and a capacitor element formed in the capacitor element formation region AR2.

  First, the structure of the memory cell of the flash memory will be described. The semiconductor device includes a p-type well 12, a gate insulating film 13, a control gate electrode 15, a memory gate electrode 26, an insulating film 27a as a gate insulating film, and a low concentration impurity diffusion region as a source region and a drain region. 28 and a high-concentration impurity diffusion region 30. The gate insulating film 13, the control gate electrode 15, the insulating film 27a, and the memory gate electrode 26 form a memory cell.

  As shown in FIG. 12, in the memory cell formation region AR <b> 1, a p-type well 12 is formed on the semiconductor substrate 10, and a memory cell is formed on the p-type well 12. The memory cell includes a selection unit that selects a memory cell and a storage unit that stores information.

  First, the configuration of a selection unit that selects a memory cell will be described. The memory cell has a gate insulating film 13 formed on the semiconductor substrate 10, that is, the p-type well 12, and a control gate electrode 15 is formed on the gate insulating film 13. The gate insulating film 13 is made of an insulating film IF1 in the same layer as the insulating film IF1 between the electrode 16 and the semiconductor substrate 10, such as a silicon oxide film. The control gate electrode 15 includes a conductive film CF1 such as a polysilicon film and a metal silicide film 33 such as a cobalt silicide film formed on the surface of the conductive film CF1. That is, the control gate electrode 15 is composed of the conductive film CF1 in the same layer as the conductive film CF1 constituting the electrode 16. The metal silicide film 33 is formed to reduce the resistance of the control gate electrode 15. The control gate electrode 15 has a function of selecting a memory cell. That is, a specific memory cell is selected by the control gate electrode 15, and a write operation, an erase operation, or a read operation is performed on the selected memory cell.

  Next, the configuration of the storage unit of the memory cell will be described. A memory gate electrode 26 is formed on one side surface of the control gate electrode 15 via an insulating film 27a. The memory gate electrode 26 has a sidewall-like shape formed on one side surface of the control gate electrode 15, and for example, a conductive film CF2 such as a polysilicon film and a cobalt silicide formed on the surface of the conductive film CF2. And a metal silicide film 33 such as a film. That is, the memory gate electrode 26 is composed of the conductive film CF2 in the same layer as the conductive film CF2 constituting the electrode 23. The metal silicide film 33 is formed to reduce the resistance of the memory gate electrode 26.

  An insulating film 27 a as a gate insulating film is formed between the control gate electrode 15 and the memory gate electrode 26 and between the memory gate electrode 26 and the semiconductor substrate 10. The insulating film 27a is made of the same insulating film IF2 as the insulating film IF2 constituting the capacitive insulating film 27. As shown in FIG. 13, the insulating film IF2 constituting the insulating film 27a includes a silicon oxide film 17 formed on the semiconductor substrate 10 and a charge storage film 25 (silicon nitride film) formed on the silicon oxide film 17. A film 18) and a silicon oxide film 19 formed on the charge storage film 25 are formed. The silicon oxide film 17 functions as a gate insulating film formed between the memory gate electrode 26 and the semiconductor substrate 10. The gate insulating film made of the silicon oxide film 17 also has a function as a tunnel insulating film. For example, the memory portion of the memory cell stores and erases information by injecting electrons from the semiconductor substrate 10 through the silicon oxide film 17 into the charge storage film 25 or injecting holes into the charge storage film 25. Therefore, the silicon oxide film 17 functions as a tunnel insulating film.

  The charge storage film 25 formed on the silicon oxide film 17 has a function of storing charges. Specifically, in the first embodiment, the charge storage film 25 is formed of the silicon nitride film 18. The memory unit of the memory cell according to the first embodiment controls the current flowing in the semiconductor substrate 10 under the memory gate electrode 26, that is, in the p-type well 12, depending on the presence / absence of charges stored in the charge storage film 25. Thus, information is stored. That is, information is stored by utilizing the fact that the threshold voltage of the current flowing in the semiconductor substrate 10 under the memory gate electrode 26 changes depending on the presence or absence of charges accumulated in the charge storage film 25.

  In the first embodiment, an insulating film having a trap level is used as the charge storage film 25. As an example of the insulating film having the trap level, the silicon nitride film 18 can be given, but not limited to the silicon nitride film, for example, an aluminum oxide film (alumina) may be used. When an insulating film having a trap level is used as the charge storage film 25, charges are trapped in the trap level formed in the insulating film. Thus, charges are accumulated in the insulating film by trapping the charges at the trap level.

  A memory gate electrode 26 is formed on one side wall, that is, one side surface of both side walls of the control gate electrode 15, but a side wall 29a made of a silicon oxide film is formed on the other side wall, that is, the other side surface. Is formed. Similarly, a control gate electrode 15 is formed on one side wall, that is, one side surface of both side walls of the memory gate electrode 26, and a side wall made of a silicon oxide film is formed on the other side wall, that is, the other side surface. 29a is formed.

  A pair of shallow low-concentration impurity diffusion regions 28, which are n-type semiconductor regions, are formed in the semiconductor substrate 10 immediately below the sidewall 29a, and an outer region in contact with the pair of shallow low-concentration impurity diffusion regions 28. A pair of deep high-concentration impurity diffusion regions 30 are formed. This deep high-concentration impurity diffusion region 30 is also an n-type semiconductor region, and a metal silicide film 33 made of, for example, a cobalt silicide film is formed on the surface of the high-concentration impurity diffusion region 30. The pair of low-concentration impurity diffusion regions 28 and the pair of high-concentration impurity diffusion regions 30 form a source region or drain region of the memory cell. By forming the source region and the drain region with the low-concentration impurity diffusion region 28 and the high-concentration impurity diffusion region 30, the source region and the drain region can have an LDD (Lightly Doped Drain) structure.

  One of the source region and the drain region is formed in alignment with the control gate electrode 15, and the other is formed in alignment with the memory gate electrode 26.

  Here, the transistor including the gate insulating film 13, the control gate electrode 15, and the above-described source region and drain region is referred to as a selection transistor. On the other hand, the transistor including the insulating film 27a, the memory gate electrode 26, and the above-described source region and drain region is referred to as a memory transistor. Thereby, it can be said that the selection part of a memory cell is comprised from the selection transistor, and the memory | storage part of the memory cell is comprised from the memory transistor. In this way, a memory cell is configured.

  Next, a wiring structure connected to the memory cell will be described. An interlayer insulating film 34 made of a silicon oxide film is formed on the memory cell so as to cover the memory cell. In this interlayer insulating film 34, a contact hole CH 4 is formed which penetrates the interlayer insulating film 34 and reaches the metal silicide film 33 formed on the surface of the high concentration impurity diffusion region 30 constituting the source region and the drain region. Yes. A conductive film is embedded in the contact hole CH4. As this conductive film, a titanium / titanium nitride film as a barrier conductor film is first formed, and then a tungsten film is formed so as to fill the contact hole CH4. Thus, by embedding the titanium / titanium nitride film and the tungsten film in the contact hole CH4, the plug PG4 made of the conductive film embedded in the contact hole CH4 and electrically connected to the source region or the drain region is formed. ing. A wiring HL4 is formed on the interlayer insulating film 34, and the wiring HL4 and the plug PG4 are electrically connected. The wiring HL4 is made of, for example, a laminated film of a titanium / titanium nitride film, an aluminum film, and a titanium / titanium nitride film.

  Note that the above-described plugs PG1, PG2, and PG3 are formed in the same manner as the plug PG4, and the above-described wirings HL1, HL2, and HL3 are also formed in the same manner as the wiring HL4.

  The memory cell according to the first embodiment is configured as described above, and the operation of the memory cell will be described below. Here, the voltage applied to the control gate electrode 15 is Vcg, and the voltage applied to the memory gate electrode 26 is Vmg. Further, voltages applied to the source region and the drain region are Vs and Vd, respectively, and a voltage applied to the semiconductor substrate 10, that is, the p-type well 12, is Vb. The injection of electrons into the silicon nitride film 18 that is the charge storage film 25 is defined as “writing”, and the injection of holes into the silicon nitride film 18 is defined as “erasing”.

  First, the write operation will be described. The writing operation is performed by hot electron writing called a so-called source side injection method. As the write voltage, for example, the voltage Vs applied to the source region is 6V, the voltage Vmg applied to the memory gate electrode 26 is 12V, and the voltage Vcg applied to the control gate electrode 15 is 1.5V. Then, the voltage Vd applied to the drain region is controlled so that the channel current at the time of writing becomes a certain set value. The voltage Vd at this time is determined by the set value of the channel current and the threshold voltage of the selection transistor having the control gate electrode 15, and is, for example, about 1V. The voltage Vb applied to the p-type well 12, that is, the semiconductor substrate 10, is 0V.

  An explanation will be given of the movement of electric charges when a writing operation is performed by applying such a voltage. As described above, by applying a potential difference between the voltage Vs applied to the source region and the voltage Vd applied to the drain region, electrons flow through the channel region formed between the source region and the drain region. The electrons flowing through the channel region are accelerated in the channel region near the boundary between the control gate electrode 15 and the memory gate electrode 26 and become hot electrons. Then, hot electrons are injected into the charge storage film 25 under the memory gate electrode 26, that is, into the silicon nitride film 18 by an electric field of a positive voltage (Vmg = 12 V) applied to the memory gate electrode 26. The injected hot electrons are trapped at the trap level in the silicon nitride film 18, and as a result, electrons are accumulated in the silicon nitride film 18 and the threshold voltage of the memory transistor is increased. In this way, the write operation is performed.

  Next, the erase operation will be described. The erasing operation is performed by, for example, BTBT (Band to Band Tunneling) erasing using the band-to-band tunneling phenomenon. In BTBT erase, for example, the voltage Vmg applied to the memory gate electrode 26 is −6 V, the voltage Vs applied to the source region is 6 V, the voltage Vcg applied to the control gate electrode 15 is 0 V, and 0 V is applied to the drain region. As a result, holes generated by the band-band tunneling phenomenon at the end of the source region due to the voltage applied between the source region and the memory gate electrode are accelerated by the high voltage applied to the source region to become hot holes. . A part of the hot holes is attracted to the negative voltage applied to the memory gate electrode 26 and injected into the silicon nitride film 18. The injected hot holes are captured by trap levels in the silicon nitride film 18, and the threshold voltage of the memory transistor is lowered. In this way, the erase operation is performed.

  Next, the reading operation will be described. In reading, the voltage Vd applied to the drain region is Vdd (1.5 V), the voltage Vs applied to the source region is 0 V, the voltage Vcg applied to the control gate electrode 15 is Vdd (1.5 V), and the memory gate electrode 26 is read. The applied voltage Vmg is set to Vdd (1.5 V), and current is applied in the direction opposite to that at the time of writing. The voltage Vd to be applied to the drain region and the voltage Vs to be applied to the source region may be switched to 0 V and 1.5 V, respectively. At this time, if the memory cell is in a write state and the threshold voltage is high, no current flows through the memory cell. On the other hand, when the memory cell is in the erased state and the threshold voltage is low, a current flows through the memory cell.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the semiconductor device according to the first embodiment will be described.

  14 to 31 are cross-sectional views during the manufacturing process of the semiconductor device according to the first embodiment. 14 to 31 show the same cross section as the cross section shown in FIG.

  First, as shown in FIG. 14, a semiconductor substrate 10 made of a silicon single crystal into which a p-type impurity such as boron (B) is introduced is prepared. Then, an element isolation region 11 that separates, for example, a low breakdown voltage MISFET formation region and a high breakdown voltage MISFET formation region is formed in the semiconductor substrate 10. The element isolation region 11 is provided to prevent the elements from interfering with each other. The element isolation region 11 can be formed using, for example, a LOCOS (Local Oxidation of Silicon) method or an STI (Shallow Trench Isolation) method.

  For example, in the STI method, the element isolation region 11 is formed as follows. That is, an element isolation trench is formed in the semiconductor substrate 10 using a photolithography technique and an etching technique. Then, a silicon oxide film is formed on the semiconductor substrate 10 so as to fill the element isolation trench, and then unnecessary silicon oxide formed on the semiconductor substrate 10 by a chemical mechanical polishing (CMP) method. Remove the membrane. Thereby, the element isolation region 11 in which the silicon oxide film is buried only in the element isolation trench can be formed. In FIG. 14, the element isolation region 11 is not formed in the memory cell formation region AR1 on the surface 10a side of the semiconductor substrate 10 and the element isolation region 11 in the capacitor element formation region AR2 on the surface 10a side of the semiconductor substrate 10. The region where is formed.

  Next, impurities are introduced into the semiconductor substrate 10 to form the p-type well 12. The p-type well 12 is formed by introducing a p-type impurity such as boron into the semiconductor substrate 10 by ion implantation. In the memory cell formation region AR1, a semiconductor region (not shown) for forming a channel of the selection transistor is formed in the surface region of the p-type well 12. This channel forming semiconductor region is formed to adjust the threshold voltage for forming the channel.

Next, as shown in FIG. 15, an insulating film IF1 is formed on the semiconductor substrate 10 in the memory cell formation region AR1 and the capacitor element formation region AR2. The insulating film IF1 is made of, for example, a silicon oxide film, and can be formed using, for example, a thermal oxidation method. However, the insulating film IF1 is not limited to the silicon oxide film and can be variously changed. For example, the insulating film IF1 may be a silicon oxynitride film (SiON). That is, a structure in which nitrogen is segregated at the interface between the insulating film IF1 and the semiconductor substrate 10 may be employed. The silicon oxynitride film has a higher effect of suppressing generation of interface states in the film and reducing electron traps than the silicon oxide film. Therefore, the hot carrier resistance of the insulating film IF1 can be improved, and the insulation resistance can be improved. Further, the silicon oxynitride film is less likely to diffuse impurities than the silicon oxide film. For this reason, by using a silicon oxynitride film as the gate insulating film 13, it is possible to suppress fluctuations in the threshold voltage caused by diffusion of impurities in the control gate electrode 15 toward the semiconductor substrate 10 side. In order to form the silicon oxynitride film, for example, the semiconductor substrate 10 may be heat-treated in an atmosphere containing nitrogen such as NO, NO _2, or NH ₃ . In addition, after the insulating film IF1 made of a silicon oxide film is formed on the surface of the semiconductor substrate 10, the semiconductor substrate 10 is heat-treated in an atmosphere containing nitrogen, and nitrogen is segregated at the interface between the insulating film IF1 and the semiconductor substrate 10. The same effect can be obtained also.

  The insulating film IF1 may be formed of a high dielectric constant film having a dielectric constant higher than that of, for example, a silicon nitride film. Thereby, even if the capacitance is the same, the physical film thickness can be increased, so that the leakage current can be reduced.

For example, a hafnium oxide (HfO ₂ ) film, which is one of hafnium oxides, is used as the high dielectric film. Instead of the hafnium oxide film, a hafnium aluminate (HfAlO) film, hafnium oxynitride (HfON) is used. ), Other hafnium-based insulating films such as a hafnium silicate (HfSiO) film and a hafnium silicon oxynitride (HfSiON) film can also be used. Further, a hafnium-based insulating film in which an oxide such as tantalum oxide, niobium oxide, titanium oxide, zirconium oxide, lanthanum oxide, or yttrium oxide is introduced into these hafnium-based insulating films can also be used. Since the hafnium-based insulating film has a dielectric constant higher than that of the silicon oxide film or the silicon oxynitride film similarly to the hafnium oxide film, the same effect as that obtained when the hafnium oxide film is used can be obtained.

  Then, in the memory cell formation region AR1 and the capacitor element formation region AR2, a conductive film CF1 made of, for example, a polysilicon film is formed on the insulating film IF1. The conductive film CF1 made of the polysilicon film can be formed using, for example, a CVD (Chemical Vapor Deposition) method. Then, an n-type impurity such as phosphorus or arsenic is introduced into the conductive film CF1 made of a polysilicon film by using a photolithography technique and an ion implantation method.

  Next, as shown in FIG. 16, in the memory cell formation region AR1 and the capacitor element formation region AR2, the conductive film CF1 and the insulating film IF1 are processed, that is, patterned by etching using the patterned resist film as a mask. Then, in the memory cell formation region AR1, the control gate electrode 15 made of the conductive film CF1 and the gate insulating film 13 made of the insulating film IF1 between the control gate electrode 15 and the semiconductor substrate 10 are formed. In the capacitor element formation region AR2, the electrode 16 made of the conductive film CF1 and the dummy electrode DE made of the conductive film CF1 are formed. The control gate electrode 15 is a gate electrode of a selection transistor of the memory cell. In this manner, the capacitor electrode 16 and the dummy electrode DE are formed in the process of forming the control gate electrode 15 of the memory cell.

  Here, n-type impurities are introduced into the control gate electrode 15 in the conductive film CF1 made of a polysilicon film. For this reason, the work function value of the control gate electrode 15 can be set to a value in the vicinity of the conduction band of silicon (4.15 eV), so that the threshold voltage of the selection transistor that is an n-channel MISFET can be reduced. .

  Here, in the case of manufacturing the semiconductor device according to the third modification of the first embodiment, instead of the process described with reference to FIG. 16, a modification described below with reference to FIGS. Various steps can be performed.

  First, after the process described with reference to FIG. 15, as shown in FIG. 17, an insulating film IF3 is formed on the conductive film CF1 made of a polysilicon film. For example, the insulating film IF3 made of a silicon nitride film can be formed using a CVD method or the like. As a material of the insulating film IF3, an insulating film made of another material functioning as a cap insulating film, a hard mask film, or a spacer film can be used instead of the silicon nitride film.

  Next, as shown in FIG. 18, the insulating film IF3 is processed by etching using the patterned resist film as a mask, and the insulating film IF3 is removed in a region where the metal silicide film is formed in the capacitor element formation region AR2. The insulating film IF3 is left in a region other than the region where the metal silicide film is formed in the capacitive element formation region AR2. As shown in FIG. 18, the insulating film IF3 can be left in the memory cell formation region AR1.

  Next, as shown in FIG. 19, the insulating film IF3, the conductive film CF1, and the insulating film IF1 are processed by etching using the patterned resist film as a mask. Thereby, the cap insulating film CP1 including the gate insulating film 13, the control gate electrode 15, and the insulating film IF3 on the control gate electrode 15 is formed in the memory cell formation region AR1. In addition, the electrode 16 is formed in the capacitive element formation region AR2. A cap insulating film CP1 made of an insulating film IF3 is formed on a part of the upper surface of the electrode 16. In addition, after performing the process shown in FIG. 19, the process similar to the process after FIG. 20 can be performed similarly to after performing the process shown in FIG.

  Next, as shown in FIG. 20, in the memory cell formation region AR1 and the capacitor element formation region AR2, the surface of the control gate electrode 15, the surface of the electrode 16, and the surface of the dummy electrode DE are formed on the semiconductor substrate 10. Then, the insulating film IF2 is formed. In FIG. 20, the insulating film IF2 is illustrated as a single layer film. However, as illustrated in an enlarged view in FIG. 21, the insulating film IF2 includes, for example, a silicon oxide film 17 and silicon nitride on the silicon oxide film 17. The film 18 and the silicon oxide film 19 on the silicon nitride film 18 are so-called ONO films. The insulating film IF2 can be formed using, for example, a CVD method. For example, the silicon oxide film 17 has a thickness of 5 nm, the silicon nitride film 18 has a thickness of 10 nm, and the silicon oxide film 19 has a thickness of 5 nm.

  Of the insulating film IF2, the silicon nitride film 18 is a film that becomes the charge storage film 25 (see FIG. 13) of the memory transistor in the memory cell formation region AR1. In the first embodiment, the silicon nitride film 18 is used as the charge storage film 25, but another insulating film having a trap level may be used as the charge storage film 25. For example, an aluminum oxide film (alumina film) can be used as the charge storage film 25.

  Next, as shown in FIG. 20, a conductive film CF2 made of, for example, a polysilicon film is formed on the insulating film IF2 in the memory cell formation region AR1 and the capacitive element formation region AR2. The conductive film CF2 made of a polysilicon film can be formed by using, for example, a CVD method.

  Next, as shown in FIG. 22, in the memory cell formation region AR1 and the capacitor element formation region AR2, the conductive film CF2 made of, for example, a polysilicon film is etched back by anisotropic etching. Thereby, in the memory cell formation region AR1, the side walls 22a and the side walls 22b made of the conductive film CF2 are left on the side walls on both sides of the control gate electrode 15, that is, the side surfaces, with the insulating film IF2 interposed therebetween. On the other hand, in the capacitive element formation region AR2, the conductive film CF2 is left as an integral part through the insulating film IF2 between the electrode 16 and the dummy electrode DE, on the peripheral side surface of the electrode 16, and on the peripheral side surface of the dummy electrode DE. The electrode 23 made of the conductive film CF2 is integrally formed. For this reason, the electrode 16 and the electrode 23 do not overlap in plan view.

  Here, in the case of manufacturing the semiconductor device according to the second modification of the first embodiment, after performing the process described with reference to FIG. 20, the process described with reference to FIG. The following steps described with reference to No. 24 can be performed.

  First, as shown in FIG. 23, after a resist film PR1 is applied on the semiconductor substrate 10, the resist film PR1 is subjected to exposure / development processing for patterning. In this patterning, in the capacitive element formation region AR2, the conductive film CF2 is covered with the resist film PR1 in the region where the electrode 23 is formed on the upper surface of the electrode 16, and the conductive film CF2 is exposed in the other regions. Done.

  Next, as shown in FIG. 24, by etching back the conductive film CF2 made of a polysilicon film by anisotropic etching, in the memory cell formation region AR1, the sidewalls on both sides of the control gate electrode 15, that is, the side surfaces are formed. The side wall 22a and the side wall 22b made of the conductive film CF2 are left. On the other hand, in the capacitive element formation region AR2, for example, the conductive film CF2 made of, for example, a polysilicon film is anisotropically etched, so that the gap between the electrode 16 and the dummy electrode DE, the peripheral side surface of the electrode 16, and the periphery of the dummy electrode DE. An electrode 23 made of the conductive film CF2 formed integrally is formed on the side surface. Further, in the capacitive element formation region AR2, the conductive film CF2 made of a polysilicon film is etched using the resist film PR1 as a mask, so that a part of the upper surface of the electrode 16 is formed on the electrode 23 via the insulating film IF2. Is formed. At this time, in a partial region of the upper surface of the electrode 16, the electrode 16 and the electrode 23 overlap in plan view. Thereafter, the patterned resist film PR1 is removed. Note that after the step shown in FIG. 24 is performed, the same steps as those in FIG. 25 and subsequent steps can be performed in the same manner as after the step shown in FIG.

  Next, as shown in FIG. 25, after applying a resist film PR2 on the semiconductor substrate 10, the resist film PR2 is subjected to exposure / development treatment to pattern the resist film PR2. The patterning is performed so as to completely cover the capacitive element formation region AR2 while opening a part of the memory cell formation region AR1. Specifically, it is performed so that one side wall of the control gate electrode 15 in the memory cell formation region AR1, that is, the side wall 22b formed on the side surface is exposed. For example, in FIG. 25, the side wall 22b formed on the left side wall of the control gate electrode 15 is exposed.

  Next, as shown in FIG. 26, the sidewall 22b exposed on the left sidewall of the control gate electrode 15 is removed by etching using the patterned resist film PR2 as a mask. At this time, the side wall 22a formed on the right side wall of the control gate electrode 15 remains unremoved because it is covered with the resist film PR2. The sidewall 22a is a portion that becomes the memory gate electrode 26 (see FIG. 27 described later). In the capacitive element formation region AR2, the electrode 23 remains without being removed because it is protected by the resist film PR2. Thereafter, the patterned resist film PR2 is removed.

  Subsequently, as shown in FIG. 27, in the memory cell formation region AR1 and the capacitor element formation region AR2, any of the exposed insulating film IF2, that is, the electrode 23 and the side wall 22a that is a portion to be the memory gate electrode 26 is formed. The portion of the insulating film IF2 that is not covered is removed by etching. That is, in the memory cell formation region AR1, a portion of the insulating film IF2 between the control gate electrode 15 and the memory gate electrode 26 and a portion between the memory gate electrode 26 and the semiconductor substrate 10 are left. Other parts are removed. In the capacitive element formation region AR2, in the insulating film IF2, a portion between the electrode 16 and the electrode 23, a portion between the dummy electrode DE and the electrode 23, and a portion between the electrode 23 and the semiconductor substrate 10 are provided. The part is left and the other part is removed.

  In this way, in the memory cell formation region AR1, the sidewall 22a made of the conductive film CF2 is left through the insulating film IF2 only on the right side wall, that is, the side surface of the control gate electrode 15, and the sidewall-shaped memory gate is formed. Electrode 26 is formed. Further, in the insulating film IF2, a portion between the control gate electrode 15 and the memory gate electrode 26 and a portion between the memory gate electrode 26 and the semiconductor substrate 10 are left, and the remaining insulating film IF2 is insulated. The film 27a is formed. At this time, in the insulating film 27a, the silicon nitride film 18 (see FIG. 21) constituting the insulating film 27a becomes the charge storage film 25 (see FIG. 13).

  On the other hand, in the capacitive element formation region AR2, in the insulating film IF2, a portion between the electrode 16 and the electrode 23, a portion between the dummy electrode DE and the electrode 23, and a portion between the electrode 23 and the semiconductor substrate 10 are provided. The portion is left, and the remaining insulating film IF2 becomes the capacitive insulating film 27. The capacitor insulating film 27 includes a silicon oxide film 17, a silicon nitride film 18, and a silicon oxide film 19 (see FIG. 21). A capacitor element is formed by the electrode 16, the electrode 23, and the capacitor insulating film 27.

  At this point, since the conductive film CF1 is formed of a polysilicon film, the memory gate electrode 26 of the memory cell and the electrode 23 of the capacitor element are formed of a polysilicon film.

  Next, as shown in FIG. 28, by using a photolithography technique and an ion implantation method, shallow low-concentration impurity diffusion regions 28 aligned with the control gate electrode 15 and the memory gate electrode 26 are formed in the memory cell formation region AR1. Form. The shallow low-concentration impurity diffusion region 28 is an n-type semiconductor region into which an n-type impurity such as phosphorus or arsenic is introduced.

  Subsequently, as illustrated in FIG. 29, an insulating film made of a silicon oxide film is formed on the semiconductor substrate 10. The insulating film made of a silicon oxide film can be formed using, for example, a CVD method. Then, the sidewalls 29a and 29b are formed by anisotropically etching the insulating film. In the memory cell formation region AR1, a sidewall 29a made of an insulating film is formed on the left side wall, that is, the side surface of the control gate electrode 15, and the right side wall, that is, the side surface of the memory gate electrode 26. On the other hand, in the capacitive element formation region AR2, a sidewall 29b made of an insulating film is formed on the side wall, that is, the side surface of the electrode 23. The insulating films constituting these sidewalls 29a and 29b are formed by a single layer film of a silicon oxide film. However, the insulating film is not limited to this. For example, the insulating film is formed by a laminated film of a silicon nitride film and a silicon oxide film. Also good.

  Here, in the case of manufacturing the semiconductor device according to the second modification of the first embodiment, in the process described with reference to FIG. 29, the semiconductor device is formed on the upper surface of the electrode 16 in the electrode 23 in the capacitor element formation region AR2. A side wall 29c (see FIG. 8) is formed on the side wall of the portion.

  Next, as shown in FIG. 30, a deep high-concentration impurity diffusion region 30 aligned with the sidewall 29a is formed in the memory cell formation region AR1 by using a photolithography technique and an ion implantation method. The deep high-concentration impurity diffusion region 30 is an n-type semiconductor region into which an n-type impurity such as phosphorus or arsenic is introduced. The deep high-concentration impurity diffusion region 30 and the shallow low-concentration impurity diffusion region 28 form a source region and a drain region of the memory cell. Thus, by forming the source region and the drain region with the shallow low-concentration impurity diffusion region 28 and the deep high-concentration impurity diffusion region 30, the source region and the drain region can have an LDD structure. Thus, after the high concentration impurity diffusion region 30 is formed, a heat treatment at about 1000 ° C. is performed. Thereby, the introduced impurities are activated.

  Next, as shown in FIG. 31, metal is formed on the surface of the control gate electrode 15, the memory gate electrode 26, the electrode 16, the electrode 23, the dummy electrode DE, and the high-concentration impurity diffusion region 30 as the source region and the drain region. A silicide film 33 is formed.

  First, a metal film made of, for example, a cobalt film is formed on the semiconductor substrate 10 in the memory cell formation region AR1 and the capacitor element formation region AR2. At this time, in the memory cell formation region AR1, a metal film is formed so as to be in direct contact with the exposed control gate electrode 15 and memory gate electrode 26. Similarly, the metal film is also in direct contact with the deep high concentration impurity diffusion region 30. On the other hand, in the capacitive element formation region AR2, the metal film is in direct contact with part of the electrode 16 and part of the electrode 23. For example, a metal film made of a cobalt film can be formed using, for example, a sputtering method. The thickness of the metal film is, for example, 10 nm.

Then, the first heat treatment is performed on the semiconductor substrate 10. Thereafter, the surface of the semiconductor substrate 10 is cleaned. This cleaning is performed by APM (Ammonium hydroxide hydrogen peroxide mixture cleaning) cleaning and HPM cleaning. APM cleaning is a mixed chemical solution composed of ammonium hydroxide (NH ₄ OH) / hydrogen peroxide (H ₂ O ₂ ) / pure water (H ₂ O), and is a cleaning that has a large effect of removing particles and organic substances. On the other hand, the HPM cleaning is a mixed chemical solution composed of hydrochloric acid (HCl) / hydrogen peroxide (H ₂ O ₂ ) / pure water (H ₂ O), and is a cleaning having a large effect on removing metals. Subsequently, after the cleaning, a second heat treatment is performed.

  Thereby, as shown in FIG. 31, in the memory cell formation region AR1, the conductive films CF1 and CF2 made of polysilicon film and the cobalt film are formed on the surface of the control gate electrode 15 and the surface of the memory gate electrode 26. A metal silicide film 33 made of a cobalt silicide film is formed by reacting with the metal film. As a result, the control gate electrode 15 has a laminated structure of the conductive film CF1 made of a polysilicon film and the metal silicide film 33 made of a cobalt silicide film. The memory gate electrode 26 has a stacked structure of a conductive film CF2 made of a polysilicon film and a metal silicide film 33 made of a cobalt silicide film. The metal silicide film 33 made of a cobalt silicide film is formed to reduce the resistance of the control gate electrode 15 and the memory gate electrode 26. The gate insulating film 13, the control gate electrode 15, the memory gate electrode 26, and the insulating film 27a form a memory cell.

  Similarly, by the heat treatment described above, the high-concentration impurity diffusion region 30 made of silicon also reacts with the metal film made of the cobalt film on the surface of the high-concentration impurity diffusion region 30, and the metal silicide film 33 made of the cobalt silicide film. Is formed. Therefore, the resistance can be reduced even in the high concentration impurity diffusion region 30.

  On the other hand, in the capacitive element formation region AR2, the conductive films CF1 and CF2 made of the polysilicon film react with the metal film made of the cobalt film on the surface of the electrode 16, the surface of the dummy electrode DE, and the surface of the electrode 23. A metal silicide film 33 made of a cobalt silicide film is formed. As a result, the electrode 16 and the dummy electrode DE each have a laminated structure of the conductive film CF1 made of a polysilicon film and the metal silicide film 33 made of a cobalt silicide film. The electrode 23 has a laminated structure of a conductive film CF2 made of a polysilicon film and a metal silicide film 33 made of a cobalt silicide film. The metal silicide film 33 made of a cobalt silicide film is formed to reduce the resistance of the electrode 16, the dummy electrode DE and the electrode 23.

  Then, the unreacted metal film is removed from the semiconductor substrate 10. In the first embodiment, an example in which a cobalt silicide film is formed as the metal silicide film 33 has been described. Instead of the cobalt silicide film, for example, a nickel silicide film or a titanium silicide film is used as the metal silicide film 33. You may make it form.

  As described above, the memory cell can be formed in the memory cell formation region AR1, and the capacitor in the first embodiment can be formed in the capacitor element formation region AR2.

  When manufacturing the semiconductor device according to the third modification of the first embodiment, the cap insulating film on the upper surface of the electrode 16 is used in the step described with reference to FIG. In the region where CP1 is formed, the metal silicide film 33 is not formed.

  Next, the wiring process will be described with reference to FIG. As shown in FIG. 12, an interlayer insulating film 34 is formed on the surface 10 a of the semiconductor substrate 10. The interlayer insulating film 34 is formed of, for example, a silicon oxide film, and can be formed using, for example, a CVD method using TEOS (Tetra Ethyl Ortho Silicate) as a raw material. Thereafter, the surface of the interlayer insulating film 34 is planarized using, for example, a CMP method.

  Subsequently, contact holes CH1, CH2, and CH4 are formed in the interlayer insulating film 34 by using a photolithography technique and an etching technique. At this time, in the memory cell formation region AR1, a contact hole CH4 that penetrates the interlayer insulating film 34 and reaches the source region or the drain region is formed. In the capacitive element formation region AR2, contact holes CH1 and CH2 are formed. The contact hole CH1 penetrates the interlayer insulating film 34 and reaches the electrode 16. Further, the contact hole CH2 penetrates the interlayer insulating film 34 and reaches a portion formed on the side surface of the electrode 23 opposite to the electrode 16 side of the dummy electrode DE.

  Then, a titanium / titanium nitride film is formed on the interlayer insulating film 34 including the bottom and inner walls of the contact holes CH1, CH2, and CH4. The titanium / titanium nitride film is composed of a laminated film of a titanium film and a titanium nitride film, and can be formed by using, for example, a sputtering method. This titanium / titanium nitride film has a so-called barrier property that prevents, for example, tungsten, which is a material of a film to be embedded in a later process, from diffusing into silicon.

  Subsequently, a tungsten film as a conductive film is formed on the entire surface 10a of the semiconductor substrate 10 so as to fill the contact holes CH1, CH2, and CH4. This tungsten film can be formed using, for example, a CVD method. Then, the unnecessary titanium / titanium nitride film and tungsten film formed on the interlayer insulating film 34 are removed by using, for example, a CMP method, whereby the plugs PG1, PG2, and PG4 can be formed.

  Among these, plugs PG1 and PG2 are formed in the capacitive element formation region AR2. As the plug PG1, a plug PG1 made of a conductive film embedded in the contact hole CH1 and electrically connected to the electrode 16 is formed. As the plug PG2, a plug PG2 made of a conductive film embedded in the contact hole CH2 and electrically connected to the electrode 23 is formed. A plug PG1 in contact with the metal silicide film 33 formed on the surface of the electrode 16 is formed as the plug PG1, and a plug PG2 in contact with the metal silicide film 33 formed on the surface of the electrode 23 is formed as the plug PG2. Is done.

  Next, for example, a titanium / titanium nitride film, an aluminum film containing copper, and a titanium / titanium nitride film are sequentially formed on the interlayer insulating film 34 and the plugs PG1, PG2, and PG4. These films can be formed by using, for example, a sputtering method. Subsequently, these films are patterned by using a photolithography technique and an etching technique to form wirings HL1, HL2, and HL4. The wiring HL1 is electrically connected to the plug PG1, the wiring HL2 is electrically connected to the plug PG2, and the wiring HL4 is electrically connected to the plug PG4. Furthermore, although wiring is formed in the upper layer of wiring, description here is abbreviate | omitted. In this manner, the semiconductor device according to the first embodiment can be finally formed.

<Connection between electrode and plug>
The semiconductor devices of Comparative Example 1 and Comparative Example 2 will be described with reference to the drawings. FIG. 32 is a cross-sectional view showing the semiconductor device of Comparative Example 1. FIG. 33 is a cross-sectional view showing the semiconductor device of Comparative Example 2. 32 and 33 are cross-sectional views showing the structure of a memory cell of a flash memory and the structure of a capacitor element formed in an analog circuit or the like.

  In the semiconductor device of Comparative Example 1, each part in the memory cell formation region AR1, and each part other than the lower electrode 116, the upper electrode 123, the contact hole CH102, and the plug PG102 in the capacitor element formation region AR2 are described in the embodiment. This is the same as each part of the semiconductor device 1. In the semiconductor device of Comparative Example 2, each part in the memory cell formation region AR1, and each part other than the lower electrode 116, the upper electrode 123, the contact hole CH102, and the plug PG102 in the capacitor element formation region AR2 are implemented. This is the same as each part of the semiconductor device of the first embodiment.

  In the semiconductor device of Comparative Example 1, although not shown, the lower electrode 116 and the upper electrode 123 have different rectangular shapes in plan view, and the lower electrode 116 and the upper electrode 123 overlap in plan view. The lower electrode 116 and the upper electrode 123 have a non-overlapping region where they do not overlap in plan view. That is, in the X-axis direction of FIG. 32, the length of the lower electrode 116 is shorter than the length of the upper electrode 123, and in the Y-axis direction (direction perpendicular to the paper of FIG. 32) intersecting the X-axis direction. The length of 116 is longer than the length of the upper electrode 123. The capacitive element is formed in the overlapping region where the lower electrode 116 and the upper electrode 123 thus configured overlap in a plane. And in the non-overlapping area | region of the lower electrode 116, the plug (illustration omitted) electrically connected with the lower electrode 116 is formed. In the non-overlapping region of the upper electrode 123, a contact hole CH102 that penetrates the interlayer insulating film 34 and reaches the upper electrode 123 is formed, and is made of a conductive film embedded in the contact hole CH102. A connected plug PG102 is formed.

  As shown in FIG. 32, the lower electrode 116 includes a conductive film CF1 made of a polysilicon film and a metal silicide film 33 formed on the surface of the conductive film CF1. On the other hand, a sidewall 129 made of an insulating film is formed on the side wall of the step region of the upper electrode 123, and the metal silicide film 33 is not formed on the surface of the step region of the upper electrode 123. Therefore, the upper electrode 123 in the step region has a high resistance, and the plug PG102 formed in the non-overlapping region of the upper electrode 123 cannot be electrically connected to the overlapping region of the upper electrode 123 with a low resistance. The PG 102 and the upper electrode 123 cannot be electrically connected with low resistance.

  On the other hand, in the semiconductor device of Comparative Example 2, the lower electrode 116 and the upper electrode 123 have different rectangular shapes in plan view, but the upper electrode 123 is included in the region where the lower electrode 116 is formed in plan view. The upper electrode 123 overlaps the lower electrode 116 in plan view over the entire surface. Therefore, in the semiconductor device of Comparative Example 2, the lower electrode 116 includes an overlapping region where the lower electrode 116 and the upper electrode 123 overlap in a plan view and a non-overlapping region where the lower electrode 116 and the upper electrode 123 do not overlap in a plan view. Have. A plug (not shown) electrically connected to the lower electrode 116 is formed in a non-overlapping region of the lower electrode 116, but the plug PG 102 electrically connected to the upper electrode 123 is connected to the lower electrode 116. 116 is formed in an overlapping area with 116. A metal silicide film 33 is formed on the entire surface of the upper electrode 123. Therefore, the plug PG102 and the upper electrode 123 can be electrically connected with low resistance.

  However, in the semiconductor device of Comparative Example 2, the thickness of the capacitive element is the sum of the thickness of the lower electrode 116, the thickness of the capacitive insulating film 27, and the thickness of the upper electrode 123. Further, the thickness of the conductive film CF1 constituting the lower electrode 116 is equal to the thickness of the conductive film CF1 constituting the control gate electrode 15. Therefore, the height position of the upper surface of the upper electrode 123 of the capacitive element is higher than the height position of the upper surface of the control gate electrode 15 in the memory cell, for example, and higher than the height position of the upper surface of the source region or drain region in the memory cell. high. That is, the distance DST1 in the thickness direction from the lower surface of the wiring HL2 on the capacitive element to the upper surface of the upper electrode 123 of the capacitive element is the thickness direction distance from the lower surface of the wiring HL4 on the memory cell to the upper surface of the control gate electrode 15. It is shorter than the distance DST2 and shorter than the distance DST3 in the thickness direction from the lower surface of the wiring HL4 to the upper surface of the source region or drain region.

  Therefore, when the contact hole CH4 that reaches the source region or the drain region through the interlayer insulating film 34 and the contact hole CH102 that reaches the upper surface of the upper electrode 123 through the interlayer insulating film 34 are formed in the same process. The contact hole CH102 may reach the lower electrode 116 through the upper electrode 123 and the capacitor insulating film 27. In such a case, the upper electrode 123 and the lower electrode 116 may be short-circuited by the plug PG102 made of the conductive film embedded in the contact hole CH102, and the performance of the semiconductor device is deteriorated.

  Further, when the height from the upper surface of the semiconductor substrate 10 to the lower surfaces of the wirings HL2 and HL4 decreases with the miniaturization of the semiconductor device, the thickness direction from the lower surface of the wiring HL4 to the upper surface of the source region or the drain region is increased. Compared with the rate at which the distance decreases, the rate at which the distance in the thickness direction from the lower surface of the wiring HL2 to the upper surface of the upper electrode 123 decreases increases. Therefore, the possibility that the upper electrode 123 and the lower electrode 116 are short-circuited by the plug PG102 made of the conductive film embedded in the contact hole CH102 is further increased, and the performance of the semiconductor device is further deteriorated.

<Main features and effects of the present embodiment>
On the other hand, in the first embodiment, the contact hole CH2 passes through the interlayer insulating film 34 and reaches a portion of the electrode 23 formed on the side surface opposite to the electrode 16 side of the dummy electrode DE. In the first embodiment, the plug PG2 made of a conductive film embedded in the contact hole CH2 penetrates the interlayer insulating film 34 and is on the side surface of the electrode 23 opposite to the electrode 16 side of the dummy electrode DE. It is electrically connected directly to the formed part. In the portion of the electrode 23 opposite to the electrode 16 side of the dummy electrode DE, an electrode 23 as a sidewall having the dummy electrode DE as a core is formed. With such a configuration, the plug PG2 can be electrically connected to any part of the electrode 23 via the metal silicide film 33 formed on the surface of the electrode 23 and having a relatively small electrical resistance. Therefore, the plug PG2 can be electrically connected to any part of the electrode 23 with a low resistance.

  In the first embodiment, the portion of the electrode 23 formed on the side surface opposite to the electrode 16 side of the dummy electrode DE does not overlap the electrode 16 in plan view. Therefore, the contact hole CH2 does not pass through the interlayer insulating film 34, the electrode 23, and the capacitor insulating film 27 and reach the electrode 16, but the electrode 23 and the electrode 16 are formed by the plug PG2 made of a conductive film embedded in the contact hole CH2. Are not short-circuited, so that the performance of the semiconductor device can be improved.

  As shown in FIG. 8, in the second modification of the first embodiment, a sidewall 29c made of an insulating film is formed on the side surface of the portion of the electrode 23 formed on the upper surface of the electrode 16. ing. However, as shown in FIG. 32, in the first comparative example, in the step region of the upper electrode 123, compared with the height of the side surface on which the sidewall 129 made of an insulating film is formed, the second of the first embodiment. In the modification, the height of the side surface on which the sidewall 29c is formed is small. Therefore, in the second modification of the first embodiment, the plug PG2 and the electrode 23 are electrically connected as compared with the comparative example 1 in which the plug PG102 and the upper electrode 123 cannot be electrically connected with low resistance. It is possible to connect with lower resistance.

(Embodiment 2)
In the first embodiment, the dummy electrode DE is formed and the plug PG2 is electrically connected to the portion of the electrode 23 formed on the side surface of the dummy electrode DE (see FIG. 3). On the other hand, in the second embodiment, the dummy electrode DE is not formed, the opening OP2 is formed in the electrode 16, and the plug PG2 is electrically connected to the electrode 23 formed in the opening OP2 formed in the electrode 16. An example of connection (see FIG. 35 described later) will be described.

  FIG. 34 is a plan view showing the capacitive element in the second embodiment, and FIG. 35 is a cross-sectional view showing the capacitive element in the second embodiment. FIG. 35 is a cross-sectional view taken along line AA of FIG. As shown in FIGS. 34 and 35, the semiconductor device of the second embodiment is the same as the semiconductor device of the first embodiment except for the arrangement of electrode 16, electrode 23, plug PG1, and plug PG2. it can.

  As shown in FIGS. 34 and 35, the semiconductor device has the electrode 16 made of the conductive film CF1 formed on the element isolation region 11, but unlike the first embodiment, the semiconductor device has a dummy electrode DE (see FIG. 3). I don't have it. On the other hand, the semiconductor device has an opening OP2 that penetrates the electrode 16, unlike the first embodiment. The semiconductor device has a conductive film CF2 formed inside the opening OP2 and an electrode 23 made of the conductive film CF2 formed integrally with the peripheral side surface of the electrode 16. The electrode 23 includes a conductive film CF2 made of, for example, a polysilicon film, and a metal silicide film 33 made of, for example, a cobalt silicide film formed on the surface of the conductive film CF2.

  As in the first embodiment, a capacitive insulating film 27 made of the insulating film IF2 is formed between the electrode 16 and the electrode 23. A capacitor element is formed by the electrode 16, the electrode 23, and the capacitor insulating film 27. An interlayer insulating film 34 is formed so as to cover the capacitive element formed by the electrode 16, the electrode 23 and the capacitive insulating film 27. In the interlayer insulating film 34, contact holes CH1 and CH2 are formed as connection holes.

  The contact hole CH1 passes through the interlayer insulating film 34 and reaches the electrode 16. The plug PG1 is made of a conductive film embedded in the contact hole CH1, and is directly electrically connected to the electrode 16.

  The contact hole CH2 reaches the electrode 23 through the interlayer insulating film 34. The plug PG2 is made of a conductive film embedded in the contact hole CH2, and is directly electrically connected to the electrode 23. With such a configuration, the plug PG2 made of a conductive film embedded in the contact hole CH2 has the metal silicide film 33 formed on the surface of the electrode 23 with a relatively small electric resistance in any part of the electrode 23. Can be electrically connected. Therefore, the plug PG2 can be electrically connected to any part of the electrode 23 with a low resistance.

  Also in the second embodiment, the electrode 16 and the electrode 23 are formed in different regions in plan view. With such a configuration, there is no possibility that the contact hole CH2 penetrates the electrode 23 and reaches the electrode 16, and it is possible to prevent the electrode 23 and the electrode 16 from being electrically short-circuited through the plug PG2.

  Preferably, the semiconductor device includes a plurality of openings OP2 penetrating the electrode 16 and an electrode 23 formed in each of the plurality of openings OP2. The plurality of openings OP2 extend in the Y-axis direction and are arranged in the X-axis direction. Thus, by having the plurality of openings OP2 penetrating the electrode 16 and the electrodes 23 formed inside each of the plurality of openings OP2, the area of the side surface of the electrode 23 facing the side surface of the electrode 16 is increased. Therefore, the capacitance of the capacitive element can be easily increased.

  Note that, similarly to the first embodiment, when the conductive film CF1 is patterned, the opening OP2 is prevented from penetrating the conductive film CF1, which is also applicable to the second and second modifications. Is possible. At this time, the semiconductor device has an opening OP <b> 2 formed in the electrode 16.

<First Modification of Capacitance Element>
FIG. 36 is a plan view showing the capacitive element in the first modification of the second embodiment, and FIG. 37 is a cross-sectional view showing the capacitive element in the first modification of the second embodiment. FIG. 37 is a cross-sectional view taken along line AA in FIG.

  In the capacitive element in the first modified example, the electrode 23 is formed not only in the opening OP2 penetrating the electrode 16 and in the peripheral surface of the electrode 16 but also in a part of the upper surface of the electrode 16. This is different from the capacitor in the second embodiment described with reference to FIGS. The other points are the same as those of the capacitor in the second embodiment.

  As shown in FIG. 36, the electrode 16 has a rectangular shape in plan view and is integrally formed. In the first modified example, the dummy electrode DE (see FIG. 3) is not formed as in the second embodiment.

  The electrode 23 is also formed in a part of the upper surface of the electrode 16 in addition to the inside of the opening OP <b> 2 and the peripheral side surface of the electrode 16. Further, a side wall 29c made of an insulating film is formed on the side surface of the portion of the electrode 23 formed on the upper surface of the electrode 16.

  In the first modification, the contact hole CH2 reaches the electrode 23 through the interlayer insulating film 34 in a region overlapping the opening OP2 in plan view. The plug PG2 made of a conductive film embedded in the contact hole CH2 is electrically connected to the electrode 23 in a region overlapping the opening OP2 in plan view. Thereby, even when the contact hole CH2 penetrates the interlayer insulating film 34 and the electrode 23 is over-etched, the contact hole CH2 can be prevented from penetrating the capacitive insulating film 27 and reaching the electrode 16. Accordingly, it is possible to prevent the electrode 16 and the electrode 23 from being short-circuited by the plug PG2 made of the conductive film embedded in the contact hole CH2, so that the performance of the semiconductor device can be improved.

  Also in the first modification, as in the second embodiment, the plug PG2 can be electrically connected to any part of the electrode 23 with a low resistance, and the electrode 16 and the electrode 23 are electrically short-circuited. And the contact hole CH2 can be easily aligned.

  On the other hand, in the first modification, the upper surface of the electrode 16 and the lower surface of the electrode 23 are opposed to each other as compared with the second embodiment, so that the capacitance of the capacitive element can be easily increased.

  Next, a case where the ratio of the thickness of the conductive film CF2 constituting the electrode 23 to the opening width of the opening OP2 is changed will be described.

  FIG. 38 is a plan view showing a capacitive element in still another example, and FIGS. 39 and 40 are cross-sectional views showing capacitive elements in still another example. 39 and 40 are cross-sectional views along the line AA in FIG.

  In the example shown in FIGS. 38 to 40, the case where two openings OP2 penetrating the electrode 16 are formed will be described.

The opening width of the opening OP2 is defined as an opening width WT1, and the thickness of the conductive film CF2 constituting the electrode 23 is defined as a thickness TH1. And in the example shown in FIG. 39, following formula (1)
WT1 ≦ 2 × TH1 Formula (1)
And At this time, as shown in FIG. 39, the inside of the opening OP2 can be filled with the conductive film CF2. Thus, when the inside of the opening OP2 is buried with the conductive film CF2, it is buried in the contact hole CH2 reaching the electrode 23 through the interlayer insulating film 34 in a region overlapping the opening OP2 in plan view. The plug PG2 made of a conductive film is electrically connected to the electrode 23 in a region overlapping the opening OP2 in plan view. Thus, even when the contact hole CH2 penetrates the interlayer insulating film 34 and the electrode 23 is over-etched, the electrode 16 and the electrode 23 are short-circuited by the plug PG2 made of the conductive film embedded in the contact hole CH2. Therefore, the performance of the semiconductor device can be improved.

  In FIG. 39, the opening width WT1 of the opening OP2 is shown as the opening width in a state where the capacitive insulating film 27 is formed on the side surface of the opening OP2 (the same applies to FIG. 40).

On the other hand, even when the opening width WT1 and the thickness TH1 of the conductive film do not satisfy the formula (1), as shown in FIG. 40, the gap between the conductive films CF2 can be further filled with the sidewall 29d made of an insulating film. Here, the thickness of the insulating film constituting the sidewall 29d is set to a thickness TH2 equal to the thickness of the insulating film constituting the sidewall 29c. At this time, in the example shown in FIG.
2 × TH1 <WT1 ≦ 2 × (TH1 + TH2) Formula (2)
And At this time, as shown in FIG. 40, the conductive film CF2 is formed on the side surface and the bottom surface of the opening OP2, and the insulating film constituting the sidewall 29d is formed on the conductive film CF2 inside the opening OP2. Therefore, the inside of the opening OP2 can be filled with the sidewall 29d through the conductive film CF2. Even when the inside of the opening OP2 is filled with the sidewall 29d via the conductive film CF2, it is buried in the contact hole CH2 that penetrates the interlayer insulating film 34 and reaches the electrode 23 in a region overlapping with the opening OP2 in plan view. The plug PG2 thus connected is electrically connected to the electrode 23 in a region overlapping the opening OP2 in plan view. Thus, even when the contact hole CH2 penetrates the interlayer insulating film 34 and the electrode 23 is over-etched, the electrode 16 and the electrode 23 are short-circuited by the plug PG2 made of the conductive film embedded in the contact hole CH2. Therefore, the performance of the semiconductor device can be improved.

<Second Modification of Capacitance Element>
FIG. 41 is a plan view showing a capacitive element in the second modification of the second embodiment, and FIG. 42 is a cross-sectional view showing the capacitive element in the second modification of the second embodiment. 42 is a cross-sectional view taken along line AA in FIG.

  The capacitive element of the second modification is that the cap insulating film CP1 is formed in a partial region of the upper surface of the electrode 16, and the semiconductor device according to the second embodiment described with reference to FIGS. And different. The other points are the same as those of the capacitor in the second embodiment.

  As shown in FIGS. 41 and 42, a cap insulating film CP1 is formed on a portion of the electrode 16 located in a region surrounding the opening OP2. The cap insulating film CP1 is made of an insulating film IF3 such as a silicon nitride film.

  Note that the metal silicide film 33 is not formed in the region of the upper surface of the electrode 16 where the cap insulating film CP1 is formed. On the other hand, the metal silicide film 33 is formed in the region near the plug PG1 on the upper surface of the electrode 16, but the cap insulating film CP1 is not formed.

  Also in the second modification, the plug PG2 can be electrically connected to any part of the electrode 23 with a low resistance as in the second embodiment, and the electrode 16 and the electrode 23 are electrically connected by the plug PG2. A short circuit can be prevented, and the capacity of the capacitor can be easily increased.

  On the other hand, in the second modification, a region of the electrode 16 that is in contact with the electrode 23 via the capacitive insulating film 27 in plan view is covered with the cap insulating film CP1. Therefore, in the second modification, it is possible to more reliably prevent the adjacent electrode 16 and the electrode 23 from being electrically short-circuited as compared with the second embodiment.

<Method for Manufacturing Semiconductor Device>
About the manufacturing method of the semiconductor device of this Embodiment 2, it is the same as the process demonstrated in Embodiment 1 using FIGS. 14-16, FIGS. 20-22, FIGS. 25-31, and FIG. These steps can be performed.

  However, in the second embodiment, the opening OP2 (see FIG. 35) is formed when the conductive film CF1 is patterned in the same process as described with reference to FIG. Further, in a process similar to the process described with reference to FIG. 20, the insulating film IF <b> 2 is formed on the semiconductor substrate 10 including the inside of the opening OP <b> 2 and the surface of the electrode 16. Further, in the same process as described with reference to FIG. 22, the conductive film CF2 is etched back, so that the conductive film CF1 is formed inside the opening OP2 and on the peripheral side surface of the electrode 16 via the insulating film IF2. Leave. In the same process as described with reference to FIG. 12, the contact hole CH2 is formed in the opening OP2 through the interlayer insulating film 34 in a region overlapping the opening OP2 in plan view. The plug PG2 is electrically connected to the electrode 23 formed inside the opening OP2.

<Main features and effects of the present embodiment>
In the second embodiment, the electrode 23 is formed inside the opening OP <b> 2 that penetrates the electrode 16. In the second embodiment, as in the first embodiment, the plug PG2 made of the conductive film embedded in the contact hole CH2 is formed inside the opening OP2 through the interlayer insulating film 34. The electrode 23 is directly electrically connected. A metal silicide film 33 is formed on the surface of the electrode 23 formed inside the opening OP2. With such a configuration, the plug PG2 is connected to any part of the electrode 23 formed inside the opening OP2 via the metal silicide film 33 having a relatively small electrical resistance formed on the surface of the electrode 23. Can be electrically connected. Therefore, the plug PG2 can be electrically connected to any part of the electrode 23 formed inside the opening OP2 with low resistance.

  In the second embodiment, the electrode 23 formed in the opening OP2 does not overlap the electrode 16 in plan view. Therefore, the contact hole CH2 does not pass through the interlayer insulating film 34, the electrode 23, and the capacitor insulating film 27 and reach the electrode 16, but the electrode 23 and the electrode 16 are formed by the plug PG2 made of a conductive film embedded in the contact hole CH2. Are not short-circuited, so that the performance of the semiconductor device can be improved.

(Embodiment 3)
In the first embodiment, the dummy electrode DE is formed and the plug PG2 is electrically connected to the portion of the electrode 23 formed on the side surface of the dummy electrode DE (see FIG. 3). On the other hand, in the third embodiment, an example in which the dummy electrode DE is not formed and the plug PG3 is electrically connected to a portion of the electrode 23 located between adjacent line portions LP1 (see FIG. 43 described later). explain.

  FIG. 43 is a plan view showing the capacitive element in the third embodiment. 43 is the same as the sectional view of the capacitive element in the first modification of the first embodiment described with reference to FIG. As shown in FIGS. 43 and 5, the capacitive element in the third embodiment is the same as the capacitive element in the first modification of the first embodiment except that the dummy electrode DE (see FIG. 3) is not formed. Can be similar.

  Therefore, in the third embodiment, the plug PG2 (see FIG. 4) in the first modification of the first embodiment is not formed, and only the plug PG1 and the plug PG3 are formed.

  In the third embodiment, as in the first embodiment, the plug PG3 can be electrically connected to the portion located between the adjacent line portions LP1 in the electrode 23 with low resistance. 23 can be prevented from being electrically short-circuited, and the capacity of the capacitor can be easily increased.

  On the other hand, in the third embodiment, as in the first modification of the first embodiment, the width of the line portion LP1 is larger than that in the first embodiment, but the plug PG1 is electrically directly connected to the line portion. Therefore, the plug PG1 can be electrically connected to the electrode 16 with a lower resistance.

  As in the first embodiment, when patterning the conductive film CF1, it is necessary to prevent the opening OP1 (see FIG. 6) formed between the adjacent line portions LP1 from penetrating the conductive film CF1. The present invention can also be applied to the third embodiment and the modifications of the third embodiment. At this time, the electrode 16 includes a connection portion CN1 that connects the bottom portions of the adjacent line portions LP1 as shown in FIG.

<First Modification of Capacitance Element>
FIG. 44 is a plan view showing a capacitive element in a first modification of the third embodiment. 44 is the same as the cross-sectional view of the capacitive element in the first modification of the first embodiment described with reference to FIG.

  The capacitive element in the first modified example is provided with a line portion LP2, and the plurality of plugs PG1 are electrically directly connected not only to each of the plurality of line portions LP1 but also to the line portion LP2. FIG. 43 is different from the capacitor in the third embodiment described with reference to FIG. Other points are the same as those of the capacitor in the third embodiment.

  As shown in FIG. 44, the electrode 16 includes a plurality of line portions LP1 and line portions LP2. The plurality of line portions LP1 extend in the Y-axis direction and are arranged in the X-axis direction in plan view. The line part LP2 extends in the X-axis direction in plan view, and is connected to one end of the plurality of line parts LP1 in the Y-axis direction. With such a configuration, the plurality of line portions LP1 are electrically connected to each other via the line portion LP2, and the electrode 16 including the plurality of line portions LP1 and the line portion LP2 has a comb-like shape in plan view. Has a shape.

  The contact hole CH1 penetrates through the interlayer insulating film 34 (see FIG. 5) and reaches not only the plurality of line portions LP1 but also the line portions LP2. The plug PG1 is made of a conductive film embedded in the contact hole CH1, and is electrically connected not only to the plurality of line portions LP1 but also to the line portions LP2.

  Also in the first modification, the plug PG3 can be electrically connected to any part of the electrode 23 with a low resistance, and the electrode 16 and the electrode 23 are electrically short-circuited, as in the third embodiment. Can be prevented, and the capacitance of the capacitor can be easily increased.

  On the other hand, in the first modification, the area of the side surface of the electrode 23 facing the side surface of the electrode 16 is increased as compared with the third embodiment, so that the capacitance of the capacitive element can be easily increased. Further, in the first modification, the number of plugs PG1 that are electrically directly connected to the electrode 16 is increased as compared with the third embodiment, so that the plug PG1 is electrically connected to the electrode 16 with a lower resistance. be able to.

<Second Modification of Capacitance Element>
FIG. 45 is a plan view showing a capacitive element in a second modification of the third embodiment, and FIG. 46 is a cross-sectional view showing a capacitive element in the second modification of the third embodiment. 46 is a cross-sectional view taken along line AA in FIG.

  The capacitive element of the second modification example is the first of the third embodiment described with reference to FIGS. 44 and 5 in that a cap insulating film CP1 is formed in a partial region of the upper surface of the electrode 16. Different from the capacitive element in the modification. Other points are the same as those of the capacitive element in the first modification of the third embodiment.

  As shown in FIGS. 45 and 46, on the line part LP1 and on a part of the line part LP2, that is, on a part of the electrode 16, at least in a plan view, the capacitive insulating film 27 is interposed. A cap insulating film CP <b> 1 is formed in a region in contact with the electrode 23. The cap insulating film CP1 is made of an insulating film IF3 such as a silicon nitride film.

  Note that the metal silicide film 33 is not formed in the region where the cap insulating film CP1 is formed in the upper surface of the line portion LP1. On the other hand, in the region near the plug PG1 on the upper surface of the line portion LP2, the metal silicide film 33 is formed, but the cap insulating film CP1 is not formed.

  In the second modified example, since the metal silicide film 33 is not formed on the line portion LP1, the plug PG1 is not electrically connected directly to the line portion LP1, but is electrically connected to the line portion LP2. Directly connected.

  Similarly to the first modification of the third embodiment, the second modification can also connect the plug PG3 to any part of the electrode 23 with low resistance, and the electrode 16 and the electrode 23 can be connected by the plug PG3. Can be prevented from being electrically short-circuited, and the capacitance of the capacitor can be easily increased.

  On the other hand, in the second modification, a region of the electrode 16 that is in contact with the electrode 23 via the capacitive insulating film 27 in plan view is covered with the cap insulating film CP1. Therefore, in the second modification, it is possible to more reliably prevent the adjacent electrode 16 and the electrode 23 from being electrically short-circuited as compared to the first modification of the third embodiment.

<Method for Manufacturing Semiconductor Device>
About the manufacturing method of the semiconductor device of this Embodiment 3, it is the same as the process demonstrated in Embodiment 1 using FIGS. 14-16, FIGS. 20-22, FIGS. 25-31, and FIG. These steps can be performed.

  However, in the third embodiment, the dummy electrode DE (see FIG. 16) is not formed when patterning the conductive film CF1 in the same process as described with reference to FIG. An electrode 16 including a plurality of line portions LP1 (see FIG. 43) extending and arranged in the X-axis direction is formed by the conductive film CF1. Further, since the dummy electrode DE (see FIG. 16) is not formed in the same process as described with reference to FIG. 20, the insulating film IF2 is formed on the semiconductor substrate 10 including the surface of the electrode 16. . Further, since the dummy electrode DE (see FIG. 22) is not formed in the same process as described with reference to FIG. 22, the conductive film CF2 is etched back so that the insulating film is formed on the peripheral side surface of the electrode 16. The conductive film CF1 is left through IF2. Further, in a process similar to the process described with reference to FIG. 12, the contact hole CH3 is formed so as to penetrate the interlayer insulating film 34 and reach a portion of the electrode 23 located between the adjacent line portions LP1. The plug PG3 is electrically connected to a portion of the electrode 23 located between the adjacent line portions LP1.

<Main features and effects of the present embodiment>
In the present third embodiment, as in the first embodiment, the plug PG3 made of a conductive film embedded in the contact hole CH3 penetrates the interlayer insulating film 34 and is between the adjacent line portions LP1 in the electrode 23. It is electrically connected directly to the part located at. A metal silicide film 33 is formed on a portion of the electrode 23 located between adjacent line portions LP1. With such a configuration, the plug PG3 can be electrically connected to any part of the electrode 23 via the metal silicide film 33 formed on the surface of the electrode 23 and having a relatively small electrical resistance. Therefore, the plug PG3 can be electrically connected to any part of the electrode 23 with a low resistance.

  In the third embodiment, the electrode 23 does not overlap the electrode 16 in plan view. Therefore, the contact hole CH3 does not reach the electrode 16 through the interlayer insulating film 34, the electrode 23, and the capacitor insulating film 27, and the electrode 23 and the electrode 16 are formed by the plug PG3 made of a conductive film embedded in the contact hole CH3. Are not short-circuited, so that the performance of the semiconductor device can be improved.

(Embodiment 4)
In Embodiment 1, an example in which one capacitor is formed over the element isolation region has been described. In Embodiment 4, a structure in which a plurality of capacitors are formed over a conductive semiconductor substrate will be described.

  The planar arrangement of the capacitive elements in the fourth embodiment is the same as the planar arrangement of the capacitive elements in the first embodiment described with reference to FIG. Differences between the fourth embodiment and the first embodiment appear in the sectional view.

  FIG. 47 is a cross-sectional view of the capacitive element in the fourth embodiment. 47 corresponds to a cross-sectional view taken along the line AA in FIG.

  As shown in FIG. 47, an element isolation region 11 is formed in the semiconductor substrate 10, and a capacitor element is formed in an active region sandwiched between the element isolation regions 11. That is, the semiconductor device according to the fourth embodiment is formed on the lower electrode using the semiconductor substrate 10 as an electrode, the capacitive insulating film 14 made of the insulating film IF1 formed on the semiconductor substrate 10, and the capacitive insulating film 14. And an upper electrode formed of the electrode 16. A first capacitor element is formed by the lower electrode using the semiconductor substrate 10 as an electrode, the capacitor insulating film 14, and the upper electrode including the electrode 16.

  Similarly to the first embodiment, the electrode 16, the capacitor insulating film 27, and the electrode 23 form a second capacitor element.

  Although illustration is omitted, the third capacitor element can also be formed by the lower electrode using the semiconductor substrate 10 as an electrode, the capacitor insulating film 27, and the upper electrode made of the electrode 23.

  The manufacturing method of the semiconductor device in the fourth embodiment is the same as the manufacturing method of the capacitive element in the first embodiment, except that a capacitive element is formed on the semiconductor substrate 10 as an active region sandwiched between the element isolation regions 11. It is the same.

  In the fourth embodiment, the first capacitor element and the second capacitor element are formed. Therefore, by connecting the first capacitor element and the second capacitor element in parallel, it is possible to form a capacitor element having a large capacitance value with an occupied area equivalent to that of the first embodiment. Connecting the first capacitor element and the second capacitor element in parallel can be realized by setting the semiconductor substrate 10 and the electrode 23 to the same potential.

  In the fourth embodiment, the capacitive element of the first embodiment is formed not on the element isolation region 11 but on the semiconductor substrate 10 sandwiched between the element isolation regions 11. However, in the fourth embodiment, including the first embodiment, the capacitive element in each embodiment and each modification of the embodiment is sandwiched not by the element isolation region 11 but by the element isolation region 11. The present invention is also applicable when forming on the semiconductor substrate 10.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention includes at least the following embodiments.

[Appendix 1]
(A) forming a first conductive film on a semiconductor substrate;
(B) patterning the first conductive film, forming a first electrode made of the first conductive film, and forming a first dummy electrode made of the first conductive film apart from the first electrode;
(C) forming a first insulating film on the first semiconductor substrate including the surface of the first electrode and the surface of the first dummy electrode;
(D) forming a second conductive film on the first insulating film;
(E) Etching back the second conductive film between the first electrode and the first dummy electrode, on the peripheral side surface of the first electrode, and on the peripheral side surface of the first dummy electrode, Forming a second electrode leaving the second conductive film through a first insulating film;
(F) The portion of the first insulating film that is not covered with the second electrode is removed, and a first capacitive insulating film formed of the first insulating film between the first electrode and the second electrode is formed. The process of
(G) forming an interlayer insulating film so as to cover the first electrode, the second electrode, and the first capacitor insulating film;
(H) a first connection hole that reaches the first electrode through the interlayer insulating film; and a first electrode side of the first dummy electrode of the second electrode that penetrates the interlayer insulating film; Forming a second connection hole reaching the first portion formed on the opposite side surface;
(I) The third conductive film is formed of a third conductive film embedded in the first connection hole, electrically connected to the first electrode, and the third connection electrode embedded in the second connection hole. Forming a second connection electrode made of a conductive film and electrically connected to the first portion of the second electrode;
Have
In the step (f), a first capacitor element is formed by the first electrode, the second electrode, and the first capacitor insulating film.

[Appendix 2]
In the method for manufacturing a semiconductor device according to attachment 1,
In the step (e), by patterning and etching back the second conductive film, the peripheral surface of the first electrode, the periphery of the first dummy electrode, between the first electrode and the first dummy electrode. A method of manufacturing a semiconductor device, wherein the second electrode is formed on a side surface and in a partial region of the upper surface of the first electrode, leaving the second conductive film through the first insulating film.

[Appendix 3]
In the method for manufacturing a semiconductor device according to attachment 1,
(J) After the step (f) and before the step (g), a first metal silicide film is formed on the surface of the first conductive film, and a second metal silicide film is formed on the surface of the second conductive film. Forming a process,
Have
In the step (i), the first connection electrode in contact with the first metal silicide film is formed, and the second connection electrode in contact with the second metal silicide film is formed.

[Appendix 4]
In the method for manufacturing a semiconductor device according to attachment 1,
(K) Before the step (a), in the first region on the first main surface side of the semiconductor substrate and the second region on the first main surface side of the semiconductor substrate, the first of the semiconductor substrate Forming a second insulating film on the main surface;
Have
In the step (a), the first conductive film is formed on the second insulating film in the first region and the second region,
In the step (b), the first conductive film and the second insulating film are patterned in the first region and the second region, and the first electrode and the first dummy electrode are formed in the first region. Forming a first gate electrode made of the first conductive film and a first gate insulating film made of the second insulating film between the first gate electrode and the semiconductor substrate in the second region; And
In the step (c), in the first region and the second region, the surface of the first electrode, the surface of the first dummy electrode, and the surface of the first gate electrode are formed on the first semiconductor substrate. Forming the first insulating film;
In the step (d), the second conductive film is formed on the first insulating film in the first region and the second region,
In the step (e), by etching back the second conductive film in the first region and the second region, the second electrode is formed in the first region, and in the second region, Forming a second gate electrode on the side surface of the first gate electrode, leaving the second conductive film through the first insulating film;
In the step (f), in the first region and the second region, a portion of the first insulating film that is not covered by any of the second electrode and the second gate electrode is removed, and the first region is removed. Forming the first capacitor insulating film in a region; and, in the second region, the first insulating film between the first gate electrode and the second gate electrode, and the second gate electrode and the semiconductor. Forming a second gate insulating film made of the first insulating film between the substrate and the substrate;
(L) After the step (f) and before the step (g), in the second region, the source region and the drain region are aligned with the first gate electrode and the second gate electrode in the semiconductor substrate. The process of forming into,
Have
In the step (g), in the first region and the second region, the first electrode, the second electrode, the first capacitance insulating film, the first gate electrode, the second gate electrode, the second Forming the interlayer insulating film so as to cover the gate insulating film, the source region and the drain region;
In the step (h), the first connection hole and the second connection hole are formed in the first region, and in the second region, the third region reaches the source region through the interlayer insulating film. Forming a connection hole and a fourth connection hole reaching the drain region through the interlayer insulating film;
In the step (i), the first connection electrode and the second connection electrode are formed in the first region, and the third conductive film embedded in the third connection hole is formed in the second region. Forming a third connection electrode electrically connected to the source region, and comprising the third conductive film embedded in the fourth connection hole, and a fourth connection electrically connected to the drain region. Forming electrodes,
In the step (l), a memory cell is formed by the first gate insulating film, the first gate electrode, the second gate electrode, and the second gate insulating film.

[Appendix 5]
In the method for manufacturing a semiconductor device according to attachment 1,
(M) a step of forming an element isolation region in the semiconductor substrate before the step (a);
Have
In the step (a), the first conductive film is formed on the element isolation region.

[Appendix 6]
(A) forming a first conductive film on a semiconductor substrate;
(B) patterning the first conductive film to form a first electrode made of the first conductive film and a first opening penetrating the first electrode;
(C) forming a first insulating film on the first semiconductor substrate including the inside of the first opening and the surface of the first electrode;
(D) forming a second conductive film on the first insulating film;
(E) Etching back the second conductive film, leaving the second conductive film inside the first opening and on the peripheral side surface of the first electrode with the first insulating film interposed therebetween. Forming a second electrode;
(F) The portion of the first insulating film that is not covered with the second electrode is removed, and a first capacitive insulating film formed of the first insulating film between the first electrode and the second electrode is formed. The process of
(G) forming an interlayer insulating film so as to cover the first electrode, the second electrode, and the first capacitor insulating film;
(H) forming a first connection hole that reaches the first electrode through the interlayer insulating film, and a second connection hole that reaches the second electrode through the interlayer insulating film;
(I) The third conductive film is formed of a third conductive film embedded in the first connection hole, electrically connected to the first electrode, and the third connection electrode embedded in the second connection hole. Forming a second connection electrode made of a conductive film and electrically connected to the second electrode;
Have
In the step (f), a first capacitor element is formed by the first electrode, the second electrode, and the first capacitor insulating film.

[Appendix 7]
(A) forming a first conductive film on a semiconductor substrate;
(B) patterning the first conductive film to form a first electrode made of the first conductive film;
(C) forming a first insulating film on the first semiconductor substrate including the surface of the first electrode;
(D) forming a second conductive film on the first insulating film;
(E) forming a second electrode by etching back the second conductive film, leaving the second conductive film on the peripheral side surface of the first electrode via the first insulating film;
(F) The portion of the first insulating film that is not covered with the second electrode is removed, and a first capacitive insulating film formed of the first insulating film between the first electrode and the second electrode is formed. The process of
(G) forming an interlayer insulating film so as to cover the first electrode, the second electrode, and the first capacitor insulating film;
(H) forming a first connection hole that reaches the first electrode through the interlayer insulating film, and a second connection hole that reaches the second electrode through the interlayer insulating film;
(I) The third conductive film is formed of a third conductive film embedded in the first connection hole, electrically connected to the first electrode, and the third connection electrode embedded in the second connection hole. Forming a second connection electrode made of a conductive film and electrically connected to the second electrode;
Have
In the step (f), a first capacitor element is formed by the first electrode, the second electrode, and the first capacitor insulating film,
In the step (b), the first electrode including a plurality of first line portions each extending in a first direction and arranged in a second direction intersecting the first direction in a plan view. A method for manufacturing a semiconductor device, comprising: forming a first conductive film.

[Appendix 8]
A semiconductor substrate;
A first electrode comprising a first conductive film formed on the semiconductor substrate;
A first dummy electrode formed on the semiconductor substrate apart from the first electrode and made of a second conductive film in the same layer as the first conductive film;
A second electrode composed of a third conductive film formed between the first electrode and the first dummy electrode, a peripheral side surface of the first electrode, and a peripheral side surface of the first dummy electrode;
A first capacitive insulating film made of a first insulating film formed between the first electrode and the second electrode;
An interlayer insulating film formed to cover the first electrode, the second electrode, and the first capacitor insulating film;
A first connection hole reaching the first electrode through the interlayer insulating film;
A second connection hole that penetrates through the interlayer insulating film and reaches a first portion of the second electrode that is formed on a side surface opposite to the first electrode side of the first dummy electrode;
A first connection electrode comprising a fourth conductive film embedded in the first connection hole and electrically connected to the first electrode;
A second connection electrode made of a fifth conductive film embedded in the second connection hole and electrically connected to the first portion of the second electrode;
Have
A first capacitive element is formed by the first electrode, the second electrode, and the first capacitive insulating film;
The first electrode is
A plurality of first line portions each extending in a first direction and arranged in a second direction intersecting the first direction in a plan view;
A connecting portion connecting the bottoms of the adjacent first line portions;
Including
The first dummy electrode is a semiconductor device that extends in the second direction and is disposed on one side in the first direction of the plurality of first line portions in plan view.

[Appendix 9]
A semiconductor substrate;
A first electrode comprising a first conductive film formed on the semiconductor substrate;
A first opening formed in the first electrode;
A second electrode made of a second conductive film formed inside the first opening and on a peripheral side surface of the first electrode;
A first capacitive insulating film made of a first insulating film formed between the first electrode and the second electrode;
An interlayer insulating film formed to cover the first electrode, the second electrode, and the first capacitor insulating film;
A first connection hole reaching the first electrode through the interlayer insulating film;
A second connection hole penetrating through the interlayer insulating film and reaching a first portion of the second electrode formed in the first opening;
A first connection electrode made of a third conductive film embedded in the first connection hole and electrically connected to the first electrode;
A second conductive electrode made of a fourth conductive film embedded in the second connection hole, electrically connected to the first portion of the second electrode;
Have
A semiconductor device, wherein a first capacitor element is formed by the first electrode, the second electrode, and the first capacitor insulating film.

[Appendix 10]
A semiconductor substrate;
A first electrode comprising a first conductive film formed on the semiconductor substrate;
A second electrode made of a second conductive film formed on a peripheral side surface of the first electrode;
A first capacitive insulating film formed between the first electrode and the second electrode;
An interlayer insulating film formed to cover the first electrode, the second electrode, and the first capacitor insulating film;
A first connection hole reaching the first electrode through the interlayer insulating film;
A second connection hole that penetrates the interlayer insulating film and reaches the second electrode;
A first connection electrode made of a third conductive film embedded in the first connection hole and electrically connected to the first electrode;
A second connection electrode made of a fourth conductive film embedded in the second connection hole and electrically connected to the second electrode;
Have
A first capacitive element is formed by the first electrode, the second electrode, and the first capacitive insulating film;
The first electrode is
A plurality of first line portions each extending in a first direction and arranged in a second direction intersecting the first direction in a plan view;
A connecting portion connecting the bottoms of the adjacent first line portions;
Including a semiconductor device.

1 CPU
2 RAM
3 Analog circuit 4 Flash memory 10 Semiconductor substrate 10a Surface 11 Element isolation region 12 P-type well 13 Gate insulating film 14 Capacitor insulating film 15 Control gate electrodes 16 and 23 Electrodes 17 and 19 Silicon oxide film 18 Silicon nitride films 22a and 22b Side walls 25 charge storage film 26 memory gate electrode 27 capacitive insulating film 27a insulating film 28 low concentration impurity diffusion regions 29a to 29d sidewall 30 high concentration impurity diffusion region 33 metal silicide film 34 interlayer insulating film AR1 memory cell region AR2 capacitive element formation region CF1 , CF2 conductive film CH1 to CH4 contact hole CHP semiconductor chip CN1 connection portion CP1 cap insulating film DE dummy electrodes DST1 to DST3 distance HL1 to HL4 wiring IF1 to IF3 insulating film LP1, LP2 line portions OP1, OP Opening PD pad PG1~PG4 plug PR1, PR2 resist film TH1, TH2 thickness WT1 opening width

Claims (10)

A semiconductor substrate;
A first electrode comprising a first conductive film formed on the semiconductor substrate;
A first opening penetrating the first electrode;
A second electrode made of a second conductive film formed inside the first opening and on a peripheral side surface of the first electrode;
A first capacitive insulating film made of a first insulating film formed between the first electrode and the second electrode;
An interlayer insulating film formed to cover the first electrode, the second electrode, and the first capacitor insulating film;
A first connection hole reaching the first electrode through the interlayer insulating film;
A second connection hole penetrating through the interlayer insulating film and reaching a first portion of the second electrode formed in the first opening;
A first connection electrode made of a third conductive film embedded in the first connection hole and electrically connected to the first electrode;
A second conductive electrode made of a fourth conductive film embedded in the second connection hole, electrically connected to the first portion of the second electrode;
Have
A semiconductor device, wherein a first capacitor element is formed by the first electrode, the second electrode, and the first capacitor insulating film. The semiconductor device according to claim 1,
The second electrode is composed of the second conductive film formed in the first opening and a partial region of the upper surface of the first electrode,
The second connection hole is a semiconductor device that reaches the second electrode through the interlayer insulating film in a region overlapping the first opening in a plan view. The semiconductor device according to claim 2,
In plan view, the first opening extends in a first direction,
The semiconductor device, wherein the inside of the first opening is filled with the second conductive film. The semiconductor device according to claim 2,
In plan view, the first opening extends in a first direction,
The second conductive film is formed on a side surface and a bottom surface of the first opening,
A second insulating film formed on the second conductive film inside the first opening;
The inside of the first opening is a semiconductor device embedded with the second insulating film via the second conductive film. The semiconductor device according to claim 2,
A cap insulating film formed in a region surrounding the first opening in the upper surface of the first electrode;
The first connection hole is a semiconductor device that penetrates through the interlayer insulating film and reaches a region of the upper surface of the first electrode where the cap insulating film is not formed. The semiconductor device according to claim 1,
An element isolation region formed in the semiconductor substrate;
The semiconductor device, wherein the first electrode includes the first conductive film formed on the element isolation region. A semiconductor substrate;
A first electrode comprising a first conductive film formed on the semiconductor substrate;
A second electrode made of a second conductive film formed on a peripheral side surface of the first electrode;
A first capacitive insulating film formed between the first electrode and the second electrode;
An interlayer insulating film formed to cover the first electrode, the second electrode, and the first capacitor insulating film;
A first connection hole reaching the first electrode through the interlayer insulating film;
A second connection hole that penetrates the interlayer insulating film and reaches the second electrode;
A first connection electrode made of a third conductive film embedded in the first connection hole and electrically connected to the first electrode;
A second connection electrode made of a fourth conductive film embedded in the second connection hole and electrically connected to the second electrode;
Have
A first capacitive element is formed by the first electrode, the second electrode, and the first capacitive insulating film;
The first electrode includes a plurality of first line portions each extending in a first direction and arranged in a second direction intersecting the first direction in plan view. The semiconductor device according to claim 7.
The second electrode is formed between the adjacent first line portions,
The first connection hole passes through the interlayer insulating film and reaches the first line portion,
The second connection hole passes through the interlayer insulating film and reaches a first portion located between the adjacent first line portions of the second electrode,
The first connection electrode is electrically connected to the first line portion,
The semiconductor device, wherein the second connection electrode is electrically connected to the first portion of the second electrode. The semiconductor device according to claim 8.
The first electrode includes a second line portion that extends in the second direction in plan view and is connected to one end of each of the plurality of first line portions;
A third connection hole passing through the interlayer insulating film and reaching the second line portion;
A third connection electrode made of a fifth conductive film embedded in the third connection hole and electrically connected to the second line portion;
A semiconductor device. The semiconductor device according to claim 7.
The first electrode includes a third line portion that extends in the second direction in plan view and is connected to one end of each of the plurality of first line portions;
A cap insulating film formed on an upper surface of the first line portion;
The second electrode is formed between the adjacent first line portions,
The first connection hole passes through the interlayer insulating film and reaches the third line portion,
The second connection hole penetrates the interlayer insulating film and reaches a second portion located between the adjacent first line portions of the second electrode,
The first connection electrode is electrically connected to the third line portion,
The semiconductor device, wherein the second connection electrode is electrically connected to the second portion of the second electrode.

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