JP2003244940A - Semiconductor device equipped with boosting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is equipped with a boosting circuit constituted so that it can avoid an adverse influence on other circuits by lessening a voltage ripple at start-up by changing the conditions of boosting action so as to suppress current consumption at the start-up. <P>SOLUTION: A charge pump unit, which has a MOS transistor and a capacitor supplied with clocks at its the other end, is equipped with a plurality of charge pump means which are connected in series and a clock-generating means which generates capacity limiting clocks with their current supply capacity to a capacitor being limited as clocks until predetermined specified conditions are satisfied (for example, time or output voltage value) after receiving a start signal. Hereby, this suppresses the current consumption at the start of a boosting circuit, thereby lessening the ripple of a power voltage. <P>COPYRIGHT: (C)2003,JPO

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a booster circuit for obtaining a high voltage from a low voltage power supply. 2. Description of the Related Art Conventionally, as semiconductor devices (hereinafter, ICs) such as EEPROMs and flash memories have a single low-voltage power supply, for example, a voltage necessary for writing or erasing stored contents has been reduced by the IC. , The power supply voltage is being boosted. For this purpose, a booster circuit such as a charge pump circuit is provided in the IC. FIG. 7 is a diagram showing a configuration of a conventional booster circuit. In FIG. 7, the first-stage charge pump unit U1
, An N-stage charge pump unit (hereinafter, may be referred to as a unit) is connected in series from the output stage to a charge pump unit Un, and a high-current pump CP
1. The power supply voltage Vd is applied to the first unit U1.
d (for example, 2V or 3V) is supplied. Further, from the output side of the unit Un of the output stage, an output smoothing circuit including an N-type MOS transistor Qo for a high withstand voltage having a source and a gate connected, and a capacitor Co connected between the drain side and a ground potential is provided. Via the power supply voltage Vdd
Output voltage Vout (for example, 10
V) is output. Each of the units U1 to Un has a similar configuration. For example, when the unit U1 is described as an example, it includes an N-type MOS transistor Q1 for high withstand voltage and a capacitor C1. The source S of the N-type MOS transistor Q1 is supplied with the power supply voltage Vdd and is connected to the gate G, which is a so-called diode connection. The drain D is the N-type MOS of the next unit U2.
The substrate is connected to the source S of the transistor Q2, and its substrate is connected to the lowest potential point, in this example, the ground potential. The capacitor C1 has one end connected to the drain D and the other end connected to a clock line (in this case, a clock line of the first clock CLK1). The capacitor of each unit is connected to the clock line of the first clock CLK1 in the odd-numbered units U1, U3, etc., and is connected to the even-numbered units U2, U3.
4 is connected to the clock line of the second clock CLK2. A first clock CLK1 and a second clock C
LK2 is, for example, a two-phase clock that has the same amplitude voltage as the power supply voltage Vdd, has a predetermined frequency, and changes in almost the opposite phase. The first clock CLK1 is output by amplifying the clock signal clk in the first buffer B1. The second clock CLK2 is a clock signal cl.
k is inverted by the inverting circuit NOT1, amplified by the second buffer B2, and output. In the booster circuit of FIG. 7, upon receiving a start signal (not shown), clock signal clk is driven to an H level /
When the change to the L level starts alternately, the first buffer B1
And the inverting circuit NOT1 and the second buffer B2,
The clock CLK1 and the second clock CLK2 start to change in the opposite phase. In response to the start of the operation of the first clock CLK1 and the second clock CLK2, the units U1 to Un simultaneously start the charge pump operation, and the power supply voltage Vdd is sequentially charged up and boosted for each unit. Output voltage Vout is output. This output voltage Vout
Is supplied to a predetermined terminal such as an EEPROM. In this booster circuit, the capacitors C1 to Cn of each unit U1 to Un
A capacitor having a relatively large capacity is used so that a required current can be supplied together with the output voltage Vout. Therefore, immediately after the start, a large current is consumed by the units U1 to Un that start operating at the same time.
The power supply voltage drops due to the voltage drop and becomes unstable. This fluctuation of the power supply voltage occurs every time the booster circuit is started. Therefore, a malfunction (eg, a write operation or a read operation) of a logic circuit or the like in a semiconductor device in which the booster circuit is incorporated may cause a malfunction. It may cause adverse effects such as inducing. If the capacity of the power supply circuit is allowed to withstand a current change, such a change can be avoided. However, for example, in a semiconductor device which is required to be reduced in size and weight such as for a portable device, It is difficult to have room. Therefore, the present invention reduces the voltage fluctuation at the start-up by changing the conditions of the boosting operation so as to suppress the current consumption at the start-up, thereby avoiding adverse effects on other circuits. It is an object of the present invention to provide a semiconductor device provided with a booster circuit configured. According to a first aspect of the present invention, there is provided a semiconductor device having a booster circuit, a MOS transistor having an input terminal and an output terminal, and one end connected to the output terminal of the MOS transistor. A charge pump unit having a capacitor connected to the other end and supplied with a clock, a plurality of charge pump units connected in series to output an output voltage whose power supply voltage has been boosted, and the generation of the clock in response to a start signal The clock generating means is configured to limit a current supply capability to the capacitor as the clock at least until the predetermined condition is satisfied after receiving the start signal. And generating a limited-capacity clock. According to the semiconductor device having the booster circuit according to the first aspect of the present invention, a period from when the start signal is received to when a predetermined condition, for example, time or output voltage value, is satisfied. Is supplied with a clock having a limited current supply capability to the capacitors of all the charge pump units.
Therefore, current consumption at the time of starting the booster circuit is suppressed, so that fluctuations in the power supply voltage can be reduced and influence on other circuits can be avoided. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device having a booster circuit according to the present invention will be described below with reference to FIGS. FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a diagram illustrating a circuit configuration of a semiconductor device including a booster circuit. FIG. 2 is a diagram illustrating a configuration example of a buffer that generates a clock, and FIG. 3 is a diagram illustrating a clock with a limited capacity and a normal clock. In FIG. 1, similarly to the conventional circuit shown in FIG. 7, N-stage units are connected in series from a first-stage charge pump unit U1 to an output-stage charge pump unit Un, and a high-current pump CP serving as charge pump means is provided.
The power supply voltage Vdd (for example, 2 V or 3 V) is supplied to the unit U1, and an N-type MOS transistor Qo, a capacitor C
a predetermined output voltage Vou via an output smoothing circuit
t (for example, 10 V) is output. Each unit U1
Un is the same as in the conventional FIG. 7, and corresponding components are denoted by the same reference numerals. Note that an output smoothing circuit including an N-type MOS transistor Qo and a capacitor Co is
In the first embodiment of FIG. 1, a clock signal generator CG for receiving a start signal St and outputting a clock signal clk, and a start signal St may be included in the high current pump CP1. After a predetermined time τ, the timer TD of the on-delay operation for raising the start-up control signal Scon from the L level to the H level, an inverting circuit NOT1 for inverting the clock signal clk, and the clock signal clk are input and synchronized with Start-up control signal Sc
The controllable first buffer B11 in which the current drive capability is controlled by ON, and the controllable control in which the clock drive signal clk inverted by the inverting circuit NOT1 is input and synchronized with the clock signal clk, and the current drive capability is controlled by the start-up control signal Scon. Second
And a buffer B21. These form a clock generating means. FIG. 2 is a diagram showing a configuration example of the controllable first buffer B11 (or the controllable second buffer B21) used in the first embodiment. In FIG.
A P-type MOS transistor Q21, a P-type MOS transistor Q22, an N-type M
OS transistor Q23 and N-type MOS transistor Q
24 are connected in this order. The start-up control signal Scon is supplied to the gate of the MOS transistor Q21 via the inverting circuit NOT3, and the start-up control signal Scon is directly supplied to the gate of the MOS transistor Q24. The MOS transistor Q21 is connected in parallel with a diode-connected P-type MOS transistor Q25, and the MOS transistor Q24 is connected in parallel with a diode-connected N-type MOS transistor Q26. Then, the MOS transistors Q22, Q2
The clock signal clk (or an inverted signal of the clock signal clk) is supplied to the gate of the third MOS transistor Q3, and the gate of the MOS transistor Q22 and the first MOS transistor Q23
The clock CLK1 (or the second clock CLK2) is output. Now, the operation of the booster circuit according to the present invention will be described with reference to FIGS. First, when the start signal St rises (H level), the clock signal generator CG immediately starts oscillating and generates a clock signal clk, while the timer TD starts measuring a predetermined time τ. I do. The clock signal clk is directly supplied to the controllable first buffer B11, and is also supplied to the controllable second buffer B21 via the inverting circuit NOT1. Thereby, the controllable first buffer B
11 and the controllable second buffer B21, a first clock CLK1 and a second clock CLK2, which are two-phase clocks having a predetermined frequency and changing in almost opposite phases, are:
Each is generated. A predetermined time τ from the rise of the start signal St
Since the start-up control signal Scon is at the L level state until the time elapses, the MOS transistor Q21
And the MOS transistor Q24 is off. Therefore, during the predetermined time τ, the diode-connected MOS transistor Q25 and MOS transistor Q2
6, the first clock CLK1 and the second clock CLK
2 will be output. The MOS transistor Q25 and the MOS
In the transistor Q26, the threshold voltage Vth
Since only a voltage drop occurs, as shown in FIG. 3A, the first clock CLK1 and the second clock CLK2
(I.e., the voltage difference between the H level and the L level) becomes smaller by that amount, and becomes Vdd-2Vth. The current consumption of the high current pump CP1 increases as the capacitance of the capacitors of the units U1 to Un increases.
The larger the fluctuation width of the opposite end (clock line side) of the capacitor is, the larger the fluctuation width of the first clock CLK1 and the second clock CLK2 is. Since the fluctuation width of the first clock CLK1 and the second clock CLK2 is reduced as described above, the ability of each unit U1 to Un to supply current to the capacitors C1 to Cn is limited. The current consumption is reduced. In particular, immediately after the start-up of the booster circuit, a large current (for example, 100 mA) is consumed, but the current consumed is reduced (for example, 40 mA) by limiting the current supply capability as in this embodiment. Therefore, although the time required for the output voltage Vout to reach the predetermined voltage value is slightly longer, the current consumption at the time of starting the booster circuit is suppressed, so that the fluctuation of the power supply voltage is reduced and the output voltage to other circuits is reduced. The effect of can be avoided. When a predetermined time τ has elapsed after the start, the start-time control signal Scon goes high, and the MOS
The transistor Q21 and the MOS transistor Q24 turn on. Thereby, the MOS transistors Q25 and M
Since the voltage drop due to the OS transistor Q26 is eliminated, the first clock CLK1 and the second clock CLK2
Is the fluctuation width of the power supply voltage Vdd, as shown in FIG. The current consumption of the booster circuit in the normal operation state depends on the load conditions, but is, for example, about 10 to 20 mA, which is much smaller than the current consumed at startup. Can be reduced. FIG. 4 is a diagram showing another embodiment of the first controllable buffer B11 and the second controllable buffer B21.
In this embodiment, the diode-connected MOS transistors Q25 and MOS
Instead of the constant voltage drop element of the transistor Q26, a resistor R
1 and a resistor R2. Since the resistors R1 and R2 function as current limiting elements, the controllable first buffer B1 shown in FIG.
1. The controllable second buffer B21 can also perform the current capability limiting function at the time of startup. Further, the resistance R
Similar effects can be obtained by providing another constant current source circuit instead of 1 and R2. This alternative to the resistor and the constant current source can be similarly applied to other embodiments. FIG. 5 shows a second embodiment of the present invention.
FIG. 3 is a diagram illustrating a circuit configuration of a semiconductor device including a booster circuit. In the second embodiment shown in FIG. 5,
For each of the units U1 to Un of the high current pump CP1,
Clamping means is provided for clamping the output voltage to the highest voltage supplied, that is, the power supply voltage Vdd. This clamping means comprises the units U1 to U
MOS provided between the output side of n and the power supply voltage Vdd
It is composed of transistors Q11 to Q1n (N-type MOS transistors in this example). The N-type MOS transistors Q11 to Q1n transmit the start signal St to the inverting circuit N
ON / OFF is controlled by the signal inverted by OT2. In the second embodiment, the configuration other than the clamp means is the same as that in the first embodiment of FIG. In FIG. 5, when the booster circuit is stopped, the N-type MOS transistors Q11 to Q1n are on, so the output voltages of the units U1 to Un, that is, all the capacitors C1 to Cn are connected to the power supply voltage. It is clamped to Vdd. When the start signal St rises, its H level is inverted by the inverting circuit NOT2 and becomes L level, so that the N-type MOS transistors Q11 to Q1n are turned off, whereby the clamp to the power supply voltage Vdd is released. You. Thereafter, the boosting operation is performed in the same manner as in the first embodiment shown in FIG. 1. At this time, the charging of the capacitors is required because each capacitor is clamped in advance to the power supply voltage Vdd. Low current consumption. Therefore, the current consumption at the time of starting can be further reduced as compared with the first embodiment. Further, if the current consumption is the same, the time for limiting the current capability can be shortened. In FIG. 5, when the booster circuit is stopped, the first controllable buffer B11 and the second controllable buffer B21 are normally controlled according to the conditions of the clock signal generator CG.
Are at H level and the other is at L level.
However, by adding a simple logic circuit controlled in accordance with the start signal St to the controllable first buffer B11 and the controllable second buffer B21, both outputs can be fixed at the L level. In this case, all the capacitors C1 to Cn can be charged to the power supply voltage Vdd. FIG. 6 shows a third embodiment of the present invention.
FIG. 3 is a diagram illustrating a circuit configuration of a semiconductor device including a booster circuit. In the third embodiment shown in FIG. 6,
Voltage comparison means V that compares the output voltage Vout of the booster circuit with a predetermined reference voltage and generates a start-up control signal Scon
com is provided. Thereby, the timer TD provided in the first and second embodiments is removed. An AND circuit AND is provided in place of the clock signal generator CG provided in the first and second embodiments, and a start signal St and a clock signal c supplied from the outside are provided.
A clock signal clk is output from the AND circuit AND according to an AND condition with lk. The provision of the AND circuit AND in place of the clock signal generator CG can be similarly performed in the first and second embodiments. Other configurations are the same as those of the second embodiment in FIG. The voltage comparison means Vcom outputs the output voltage Vou
t is divided by the resistors R3 and R4, and the comparison voltage Vs (= Vou
voltage dividing means for forming t × R3 / (R3 + R4), and dividing the power supply voltage Vdd by the resistors R5 and R6 to generate a reference voltage Vr
ef (= Vdd × R5 / (R5 + R6)), and the comparison voltage Vs is compared with the reference voltage Vref.
An operation amplifier OP1 that outputs a start-up control signal Scon when Vs> Vref, and N-type MOS transistors Q21 and Q22 connected between the resistor R3 and the ground and between the resistor R5 and the ground, respectively. In response to the rise of the start signal St, the N-type MOS transistors Q21 and Q22 are turned on, and the operational amplifier OP1 is turned on.
Is operable. As a result, wasteful power consumption during standby can be reduced. In FIG. 6, when the start signal St rises (H level), first, the MOS transistor Q11
ＱQ1n are turned off and the clamp operation is stopped. At the same time, an external clock signal clk is applied to the AND circuit AND
, The first clock CLK1 and the second clock CLK2 are respectively generated, and the charge pump operation is started. In this state, since the start-up control signal Scon is at the L level, the first clock CLK1 and the second clock C2 are set in the same manner as described in the first embodiment.
Since the fluctuation range of LK2 is small and the current supply capability to the capacitors C1 to Cn of each unit U1 to Un is limited,
The current consumption of the booster circuit is reduced. The output voltage Vout increases with the lapse of time from the rise of the start signal St. Output voltage Vo
ut becomes higher than the reference voltage Vref formed from the power supply voltage Vdd (Vs
> Vref), the output of the operational amplifier OP1, that is, the start-up control signal Scon becomes H level. As a result, the current capability limitation of the first controllable buffer B11 and the second controllable buffer B21 is released, and the first clock CLK1 and the second clock CLK2 are released.
Is the fluctuation width of the power supply voltage Vdd in the normal operation state. As described above, the output voltage Vout of the booster circuit
However, the current capability of the controllable first buffer B11 and the controllable second buffer B21 is limited until the voltage reaches a predetermined voltage after the start-up, and then the limited state is released to return to the normal state.
Therefore, although the time required for the output voltage Vout to reach the predetermined voltage value is slightly longer, the current consumption at the time of starting the booster circuit is suppressed, so that the fluctuation of the power supply voltage is reduced and the influence on other circuits is reduced. Can be avoided. In each of the embodiments described above, the current capability is limited to one stage. However, it is also possible to control the current capability to two or more other stages by using a similar method. Can be. The charge pump unit is not limited to the configuration in each of the above-described embodiments. For example, as a MOS transistor, an N-type well formed on a P-type substrate and a N-type well in the N-type well are formed. A P-type well formed, an N-type source region formed in the P-type well, an N-type drain region formed between the source region and the channel region, and an insulator formed above the channel via an insulator. Well type with a closed gate,
As the N-type well, a double-well type MOS transistor having a structure connected to a high potential point so as to be reversely biased between the P-type substrate and the P-type well can be used. Each unit may have a main NMOS transistor and a main capacitor, and a sub-NMOS transistor and a sub-capacitor, and may be configured to be driven by a four-phase clock. According to the semiconductor device having the booster circuit according to the first aspect of the present invention, a predetermined condition such as a time or an output voltage value is satisfied after the start signal is received. During this period, a clock having a limited current supply capability is supplied to the capacitors of all the charge pump units. Therefore, current consumption at the time of starting the booster circuit is suppressed, so that fluctuations in the power supply voltage can be reduced and influence on other circuits can be avoided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a circuit configuration of a semiconductor device including a booster circuit according to a first embodiment. FIG. 2 is a diagram illustrating a configuration example of a buffer that generates a clock. FIG. 3 is a diagram showing a clock with a limited current capability and a normal clock. FIG. 4 is a diagram illustrating another configuration example of a buffer that generates a clock. FIG. 5 is a diagram illustrating a circuit configuration of a semiconductor device including a booster circuit according to a second embodiment. FIG. 6 is a diagram illustrating a circuit configuration of a semiconductor device including a booster circuit according to a second embodiment. FIG. 7 illustrates a configuration of a conventional booster circuit. [Description of Signs] CP1, CP11 High current pumps U1 to Un Charge pump units Q1 to Qn, Q21 to Q26, Q11 to Q1n, Qo
MOS transistors C1 to Cn, Co capacitor B11 Controllable first buffer B21 Controllable second buffer NOT1, NOT2, NOT3 Inverting circuit CG Clock signal generator TD Timer R1 to R6 Resistance Vcom Voltage comparison means OP1 Operational amplifiers Q21, Q22 MOS transistors AND AND circuit clk Clock signal CLK1 First clock CLK2 Second clock St Start signal Scon Start control signal Vdd Power supply voltage Vout Output voltage

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Claims (1)

1. A charge pump unit comprising: a MOS transistor having an input terminal and an output terminal; and a capacitor having one end connected to the output terminal of the MOS transistor and a clock supplied to the other end. Comprises a plurality of charge pump units connected in series and outputting an output voltage whose power supply voltage has been boosted, and a clock generation unit that starts generation of the clock in response to a start signal. A boosting circuit for generating, as the clock, a performance limited clock having a limited current supply capability to the capacitor until a predetermined condition is satisfied after receiving the start signal. A semiconductor device comprising: