JP3566950B2 - Semiconductor device with booster circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device including a booster circuit for obtaining a high voltage from a low-voltage power supply.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, with the use of a single low-voltage power supply for a semiconductor device (hereinafter referred to as an IC) such as an EEPROM or a flash memory, for example, a power supply is required so that a voltage necessary for writing or erasing stored contents is obtained inside the IC. The voltage is increasing. For this purpose, a booster circuit such as a charge pump circuit is provided in the IC.
[0003]
FIG. 7 is a diagram showing a configuration of a conventional booster circuit. In FIG. 7, N stages of charge pump units (hereinafter, sometimes referred to as units) are connected in series from a first stage charge pump unit U1 to an output stage charge pump unit Un to form a high current pump CP1. ing. The power supply voltage Vdd (for example, 2 V or 3 V) is supplied to the first unit U1. Further, from the output side of the unit Un of the output stage, an output smoothing circuit including an N-type MOS transistor Qo for a high withstand voltage having a source and a gate connected, and a capacitor Co connected between the drain side and a ground potential is provided. Thus, a predetermined output voltage Vout (for example, 10 V) in which the power supply voltage Vdd is boosted is output.
[0004]
Each of the units U1 to Un has the same configuration. For example, when the unit U1 is described as an example, it includes an N-type MOS transistor Q1 for high withstand voltage and a capacitor C1. The source S of the N-type MOS transistor Q1 is supplied with the power supply voltage Vdd and is connected to the gate G, which is a so-called diode connection. The drain D is connected to the source S of the N-type MOS transistor Q2 of the next unit U2, and the substrate is connected to the lowest potential point, in this example, the ground potential. The capacitor C1 has one end connected to the drain D and the other end connected to a clock line (in this case, a clock line of the first clock CLK1).
[0005]
The capacitor of each unit is connected to the clock line of the first clock CLK1 in the odd-numbered units U1 and U3, and is connected to the clock line of the second clock CLK2 in the even-numbered units U2 and U4.
[0006]
The first clock CLK1 and the second clock CLK2 are, for example, two-phase clocks that have the same amplitude voltage as the power supply voltage Vdd, have a predetermined frequency, and change in almost the opposite phase. The first clock CLK1 is output by amplifying the clock signal clk in the first buffer B1. Further, the second clock CLK2 is obtained by inverting the clock signal clk by the inverting circuit NOT1, amplifying the clock signal clk by the second buffer B2, and outputting the amplified signal.
[0007]
In the booster circuit shown in FIG. 7, when the clock signal clk starts to alternately change to the H level / L level in response to the start signal (not shown), the first buffer B1 and the inverting circuits NOT1 and the second buffer B2. , The first clock CLK1 and the second clock CLK2 start to change in opposite phases.
[0008]
In response to the start of the operation of the first clock CLK1 and the second clock CLK2, the units U1 to Un simultaneously start the charge pump operation, the power supply voltage Vdd is sequentially charged up for each unit, and the boosted output voltage Vout Is output. This output voltage Vout is supplied to a predetermined terminal such as an EEPROM.
[0009]
[Problems to be solved by the invention]
In this booster circuit, the capacitors C1 to Cn of the units U1 to Un have relatively large capacities so that a required current can be supplied together with the output voltage Vout. Therefore, immediately after the start, a large current is consumed by the units U1 to Un that start operating at the same time, so that the power supply voltage is reduced due to the voltage drop and becomes unstable. This fluctuation of the power supply voltage occurs every time the booster circuit is started. Therefore, a malfunction (eg, a write operation or a read operation) of a logic circuit or the like in a semiconductor device in which the booster circuit is incorporated may cause a malfunction. It may cause adverse effects such as inducing.
[0010]
Such fluctuations can be avoided if the power supply circuit capacity is given a margin so that it can withstand a current change.However, for a semiconductor device that is required to be reduced in size and weight, such as for a portable device, a margin is provided. It is difficult to get them.
[0011]
In view of the above, the present invention provides a booster configured to reduce the voltage fluctuation at the time of startup and to avoid adverse effects on other circuits by changing the conditions of the boosting operation so as to suppress the current consumption at the time of startup. It is an object to provide a semiconductor device provided with a circuit.
[0012]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a semiconductor device having a booster circuit, a MOS transistor having an input terminal and an output terminal, a capacitor having one end connected to the output terminal of the MOS transistor and a clock supplied to the other end. A charge pump unit that outputs a boosted output voltage of a plurality of power supply voltages connected in series;
Clock generating means for receiving the start signal and starting generation of the clock,
Said clock generating means, the at least until the start signal receiving a predetermined condition is satisfied which is predetermined from, Rutotomoni amplitude current supply capability is limited to the capacitor as the clock from the supply voltage And generating a clock having an amplitude of the power supply voltage after the predetermined condition is satisfied .
[0013]
According to the semiconductor device having the booster circuit of claim 1 of the present invention, a period from when the start signal is received to when a predetermined condition such as a time or an output voltage value is satisfied is satisfied. A clock having a limited current supply capability is supplied to the capacitor of the charge pump unit. Therefore, current consumption at the time of starting the booster circuit is suppressed, so that fluctuations in the power supply voltage can be reduced and influence on other circuits can be avoided.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a semiconductor device including a booster circuit according to the present invention will be described with reference to FIGS.
[0015]
FIG. 1 is a diagram showing a circuit configuration of a semiconductor device having a booster circuit according to a first embodiment of the present invention. FIG. 2 is a diagram illustrating a configuration example of a buffer that generates a clock, and FIG. 3 is a diagram illustrating a clock with a limited capacity and a normal clock.
[0016]
In FIG. 1, similarly to the conventional FIG. 7, N-stage units are connected in series from a first-stage charge pump unit U1 to an output-stage charge pump unit Un to form a high-current pump CP1 as charge pump means. The power supply voltage Vdd (for example, 2 V or 3 V) is supplied to the unit U1, and a predetermined output voltage Vout (from an output stage unit Un) is output via an output smoothing circuit including an N-type MOS transistor Qo and a capacitor Co. For example, 10 V) is output. Each of the units U1 to Un is the same as in the conventional FIG. 7, and the corresponding components are denoted by the same reference numerals. Note that an output smoothing circuit including an N-type MOS transistor Qo and a capacitor Co may be included in the high current pump CP1.
In the first embodiment shown in FIG. 1, a clock signal generator CG which receives a start signal St and outputs a clock signal clk, and a start time control signal Scon is changed from an L level after a predetermined time τ after receiving the start signal St. An on-delay operation timer TD that rises to the H level, an inverting circuit NOT1 that inverts the clock signal clk, and a controllable control in which the current driving capability is controlled in synchronization with the clock signal clk and synchronized with the clock signal clk. The control circuit includes a first buffer B11 and a controllable second buffer B21 to which a clock signal clk inverted by the inverting circuit NOT1 is input, synchronized with the clock signal clk, and whose current drive capability is controlled by the start-up control signal Scon. These form a clock generating means.
[0018]
FIG. 2 is a diagram showing a configuration example of the controllable first buffer B11 (or the controllable second buffer B21) used in the first embodiment. In FIG. 2, a P-type MOS transistor Q21, a P-type MOS transistor Q22, an N-type MOS transistor Q23 and an N-type MOS transistor Q24 are connected in this order between the power supply voltage Vdd and the ground.
[0019]
The start-up control signal Scon is supplied to the gate of the MOS transistor Q21 via the inverting circuit NOT3, and the start-up control signal Scon is directly supplied to the gate of the MOS transistor Q24. The MOS transistor Q21 is connected in parallel with a diode-connected P-type MOS transistor Q25, and the MOS transistor Q24 is connected in parallel with a diode-connected N-type MOS transistor Q26.
[0020]
Then, a clock signal clk (or an inverted signal of the clock signal clk) is supplied to the gates of the MOS transistors Q22 and Q23, and a first clock CLK1 (or a second clock CLK2) is supplied from a connection point between the MOS transistors Q22 and Q23. Is output.
[0021]
Now, the operation of the booster circuit thus configured according to the present invention will be described with reference to FIGS.
[0022]
First, when the start signal St rises (H level), the clock signal generator CG immediately starts oscillating and generates the clock signal clk, while the timer TD starts measuring a predetermined time τ. The clock signal clk is directly supplied to the controllable first buffer B11, and is also supplied to the controllable second buffer B21 via the inverting circuit NOT1. As a result, the controllable first buffer B11 and the controllable second buffer B21 respectively generate a first clock CLK1 and a second clock CLK2, which are two-phase clocks having a predetermined frequency and changing in almost opposite phases. You.
[0023]
Until a predetermined time τ has elapsed from the rise of the start signal St, the start-time control signal Scon is at the L level, and during this time, the MOS transistor Q21 and the MOS transistor Q24 are off. Therefore, during the predetermined time τ, the first clock CLK1 and the second clock CLK2 are output via the diode-connected MOS transistors Q25 and Q26.
[0024]
In the MOS transistor Q25 and the MOS transistor Q26, a voltage drop occurs by the threshold voltage Vth. Therefore, as shown in FIG. 3A, the fluctuation width of the amplitude of the first clock CLK1 and the second clock CLK2. (That is, the voltage difference between the H level and the L level) decreases by that amount, and becomes Vdd-2Vth. The current consumption of the high current pump CP1 increases as the capacitance of the capacitors of the units U1 to Un increases, and increases as the fluctuation width at the opposite end (clock line side) of the capacitors increases. Since the fluctuation width of CLK2 is reduced, the current consumption is reduced.
[0025]
Since the fluctuation width of the first clock CLK1 and the second clock CLK2 is reduced as described above, the current supply capability of the units U1 to Un to the capacitors C1 to Cn is limited. Is reduced. In particular, immediately after the start-up of the booster circuit, a large current (for example, 100 mA) is consumed, but the current consumed is reduced (for example, 40 mA) by limiting the current supply capability as in this embodiment.
[0026]
Therefore, although the time required for the output voltage Vout to reach the predetermined voltage value is slightly longer, the current consumption at the time of starting the booster circuit is suppressed, so that the fluctuation of the power supply voltage is reduced and the influence on other circuits is reduced. Can be avoided.
[0027]
Then, when a predetermined time τ has elapsed after the activation, the activation control signal Scon becomes H level, and the MOS transistors Q21 and Q24 are turned on. As a result, the voltage drop due to the MOS transistor Q25 and the MOS transistor Q26 is eliminated, so that the first clock CLK1 and the second clock CLK2 have the fluctuation width of the power supply voltage Vdd as shown in FIG. The current consumption of the booster circuit in the normal operation state depends on the load conditions, but is, for example, about 10 to 20 mA, which is much smaller than the current consumed at startup. Can be reduced.
[0028]
FIG. 4 is a diagram showing another embodiment of the first controllable buffer B11 and the second controllable buffer B21. In this embodiment, a resistor R1 and a resistor R2 are provided instead of the constant voltage drop elements of the diode-connected MOS transistors Q25 and Q26 provided for limiting the current capability in FIG.
[0029]
Since the resistors R1 and R2 function as current limiting elements, the controllable first buffer B11 and the controllable second buffer B21 in FIG. 4 can also perform the current capability limiting function at the time of startup. Further, a similar effect can be obtained by providing another constant current source circuit instead of the resistors R1 and R2. This alternative to the resistor and the constant current source can be similarly applied to other embodiments.
[0030]
FIG. 5 is a diagram illustrating a circuit configuration of a semiconductor device including a booster circuit according to the second embodiment of the present invention.
[0031]
In the second embodiment shown in FIG. 5, each unit U1 to Un of the high current pump CP1 is provided with a clamp means for clamping the output side voltage to the highest voltage supplied, that is, the power supply voltage Vdd. Have been.
[0032]
This clamping means is composed of MOS transistors Q11 to Q1n (N-type MOS transistors in this example) provided between the output sides of the units U1 to Un and the power supply voltage Vdd. ON / OFF of the N-type MOS transistors Q11 to Q1n is controlled by a signal obtained by inverting a start signal St by an inverting circuit NOT2. In the second embodiment, the configuration other than the clamp means is the same as that in the first embodiment of FIG.
[0033]
In FIG. 5, when the booster circuit is stopped, the N-type MOS transistors Q11 to Q1n are on, so that the output voltages of the units U1 to Un, that is, all the capacitors C1 to Cn are clamped to the power supply voltage Vdd. Have been.
[0034]
When the start signal St rises, its H level is inverted by the inverting circuit NOT2 and becomes L level, so that the N-type MOS transistors Q11 to Q1n are turned off, whereby the clamp to the power supply voltage Vdd is released.
[0035]
Thereafter, the boosting operation is performed in the same manner as in the first embodiment of FIG. 1. At this time, since the capacitors are clamped in advance to the power supply voltage Vdd, the current consumption required for charging the capacitors is reduced. Less is needed. Therefore, the current consumption at the time of starting can be further reduced as compared with the first embodiment. Further, if the current consumption is the same, the time for limiting the current capability can be shortened.
[0036]
In FIG. 5, when the booster circuit is stopped, one of the outputs of the controllable first buffer B11 and the controllable second buffer B21 is normally H level according to the condition of the clock signal generator CG. The other goes to L level. However, by adding a simple logic circuit controlled in accordance with the start signal St to the controllable first buffer B11 and the controllable second buffer B21, both outputs can be fixed at the L level. In this case, all the capacitors C1 to Cn can be charged to the power supply voltage Vdd.
[0037]
FIG. 6 is a diagram illustrating a circuit configuration of a semiconductor device including a booster circuit according to the third embodiment of the present invention.
[0038]
In the third embodiment shown in FIG. 6, a voltage comparing means Vcom for comparing the output voltage Vout of the booster circuit with a predetermined reference voltage and generating a start-up control signal Scon is provided. Thereby, the timer TD provided in the first and second embodiments is removed. Further, an AND circuit AND is provided in place of the clock signal generator CG provided in the first and second embodiments, and AND circuit AND is provided according to the AND condition between the start signal St and the clock signal clk supplied from the outside. The clock signal clk is output from the circuit AND. The provision of the AND circuit AND in place of the clock signal generator CG can be similarly performed in the first and second embodiments. Other configurations are the same as those of the second embodiment in FIG.
[0039]
The voltage comparison means Vcom divides the output voltage Vout by the resistors R3 and R4 to form a comparison voltage Vs (= Vout × R3 / (R3 + R4)), and divides the power supply voltage Vdd by the resistors R5 and R6. A voltage dividing means for forming a reference voltage Vref (= Vdd × R5 / (R5 + R6)), and an operational amplifier OP1 for comparing the comparison voltage Vs with the reference voltage Vref and outputting a start-up control signal Scon when Vs> Vref. , And N-type MOS transistors Q21 and Q22 connected between the resistor R3 and the ground and between the resistor R5 and the ground, respectively. Then, in response to the rise of the start signal St, the N-type MOS transistors Q21 and Q22 are turned on, and the operational amplifier OP1 is enabled. As a result, wasteful power consumption during standby can be reduced.
[0040]
In FIG. 6, when the start signal St rises (H level), first, the MOS transistors Q11 to Q1n are turned off and the clamp operation is stopped. At the same time, since the external clock signal clk is supplied via the AND circuit AND, the first clock CLK1 and the second clock CLK2 are respectively generated, and the charge pump operation is started.
[0041]
In this state, the start-up control signal Scon is at the L level, so that the variation width of the first clock CLK1 and the second clock CLK2 is small and the units U1 Since the current supply capability to the capacitors Un to Un of the capacitors C1 to Cn is limited, the current consumption of the booster circuit is reduced.
[0042]
The output voltage Vout increases with the lapse of time from the rise of the start signal St. When the comparison voltage Vs formed from the output voltage Vout becomes higher than the reference voltage Vref formed from the power supply voltage Vdd (Vs> Vref), the output of the operational amplifier OP1, that is, the start-up control signal Scon becomes H level.
[0043]
As a result, the current capability limitation of the controllable first buffer B11 and the controllable second buffer B21 is released, and the first clock CLK1 and the second clock CLK2 have the fluctuation width of the power supply voltage Vdd in the normal operation state.
[0044]
As described above, the current capability of the controllable first buffer B11 and the controllable second buffer B21 is limited until the output voltage Vout of the booster circuit reaches a predetermined voltage after startup, and then the limited state is released and the normal state is released. Return to Therefore, although the time required for the output voltage Vout to reach the predetermined voltage value is slightly longer, the current consumption at the time of starting the booster circuit is suppressed, so that the fluctuation of the power supply voltage is reduced and the influence on other circuits is reduced. Can be avoided.
[0045]
In each of the above embodiments, the current capability is limited to one stage, but the control of the current capability to two or more other stages can be performed by using a similar method.
[0046]
Further, the charge pump unit is not limited to the configuration in each of the embodiments described above. For example, as a MOS transistor, an N-type well formed on a P-type substrate and a MOS transistor formed in the N-type well are used. A P-type well, an N-type source region formed in the P-type well, an N-type drain region formed between the source region and the channel region, and a gate formed above the channel via an insulator. The N-type well is a double-well type MOS transistor which is connected to a high potential point so that a reverse bias is applied between the N-type well and the P-type substrate. Can be used. Each unit may have a main NMOS transistor and a main capacitor, and a sub-NMOS transistor and a sub-capacitor, and may be driven by a four-phase clock.
[0047]
【The invention's effect】
According to the semiconductor device provided with the booster circuit according to claim 1, all charge pump units are provided from when the start signal is received to when a predetermined condition such as a time or an output voltage value is satisfied. Are supplied with a clock having a limited current supply capability. Therefore, current consumption at the time of starting the booster circuit is suppressed, so that fluctuations in the power supply voltage can be reduced and influence on other circuits can be avoided.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a circuit configuration of a semiconductor device including a booster circuit according to a first embodiment.
FIG. 2 is a diagram illustrating a configuration example of a buffer that generates a clock.
FIG. 3 is a diagram showing a clock with a limited current capability and a normal clock.
FIG. 4 is a diagram illustrating another configuration example of a buffer that generates a clock.
FIG. 5 is a diagram illustrating a circuit configuration of a semiconductor device including a booster circuit according to a second embodiment.
FIG. 6 is a diagram illustrating a circuit configuration of a semiconductor device including a booster circuit according to a second embodiment.
FIG. 7 illustrates a configuration of a conventional booster circuit.
[Explanation of symbols]
CP1, CP11 High current pumps U1 to Un Charge pump units Q1 to Qn, Q21 to Q26, Q11 to Q1n, Qo MOS transistors C1 to Cn, Co capacitor B11 Controllable first buffer B21 Controllable second buffer NOT1, NOT2, NOT3 Inverting circuit CG Clock signal generator TD Timer R1 to R6 Resistance Vcom Voltage comparing means OP1 Operational amplifier Q21, Q22 MOS transistor AND AND circuit clk Clock signal CLK1 First clock CLK2 Second clock St Start signal Scon Start control signal Vdd Power supply voltage Vout output voltage

Claims (1)

A plurality of charge pump units each having a MOS transistor having an input end and an output end and a capacitor having one end connected to the output end and a clock supplied to the other end are connected in series to increase the power supply voltage. Charge pump means for outputting the output voltage,
Clock generating means for receiving the start signal and starting generation of the clock,
Said clock generating means, the at least until the start signal receiving a predetermined condition is satisfied which is predetermined from, Rutotomoni amplitude current supply capability is limited to the capacitor as the clock from the supply voltage A semiconductor device comprising a booster circuit, wherein the semiconductor device generates a clock having a small capacity limit and generates a clock having the amplitude of the power supply voltage after the predetermined condition is satisfied .

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