JP2003242725A - Signal reproducing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal reproducing device capable of controlling a modulation degree to be fixed and optimizing a DC level while securing a dynamic range even for reproducing signals of a vertically asymmetrical waveform. <P>SOLUTION: The reproducing signals of different modulation degrees and DC levels are inputted to an A/D converter 11 and sampled and then the modulation degree is controlled to an optimum state on the basis of boost amount setting signals BG(b) and BG(a, c) in a prefilter circuit 12. In an ATC circuit 13, the DC level of the input reproducing signals is optimized. Thereafter, in an AGC circuit 14, gain is controlled by using mutually different three threshold levels so as to almost fix the level of the cycle of the minimum inversion interval. Thereby, the reproducing signals outputted from the AGC circuit 14 as a result are turned to the signals for which the modulation degree, the DC level and a signal level are respectively optimized. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

The present invention relates to a signal reproducing device, and more particularly to a signal reproducing device for decoding a digital signal reproduced from a recording medium such as an optical disk.

[0002]

2. Description of the Related Art In a signal reproducing apparatus for reproducing a high density recorded digital signal on an optical disk, the recording signal shape changes and the duty ratio of the reproduced signal changes due to variations in the sensitivity of the optical disk and aging of the semiconductor laser. In some cases, the ATC (Automatic Threshold Control) that appropriately controls the threshold of the binary comparator of the reproduced signal by DC.
l) and AGC (Autom
atic Gain Control).

In the ATC control, a threshold value is set to an intermediate value of the peak-to-peak values of the reproduced signal, or the value of the reproduced signal in the preamble portion is held, so that the digital signal on the optical disk is high. There is a problem that the error margin cannot be secured as the density is recorded. In particular,
On optical discs, the center level of the playback signal fluctuates,
Since the reproduced signal waveform may be vertically asymmetrical, these ATC controls cannot control the threshold value appropriately.

As a method for solving this problem, a DVD
For optical discs such as (Digital Versatile Disc), the duty ratio of the scrambled reproduction signal is 5 on average.
By taking advantage of the fact that it is 0:50, a method is adopted in which the average value is fed back to obtain an appropriate threshold value.

However, this method has no concern about AGC control. As it is, the signal is too large,
Since the output signal will be saturated beyond the dynamic range of the A / D converter, or the signal will be too small and the error rate will deteriorate, separate AGC control will be provided.
With AGC control that keeps the signal level constant by using the detection output by a simple peak hold, the operation of the PLL circuit in the subsequent stage may become unstable or the error rate may deteriorate when the modulation degree of the signal is low. There is a nature.

Therefore, the applicant of the present invention has previously disclosed the Japanese Patent Laid-Open No. 2000-2.
In Japanese Patent Laid-Open No. 00464, a new signal reproducing device which solves the above problem is proposed. In order to solve the above-mentioned problem, this is a DC control for controlling the DC level of the input reproduction signal based on the DC error signal, and a gain control for controlling the amplitude of the input reproduction signal based on the gain error signal. For each of the control means that executes at least one and the three or more threshold levels different from each other that are smaller than the maximum amplitude of the reproduction signal extracted by the control means, the number of times the reproduction signal has crossed is separately accumulated, and When any one of the integrated values of has reached the set value, all integrated values are cleared, and the number of times the playback signal crosses the threshold level of 3 or more again is integrated separately for each threshold level. Repeatedly, the number of integrated thresholds equal to the number of threshold levels of the cross extractor or the integrated value is set. Based on the relative magnitude of the integrated value of the time value has been reached, in which a structure having an error detection unit for generating and outputting at least one of the DC error signal and the gain error signal.

[0007]

However, in the signal reproducing apparatus proposed by the applicant of the present invention, when the modulation degree of the reproduced signal taken out by the control means is extremely small, the AGC is performed.
In order to significantly increase the gain of the signal, the dynamic range due to the bit limitation of the circuit (RL in FIG.
18) is narrow, it may be saturated as shown by b and c in FIG. 18, and the error rate may be significantly deteriorated. Note that in FIG. 18, Th0, Th1, and T
h2 indicates three threshold levels different from each other, which are smaller than the maximum amplitude of the reproduction signal.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a signal reproducing device capable of optimizing a DC level by controlling a modulation degree constant while securing a dynamic range even for a reproduced signal having a vertically asymmetrical waveform.

Another object of the present invention is to provide a signal reproducing apparatus capable of appropriately controlling each of ATC, AGC and frequency even for a reproduced signal of a recording medium recorded at high density.

[0010]

In order to achieve the above object, the signal reproducing apparatus of the first invention is a sampling apparatus for sampling a reproduced signal reproduced from a recording medium at a predetermined clock and outputting a sampled signal. Means for filtering the post-sampling signal to optimize the modulation degree based on the boost amount setting signal, and outputting the post-filtering signal, and controlling the DC level for the post-filtering signal DC and gain control means for sequentially performing DC control and gain control for controlling the signal amplitude based on the gain error signal, and D
An output signal that has been subjected to both DC control and gain control by C and gain control means, or a signal that has been subjected to gain control by DC and gain control means and has not yet been subjected to DC control, as an input signal; It has an envelope detection means for detecting at least one of the upper envelope and the lower envelope, and boost amount calculation means for generating a boost amount setting signal based on the output detection signal of the envelope detection means. The output control signal is subjected to both DC control and gain control by the gain control means.

According to the present invention, after the sampling degree of the reproduction signal is optimized by the filtering means whose adaptive filter characteristic is changed based on the boost amount setting signal, the DC degree is controlled by the DC and gain control means. It is possible to decode the obtained signal by optimizing the DC level according to (4) and optimizing the signal level through gain control.

In order to achieve the above object, the signal reproducing device of the second invention is obtained by binarizing the DC and gain control means of the first invention by binarizing the DC-controlled signal. It is characterized in that the DC control for controlling the DC level of the input signal is performed so that the average value of the duty of the binarized signal is in the center of the two values. According to the present invention, DC control can be performed with a simple configuration.

Further, in order to achieve the above object, the signal reproducing apparatus of the third invention has three or more different DC and gain control means of the first invention, which are smaller than the maximum amplitude of the filtered signal and are different from each other. For each of the threshold levels of, the number of times the input signal has crossed per unit time is integrated separately, and the relative magnitude of each integrated value when any of the three integrated values reaches the set value. It is characterized in that a DC error signal is generated based on the relationship to perform DC control.

Further, in order to achieve the above-mentioned object, the signal reproducing apparatus of the fourth invention is characterized in that the DC and gain control means of the first to third inventions are mutually smaller than the maximum amplitude of the filtered signal. For each of three or more different threshold levels, the number of times the input signal has traversed per unit time is separately integrated, and among these three integrated values,
The present invention is characterized in that a gain error signal is generated and gain control is performed based on the relative magnitude relation between the respective integrated values when any of the integrated values reaches the set value.

In order to achieve the above object, the signal reproducing apparatus of the fifth invention comprises sampling means for sampling the reproduced signal reproduced from the recording medium at a predetermined clock and outputting the sampled signal, and sampling means. ATC means for controlling the DC level for the rear signal, and A
The output signal of the TC means is subjected to filtering for optimizing the modulation degree based on the boost amount setting signal, and the filtering means for outputting the filtered signal and the amplitude of the filtered signal are controlled based on the gain error signal. AGC means for performing gain control, an envelope detection means for receiving the output signal of the AGC means as an input signal, and detecting at least one of the upper envelope and the lower envelope, and an output detection signal of the envelope detection means. Based on this, it has a boost amount calculating means for generating a boost amount setting signal, and decodes the signal after gain control outputted from the AGC means.

According to the present invention, the ATC means optimizes the DC level of the sampled signal obtained by sampling the reproduction signal, and then the adaptive filter characteristic is changed based on the boost amount setting signal. It is possible to decode the finally obtained signal by optimizing the modulation degree of the signal by the means and further optimizing the signal level by the gain control by the AGC means.

Further, in order to achieve the above object, in the signal reproducing apparatus of the sixth invention, the boost amount calculating means of the first invention or the fifth invention is provided with an upper envelope detection signal output from the envelope detecting means. And a lower envelope detection signal, the selection signal having a larger absolute value, or a predetermined selection of one envelope detection signal, a reference value generation device for generating a reference value, and a selection device. The subtraction means is configured to subtract the detected signal and the reference value to generate and output a boost amount setting signal.

In order to achieve the above object, the signal reproducing method of the present invention comprises a first step of sampling a reproduced signal reproduced from a recording medium at a predetermined clock and outputting a sampled signal, and a sampling step. The second step of filtering the post signal to optimize the modulation degree based on the boost amount setting signal and outputting the post-filter signal, and the DC control of controlling the DC level of the post-filter signal And a third step of sequentially performing a gain control for controlling the signal amplitude based on the gain error signal, an output signal subjected to both DC control and gain control, or a gain control, and D
A fourth step of receiving a signal before being subjected to C control as an input signal, and detecting at least one of an upper envelope and a lower envelope of the input envelope;
A fifth step of generating a boost amount setting signal based on the envelope detection signal, and decoding the output signal subjected to both the DC control and the gain control in the third step.

Further, in order to achieve the above object, a signal reproducing method of another invention comprises a first step of sampling a reproduced signal reproduced from a recording medium at a predetermined clock and outputting a sampled signal, The second step of controlling the DC level of the sampled signal, and the filtering of the signal DC-controlled by the second step to optimize the modulation degree based on the boost amount setting signal, A third step of outputting the filtered signal, a fourth step of executing a gain control for controlling the amplitude of the filtered signal based on the gain error signal, and a signal of the gain-controlled signal by the fourth step. A fifth step of detecting at least one of the upper envelope and the lower envelope, and a fifth step Based on the envelope detection signal by, and a sixth step of generating a boost amount setting signal, and wherein to decode the signal after gain control obtained by the fourth step.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a first embodiment of a signal reproducing apparatus according to the present invention. In the figure, a reproduction signal reproduced from a recording medium such as an optical disk is pre-amplified by a preamplifier (not shown) and then A / D
It is supplied to the converter 11, converted into a digital signal based on the system clock, and supplied to the pre-filter circuit 12. The pre-filter circuit 12 uses a boost amount setting signal BG output from a boost amount calculation circuit 19 described later.
(B), the input reproduction signal is filtered based on BG (a, c).

The reproduction signal filtered and taken out by the pre-filter circuit 12 is supplied to the ATC circuit 13, where DC control is performed so that the DC level agrees with the optimum threshold value, and further supplied to the AGC circuit 14. , The signal amplitude of the minimum run length cycle is controlled to be substantially constant. The output reproduction signal of the AGC circuit 14 is supplied to the equalizer / PLL 15 and subjected to clock generation and equalization processing (for example, adaptive equalization to match the partial response characteristic).

The output reproduction signal of the equalizer / PLL 15 is supplied to the decoding circuit 16, where it is binarized by, for example, Viterbi decoding. The reproduced signal binarized by the decoding circuit 16 is supplied to the ECC circuit 17 to be error-corrected and then output.

The output reproduction signal of the AGC circuit 14 is
It is also supplied to the envelope detection circuit 18, where both the upper and lower envelopes A and B are detected, and then supplied to the boost amount calculation circuit 19 to calculate the boost amount and the boost amount setting signal BG (b). And BG (a, c)
And is supplied to the pre-filter circuit 12. In this embodiment, the pre-filter circuit 12 and the ATC circuit 1 described above are used.
3, a feedback loop circuit including an AGC circuit 14, an envelope detection circuit 18, and a boost amount calculation circuit 19 is used to extract an optimized signal of modulation degree, DC level and signal level from the AGC circuit 14. Next, the feedback loop circuit will be described in more detail.

FIG. 2 is a block diagram showing an example of the prefilter circuit 12. In the figure, two-stage cascaded delay devices 21 and 22, amplifiers 23, 24 and 25, and amplifiers 23 to 2 are connected.
The adder 26 for adding the respective output signals of 5 constitutes a transversal filter, and the boost amount setting signal B
The gains (tap coefficients) G1 and G3 of the amplifiers 23 and 25 are changed by G (a, c) to set the boost amount setting signal BG.
By changing the gain (tap coefficient) G2 of the amplifier 24 by (b), the boost amount is changed. Here, when the polarities of G1 and G3 and G2 are different,
Boost (high frequency emphasis), and when the polarities are the same-
It becomes the boost (high frequency attenuation).

That is, the reproduction signal sampled by the A / D converter 11 in FIG. 1 (post-sampling signal)
Are sequentially delayed by the sampling periods T by the delay units 21 and 22 of FIG. The input sampled signal and the output signal of the delay device 22 are amplified by the amplifiers 23 and 25 with a gain according to the boost amount setting signal BG (a, c), and the output signal of the delay device 21 is boosted by the amplifier 24. It is amplified with a gain according to the quantity setting signal BG (b).
The output signals of the amplifiers 23, 24 and 25 are added by the adder 26.
Is output to the pre-filter output signal.

FIG. 3 is a block diagram showing an example of the ATC circuit 13 shown in FIG. The configuration shown in FIG. 3 is a configuration based on a method called Duty Cancel, in which the input pre-filter output signal is supplied to a calculator 31 and a low-pass filter (LPF) 33 to be described later.
After being subtracted from the control signal from, the signal is output as an ATC output signal and supplied to the binarization circuit 32.

The binarization circuit 32 is the AT from the arithmetic unit 31.
The C output signal is compared with a predetermined threshold value, and binarization is performed depending on whether the C output signal is larger or smaller than the threshold value. The binarized signal from the binarization circuit 32 is supplied to the LPF 33 and integrated, and then supplied to the calculator 31 as a control signal. By such an operation, the output signal of the A / D converter 11 is adjusted so that the average value of the duty of the binarized signal becomes the center of the binary value regardless of the waveform distortion and the vertical asymmetry. , The DC level is controlled so that it becomes 1/2, and as a result, the DC level is controlled to the correct zero-cross point including the waveform of the minimum run length cycle and supplied to the AGC circuit 14. To be done.

FIG. 4 shows a block diagram of an example of the AGC circuit 14 of FIG. The AGC circuit shown in FIG. 4 is proposed by the applicant in Japanese Patent Laid-Open No. 2000-200464. In FIG. 4, the output signal of the ATC circuit 13 is supplied to the cross extraction section 42 and the error detection section 43 through the gain control circuit 41.

The cross extraction unit 14 is, as shown in FIG.
A first threshold level Th0 that is an intermediate level set around the original center level of the reproduction signal S in the minimum inversion interval of the reproduction signal S, a second threshold level Th1 that is higher than this, and Th0. A total of 3 small third threshold levels Th2
Three threshold levels are preset, and these three threshold levels Th0, Th1 and Th are set.
Independently integrating the number of times the playback signal crosses for each of the two, and when any of these three integrated values reaches the preset set value, clear all three integrated values and perform the same operation again. It is configured to repeat.

FIG. 6 is a circuit system of an example of the cross extraction unit 42.
The figure is shown. In the figure, the gain control circuit 4 shown in FIG.
The reproduction signal S shown in FIG.
Cross detector 421₁, 421₂And 4
21₃And the cross detector 421₁, 421₂And 421₃To
Comparators 422 provided in a one-to-one correspondence₁422 ₂Over
And 422₃And the comparator 422₁422₂And 422₃Out of
And a 3-input OR circuit 423 to which a force signal is input.
Has been.

Cross detectors 421 ₁ , 421 ₂ and 421
Each of the ₃ has a threshold level (threshold) shown in FIG.
Threshold levels Th1, Th0 and Th shown in
The preset threshold value is set to 2, and the integrated values (cross count values) C1, C0 and C2 obtained by counting the set threshold level every time the input reproduction signal S crosses are output.
Here, the interval P between the threshold levels Th0 and Th1
And the spacing P between Th0 and Th2 is set equal, and
The interval P is set smaller than the minimum value Q of the amplitude at the minimum inversion interval. As a result, any one of these three threshold levels Th1 to Th3 will always show the correct zero-cross value (in the example of FIG. 5, the threshold level Th.
0).

[0032] Referring back to FIG. 6 again, the cross count value retrieved from each cross detector 421 _{1-421 3} is supplied to a comparator 422 _{1-422 3,} the common settings here The size is compared separately. This set value is set to the original average zero-cross count value in a period sufficiently long with respect to the minimum inversion interval. Comparator 4
22 _{1-422 3} are each configured to output a coincidence signal of high level when matching the above settings.

Therefore, of the comparators 422 _{1 to} 422 ₃ , the one having the earliest input integrated value (cross count value) that has reached the set value outputs a coincidence signal, which is cross-detected as a reset pulse through the OR circuit 423. Vessel 42
11 _{1 to} 421 ₃ are commonly supplied to reset the integrated value (cross count value) thereof, and also reset a part of the error detection unit 43 described later. As described above, since any one of the three threshold levels Th0 to Th2 always shows the correct zero cross value, it is considered that the integrated value which reaches the set value earliest always includes the minimum inversion interval. It is used for error calculation.

The above three threshold levels Th
Of 0, Th1 and Th2, the reproduction signal should cross the central threshold level Th0 most often within a predetermined unit time. Therefore, normally, the number of times of crossing the central threshold level Th0 in a predetermined unit time is integrated. The value C0 should reach the above set value earliest.

Therefore, the error detector 43 shown in FIG.
Is an integrated value C0 of the number of crosses of the central threshold level Th0 and an integrated value C1 of the number of crosses of the upper threshold level Th1 in the cross extraction unit 42.
And a gain error signal is generated so that the integrated values C1 and C2 have a constant ratio with respect to the integrated value C0 based on the comparison result of the integrated value C2 of the number of times of crossing the lower threshold level Th2.

Next, the method of generating the gain error signal of the error detection unit 43 will be described with reference to the flowchart of FIG. 7. The error detection unit 43 detects that the output reset signal of the cross extraction unit 42 becomes H level, , When the above set value is reached (step S1), the integrated value C0 ≧ C1
Then, it is determined whether or not C0 ≧ C2 (step S2).

When C0 ≧ C1 and C0 ≧ C2, that is, when the integrated value C0 of the number of crosses of the central threshold level Th0 in a predetermined unit time is larger than the other integrated values C1 and C2, the reproduction is performed. Since the signal is in the original amplitude range, the integrated value C1 of the number of crosses on the upper side is
And the integrated value C2 of the number of times of crossing on the lower side are both larger than a predetermined value smaller than the integrated value C0 of the number of times of crossing in the center (in consideration of the influence of noise, for example, a value of about 70% of C0). It is determined (step S3).

When both the integrated values C1 and C2 are larger than the above predetermined value, it is judged that the amplitude of the reproduced signal is large and a gain error signal for lowering the gain is generated (step S).
4). On the other hand, when at least one of the integrated values C1 and C2 is less than or equal to the predetermined value, it is determined whether both integrated values C1 and C2 are both smaller than the predetermined value (step S5), and the integrated values C1 and C2 are determined. If both are smaller than the predetermined value, it is judged that the amplitude of the reproduction signal is small and a gain error signal for increasing the gain is generated (step S6).

On the other hand, when the reset signal is not at H level, the gain error signal is not generated because the integrated value is being calculated (step S7). Further, the integrated value C0 is the integrated value C1.
When it is smaller than at least one of C1 and C2, or when one of the integrated values C1 and C2 is equal to or less than the predetermined value, the amplitude of the reproduction signal is shifted to the upper side or the lower side, and the correct determination of the gain cannot be performed. Therefore, in this case, the error detector 15 does not generate a gain error signal (holds the current gain) (step S7). Furthermore, when it is determined in step S5 that C1 = C2, there is no gain error, and thus no gain error signal is generated (step S5).
7). Based on the gain error signal generated in this way, the gain control circuit 41 of FIG. 4 performs gain control to vary the amplitude of the reproduction signal (AGC control).

By the above operation, the DC level of the cycle with a small run length is not dependent on the modulation degree of the signal (corresponding to the ratio of the absolute value level of the cycle with a large run length to the cycle with a small run length). It becomes possible to control to an appropriate position and to control the size of the cycle with a small run length to a substantially constant value.

Referring again to FIG. 1, the envelope detection circuit 18 receives as an input the signal output from the AGC circuit 14 as shown by the solid line in FIG. The envelope B on the side is detected and output. The detection method can be realized by using a known method such as peak hold.

FIG. 9 is a block diagram showing an example of the boost amount calculation circuit 19 shown in FIG. In the figure, the upper envelope detection signal envelope A detected by the envelope detection circuit 18 is supplied to the absolute value circuit 51, and the lower envelope detection signal envelope B is supplied to the absolute value circuit 5.
2 is supplied. The absolute value circuit 51 and the absolute value circuit 52 are
Calculate the absolute value of the input signal (in the case of 2's complement display),
The size is supplied to the selection circuit 53.

The selection circuit 53 selects the envelope detection signal having the larger absolute value and outputs it to the subtraction circuit 54.
The subtraction circuit 54 subtracts the predetermined reference value generated by the reference value generation circuit 55 from the envelope detection signal selected by the selection circuit 53, and outputs the boost amount setting signal BG.
(B) and BG (a, c) are output, respectively. Here, the boost amount setting signals BG (b) and BG (a, c)
Is in a relationship in which, for example, 1-2BG (a, c) corresponds to BG (b).

By the above operation, the boost amount calculation circuit 1
In 9, the deviation between the larger absolute value of the envelope of the signal after AGC and the predetermined reference value is output as an error (boost amount setting signal).

The envelope detection signal input to the boost amount calculation circuit 19 may be either the envelope A or the envelope B. A block diagram of the boost amount calculation circuit 19 in this case is shown in FIG. As shown in the figure, the boost amount calculation circuit 19 subtracts one predetermined envelope detection signal of the envelope A and the envelope B and the reference value from the reference value generation circuit 55 by the subtraction circuit 56. , Output boost amount setting signal.

Next, the operation of the main part of the signal reproducing apparatus having the above configuration will be described with reference to FIG. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals. In FIG. 11, reproduction signals having different modulation levels and DC levels are input to the A / D converter 11 and sampled, and then the boost amount setting signals BG (b), BG are supplied to the pre-filter circuit 12.
Based on (a, c), the modulation degree is controlled to the optimum state. Boost amount setting signals BG (b), BG (a, c)
Is an error signal for controlling the envelope of the output signal of the AGC circuit 14 to have a predetermined magnitude.

Next, in the ATC circuit 13, the DC level of the input reproduction signal is optimized. After that, in the AGC circuit 14, the three threshold levels Th are set so that the level of the cycle of the minimum inversion interval becomes substantially constant.
It is controlled using 0, Th1 and Th2. By subjecting the input reproduction signal to the signal processing by such a skillful loop configuration, the reproduction signal output from the AGC circuit 14 as a result has a modulation degree, a DC level and a signal level, respectively, as shown in FIG. Is the optimized signal. As a result, the subsequent equalizer / PLL shown in FIG.
The operation of 15 and the Viterbi decoding operation of the decoding circuit 16 are stabilized, and decoding that can converge rapidly can be performed.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 12 shows a block diagram of a second embodiment of the signal reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. In the second embodiment, the connection order of the pre-filter circuit 12 and the ATC circuit 13 of the first embodiment is reversed. First, with respect to the output digital reproduction signal of the A / D converter 11, The ATC circuit 60 optimizes the DC level, and then the pre-filter circuit 61 optimizes the modulation degree. In this embodiment, the same effect as that of the first embodiment can be obtained.

Next, a third embodiment of the present invention will be described. FIG. 13 shows a block diagram of a third embodiment of a signal reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. The third embodiment is similar to the ATC circuit 1 of the first embodiment.
3 and the AGC circuit 14 are connected in reverse order, and the output reproduction signal of the pre-filter circuit 12 is first processed by the AG
The C circuit 62 optimizes the signal level, and then the ATC circuit 63 optimizes the DC level.
In this embodiment, the same effect as that of the first embodiment can be obtained.

As shown in FIG. 13, the envelope reproduction circuit 18 receives the output reproduction signal of the AGC circuit 62. That is, the ATC circuit 63 is removed from the feedback loop.

Next, a fourth embodiment of the present invention will be described. FIG. 14 shows a block diagram of a fourth embodiment of a signal reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. In the fourth embodiment, the ATC circuit 13 and the AGC circuit 1 are
4 is deleted and an AGC / ATC circuit 64 is inserted instead.

The AGC / ATC circuit 64 is the AGC of FIG.
An ATC operation difference is added to the AGC operation of the circuit 14, and the circuit configuration shown in FIG. 15 proposed by the present applicant in Japanese Patent Laid-Open No. 2000-200464 can be used.
15, the gain control circuit 72 has the same function as the gain control circuit 41 of FIG. 4, and the cross extraction unit 73 has the same function as the cross extraction unit 42 of FIG. In addition, FIG.
The DC control circuit 71 controls the DC level of the input signal based on the DC error input from the error detector 74. In addition to the function (AGC error extraction) of the error detection unit 43 of FIG. 4, the error detection unit 74 of FIG. 15 has a function of outputting a DC error according to the following processing procedure.

Next, the operation of the error detector 74 will be described. The error detection unit 74 includes an integrated value C0 of the number of crosses of the central threshold level Th0 in the cross extraction unit 73, an integrated value C1 of the number of crosses of the upper threshold level Th1, and a lower threshold level Th2.
Based on the comparison result of the integrated value C2 of the number of crosses, the central threshold level Th0 in a predetermined unit time
The DC error signal is generated so that the integrated value C0 of the number of times of crossing becomes greater than the integrated values C1 and C2, and the balance of the integrated values C1 and C2 becomes equal.
The gain error signal is generated so that the integrated values C1 and C2 have a constant ratio to the integrated value C0. The method of generating this gain error signal is the same as that of the error detection unit 43.

Next, the method of generating the DC error signal of the error detector 74 will be described with reference to the flowchart of FIG. 16. The error detector 74 detects when the output reset signal of the cross extraction unit 73 becomes H level, that is, When the set value is reached (step S11), it is determined whether the integrated value C1 of the upper cross times and the integrated value C2 of the lower cross times are equal (step S12), and it is determined that they are not equal. Determines whether C1> C2 (step S13).

When C1> C2, it is determined that the position of the reproduction signal is higher than the plurality of threshold levels, that is, the DC level of the reproduction signal is shifted to the upper side, and the DC level of the reproduced signal is shifted to the lower side. A DC error signal for shifting is generated (step S14). When C1 <C2, a DC error signal for shifting the DC level of the reproduced signal to the upper side by judging that the position of the reproduced signal is lower than the plurality of threshold levels, that is, the DC level of the reproduced signal is deviated to the lower side. Is generated (step S15).

When it is determined in step S11 that the reset signal is not at H level, the integrated value is not obtained, and when it is determined in step S12 that C1 = C2, the DC level of the reproduction signal is deviated. If not, a DC error signal indicating that there is no DC error is generated (step S16). The DC control circuit 71 performs DC control based on this DC error signal (ATC control). Also in the fourth embodiment, the same effect as that of the first embodiment can be obtained.

The present invention is not limited to the above-described embodiment, and for example, the pre-filter circuit 12 has three delay stages 21, 2 connected in cascade as shown in FIG.
2 and 27 and four amplifiers 23, 24, 25 and 28
And an adder 29 that adds the output signals of the amplifiers 23 to 25 and 28 to each other (4 taps (tap coefficients G1 to G).
The transversal filter configuration of 4) may be adopted.

Here, the boost amount setting signal BG (a,
The gain (tap coefficient) of the amplifiers 23 and 28 is changed by c), and the amplifier 2 is changed by the boost amount setting signal BG (b).
By varying the gain (tap coefficient) of 4 and 25, the boost amount is varied. According to this configuration, the center of time, which was at the position of G2 in FIG. 2, shifts between G2 and G3, but the same characteristics as in FIG. 2 can be obtained.

The number of threshold levels used in the cross extraction units 42 and 73 may be four or more. Further, the present invention is not limited to a signal reproducing device for decoding a digital signal reproduced from a recording medium, but may be wired or wireless. It can also be applied to digital signals transmitted and received by.

[0060]

As described above, according to the present invention,
After optimization of the modulation degree of the signal after sampling of the reproduction signal by the filtering means in which the adaptive filter characteristic is changed based on the boost amount setting signal, the DC level is optimized by the DC control by the DC and gain control means. ,
Since the signal level is optimized by gain control and the obtained signal is decoded, the equalizer / PL in the subsequent stage is
It is possible to realize a stable operation by L, maximize the Viterbi decoding operation by the decoding circuit, and realize a signal reproducing device capable of quickly converging an irregular reproduced signal.

Further, according to the present invention, since it is a full digital structure, it is easy to make a semiconductor large-scale integrated circuit (LSI), shorten the LSI development period, improve productivity, and have no variation in characteristics. When integrated into a circuit, the size and reliability can be improved as compared with a device using an analog circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of an example of a pre-filter circuit in FIG.

3 is a block diagram of an example of an ATC circuit in FIG.

FIG. 4 is a block diagram of an example of an AGC circuit in FIG.

5 is a diagram showing an example of a reproduced signal waveform reproduced by the device of the present invention and a relationship between threshold levels in the cross extraction unit of FIG.

FIG. 6 is a circuit system diagram of an example of a cross extraction unit in FIG.

7 is a flowchart of an example of a gain error signal generation method by the error detection unit in FIG.

8 is an explanatory diagram of an example of an input signal waveform of the envelope detection circuit in FIG. 1 and a level to be detected.

FIG. 9 is a block diagram of an example of a boost amount calculation circuit in FIG.

FIG. 10 is a block diagram of another example of the boost amount calculation circuit in FIG.

11 is a block diagram and a waveform diagram for explaining the operation of the main part of FIG.

FIG. 12 is a block diagram of a second embodiment of the present invention.

FIG. 13 is a block diagram of a third embodiment of the present invention.

FIG. 14 is a block diagram of a fourth embodiment of the present invention.

15 is a block diagram of an example of an AGC / ATC circuit in FIG.

16 is a flowchart of an example of a DC error signal generation method by the error detection unit in FIG.

FIG. 17 is a block diagram of another example of the pre-filter circuit.

FIG. 18 is a signal waveform diagram for explaining a conventional problem.

[Explanation of symbols]

11 A / D converter 12, 61 Pre-filter circuit 13, 60 ATC circuit 14, 62 AGC circuit 15 Equalizer / PLL 16 Decoding circuit 17 ECC circuit 18 Envelope detection circuit 19 Boost amount calculation circuit 21, 22, 27 Delay device 23, 24, 25, 28 Amplifier 26, 29 Adder 31 Operator 32 Binarization circuit 33 Low pass filter (LPF) 51, 52 Absolute value circuit 53 Selection circuit 54, 56 Subtraction circuit 55 Reference value generation circuit 64 AGC / ATC circuit 421 _{1 to} 421 ₃ cross detector 422 _{1 to} 422 ₃ comparator 423 OR circuit

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5D044 BC02 CC04 FG01 FG02 FG04                       FG06 GL02 GM18                 5D090 AA01 BB02 BB03 BB04 CC04                       DD03 EE14 FF42

Claims (6)

[Claims] 1. Sampling means for sampling a reproduced signal reproduced from a recording medium at a predetermined clock and outputting a sampled signal, and an optimum modulation degree for the sampled signal based on a boost amount setting signal. Filtering to
Filtering means for outputting a filtered signal, DC control for controlling the DC level of the filtered signal, and DC and gain for sequentially performing gain control for controlling the signal amplitude based on the gain error signal. A control means and an output signal that has been both DC controlled and gain controlled by the DC and gain control means, or the gain control is performed by the DC and gain control means, and before the DC control is performed. Signal as an input signal, and an envelope detection means for detecting at least one of the upper envelope and the lower envelope, and a boost for generating the boost amount setting signal based on the output detection signal of the envelope detection means. An amount calculation means, and the DC control and gain control by the DC and gain control means. Signal reproducing apparatus characterized by decoding the output signal both control has been performed. 2. The DC and gain control means controls the DC of the input signal so that the average value of the duty of the binarized signal obtained by binarizing the DC-controlled signal is in the center of the binary. 2. The signal reproducing apparatus according to claim 1, wherein DC control for controlling the level is performed. 3. The DC and gain control means, for each of three or more threshold levels different from each other, which are smaller than the maximum amplitude of the filtered signal,
The number of times per unit time that the input signal has crossed is integrated separately, and based on the relative magnitude relationship of each integrated value when one of the three integrated values reaches the set value,
The signal reproducing device according to claim 1, wherein a DC error signal is generated to perform the DC control. 4. The DC and gain control means, for each of three or more threshold levels different from each other that are smaller than the maximum amplitude of the filtered signal,
The number of times per unit time that the input signal has crossed is integrated separately, and based on the relative magnitude relationship of each integrated value when one of the three integrated values reaches the set value,
4. The signal reproducing apparatus according to claim 1, wherein the gain error signal is generated and the gain control is performed. 5. Sampling means for sampling a reproduced signal reproduced from a recording medium at a predetermined clock and outputting a sampled signal, ATC means for controlling a DC level for the sampled signal, Filtering means for filtering the output signal of the ATC means to optimize the modulation degree based on the boost amount setting signal and outputting the filtered signal, and controlling the amplitude of the filtered signal based on the gain error signal AGC means for performing gain control, an envelope detecting means for receiving an output signal of the AGC means as an input signal, and detecting at least one of an upper envelope and a lower envelope of the AGC means, and an output of the envelope detecting means. Based on the detection signal, the boost amount setting And a boost amount calculating means for generating a signal, the signal reproducing apparatus characterized by decoding the signal after gain control that is output from the AGC means. 6. The boost amount calculation means is a detection signal having a larger absolute value of each of the upper envelope detection signal and the lower envelope detection signal output from the envelope detection means, or one predetermined envelope. Selection means for selecting a detection signal, reference value generation means for generating a reference value, subtraction for subtracting the detection signal and the reference value selected by the selection means to generate and output the boost amount setting signal 6. The signal reproducing apparatus according to claim 1 or 5, further comprising means.