JP4106646B2 - Digital signal reproduction device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital signal reproducing apparatus, and more particularly to a digital signal reproducing apparatus for decoding a digital signal reproduced from a recording medium such as an optical disk.
[0002]
[Prior art]
In a digital signal playback device that plays back digital signals recorded on an optical disk at high density, the recording signal shape changes due to variations in the sensitivity of the optical disk or aging of the semiconductor laser, and the DC component of the playback signal fluctuates. Therefore, a slice level control that appropriately controls the threshold value of the binary comparison of the reproduction signal is used. For example, in the detection system, the DC component of the signal and the duty shift after binarization are detected, and in the control system, the threshold level or the DC level of the reproduction signal is controlled. This can be realized by using slice level control means for controlling the slice level. Even in the DVD standard, a jitter measurement system is defined by a method of detecting a duty shift after binarization and feeding it back as a threshold level (see FIG. 42).
[0003]
A reproduction signal and a threshold level, which is a slice level, are input to the comparator 901, and the output is output as binary data and simultaneously input to the OP amplifier 902. The amplified signal is low-pass filtered by an OP amplifier 903, a low-frequency component generated by the duty is extracted, and supplied to the amplifier 901 as a slice level (threshold level).
[0004]
When this is displayed in a functional block diagram, it is as shown in FIG. A reproduction signal and a slice level (threshold level) are inputted to the binarizing means 904, and the output is outputted as binarized data and simultaneously supplied to the amplifying means 905. The output of the amplifying circuit 905 is supplied to the integrating means 906, and low frequency components generated by the duty are extracted by low frequency filtering. The output is supplied to the binarization means as a slice level (threshold level).
[0005]
With this configuration, the slice level is controlled so that it is always located at the center of the duty of the signal, the modulation during recording is random at each run length, and the occurrence probability of 1, 0 Are controlled to be almost equal, the correct slice level (threshold level) can be set without being affected by the vertical asymmetry due to the recording power peculiar to the optical disc, and it is realized with a simple circuit. Because it was possible, it was an effective means.
[0006]
[Problems to be solved by the invention]
However, in the conventional technique, when the modulation code pattern of the modulation signal to be recorded is biased, a malfunction occurs and correct detection cannot be performed. FIG. 8 shows an eye pattern for explaining this state. FIG. 8A shows a normal state, and the horizontal line at the center shows an appropriate slice level. On the other hand, FIG. 8B shows a state in which a DC shift occurs, and FIG. 8C shows a case in which the vertical symmetry is broken by laser power or the like, both of which are in the state of FIG. Since the correct determination cannot be made at the same slice level (horizontal line in the center of FIG. 8), the above-described slice level control or the like attempts to lower the slice level (or increase the signal) in this case.
[0007]
Further, FIG. 8D shows a case where the modulation code pattern is biased, and the appropriate slice level is preferably the same position as in FIG. However, in the conventional slice level control, it is impossible to discriminate the difference between the states of FIG. 8B and FIG. 8C and the state of FIG. 8D. Even though it is not necessary, control is performed in the direction of lowering the slice level (or raising the signal), and correct reproduction cannot be performed.
[0008]
Therefore, in the case of a DVD or the like, the low-frequency component is reduced as much as possible by using DSV control, an alternative table, a sync pattern, a combined bit, etc. when generating a modulation signal on the recording side, so that the state of FIG. The system has been configured so that the occurrence frequency / degree is suppressed, and the slice level control at the time of reproduction does not need to correspond.
[0009]
However, as the density increases, the modulation efficiency of the modulation signal has become important, and it is necessary to reduce the number of combined bits and the like for sufficiently reducing the low frequency components.
[0010]
As described above, it is conceivable to reduce the influence by pre-reading the data pattern at the time of generating the modulation signal and switching the Sync pattern. However, in FIG. 8B and FIG. 8) is brought to the state of FIG. 8A, the role of the slice level control circuit is, so that time constant reacts to the change of the DC component also in the case of FIG. 8D, that is, malfunction. As a result, the slice level fluctuates, and an area that cannot be correctly reproduced is generated in the sync. This is shown in FIG. Therefore, it has been desired to improve the appropriate slice level control that can cope with the state of FIG.
[0011]
The present invention has been made in view of the above points, and appropriately copes with all the states shown in FIGS. 8B, 8C, and 8D with respect to a reproduction signal of a recording medium recorded with high density. It is an object of the present invention to provide a digital signal reproducing apparatus including a slice level control that can be performed.
[0012]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the present invention A digital signal reproducing apparatus having binarizing means, code deviation detecting means, and slice level control signal output means, wherein the binarizing means receives a reproduction signal reproduced from a recording medium as one input. On the other hand, the slice level signal for selecting the amplification gain from the slice level control signal output means is used as the other input, and the reproduction signal is binarized based on the slice level signal to output a binarized signal, The code deviation detection means includes no-crossing detection means, randomness detection means, deviation extraction means, and deviation information output means, and the no-crossing detection means includes a predetermined run length in the binarized signal. It is detected whether or not the above pattern exists, and the detection result is output as non-crossing information. The randomness detection means includes the bias extraction means in the binarized signal. Detecting whether or not a pattern having a predetermined run length or more exists in the polarity opposite to the force value, and outputting the detection result as random information, wherein the bias extraction means is configured to output the no-crossing information or the Reset based on the input of random information, input the binarized signal, convert the value of 1 or 0 to +1 or −1, perform cumulative addition, find the absolute value of the cumulative addition output, By comparing with a threshold value, the appearance ratio of the 1 or 0 value exceeds the predetermined threshold in the modulation code pattern consisting of 1 or 0 value in the binarized signal. The presence / absence of the bias is extracted and the presence / absence of the bias is output as modulation code pattern bias information. The slice level control signal output means comprises a gain switching means and an integrating means, and the gain switching means In accordance with the modulation code pattern deviation information from the code deviation detecting means, the amplification gain of the binarized signal output from the binarizing means is selected and amplified, and the amplified output is integrated into the integrating means And the integrating means performs low-pass filtering on the signal input from the gain switching means to extract a low-frequency component, and outputs the extracted low-frequency component as the slice level to the binarizing means. To A digital signal reproducing apparatus is provided.
[0015]
Further, in order to solve the above-described problems, the present invention is based on sampling means for sampling an input reproduction signal with a predetermined clock and outputting a sampled signal, and based on the DC level control signal, DC control means for controlling a DC level, binarization means for slicing or decoding the sampled signal or the signal obtained by filtering the sampled signal and outputting the binarized signal, and the binarized signal DC level control signal output means for outputting the DC level control signal based on a signal, and code bias detection means for detecting a modulation code pattern bias based on the binarized signal and outputting modulation code pattern bias information And changing a control response characteristic of the DC control means based on the modulation code pattern bias information. Properly is to provide a digital signal reproducing apparatus characterized by stopping the DC control.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a first embodiment of a digital signal reproducing apparatus according to the present invention.
[0018]
The binarizing means 1 and integrating means 4 have the same configuration as the binarizing means 904 and integrating means 906 in FIG.
[0019]
In the figure, a reproduction signal reproduced from a recording medium such as an optical disk is preamplified by a preamplifier (not shown) and then input to the binarizing means 1 in FIG. The binarizing means 1 compares the reproduction signal with the slice level supplied from the integrating means 4 and outputs a binarized signal. The binarized signal is output to the outside of the block as demodulated data, and is also supplied to the gain switching means 3 and the code deviation detecting means 2.
[0020]
The code deviation detecting means 2 forms a main part of the present invention, determines whether or not there is a deviation in the modulation code, and supplies the resulting modulation code pattern deviation information to the gain switching means 3. Details of the inside will be described later.
[0021]
The gain switching means 3 supplies the result to the integrating means 4 while appropriately selecting the amplification gain according to the modulation code pattern deviation information supplied from the code deviation detecting means 2.
[0022]
FIG. 2 shows an example of the internal configuration of the gain switching means 3. The input binarized signal is supplied to the amplifying means 31 and the amplifying means 32 having different gains. Each output is input to the SW 33, and the SW 33 selects one of the inputs of the amplifying unit 2 and the amplifying unit 3 based on the modulation code pattern bias information and supplies the selected input to the integrating unit 4.
[0023]
Here, two types of gains (gains) are shown, but it goes without saying that more gains may be prepared and fine selection may be performed.
[0024]
FIG. 3 shows another example of the internal configuration of the gain switching means 3. In this example, the value of the modulation code pattern bias information is handled as a coefficient, the amplification and multiplication means 34 multiplies the binarized signal by a coefficient, and the result is supplied to the integration means 4. It is characterized by finer control.
[0025]
The integration unit 4 performs low-pass filtering on the input signal, extracts a low-frequency component, and supplies it to the binarization unit 1 as a slice level (threshold level).
[0026]
In this embodiment, when the code deviation detecting means 2 determines that the modulation code is biased, the gain switching means 3 selects the smaller gain, and as a result, the time constant in the slice level feedback loop becomes larger. (Slow response) and slow response. That is, a correct binarized signal can be obtained by reducing the change in slice level due to malfunction. At this time, as an extreme example of gain switching, it goes without saying that the gain may be set to 0 to be in a hold state (non-response state).
[0027]
Next, the configuration of the code deviation detecting means 2 will be described with reference to FIG. The binarized signal supplied from the binarizing means of FIG. As shown in It is supplied and input to the bias extraction means 22 and also input to the non-crossing detection means 24 and the randomness detection means 25. The no-crossing detecting means 24 detects whether or not a pattern longer than a predetermined run length exists in the binarized signal and outputs it as no-crossing information. Randomness detecting means 25 detects whether or not a pattern having a predetermined run length or more exists in the signal after binarization in the opposite polarity to the output value of the bias extracting means, and the random information Output as. The bias extraction means 22 extracts the low frequency component of the binarized signal or the bias of the modulation code pattern, and resets the value as appropriate based on the input non-crossing information and random information. The output of the bias extraction unit 22 is input to the bias information output unit 23 and compared with a predetermined value, and the result is supplied to the gain switching unit 3 as modulation code pattern bias information.
[0028]
FIG. 5 shows an example of the inside of the bias extraction means 22 and the bias information output means 23. The input binarized signal is input to the SW 225 and the output of the “1” generator 223 and the “−1” generator 224 is switched. The output of the SW 225 is input to the adder 226 and added with the output of the coefficient unit 227 set to a gain coefficient k times. The output of the adder 226 is input to the D-FF 222. Similarly, a clock synchronized with a channel rate (not shown) is supplied to the D-FF 222, and is delayed by one clock (one bit) at that timing. The Q output of the D-FF 222 is supplied to the coefficient unit 227, is also output to the terminal 228, and is supplied to the bias information output means 23. Inside the bias information output means 23, the absolute value circuit 230 calculates an absolute value, and the comparison circuit compares the output with a predetermined value (not shown). The determination result is output as modulation code pattern bias information.
[0029]
The low frequency component of the code pattern of the binarized signal is extracted from the Q output of the D-FF 222. When the low frequency component is small, it approaches the average value 0, and when the low frequency component is large, the low frequency component is separated from zero. Therefore, it is considered that the larger the absolute value of this value, the greater the bias of the code. Therefore, when the absolute value exceeds a predetermined value, it is determined that the modulation code is biased.
[0030]
However, there is a case where the absolute value increases even though a normal signal with a small bias of the original code is input. When the signal does not intersect with the slice level (extreme state in FIG. 8B), it slightly intersects (state shown in FIG. 8B or FIG. 8C). In this case, it is misjudgment.
[0031]
Therefore, as shown in FIG. 5, based on non-crossing information and random information, when it is considered that there is no crossing state or random signal input state, the D-FF 222 is reset and the output of the bias detection means 22 is forcibly set. Set to zero. By adopting such a configuration, the output of the bias information output means 23 also becomes information that the modulation code pattern is not biased (or cannot be determined), and erroneous determination can be eliminated.
[0032]
In the case of FIG. 5, if no-crossing information indicates 1 when there is no crossing, 0 indicates otherwise, and random information indicates 0 when randomness is strong and 1 indicates otherwise, A logical sum of random information is calculated by an OR circuit 221 and input to the D-FF 222 as a reset signal.
[0033]
Next, a specific example of the no-cross detection means 24 will be described with reference to FIG. The supplied binarized signal is supplied to the tap delay block 241 and is delayed by one bit at a clock timing (not shown) by a tap delay realized by a plurality of cascade-connected D-FFs and the like. Columns TD1-TDn are obtained. Here, n is an arbitrary integer, but in order to make the non-crossing information more accurate, it is desirable to select a number larger than the maximum run length limit of the modulation code. The TD1 to TDn are supplied to the AND block 242 and the NOR block 243. The AND block 242 detects all “1” states and the NOR block 243 detects all “0” states, and the OR block 244 performs an OR operation on them. After calculating, the result is output as no-crossing information. When the no-crossing information is “1”, it indicates that no intersection has occurred, and when the no-crossing information is “0”, it indicates that there is an intersection. If the D-FF 222 of the bias detection means is reset at the time when no-crossing is detected (the state of “1”), the extremely shifted state of FIG. 8B is erroneously determined as the state of FIG. There is nothing to do.
[0034]
A specific example of the randomness detecting means 25 will be described with reference to FIG. The binarized signal supplied from the terminal 21 is supplied to the tap delay block 251 and is delayed by one bit at a clock timing (not shown) by a tap delay realized by a plurality of cascaded D-FFs. The obtained data strings TR1 to TRm are obtained. Here, m is an arbitrary integer, but in order to make the random information more accurate, it is desirable to select an average value or a value slightly larger than the run length limit of the modulation code. TR1 to TRm are supplied to the AND block 252 and the NOR block 253. The AND block 252 detects all “1” states and the NOR block 253 detects all “0” states, and the AND block 256 and the AND block 257 detect them. Supplied respectively.
[0035]
Further, the output signal of the bias detecting means 22 is supplied to the binarization block 254, and “1” is output when the polarity is +, and “0” is output when the polarity is −. The output is supplied to the AND block 257 and also supplied to the AND block 256 via the NOT block 255. The NOT block has a function of inverting logic.
[0036]
The AND block 256 and the AND block 257 calculate the logical product of the two input signals, and the respective results are supplied to the OR block 258. The OR block 258 calculates the logical sum of the two input signals and outputs it as random information.
[0037]
The operation of the randomness detecting means 25 will be described with reference to FIG.
[0038]
In the state of FIG. 8 (d), the output of the bias detection means should be directed to the lower side (− side) of the figure, and at that time, indicated by m on the upper side (+ side) of the opposite side figure. There is no run length average or slightly longer than this. That is, the no-cross information that is the calculation result of the configuration shown in FIG. 7 indicates “0”.
[0039]
Even in the extremely shifted state of FIG. 8B or the state of FIG. 8C, the output of the bias detecting means should be directed to the lower side (− side) of FIG. 8, but the randomness is high. On the opposite side (upper side) of the figure, there is a run length as indicated by m or a run length slightly larger than that. When such a run length appears, the no-crossing information that is the calculation result of the configuration shown in FIG. 7 is “1”, and at that time (the state of “1”), the bias detection means D− If the FF 222 is reset, the absolute value does not exceed a predetermined value, so that the state that is extremely deviated in FIG. 8B or the state in FIG. 8C is misidentified as the state in FIG. Is solved.
[0040]
Next, another embodiment will be described. Although FIG. 1 shows the one corresponding to the conventional example, it can also be applied to digital signal processing and PRML signal processing.
[0041]
A second embodiment is shown in FIG. The reproduction signal is input to the DC control means 10. The DC control means 10 controls the DC level of the reproduction signal based on the DC error signal supplied from the error detection means 15a. The output is input to the A / D converter 11 and sampling is performed with a clock supplied from the PLL 13. The output of the A / D conversion 11 is supplied to the binarizing means 16 a and also input to the equalizer 12. The equalizer performs appropriate filtering and then provides its output to the PLL 13 and the decoder 14. The decoding 14 outputs the binarized data using slice detection or Viterbi decoding, and supplies it to the ECC or the like. The binarizing means 16a binarizes the input signal and supplies the binarized signal as a result to the error detecting means 15a. The error detection means 15a extracts the low frequency component of the binarized signal and outputs a DC error signal obtained as a result.
[0042]
An example of the internal configuration of the error detection means 15a is shown in FIG. The input binarized signal is input to the gain switching means 155, amplified to a predetermined gain, and then the low frequency component is extracted by the integrating means 156. The result is a DC error signal. Further, the binarized signal forms a main part of the present invention, and it is determined whether or not the modulation code is biased, and the resulting modulation code pattern bias information is supplied to the gain switching means 155. . The details of the inside are the same as those described with reference to FIGS. This form is characterized in that the DC level of the signal is controlled instead of the slice level.
[0043]
A third embodiment is shown in FIG. The same functional blocks as those in FIG. 10 are denoted by the same reference numerals, and the description thereof is omitted. The binarizing means 16b and the error detecting means 15b are used instead of the binarizing means 16a and the error detecting means 15a of FIG. 10, and the output of the equalizer 12 is supplied to the binarizing means 16b. The operations of the binarizing means 16b and the error detecting means 15b are the same as those of the binarizing means 16a and the error detecting means 15a, respectively. This form is characterized in that the DC level is controlled based on information on the output of the equalizer.
[0044]
A fourth embodiment is shown in FIG. The same functional blocks as those in FIG. 10 are denoted by the same reference numerals, and description thereof is omitted. Instead of the binarization means 16a and the error detection means 15a in FIG. 10, an error detection means 15c is used, and the output of the decoding 14 is supplied to the error detection means 15c as a binarized signal. The operation of the error detection 15c is the same as that of the error detection means 15a. This mode is characterized in that the DC level is controlled based on the information of the decoded output.
[0045]
A fifth embodiment is shown in FIG. The same functional blocks as those in FIG. 10 are denoted by the same reference numerals, and description thereof is omitted. The reproduction signal is supplied to the A / D converter 10, sampled, and then supplied to the DC control means 17. The DC control means 10 controls the DC level of the reproduction signal based on the DC error signal supplied from the error detection means 15d. The output is supplied to the equalizer 12 and also supplied to the binarizing means 16d. The output of the binarizing means 16d is supplied to the error detecting means 15d. The operations of the binarizing unit 16d and the error detecting unit 15d are the same as those of the binarizing unit 16a and the error detecting unit 15a, respectively. This form is characterized in that it is intended to control the DC level in the signal after sampling.
[0046]
A sixth embodiment is shown in FIG. The same functional blocks as those in FIG. 14 are denoted by the same reference numerals, and description thereof is omitted. The binarizing means 16e and the error detecting means 15e are used in place of the binarizing means 16d and the error detecting means 15d in FIG. 14, and the output of the equalizer 12 is supplied to the binarizing means 16e. The operations of the binarizing means 16e and the error detecting means 15e are the same as those of the binarizing means 16d and the error detecting means 15d, respectively. This form is characterized in that the DC level is controlled based on information on the output of the equalizer.
[0047]
A seventh embodiment is shown in FIG. The same functional blocks as those in FIG. 14 are denoted by the same reference numerals, and description thereof is omitted. Instead of the binarizing means 16d and the error detecting means 15d in FIG. 14, an error detecting means 15f is used, and the output of the decoding 14 is supplied to the error detecting means 15f as a binarized signal. The operation of the error detection means 15f is the same as that of the error detection means 15d. This mode is characterized in that the DC level is controlled based on the information of the decoded output.
[0048]
An eighth embodiment is shown in FIG. The same functional blocks as those in FIG. 14 are denoted by the same reference numerals, and description thereof is omitted. The binarization means 16g and the error detection means 15g are used instead of the binarization means 16d and the error detection means 15d in FIG. 14, and the output of the A / D converter 10 is supplied to the binarization means 16g. ing. The operations of the binarizing means 16g and the error detecting means 15g are the same as those of the binarizing means 16d and the error detecting means 15d, respectively. This mode is characterized in that the DC level is controlled based on the information of the output of A / D and the feedforward operation is going to be performed.
A ninth embodiment is shown in FIG. The same functional blocks as those in FIG. 10 are denoted by the same reference numerals, and description thereof is omitted. The PLL 13 is deleted, and the output of the A / D converter 11 is resampled via the DPLL 18 and is supplied to the equalizer 12 after becoming a data string of the channel rate. Although the binarizing means 16h and the error detecting means 15h are used in place of the binarizing means 16a and the error detecting means 15a in FIG. 10, the operations of the binarizing means 16h and the error detecting means 15h are binarized. The same as the means 16a and the error detection means 15a. This form is characterized in that it is compatible with DPLL.
[0049]
A tenth embodiment is shown in FIG. The same functional blocks as those in FIG. 18 are denoted by the same reference numerals, and description thereof is omitted. Instead of the binarizing means 16h and the error detecting means 15h in FIG. 18, the binarizing means 16i and the error detecting means 15i are used, and the output of the DPLL 18 is supplied to the binarizing means 16i. The operations of the binarizing means 16i and the error detecting means 15i are the same as those of the binarizing means 16h and the error detecting means 15h, respectively. This form is characterized in that the DC level is controlled based on the output information of the DPLL.
[0050]
An eleventh embodiment is shown in FIG. The same functional blocks as those in FIG. 18 are denoted by the same reference numerals, and description thereof is omitted. The binarizing means 16j and the error detecting means 15j are used instead of the binarizing means 16h and the error detecting means 15h in FIG. 18, and the output of the equalizer 12 is supplied to the binarizing means 16j. The operations of the binarizing means 16j and the error detecting means 15j are the same as those of the binarizing means 16h and the error detecting means 15h, respectively. This embodiment is characterized in that the DC level is controlled based on the output information of the equalizer 12.
[0051]
A twelfth embodiment is shown in FIG. The same functional blocks as those in FIG. 18 are denoted by the same reference numerals, and description thereof is omitted. Instead of the binarization means 16h and the error detection means 15h in FIG. 18, an error detection means 15k is used, and the output of the decoding 14 is supplied to the error detection means 15k as a binarized signal. The operation of the error detection means 15c is the same as that of the error detection means 15h. This mode is characterized in that the DC level is controlled based on the information of the decoded output.
[0052]
Next, the effect of the present invention will be described based on the result of simulation using the first embodiment and the ninth embodiment. 24 to 27 show the characteristics of the conventional system described with reference to FIGS. 42 and 43. FIG. 24 shows the reproduction signal, slice level, and binarized signal from the top, with the horizontal axis indicating time and the vertical axis indicating level. The reproduction signal is switched at the horizontal axis 2400 from the state of FIG. 8A described in FIG. 8 to the state of FIG. 8D. An enlarged view of this part is shown in FIG. Although it is an extreme example of the signal, it can be seen from this timing that the slice level control malfunctions and the slice level is starting to fall. As shown in FIG. 24, the final value of the slice level is almost attached to the lower part of the signal, and correct binary data cannot be obtained.
[0053]
FIG. 26 is an eye pattern of the PLL output unit when the function of the present application is turned off using the ninth embodiment. The DC level of the signal is greatly changed due to a malfunction, and the lock is released. (Originally, it is desirable that the horizontal lines are connected.) FIG. 27 further shows the eye pattern after the equalizer. Again, it can be seen that the DC level of the signal is greatly changed due to a malfunction, and the lock is released. (Originally, it is desirable that the horizontal lines are connected.) FIG. 28 shows the output of the D-FF 222 described with reference to FIG. 5 in a state in which the function of the present application is turned off. It can be seen that the absolute value is large (bias is detected). FIG. 29 further shows the modulation code pattern bias information that has passed through the bias information output means 23, and it can be seen that it is correctly and quickly discriminated (from 0 to 1).
[0054]
30 to 33 show characteristics of the present application using the first embodiment described in FIG. FIG. 30 shows the reproduction signal, slice level, and binarized signal from the top, with the horizontal axis indicating time and the vertical axis indicating level. The reproduction signal is switched at the horizontal axis 2400 from the state of FIG. 8A described in FIG. 8 to the state of FIG. 8D. An enlarged view of this part is shown in FIG. In this case, since the mode is switched in a relatively short time from the switching timing and the response is delayed, it can be seen that the way of decreasing the slice level is delayed. As shown in FIG. 30, the final value of the slice level is hardly lowered, and correct binary data can be obtained. FIG. 32 is an eye pattern of the PLL output unit when the function of the present application is turned on using the ninth embodiment. Since the change in the DC level of the signal is suppressed by switching the mode, the lock is not released and the horizontal line is connected. Although the lock is released at the horizontal axis 9800, in this case, since the length of one sync is about 6000, it can be held up to the next sync sufficiently, and the signal itself is improved thereafter. It turns out that it is enough. If a longer response is required as a specification, the response characteristic may be set slower. FIG. 33 further shows the eye pattern after the equalizer. Again, since the change in the DC level of the signal is suppressed by switching the mode, the lock is not released and the horizontal line is connected. Although the lock is released at the horizontal axis 9800, in this case, since the length of one sync is about 6000, it can be held up to the next sync sufficiently, and the signal itself is improved thereafter. It turns out that it is enough. If a longer response is required as a specification, the response characteristic may be made slower.
[0055]
From the above results, the effect of the present application for changing the response of slice level control or DC control based on modulation code pattern bias information was confirmed.
[0056]
Next, effects of the non-crossing detection unit and the randomness detection unit will be described with reference to FIGS. FIG. 34 shows the DC control means output signal when DC control is performed using the ninth embodiment from the extreme state of FIG. 8B (the state where the DC of the reproduction signal is greatly shifted to the + side). The horizontal axis indicates time, and the vertical axis indicates level. The function of the present application is in a state of being turned off (invalid). At this time, since the vertical axis 0 is the slice level of the binarization means, it can be seen that the horizontal axis converges around 6000 and is an appropriate DC level.
[0057]
FIG. 35 shows the state of the D-FF 222 described with reference to FIG. 5 in a state where the non-crossing detection means and the randomness detection means are turned off (the reset signal in FIG. 5 is fixed to 0 so as not to be reset). The output is shown, and the absolute value is considerably large until convergence (up to the horizontal axis 6000). FIG. 36 further shows the modulation code pattern bias information that has passed through the bias information output means 23, and it is erroneously discriminated from the state of FIG. 8D in which the code pattern is biased (from 0 to 1). I understand).
[0058]
However, FIG. 37 shows non-crossing information at this time, and it can be seen that a non-crossing state is detected between 0 and 3000 on the horizontal axis (from 0 to 1). Further, FIG. 38 shows random information, and it can be seen that the random state is intermittently detected (between 0 and 1) between about 2300 to 8200 on the horizontal axis. FIG. 39 is a logical OR of these two pieces of information, and corresponds to the reset signal of FIG. That is, the erroneous determination described above can be avoided by generating the reset signal intermittently and sufficiently between 0 and 8200 which converges sufficiently. FIG. 40 shows the output of the D-FF 222 described with reference to FIG. 5 when the reset signal is turned on (valid), and it can be seen that the absolute value is small. As a result, the modulation code pattern bias information shown in FIG. 41 also remains 0, and is not distinguished from the state of FIG. 8D where the code pattern is biased. Therefore, it is possible to converge quickly without erroneous determination.
[0059]
From the above results, the effect of the present application for resetting the value inside the bias detection means based on the no-crossing information and the random information was confirmed.
[0060]
Next, another example of the bias extraction unit will be described. This is to detect the deviation of the modulation code pattern by utilizing the correlation with the code pattern set in advance instead of the low frequency component of the binarized signal in the deviation detection means 22.
[0061]
FIG. 22 shows the configuration and corresponds to the “1” generator 223, the “−1” generator 224, and the SW 225 in FIG. The input binarized signal is supplied to the tap delay block 250, and a data string TZ1 delayed by one bit at a clock timing (not shown) by a tap delay realized by a plurality of cascaded D-FFs or the like. TZp is obtained. Here, p is an arbitrary integer. Furthermore, in order to correlate TZ1 to TZn with a preset code pattern, an exclusive OR is calculated for each bit. FIG. 2 Now, a case where p = 16 will be described, and a case where “... 00001110000...” Is selected as a representative example of the bit code pattern is shown. This is because when the modulation signal run length is limited, if the modulation code is biased, either the upper or lower inversion interval approaches the minimum inversion interval, and the other approaches the maximum inversion interval. In this case, assuming that the minimum inversion interval = 3, the central three bits are set to “1”, and the other bits are set to “0”. In this case, since the exclusive OR with 0 is the same as nothing and the exclusive OR with 1 is the same as inversion, only the portion corresponding to “1” is inverted in FIG. .
[0062]
Further, the p bit which is the result is added, and 8 which is p / 2 is subtracted. Further, when the no-crossing information supplied from the no-crossing detecting means 24 is 1, this result is output as 0, and when it is 0, it is output as it is and supplied to the adder 226.
[0063]
By using the correlation in this way, it is possible to accurately determine the degree of bias without depending on a specific pattern. Further, even when the state of FIG. 8B becomes extreme and the frequency at which the signal crosses the slice level becomes low, it can be dealt with. This is because the period in which the no-crossing information indicates no-crossing does not react, and the interval at which the minimum inversion interval appears is not limited. Since the correlation is basically used, the feature of this embodiment is that when a signal having no correlation is input, the mode is automatically returned to the normal mode.
[0064]
Also, it is possible that the input 0 and 1 of TZ1 to TZp and 0 and 1 of the predetermined pattern correspond to −1 and +1, respectively, and the result of multiplication is added for all bits and supplied to SW255. It is. This block diagram is shown in FIG.
[0065]
Further, by detecting the correlation between the binarized data and the predetermined code pattern, the bias of the code pattern is detected. However, instead of the binary, for example, 8-bit reproduction data and the predetermined code pattern are converted into exclusive logic. Of course, a multiplier may be used instead of the sum. Furthermore, the predetermined code pattern is represented by, for example, 8-bit data that is close to the partial response characteristic of the reproduction signal, and may be configured using a multiplier instead of the exclusive OR.
[0066]
Further, the present invention is not limited to the above-described form, and it goes without saying that the equalizer circuit may be omitted depending on the system. Basically, since the code bias is not frequently generated, the most effective effect can be obtained by switching the mode quickly when it does not deteriorate the performance of the conventional system. In this sense, the present application is optimal.
[0067]
Further, since the correspondence to the code bias is basically additional, it is desirable that the circuit scale is as small as possible. Since the present application uses a 1-bit signal after binarization, the circuit scale is small and optimal.
[0068]
【The invention's effect】
As described above, according to the present invention, even when the modulation code pattern of the modulation signal to be recorded, which could not be handled in the past, is biased, correct detection can be performed without causing malfunction, In addition, by reducing the number of combined bits for sufficiently reducing the low frequency components as much as possible, the modulation efficiency of the modulation signal required as the density increases can be improved, and the conventional performance can be improved. It is possible to quickly detect and respond to a specific mode without lowering it. Furthermore, since the correspondence to code bias uses a 1-bit signal after binarization, the circuit scale is small. It has the advantage that it can be handled with a product.
[Brief description of the drawings]
FIG. 1 is a block diagram of a first exemplary embodiment of the present invention.
FIG. 2 is a block diagram showing an example of gain switching means.
FIG. 3 is a block diagram showing another example of gain switching means.
FIG. 4 is a block diagram showing an example of code deviation detecting means.
FIG. 5 is a block diagram showing an example of bias extraction means and bias information output means.
FIG. 6 is a block diagram showing a specific example of no-crossing detection means.
FIG. 7 is a block diagram showing a specific example of randomness detecting means.
FIG. 8 is a diagram illustrating characteristics of a reproduction signal waveform.
FIG. 9 is a diagram for explaining an area that is not correctly reproduced;
FIG. 10 is a block diagram of a second exemplary embodiment of the present invention.
FIG. 11 is a diagram illustrating an example of a configuration of an error detection unit.
FIG. 12 is a block diagram of a third exemplary embodiment of the present invention.
FIG. 13 is a block diagram of a fourth embodiment of the present invention.
FIG. 14 is a block diagram of a fifth embodiment of the present invention.
FIG. 15 is a block diagram of a sixth embodiment of the present invention.
FIG. 16 is a block diagram of a seventh exemplary embodiment of the present invention.
FIG. 17 is a block diagram of an eighth embodiment of the present invention.
FIG. 18 is a block diagram of a ninth embodiment of the present invention.
FIG. 19 is a block diagram of a tenth embodiment of the present invention.
FIG. 20 is a block diagram of an eleventh embodiment of the present invention.
FIG. 21 is a block diagram of a twelfth embodiment of the present invention.
FIG. 22 is a diagram illustrating an example of a bias extraction unit.
FIG. 23 is a block diagram showing another example of bias extraction means.
FIG. 24 is a diagram showing characteristics of a conventional digital signal reproduction device.
FIG. 25 is an enlarged view showing characteristics of a conventional digital signal reproduction device.
FIG. 26 is a diagram showing an example of a conventional PLL circuit output eye pattern.
FIG. 27 is a diagram showing an example of a conventional equalizer circuit output eye pattern.
28 is a diagram illustrating an output of a D-FF 222. FIG.
FIG. 29 is a diagram showing modulation code pattern bias information that has passed through the bias information output means;
FIG. 30 is a diagram illustrating a reproduction signal, a slice level, and a binarized signal using the first embodiment.
FIG. 31 is an enlarged view showing a reproduction signal, a slice level, and a binarized signal using the first embodiment.
FIG. 32 is a diagram showing an example of a PLL circuit output eye pattern using the first embodiment.
FIG. 33 is a diagram illustrating an example of an equalizer circuit output eye pattern using the first embodiment.
FIG. 34 is a diagram showing a DC control means output signal.
35 is a diagram showing an output of a D-FF 222. FIG.
FIG. 36 is a diagram showing modulation code pattern bias information that has passed through the bias information output means;
FIG. 37 is a diagram showing no-crossing information.
FIG. 38 is a diagram illustrating random information.
FIG. 39 is a diagram illustrating a logical sum of no-crossing information and random information.
40 is a diagram showing an output of a D-FF 222. FIG.
FIG. 41 is a diagram illustrating modulation code pattern bias information.
FIG. 42 is a block diagram of a conventional digital signal reproduction device.
FIG. 43 is a block diagram of a conventional digital signal reproduction device.
1 Binarization means
2 Code deviation detection means
3 Gain switching means
4 Integration means

Claims (1)

A digital signal reproduction apparatus having binarization means, code deviation detection means, and slice level control signal output means,
The binarization means includes
A reproduction signal reproduced from a recording medium is used as one input, while a slice level signal for selecting an amplification gain from the slice level control signal output means is used as the other input, and the reproduction signal is based on the slice level signal. Binarize and output the signal after binarization,
The code deviation detecting means includes
Non-crossing detection means, randomness detection means, bias extraction means, and bias information output means,
The non-crossing detecting means detects whether or not a pattern having a predetermined run length or more exists in the binarized signal, and outputs the detection result as non-crossing information,
The randomness detecting means detects whether or not a pattern having a predetermined run length or more exists in the polarity opposite to the output value of the bias extracting means in the binarized signal, The detection result is output as random information,
The bias extraction means resets based on the input of the no-crossing information or the random information, inputs the binarized signal, converts the value of 1 or 0 into +1 or −1, and then cumulatively adds it. The absolute value of the cumulative addition output is obtained and compared with a predetermined threshold value, whereby the appearance ratio of the value of 1 or 0 in the modulation code pattern consisting of the value of 1 or 0 in the binarized signal is set to the predetermined threshold value. Extracting the presence / absence of a deviation in the appearance ratio of the value of 1 or 0 exceeding, and outputting the presence / absence of the deviation as modulation code pattern deviation information;
The slice level control signal output means includes
It consists of gain switching means and integration means,
The gain switching means selects and amplifies the amplification gain of the binarized signal output from the binarization means according to the modulation code pattern deviation information from the code deviation detection means, and amplifies the amplification Output to the integration means;
The integrating means performs low-pass filtering on the signal input from the gain switching means to extract a low-frequency component, and outputs the extracted low-frequency component as the slice level to the binarizing means;
A digital signal reproducing apparatus.

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