KR100936031B1 - Apparatus for detecting binary signal using non-linear transformer - Google Patents

Abstract

Disclosed is a binary signal detection apparatus using a nonlinear transducer. The binary signal detecting device includes: a nonlinear converter for converting an input signal to have a value within a predetermined range; A level detector which receives the converted signal from the nonlinear converter and detects and outputs an optimal level value; And a Viterbi decoder for detecting a binary signal by decoding the converted signal input from the nonlinear converter according to the optimum level value input from the level detector. The binary signal detection apparatus according to the present invention can more accurately detect a binary signal by correcting a signal input to a Viterbi decoder by a nonlinear converter and using a Viterbi decoder with a corrected signal and an optimal level detected. Data stored in a data storage medium such as an optical disc can be smoothly reproduced.

Description

Apparatus for detecting binary signal using non-linear transformer}

1 is an example of a digital binary signal detection apparatus including a conventional Viterbi decoder,

2 is a block diagram showing a preferred embodiment of a binary signal detection apparatus according to the present invention;

3 is a block diagram showing a detailed structure of a nonlinear transducer;

4 shows an embodiment of a FIR filter,

5 is a graph showing a nonlinear function,

6 shows an embodiment of a level detector,

7A-7C illustrate embodiments of a destination channel filter;

8 is a flowchart for explaining an operation of a selection signal generator;

9 is a graph for explaining a specific operation of the binary signal detection apparatus according to the present invention;

10 to 14 show a binary signal detection apparatus according to the present invention including various nonlinear transducers.

The present invention relates to a binary signal detection device, and more particularly, to a binary signal detection device for detecting a binary signal from the RF signal reflected from the optical disk.

There is an optical disc as a data storage medium. The optical disc drive reproduces the binary signal recorded on the optical disc by reading a reflected wave by injecting a laser into the optical disc. At this time, the signal reflected from the optical disk is called a radio frequency (RF) signal.

Binary signals are recorded on optical disks, but RF signals are analog signals due to their disk and optical properties. Therefore, the binarization process and phase lock loop (PLL) are necessary to convert analog signals into digital signals. The binarization means can be implemented in various ways. Among them, a Viterbi decoder can be used to obtain a binary signal with less error.

1 illustrates an example of a digital binary signal detection apparatus including a conventional Viterbi decoder. The Viterbi decoder detects binary signals under optimal conditions to suit the characteristics of the channel, and is known to have better binary signal detection performance than simple sign detection circuits or run-length correction schemes. have. For a more detailed description of a detector with a Viterbi decoder, see Korean Patent Application No. 2000-0056149, "Selective Disturbance Compensation Device and 3T Correction Method for Reproducing Optical Recording Media," and Korean Patent Application No. 1998-0049542, "Data Reproduction." Device ”.

In general, when a signal having an equalizer is input to the Viterbi decoder, a better performance can be obtained by using the signal passed through the equalizer as the input signal of the Viterbi decoder. The equalizer is a type of FIR filter used to optimize channel characteristics. The equalizer may have a fixed filter coefficient or may be implemented such that the filter coefficient is changed to match the channel characteristic. For more detailed description of the equalizer, see Korean Patent Application No. 2000-0000965, "Data Reproducing Apparatus and Method for Enhancing Detection Performance by Adjusting Crystal Level Used in Data Detector," Korean Patent Application No. 2000-0056149, "Optical Recording. Selective disturbance compensation device and 3T correction method when playing media "and Korean Patent Application No. 1998-0049542," Data Reproducing Device ".

On the other hand, as the data recording density of the optical disc becomes higher, the quality of the reproduced signal becomes worse and worse, which causes malfunction. When the signal quality is poor, an error sometimes occurs beyond the level of the binarization level of the signal. In this case, the signal is not properly detected, and thus an error occurs even when a Viterbi decoder is used.

Accordingly, an aspect of the present invention is to provide a binary signal detection apparatus capable of detecting a binary signal more accurately even when an error exceeding a level of a signal binarization level occurs.

In order to achieve the above object, the binary signal detection apparatus according to the present invention, the non-linear converter for converting the input signal to have a value within a predetermined range; A level detector which receives the converted signal from the nonlinear converter and detects and outputs an optimal level value; And a Viterbi decoder for detecting a binary signal by decoding the converted signal input from the nonlinear converter according to the optimum level value input from the level detector.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Figure 2 is a block diagram showing a preferred embodiment of the binary signal detection apparatus according to the present invention. Referring to FIG. 2, a binary signal detection apparatus includes an analog-to-digital converter (ADC) 11, a DC offset canceler 12, a nonlinear converter 13, an equalizer EQ 14, and a beater. A viterbi decoder 15, a PLL 16, and a level detector 17 are included.

When the RF signal is input to the ADC 11, A / D conversion is performed. The DC offset remover 12 receives a digital signal output from the ADC 11 and removes the DC value. The waveform from which the DC value has been removed is input to the nonlinear converter 13, the DC offset canceller 12, and the PLL 16. For a detailed description of the DC offset eliminator 12 and the PLL 16, refer to Korean Patent Application No. 2000-0056149, "Selective Disturbance Compensation Device and 3T Correction Method for Reproducing Optical Recording Media" and Patent Application No. 1998-0049542, Described in the "data reproducing apparatus", the detailed description is omitted here.                     

The nonlinear converter 13 is a device for changing the shape of a signal by using a nonlinear function. The nonlinear converter 13 performs a function of forcibly saturating a waveform above a certain value or forcibly removing a waveform below a certain value. The waveform passed through the nonlinear transducer 13 is input to the equalizer 14.

Better performance can be obtained by using the equalizer (EQ) so that the signal with the optimal condition can enter the input of the Viterbi decoder 15, but when using the nonlinear converter 13, the Viterbi decoder 15 The equalizer 14 is not necessarily necessary because it is converted to a correct signal. Thus, the equalizer 14 may or may not be used.

The equalizer 14 is a type of FIR filter used to make the characteristics of the channel optimal. The equalizer 14 may have a fixed filter coefficient or may be implemented such that the filter coefficient is changed to match the channel characteristic. Detailed description of the equalizer 14 is described in Korean Patent Application No. 2000-0000965, "Data reproducing apparatus and method for improving detection performance by adjusting the crystal level used in the data detector", Korean Patent Application No. 2000-0056149 , "Selective Disturbance Compensation Device and 3T Correction Method in Optical Recording Media Reproduction" and Korean Patent Application No. 1998-0049542, "Data Reproducing Device".

The Viterbi decoder 15 is an apparatus for obtaining an optimal binary signal using statistical characteristics of the input signal. In general, in order to configure a Viterbi decoder, a level suitable for a characteristic of an input signal must be defined, and a structure having a binary signal with less error is obtained by determining a statistical characteristic of the input signal according to the level.

The level detector 17 receives the output signal of the equalizer 14 or the output signal of the nonlinear transducer 13 when the equalizer 14 is not used, detects an optimal level value, and then beats the value. Input to the non-decoder 15.

The Viterbi decoder 15 is an adaptive Viterbi decoder, and can receive optimal performance by receiving an optimal level value from the level detector 17 and using it for binary signal detection. In this case, the adaptive means receiving the level required by the Viterbi decoder 15 from the level detector 17 and using the optimal level value.

Hereinafter, the nonlinear transducer 13 will be described in more detail. 3 is a block diagram showing the detailed structure of the nonlinear transducer 13. Referring to FIG. 3, the nonlinear transducer 13 includes a plurality of FIR filters 21, 23, 24 and a nonlinear function 22.

The FIR filters 21, 23 and 24 serve to efficiently operate the nonlinear function 22 by changing the frequency characteristic of the input signal. However, even when operating with only the nonlinear function 22, if the frequency characteristics of the input signal can be satisfied, the FIR filters 21, 23, and 24 may not be used. Therefore, some or all of the FIR filters 21, 23 and 24 may not be used depending on the characteristics of the signal to be operated. In addition, the number of taps of the FIR filters 21, 23, and 24 may be configured differently.

4 is a diagram illustrating an embodiment of a FIR filter. The FIR filters 21, 23, and 24 change the frequency characteristics of the input signal. A number of delays (indicated by "delay") that delay the input signal by the unit clock (system clock) and the value of the delayed signal are provided. And a multiplier for multiplying and outputting the multipliers and adding the outputs of the multipliers a1 to an. The values a1 through an of each multiplier may have a range of real numbers including 0.

The nonlinear function 22 is a function that changes the characteristics of the signal nonlinearly and is a function represented by Equation 1 below.

Here, "| |" is an expression representing an absolute value, and "{}" is an expression representing 1 if the conditional expression in parentheses is true and 0 if it is false. x can have a range of real numbers as an input signal, and k can have a range of zero or positive real numbers as a nonlinear threshold. a is a value representing the nonlinear type and may have a value of 0 or 1.

Looking at the meaning of Equation 1 in detail can be summarized as follows.

a = 0, x |> k, x> 0, y = k

a = 0, x |> k, x <0, y = -k

a = 0, x | ≤ k, y = x

a = 1, x |> k, x> 0, y = x-k

a = 1, x |> k, x <0, y = x + k

a = 1, x | ≤ k, y = 0

5 is a graph of the nonlinear function 22 represented by equation (1).

Equation 1 will be described in more detail. Referring to FIG. 5A, when a is 0, the nonlinear function 22 serves to saturate the input signal with a nonlinear threshold when the absolute value of the input signal is greater than the nonlinear threshold, and the input signal is larger than the nonlinear threshold. If the absolute value of is small, the input signal is represented as it is.

Referring to FIG. 5B, when a is 1, the nonlinear function outputs a difference from the nonlinear threshold in the input signal when the absolute value of the input signal is greater than the nonlinear threshold, and the absolute value of the input signal is greater than the nonlinear threshold. If it is small, it will output 0.

Conventionally, when a signal of a short period is reproduced, the signal level is usually small and the jitter is large, so even if a little noise is mixed, it is often read as wrong and judged as an error. However, in the case of using the non-linear converter 13 as in the present invention, the signal of a constant level is improved by increasing the size of the short period signal without increasing jitter and improving the performance of noise and raising the level of the output signal constantly. If is input, it can be combined with the Viterbi decoder that determines the final output with optimal performance.

The level detector 17 and the adaptive Viterbi decoder 15 will be described in detail below.

Since the level detector 17 has a level required by the Viterbi decoder 15, the level detector 17 determines what level the input signal is currently at, and then averages each level and delivers the average value to the adaptive Viterbi decoder 15. The adaptive Viterbi decoder 15 receives an appropriate level for the Viterbi decoder and performs a decoding operation to obtain an optimal binary signal.

The level detector 17 is configured differently according to the code characteristic of the input signal and the type of Viterbi decoder. The code characteristics of the input signal can be divided into two types, the (2,10) code series and the (1,7) code series.In the case of the (1,7) code, 2T, the shortest period is twice the basic period. In the case of the (2,10) code, the shortest period is from the 3T signal, which is three times the fundamental period. The type of Viterbi decoder is different depending on the statistical characteristics of the input signal. The most commonly used Viterbi decoders are (a, b, a), (a, b, b, a) and (a). , b, c, b, a) type.

Hereinafter, the structures of the level detector 17 and the adaptive Viterbi decoder 15 will be described in each case.

6 shows an embodiment of the level detector 17. Referring to FIG. 6, the level detector 17 includes a plurality of delayers, a target channel filter, a selection signal generator, and a plurality of average filters.

The output signal of the nonlinear transducer 13 or equalizer 14 is input to the level detector 17. The signal input to the level detector 17 is delayed for a predetermined time using a delay that operates as a system clock. The delay can be implemented with D-flipflop. The reason for delaying the signal by the retarder is that binary data output from the Viterbi decoder 15 takes a certain time in the calculation process, and accordingly, the binary data output from the Viterbi decoder 15 is calculated. This is to perform signal processing with the input signal of the same time as used to.

On the other hand, the binary data from the Viterbi decoder 15 passes through the target channel filter. When passing through the target channel filter, an output signal having a constant level is generated according to the type of the binary signal. As the destination channel filter, a channel filter having the same type as that of the Viterbi decoder 15 is used. Examples of the destination channel filter that can be used typically are shown in FIGS. 7A to 7C.

In general, the target channel filters commonly used for optical discs are (a, b, a) type, (a, b, b, a) type and (a, b, c, b, a) type. The circuit type of the Viterbi decoder and the type of the target channel filter used are determined. The numerical condition defined by a, b, and c is a real number equal to or greater than zero.

Passing binary data through the destination channel filter results in some level output depending on the code type of the input signal and the type of destination channel filter. The number of output levels determined at this time is constantly defined, and the selection signal generator generates a selection signal according to this output level. When the output of the target channel filter enters a certain level, the selection signal generator defines and outputs a selection signal corresponding to the level.

8 is a flowchart illustrating the operation of the selection signal generator.

Referring to FIG. 8, the level may be defined in various ways according to the type of the PR type of the Viterbi decoder 15, and m kinds of levels may be selected. In this case, P denotes an output value that can be output from the target channel filter, and may be different depending on the PR type and code characteristics ((1,7) code or (2,10) code). Although the values of the input signals input to the destination channel filter are -1 and 1, the values of the input signals may be defined as 1 or 0. In this case, the number of cases is the same, but the output level value is wrong. The following shows examples of the level configuration of the selection signal generator.

1) PR (a, b, a) type- (1,7) code (2,10) code common m = 4

P1 = 2a + b

P2 = b

P3 = -b

P4 = -2a-b

2) PR (a, b, b, a) type- (1,7) code m = 7

P1 = 2a + 2b

P2 = 2b

P3 = -2a + 2b

P4 = 0

P5 = 2a-2b

P6 = -2b

P7 = -2a-2b

3) PR (a, b, b, a) type- (2,10) code m = 5

P1 = 2a + 2b

P2 = 2b

P3 = 0

P4 = -2b                     

P5 = -2a-2b

4) PR (a, b, c, b, a) type- (1,7) code m = 10

P1 = 2a + 2b + c

P2 = 2b + c

P3 = -2a + 2b + c

P4 = c

P5 = -2a + c

P6 = 2a-c

P7 = -c

P8 = 2a-2b-c

P9 = -2b-c

P10 = -2a-2b-c

5) PR (a, b, c, b, a) type- (2,10) code m = 8

P1 = 2a + 2b + c

P2 = 2b + c

P3 = -2a + 2b + c

P4 = c

P5 = -c

P6 = 2a-2b-c

P7 = -2b-c                     

P8 = -2a-2b-c

Hereinafter, a detailed operation of the binary signal detection according to the present invention will be described with reference to FIG. 9 based on the structure of the binary signal detection device shown in FIG. 2.

9 is a graph illustrating a detailed operation of binary signal detection according to the present invention. When the RF signal is input to the binary signal detection device, the DC offset remover 12 removes the DC offset and walks the PLL to sample.

Depending on how the PLL generates the error signal, the sampling point may sample the zero crossing point or the 180 degree phase difference from the zero crossing point to the system clock. In the case of using the PR (a, b, b, a) type, it is generally desirable to sample the zero crossing point, and PR (a, b, a) type or PR (a, b, c, b, a) It is desirable to sample the zero crossing point and the point 180 degrees out of phase on the system clock, but you can use the complementary circuitry to perform signal calculations, or use other methods such as double the oscillation clock to sample as many parts as you need. This is not necessary.

The second graph of FIG. 9 shows a case of sampling a portion having a 180 degree phase difference. The point indicated by the point in the second graph is the sampling point. This signal is input to the nonlinear transducer 13, and when passed through the nonlinear transducer 13, the high frequency component is amplified. Therefore, the input signal of the nonlinear converter 13 and the input signal of the Viterbi decoder 15 serve to amplify a lot of signals of short periods to more clearly distinguish the signal and to reduce errors that may appear.

Referring to the third graph of FIG. 9, an input value of the Viterbi decoder 15 is illustrated. In the case of the third graph, since the input signal of the nonlinear converter 13 is received and processed, there may be a time delay of several clocks. When the AA signal shown in the third graph passes through the Viterbi decoder 15, binary data is output. In the case of AA, since 2T and 3T signals are mixed, -1,1,1 (2T),-1, Binary data in the form of -1 (2T), 1,1,1 (3T),-1, -1, -1 (3T), 1. Binary signals may be labeled 0 and 1, but are labeled 1 and -1 for convenience.

Since the binary data has to be processed by the bidderby decoder 15, a processing time of several clocks is required, resulting in a time delay.

The binary data is input to the level detector 17. Here, the case of using a Viterbi decoder of the type (a, b, a) and the destination channel filter is illustrated. In this case, if the binary data is -1,1,1, -1, -1,1,1,1, -1, -1, -1,1, the filter and convolution of type (a, b, a) When the operation is performed, the output result is output in the form of b, b, -b, -b, b, 2a + b, b, -b, -2a-b, -b. This signal enters the selection signal generator. In the selection signal generator, the selection signals of P2, P2, P3, P3, P2, P1, P2, P3, P4, and P3 are output. The average filter includes a signal of 4.1, the second average filter contains four signals of 2.1, 1.9, 2.2, and 1.9, and the third average filter contains four signals of -2.0, -2.3, -2.0, and -1.8. The fourth average filter contains -4.3. The average value filter receives the signal as many times as the signal defined by the microcomputer means or other means and outputs the average value.

Therefore, four levels, which are levels required by the Viterbi decoder 15, are input with levels of about 4, 2, -2, and 4 to represent an optimal decoding performance. This performance of the Viterbi decoder 15 is more optimal when combined with the nonlinear transducer 13 because the nonlinear transducer 13 serves to more clearly distinguish the level of the input signal. .

10 to 14 show an embodiment of a binary signal detection apparatus according to the present invention that includes various nonlinear transducers 13.

10 shows a case of decoding a signal using a nonlinear function and a Viterbi decoder. In this case, because a = 0, the nonlinear function outputs a nonlinear threshold when the absolute value is larger than the nonlinear threshold. Therefore, when a value other than that required by the Viterbi decoder 15 is input, the signal is forced to saturate, causing malfunction. Prevent and increase performance.

The reason for this is as described above, but when the Viterbi decoder of the PR (a, b, a) type is used, the most efficient decoding can be performed when four levels are input to the Viterbi decoder. This is because the input signal can be changed to fit four levels.

In order to further improve the performance of the nonlinear converter 13 composed of only the nonlinear functions shown in FIG. 10, the binary signal detection apparatus shown in FIGS. 13).

When the FIR filter is used, the frequency characteristic of the input signal can be varied, so that the input signal can be converted into a more efficient form, thereby improving the performance of the Viterbi decoder.

The binary signal detection apparatus shown in FIGS. 13 and 14 includes a nonlinear converter 13 using a nonlinear function and an FIR filter corresponding to a = 1. Also in this case, the FIR filter can be used to change the frequency characteristics and then pass through a nonlinear function to improve the operation performance of the Viterbi decoder 15.

In the case of a = 1, the FIR filter connected after the nonlinear function is preferably a filter having a frequency characteristic of a cosine transform having a filter coefficient of 1,0,0,1 at 3 taps in order to obtain a good quality characteristic. A more detailed description of this is described in Korean Patent Application No. 2002-0075969, "Equalizer for High Density Optical Disc Reproducing Device".

As described above, the binary signal detection apparatus according to the present invention corrects the signal input to the Viterbi decoder by the nonlinear converter, and more accurately binary by using the Viterbi decoder in which the corrected signal and the optimal level are detected. The signal can be detected, so that data stored in a data storage medium such as an optical disk can be smoothly reproduced.

Claims (4)

A nonlinear converter for converting the input signal to have a value within a predetermined range; A Viterbi decoder for detecting a binary signal by decoding the converted signal inputted from the nonlinear converter according to an input optimum level value; And a level detector receiving the signal output from the nonlinear converter and the binary signal output from the Viterbi decoder to detect the optimum level value and output the detected signal to the Viterbi decoder. According to claim 1, And the nonlinear transducer converts the input signal to have a value within a predetermined range according to a predetermined nonlinear function. The method of claim 2, And wherein the nonlinear converter comprises at least one FIR filter for performing FIR filtering before or after converting the input signal according to the predetermined nonlinear function. 4. The binary signal detection apparatus of claim 3, wherein the nonlinear transducer arranges the FIR filter according to whether a value representing a nonlinear type is 0 or 1.

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