JP2003234370A - Method for connecting electronic component, and connected structure obtained by the same - Google Patents
Method for connecting electronic component, and connected structure obtained by the sameInfo
- Publication number
- JP2003234370A JP2003234370A JP2002031025A JP2002031025A JP2003234370A JP 2003234370 A JP2003234370 A JP 2003234370A JP 2002031025 A JP2002031025 A JP 2002031025A JP 2002031025 A JP2002031025 A JP 2002031025A JP 2003234370 A JP2003234370 A JP 2003234370A
- Authority
- JP
- Japan
- Prior art keywords
- metal material
- electrode
- electrodes
- components
- alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01049—Indium [In]
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電子部品の接続方
法に関し、より詳しく言えば、電極を備えた被接続部品
どうしを両者の電極を介して直接接続する方法と、この
方法により接続した電子部品を含む接続構造体に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for connecting electronic parts, and more specifically, a method for directly connecting parts to be connected having electrodes via both electrodes, and an electronic device connected by this method. A connection structure including parts.
【０００２】[0002]
【従来の技術】近年の電子機器の小型化、薄型化に伴
い、電子部品の高密度実装が強く求められている。この
ために半導体チップなどの電子部品を裸の状態で基板に
直接搭載するフリップチップ実装が用いられている。フ
リップチップ実装に使用する半導体チップの表面には突
起電極が形成されており、半導体チップはこれらの突起
電極を介して基板上の電極に接合されて、基板の配線と
電気的に接続されている。2. Description of the Related Art With the recent miniaturization and thinning of electronic equipment, there is a strong demand for high-density mounting of electronic components. For this reason, flip-chip mounting is used in which electronic components such as semiconductor chips are directly mounted on a substrate in a bare state. Projection electrodes are formed on the surface of a semiconductor chip used for flip-chip mounting, and the semiconductor chip is bonded to the electrodes on the substrate through these projection electrodes and electrically connected to the wiring of the substrate. .
【０００３】電子部品の突起電極として用いられる代表
的なものは、はんだバンプである。はんだバンプを用い
る場合の電子部品の回路基板への接続方法として、リフ
ロー接続法がある。リフロー接続法では、基板上の電極
に、はんだ付け向上のため、はんだの酸化膜除去用のフ
ラックスを塗布し、電子部品を位置合わせして基板に搭
載後、空気雰囲気あるいは窒素雰囲気の炉内ではんだバ
ンプを溶融させてリフローさせることにより、基板の電
極をはんだで濡らすとともにその上にはんだを広げて電
子部品と基板との電気的接続を行っている。一般には、
更に電子部品と回路基板との間に封止用樹脂を注入、硬
化させることで、電子部品と回路基板との機械的な接続
もなされている。リフロー法は、電子部品どうしを重ね
て積層構造体を形成する場合にも利用されている。A typical one used as a protruding electrode of an electronic component is a solder bump. There is a reflow connection method as a method of connecting an electronic component to a circuit board when a solder bump is used. In the reflow connection method, flux for solder oxide film removal is applied to the electrodes on the board to improve soldering, the electronic components are aligned and mounted on the board, and then in an air atmosphere or nitrogen atmosphere furnace. By melting and reflowing the solder bumps, the electrodes of the substrate are wetted with the solder, and the solder is spread on the electrodes to electrically connect the electronic components to the substrate. In general,
Further, a sealing resin is injected and cured between the electronic component and the circuit board to mechanically connect the electronic component and the circuit board. The reflow method is also used when stacking electronic components to form a laminated structure.
【０００４】また、高集積化、小型化の進んだ半導体デ
バイスを低温且つ低加圧力で基板に接続するのを可能に
する信頼性の高い低ダメージな実装方法として、接合電
極表面に存在する酸化皮膜を除去して電極材料金属の表
面を活性化させてから、常温にて金属原子どうしの強固
な接合（固相接合）を行う方法が知られている。酸化皮
膜を除去して接合面を活性化するためには、不活性ガス
イオンビームもしくは不活性ガス高速原子ビームを接合
電極表面に照射する方法、接合面に超音波を当てる方
法、あるいは接合面どうしを摩擦させる方法などが利用
されている。In addition, as a highly reliable and low-damage mounting method that enables highly integrated and miniaturized semiconductor devices to be connected to a substrate at low temperature and low pressure, oxidation existing on the surface of the bonding electrode is used. A method is known in which the film is removed to activate the surface of the electrode material metal and then the metal atoms are firmly bonded (solid phase bonding) at room temperature. In order to remove the oxide film and activate the bonding surface, a method of irradiating the bonding electrode surface with an inert gas ion beam or an inert gas fast atom beam, a method of applying ultrasonic waves to the bonding surface, or bonding surfaces The method of rubbing is used.
【０００５】こうして接合面を活性化済みの被接続部品
どうしを接合するまでの間、電極表面の活性化状態を維
持するために、それらの部品は真空中又は不活性ガス雰
囲気中にて保持し、そして同じ雰囲気中で接続される。Thus, in order to maintain the activated state of the electrode surface until the parts to be connected whose joint surfaces have been activated are joined, these parts are kept in a vacuum or in an inert gas atmosphere. , And connected in the same atmosphere.
【０００６】[0006]
【発明が解決しようとする課題】上述のはんだバンプに
よるリフロー接続では、一般にはんだの融点が２００℃
以上と高温であるため、電子部品に熱ダメージが生じか
ねない。また、リフロー時に溶融したはんだが電極領域
から外側へ流れ出すことにより、隣接電極間でショート
の発生を引き起こしやすい。更に、電子部品と回路基板
の熱膨脹係数が異なるため、リフローしたはんだにより
接続した接合部分には剪断応力や歪みが加わり、接続信
頼性の低下を招きやすい。In the reflow connection using the solder bumps described above, the melting point of the solder is generally 200.degree.
Since the temperature is high as above, heat damage may occur to the electronic component. In addition, the melted solder flows out from the electrode region to the outside during the reflow process, which easily causes a short circuit between the adjacent electrodes. Further, since the thermal expansion coefficients of the electronic component and the circuit board are different, shear stress or strain is applied to the joint portion connected by the reflowed solder, and the connection reliability is likely to be deteriorated.
【０００７】一方、被接続部品の電極表面を清浄にし活
性化してから接合面どうしを直接密着させて加圧し、固
相接合する方法では、もともと電極表面にサブミクロン
ないしミクロンオーダーの凹凸が存在し、清浄化しても
電極表面自体の平坦化が困難で、実効的な電極接触面積
が小さくなるため、強固な接続を実現することが困難で
ある。接続強度向上のため、接続時の加重を増加する
と、電子部品にダメージを与えることになる。また、電
極表面の凹凸をなくすために化学的機械研磨（ＣＭＰ）
などの平坦化工程を行うと、製造コストの増大、及びＴ
ＡＴ（ターン・アラウンド・タイム）の増加という問題
が生じる。On the other hand, in the method in which the electrode surfaces of the parts to be connected are cleaned and activated, the bonding surfaces are directly brought into close contact with each other and pressure is applied, and solid-phase bonding is present, the surface of the electrodes originally has irregularities of submicron or micron order. However, even if it is cleaned, it is difficult to flatten the electrode surface itself, and the effective electrode contact area is reduced, so that it is difficult to realize a strong connection. If the weight at the time of connection is increased to improve the connection strength, electronic components will be damaged. In addition, chemical mechanical polishing (CMP) to eliminate irregularities on the electrode surface
If a flattening process such as
The problem of increasing AT (turn around time) occurs.
【０００８】本発明は、上述のような従来技術の問題点
を解決し、低温且つ低加重で電子部品と回路基板のよう
な搭載基板との、あるいは電子部品どうしの、信頼性の
高い接続を可能にする方法の提供を目的とするものであ
る。The present invention solves the problems of the prior art as described above, and realizes a highly reliable connection between an electronic component and a mounting substrate such as a circuit substrate or between electronic components at low temperature and low weight. The purpose is to provide a method that makes it possible.
【０００９】[0009]
【課題を解決するための手段】本発明による電子部品接
続方法は、接続電極を備えた、少なくとも一方が電子部
品である被接続部品どうしを、両者の接続電極を介して
直接接続する方法であって、被接続部品のうちの少なく
とも一方のものの電極表面上に、ヤング率が５０ＧＰａ
以下の金属材料を付着させる工程と、この金属材料の表
面、及び被接続部品のうちの他方のものの電極表面に金
属材料を付着させていない場合はその電極表面を、活性
化処理する工程と、被接続部品の電極どうしを、上記の
付着した金属材料を介し固相接合させて、それにより被
接続部品どうしを接続する工程とを有することを特徴と
する。The electronic component connecting method according to the present invention is a method for directly connecting connected components, which are provided with connection electrodes and at least one of which is an electronic component, through the connection electrodes of both. The Young's modulus is 50 GPa on the electrode surface of at least one of the connected components.
A step of adhering the following metal material, a step of activating the surface of this metal material, and the electrode surface of the other one of the connected parts when the metal material is not attached, A step of solid-phase joining the electrodes of the parts to be connected via the above-mentioned adhered metal material, and thereby connecting the parts to be connected.
【００１０】[0010]
【発明の実施の形態】本発明の電子部品接続方法は、少
なくとも一方は半導体チップのような電子部品であり、
且つ双方が接続電極を備えた被接続部品どうしを、フリ
ップチップ接続法を利用して接続する方法である。もう
一方の被接続部品は、当該電子部品を搭載するための基
板であってもよく、あるいは別の電子部品であってもよ
い。BEST MODE FOR CARRYING OUT THE INVENTION In the electronic component connecting method of the present invention, at least one is an electronic component such as a semiconductor chip,
In addition, it is a method of connecting components to be connected, both of which have connection electrodes, using a flip chip connection method. The other connected component may be a board on which the electronic component is mounted, or another electronic component.
【００１１】少なくとも一方の被接続部品の接続電極表
面に、ヤング率が５０ＧＰａ以下の金属材料を付着させ
る。ヤング率が５０ＧＰａ以下の金属材料として使用で
きるものの例としては、Ｓｎ、Ｓｎ合金（例えば、Ｓｎ
−Ａｇ、Ｓｎ−Ｂｉ、Ｓｎ−Ａｇ−Ｃｕ、Ｓｎ−Ｉｎ、
又はＳｎ−Ｐｂ合金）などの各種はんだ材料を挙げるこ
とができる。これらの金属あるいは合金材料は、電子部
品の電極に一般的に使用される材料と固溶体を形成しや
すく、強固な結合を可能にすることから、本発明の固相
接合による被接続部品どうしの接続に適している。A metal material having a Young's modulus of 50 GPa or less is adhered to the surface of the connection electrode of at least one connected component. Examples of materials that can be used as a metal material having a Young's modulus of 50 GPa or less include Sn and Sn alloys (for example, Sn
-Ag, Sn-Bi, Sn-Ag-Cu, Sn-In,
Or various solder materials such as Sn-Pb alloy). Since these metal or alloy materials easily form a solid solution with a material generally used for electrodes of electronic parts and enable strong bonding, connection of connected parts by solid phase bonding of the present invention Suitable for
【００１２】接続電極表面に付着させる金属材料は、ヤ
ング率が５０ＧＰａ以下であることが重要である。この
ような比較的低ヤング率の金属材料は、被接続部品の固
相接合のために荷重をかけたときに、容易に塑性変形し
てレベリングされる。そのため、ＣＭＰ等での面倒な平
坦化処理を行わずに、被接続部品の強固な固相接合が可
能になる。It is important that the Young's modulus of the metal material attached to the surface of the connection electrode is 50 GPa or less. Such a metal material having a relatively low Young's modulus is easily plastically deformed and leveled when a load is applied for solid-phase joining of the components to be connected. Therefore, it is possible to perform solid phase bonding of the connected components without performing a troublesome flattening process such as CMP.
【００１３】接続電極上の金属材料の量が少なくて適度
な厚さの層を形成していなければ、一般にサブミクロン
ないしミクロンオーダーの凹凸が表面に存在する電極ど
うしを強固に接合することができない。その一方、接続
電極上の金属材料の量を必要以上に多くするのは、固相
接合時の荷重負荷による塑性変形により金属材料が電極
領域外にはみ出して、特に狭いピッチで形成された電極
の場合、隣接電極どうしのショートの原因になりかねな
いので、好ましくない。一般には、５μｍほどの厚みの
層を形成する程度の量の金属材料を付着させれば、塑性
変形した金属材料がサブミクロンないしミクロンオーダ
ーの凹凸のある電極表面においてその凹部内に十分いき
わたり、電極材料の金属との固溶化が十分に進行するの
で、微小な電極ピッチであっても、隣接電極間のショー
トを招くことなく信頼性の高い固相接合が可能になる。
従って、一般に、電極上に付着させる金属材料はその厚
さの上限を約５μｍとすれば十分である。当然ながら、
電極表面の凹凸の状況によっては、金属材料を更に厚く
付着させるのが必要な場合もあり得る。Unless the amount of metal material on the connecting electrodes is small and a layer having an appropriate thickness is formed, it is generally impossible to firmly join electrodes having unevenness of submicron or micron order on the surface. . On the other hand, increasing the amount of the metal material on the connection electrode more than necessary is because the metal material protrudes outside the electrode region due to plastic deformation due to the load load during solid-phase bonding, and the electrode formed especially at a narrow pitch. In this case, it may cause a short circuit between adjacent electrodes, which is not preferable. In general, if a metal material is deposited in an amount such that a layer having a thickness of about 5 μm is deposited, the plastically deformed metal material spreads sufficiently into the recesses on the electrode surface having irregularities of submicron to micron order, Since the solid solution of the material with the metal progresses sufficiently, solid phase bonding with high reliability can be performed without causing a short circuit between adjacent electrodes even with a fine electrode pitch.
Therefore, it is generally sufficient that the upper limit of the thickness of the metal material deposited on the electrode is about 5 μm. Of course,
Depending on the unevenness of the electrode surface, it may be necessary to deposit the metal material thicker.
【００１４】被接着部品の電極への金属材料の付着は、
その被接着部品に有害な影響を及ぼさない限り、任意の
方法で行うことができる。そのような方法の例として、
金属材料の溶融浴へ被接着部品を浸漬する浸漬法、超音
波の適用下の金属材料溶融浴へ被接着部品を浸漬する超
音波はんだ付け法、転写（印刷）法などである。The adhesion of the metallic material to the electrode of the adhered component is
It can be carried out by any method as long as it does not adversely affect the parts to be adhered. As an example of such a method,
Examples of the method include an immersion method of immersing the adhered component in a metal material melting bath, an ultrasonic soldering method of immersing the adhered component in the metal material melting bath under application of ultrasonic waves, and a transfer (printing) method.
【００１５】金属材料を付着させる電極表面には酸化皮
膜が形成されているのが普通である。固相接合による接
続では、電極材料の金属と電極表面に付着した金属とが
直接接触し合うことで強固な接続が可能になる。そこ
で、固相接合による被接続部品どうしの接続をより強固
にするためには、電極表面の酸化皮膜を除去してから金
属材料を付着させるのがより好ましい。例えばスパッタ
法を利用すれば、電極への金属材料の付着を、酸化皮膜
を除去しながら行うことができる。あるいは、不活性イ
オンビームもしくは中性原子ビームの照射（プラズマで
の処理）により、電極表面の酸化皮膜を除去することも
できる。An oxide film is usually formed on the surface of the electrode to which the metal material is attached. In the connection by solid-phase bonding, the metal of the electrode material and the metal adhering to the electrode surface are in direct contact with each other, so that a strong connection is possible. Therefore, in order to strengthen the connection between the components to be connected by solid phase bonding, it is more preferable to remove the oxide film on the electrode surface and then attach the metal material. For example, if the sputtering method is used, the metal material can be attached to the electrodes while removing the oxide film. Alternatively, the oxide film on the electrode surface can be removed by irradiation with an inert ion beam or neutral atom beam (treatment with plasma).
【００１６】電極表面への接合用金属材料の付着に続い
て、電極に付着した金属材料の表面、及び電極表面に金
属材料が付着していない被接続部品がある場合はその電
極表面を活性化させる。この活性化は、金属材料の付着
していない電極表面にはもちろん、電極に付着した金属
材料の表面にも形成されている酸化皮膜を除去して、電
極の金属材料自体及び接合用金属材料自体を表面に露出
させる処理である。この処理は、例えば、不活性イオン
ビームもしくは中性原子ビームの照射（プラズマ処理）
で行うことができる。この処理により、金属材料表面の
酸化膜をはじめ、水分や油脂分等の汚染物も除去するこ
とができる。酸化皮膜の除去は、加熱したカルボン酸雰
囲気、例えば２５０℃のギ酸蒸気中での、酸化物の還元
によって行うこともできる。活性化処理の具体的方法は
これらに限定されず、被接続部品に有害な影響を与えな
い限り、どのような方法を利用しても差し支えない。Following the adhesion of the joining metal material to the electrode surface, the surface of the metal material adhered to the electrode and, if there is a component to which the metal material is not adhered, are activated on the electrode surface. Let This activation removes the oxide film formed not only on the surface of the electrode to which the metal material is not adhered but also on the surface of the metal material adhered to the electrode, and the metal material of the electrode itself and the metal material for bonding itself. Is a process for exposing the surface. This treatment is, for example, irradiation with an inert ion beam or a neutral atom beam (plasma treatment)
Can be done at. By this treatment, it is possible to remove not only the oxide film on the surface of the metal material but also contaminants such as water and fats and oils. The oxide film can also be removed by reducing the oxide in a heated carboxylic acid atmosphere, for example, vapor of formic acid at 250 ° C. The specific method of activation treatment is not limited to these, and any method may be used as long as it does not adversely affect the connected parts.
【００１７】金属材料表面の活性化処理を終えた被接続
部品は、双方の電極が向き合って接合用金属材料を介し
て接触するように位置合わせして重ね合わせ、プレスし
て固相接合させることにより、室温で強固に結合させる
ことができる。固相接合は、場合によっては、電極上に
付着した接合用金属の融点以下の温度に加熱した条件下
で行うこともできるが、そのような加熱は必ずしも必要
ではない。プレスの際の荷重は、被接続部品の種類や接
合用金属材料の種類に応じて適当なものを選択すればよ
い。After the activation treatment of the surface of the metal material, the connected parts are aligned and overlapped so that both electrodes face each other and come into contact with each other via the metal material for bonding, and pressed to perform solid phase bonding. Thus, it is possible to firmly bond at room temperature. In some cases, the solid-phase bonding can be performed under the condition of being heated to a temperature equal to or lower than the melting point of the bonding metal attached on the electrode, but such heating is not always necessary. An appropriate load may be selected according to the type of parts to be connected and the type of metal material for joining during pressing.
【００１８】このようにして接続を完了した二つの被接
続部品は、双方の電極がその間の接合用金属材料を介し
て強固に接続された接続構造体を構成する。The two connected parts thus completed in connection form a connection structure in which both electrodes are firmly connected via the metal material for joining therebetween.
【００１９】[0019]
【実施例】以下に本発明における実施例を示す。言うま
でもなく、本発明は以下の実施例に限定されるものでは
ない。EXAMPLES Examples of the present invention will be shown below. Needless to say, the present invention is not limited to the examples below.
【００２０】図１（ａ）に示すように、半導体チップ１
０及び回路基板２０のそれぞれの電極形成部に、一般的
な無電解めっき法でニッケルの突起電極１１及び２１を
それぞれ形成する。As shown in FIG. 1A, the semiconductor chip 1
0 and nickel protruding electrodes 11 and 21 are formed on the respective electrode forming portions of the circuit board 20 and the circuit board 20 by a general electroless plating method.
【００２１】次に、図１（ｂ）に示すように、半導体チ
ップ１０の突起電極１１上に、超音波はんだ付け法によ
ってＳｎ−Ａｇはんだを付着させる。出力４０Ｗ、周波
数２０ｋＨｚの超音波振動子を装備したはんだ浴を用
い、窒素ガスを６０リットル／ｍｉｎで流しながら、は
んだ浴温度を２８０℃とし、これに半導体チップ１０を
０．５〜２秒間浸漬後、取り出してはんだを固化させる
と、電極１１上に厚さ約５μｍのＳｎ−Ａｇはんだ層１
２が形成される。Next, as shown in FIG. 1B, Sn-Ag solder is attached onto the protruding electrodes 11 of the semiconductor chip 10 by ultrasonic soldering. Using a solder bath equipped with an ultrasonic transducer having an output of 40 W and a frequency of 20 kHz, the solder bath temperature was set to 280 ° C. while flowing nitrogen gas at 60 liter / min, and the semiconductor chip 10 was immersed in this for 0.5 to 2 seconds. After that, when the solder is taken out and solidified, the Sn-Ag solder layer 1 having a thickness of about 5 μm is formed on the electrode 11.
2 is formed.
【００２２】次いで、図１（ｃ）に示すように、半導体
チップ１０と基板２０を、アルゴンプラズマが照射可能
な雰囲気を維持したチャンバー（図示せず）内に入れ、
アルゴンプラズマ３１を照射して、半導体チップの電極
１１上に形成したはんだ層１２と基板２０の電極２１の
各表面をエッチングする。これにより、はんだ層１２及
び電極２１の表面の酸化膜を、水分、油脂分等の汚染物
とともに除去し、はんだ層１２及び電極２１の各表面を
活性化させる。Then, as shown in FIG. 1C, the semiconductor chip 10 and the substrate 20 are put into a chamber (not shown) which maintains an atmosphere capable of being irradiated with argon plasma.
The surfaces of the solder layer 12 formed on the electrode 11 of the semiconductor chip and the surface of the electrode 21 of the substrate 20 are etched by irradiating with the argon plasma 31. As a result, the oxide films on the surfaces of the solder layer 12 and the electrodes 21 are removed together with contaminants such as moisture and oil and fat, and the surfaces of the solder layers 12 and the electrodes 21 are activated.
【００２３】続いて、チャンバー内を真空雰囲気（ある
いは不活性ガス雰囲気等の酸素の存在しない雰囲気）に
維持し、図１（ｄ）に示すように、半導体チップ１０と
回路基板２０をおのおのの電極１１及び２１が向き合っ
てはんだ層１２を介し接触するように位置合わせして重
ね合わせ、そして室温にて５〜１０Ｎ／ｍｍ2でプレス
して固相接合する。これにより、図２に示したような、
半導体チップ１０と回路基板２０とが双方の電極１１及
び２１とその間のＳｎ−Ａｇはんだ層１２を介して強固
に接続された、半導体チップ１０と回路基板２０との接
続構造体１が得られる。Subsequently, the inside of the chamber is maintained in a vacuum atmosphere (or an atmosphere in which oxygen does not exist, such as an inert gas atmosphere), and as shown in FIG. 1D, the semiconductor chip 10 and the circuit board 20 have respective electrodes. 11 and 21 are aligned and superposed so that 11 and 21 face each other and are in contact with each other via the solder layer 12, and pressed at room temperature at 5 to 10 N / mm 2 for solid phase bonding. As a result, as shown in FIG.
The connection structure 1 between the semiconductor chip 10 and the circuit board 20 is obtained in which the semiconductor chip 10 and the circuit board 20 are firmly connected to each other through the electrodes 11 and 21 and the Sn—Ag solder layer 12 therebetween.
【００２４】上記の例でははんだ層１２を半導体チップ
１０の電極１１上に形成したが、はんだ層は回路基板２
０の電極２１上に形成してもよく、あるいは両方の電極
上に形成してもよい。Although the solder layer 12 is formed on the electrode 11 of the semiconductor chip 10 in the above example, the solder layer 12 is formed on the circuit board 2.
It may be formed on the zero electrode 21 or on both electrodes.
【００２５】[0025]
【発明の効果】本発明によれば、被接続部品の電極表面
及び接合用金属表面の酸化物を除去し活性化させた状態
のまま、被接続部品の電極どうしを接合させるため、被
接続部品の低温且つ低荷重での接続信頼性の高い固相接
合が可能となる。同時に、固相接合では接合用金属材料
の電極領域外へのはみ出しがないか、あってもごくわず
かであるので、リフローでの接続に比べ隣接電極間のシ
ョートの発生を効果的に抑制でき、半導体デバイスの微
細・狭ピッチ接続における歩留り向上が実現できる。ま
た、接合前のＣＭＰ等のレベリング工程が不要であり、
工数を抑えることが可能となる。According to the present invention, the electrodes of the components to be connected are bonded to each other while the oxides on the surfaces of the electrodes of the components to be connected and the metal surface for bonding are removed and activated. It is possible to achieve solid-phase bonding with high connection reliability at low temperature and low load. At the same time, in solid-state bonding, there is no protrusion of the bonding metal material to the outside of the electrode region, or even if there is very little, it is possible to effectively suppress the occurrence of a short circuit between adjacent electrodes as compared to the connection by reflow, It is possible to improve the yield in fine / narrow pitch connection of semiconductor devices. Further, the leveling process such as CMP before joining is unnecessary,
It is possible to reduce man-hours.
【図１】本発明の接続方法により半導体チップと回路基
板を接続するのを説明する図である。FIG. 1 is a diagram illustrating connection between a semiconductor chip and a circuit board by a connection method of the present invention.
【図２】本発明による接続構造体を例示する図である。FIG. 2 is a diagram illustrating a connection structure according to the present invention.
１…接続構造体 １０…半導体チップ １１…電極 １２…はんだ層 ２０…回路基板 ２１…電極 1 ... Connection structure 10 ... Semiconductor chip 11 ... Electrode 12 ... Solder layer 20 ... Circuit board 21 ... Electrode
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 21/92 ６０２Ｄ (72)発明者 山岸 康男 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 Ｆターム(参考） 5E319 AA03 AB05 AC01 BB01 BB07 BB08 CC12 CD04 CD26 GG11 5F044 KK18 KK19 LL01 QQ03 QQ04─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 7 Identification code FI theme code (reference) H01L 21/92 602D (72) Inventor Yasuo Yamagishi 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu In-house F-term (reference) 5E319 AA03 AB05 AC01 BB01 BB07 BB08 CC12 CD04 CD26 GG11 5F044 KK18 KK19 LL01 QQ03 QQ04
Claims (7)
子部品である被接続部品どうしを、両者の接続電極を介
して直接接続する方法であって、被接続部品のうちの少
なくとも一方のものの電極表面上に、ヤング率が５０Ｇ
Ｐａ以下の金属材料を付着させる工程と、該金属材料の
表面、及び被接続部品のうちの他方のものの電極表面に
金属材料を付着させていない場合はその電極表面を、活
性化処理する工程と、被接続部品の電極どうしを、上記
の付着した金属材料を介し固相接合させて、それにより
被接続部品どうしを接続する工程とを有することを特徴
とする電子部品の接続方法。1. A method for directly connecting to-be-connected components, at least one of which is an electronic component, provided with a connecting electrode, through the connecting electrodes of the both, and an electrode of at least one of the to-be-connected components. Young's modulus is 50G on the surface
A step of adhering a metal material of Pa or less, and a step of activating the surface of the metal material and the electrode surface of the other of the connected parts if the metal material is not adhered And a step of solid-phase joining the electrodes of the components to be connected via the above-mentioned adhered metal material to thereby connect the components to be connected, thereby connecting the electronic components.
ｎ、Ｓｎ−Ａｇ合金、Ｓｎ−Ｂｉ合金、Ｓｎ−Ａｇ−Ｃ
ｕ合金、Ｓｎ−Ｉｎ合金、及びＳｎ−Ｐｂ合金のうちか
ら選ぶことを特徴とする、請求項１記載の方法。2. The metal deposited on the electrode surface is S
n, Sn-Ag alloy, Sn-Bi alloy, Sn-Ag-C
The method according to claim 1, wherein the method is selected from a u alloy, a Sn-In alloy, and a Sn-Pb alloy.
５μｍ以下の厚さで付着させることを特徴とする、請求
項１又は２記載の方法。3. A metal material attached to the surface of the electrode,
The method according to claim 1 or 2, characterized in that the layer is deposited with a thickness of 5 µm or less.
はんだ付け法、又は転写法により行うことを特徴とす
る、請求項１から３までのいずれか１つに記載の方法。4. The method according to claim 1, wherein the depositing of the metal material is performed by an immersion method, an ultrasonic soldering method, or a transfer method.
り、あるいは加熱したカルボン酸雰囲気への暴露により
行うことを特徴とする、請求項１から４までのいずれか
１つに記載の方法。5. The method according to claim 1, wherein the activation treatment is performed by plasma irradiation or exposure to a heated carboxylic acid atmosphere.
あり、他方が当該半導体チップを搭載する基板、又は別
の半導体チップであることを特徴とする、請求項１から
５までのいずれか１つに記載の方法。6. The semiconductor device according to claim 1, wherein one of the connected components is a semiconductor chip and the other is a substrate on which the semiconductor chip is mounted or another semiconductor chip. Method described in one.
れらの電極間に配置された接合用金属材料を介して直接
接続されている接続構造体であって、当該被接続部品ど
うしが請求項１から６までのいずれか１つの方法により
接続されていることを特徴とする接続構造体。7. A connection structure in which the parts to be connected are directly connected via both electrodes and a metal material for bonding arranged between the electrodes, and the parts to be connected are claimed. A connection structure characterized by being connected by any one of the methods 1 to 6.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002031025A JP3998484B2 (en) | 2002-02-07 | 2002-02-07 | How to connect electronic components |
| US10/347,224 US6806118B2 (en) | 2002-02-07 | 2003-01-21 | Electrode connection method, electrode surface activation apparatus, electrode connection apparatus, connection method of electronic components and connected structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002031025A JP3998484B2 (en) | 2002-02-07 | 2002-02-07 | How to connect electronic components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003234370A true JP2003234370A (en) | 2003-08-22 |
| JP3998484B2 JP3998484B2 (en) | 2007-10-24 |
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ID=27774551
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|---|---|---|---|
| JP2002031025A Expired - Fee Related JP3998484B2 (en) | 2002-02-07 | 2002-02-07 | How to connect electronic components |
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| JP (1) | JP3998484B2 (en) |
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| JP2006222436A (en) * | 2004-01-22 | 2006-08-24 | Bondotekku:Kk | Bonding method, and device created by the method and bonding apparatus |
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