JP2003224208A - Semiconductor device and its fabricating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a highly reliable DRAM hybrid semiconductor device in which a good metal silicide layer capable of suppressing junction leak and channel leak of a transistor is formed on a lightly doped diffusion layer of the source-drain region at a DRAM part, and wiring resistance and contact resistance are reduced by increasing the area of the metal silicide layer. <P>SOLUTION: After a thin oxide film sidewall 15 is formed on the sidewall of the gate electrode 13 and before a nitride film sidewall 16 is formed on the outside thereof, a silicon epi-layer 18a is formed and then a metal silicide layer 18 is formed from the silicon epi-layer 18a by a salicide method. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a DRAM-embedded semiconductor device having a DRAM section and a logic section formed on the same semiconductor substrate.

[0002]

2. Description of the Related Art A structure of a DRAM part in a conventional DRAM mixed semiconductor device in which a DRAM part and a logic part are formed on the same semiconductor substrate will be described below with reference to a sectional view shown in FIG. In the figure, 1 is a semiconductor substrate (hereinafter,
(Referred to as substrate 1), 2 is an isolation insulating film for separating elements, 3 is a gate electrode formed on the substrate 1 via a gate insulating film 4, and 5 is a nitride formed on the side wall of the gate electrode 4. A film sidewall, 6 is a low concentration diffusion layer serving as a source / drain region, and 6a is CoSi formed on the low concentration diffusion layer 6.
A metal silicide layer made of, 7 is an interlayer oxide film, 8 is a plug electrode formed by filling a contact hole 8a provided in the interlayer oxide film 7, 9 is a nitride film, 10 is an oxide film,
Reference numeral 11 is a lower electrode of the capacitor formed of the Ti film 11a and Ru film 11b, 12 is an insulating film, 13 is an upper electrode of the capacitor, 14 is an oxide film, 15 is a W plug, and 16 is a bit line.

As shown in the figure, in the DRAM memory array portion, a low concentration diffusion layer 6 is used in the source / drain regions in order to suppress the short channel effect and relax the drain electric field. Further, by forming the metal silicide layer 6a on the surface of the low concentration diffusion layer 6 by salicide, the wiring resistance and the contact resistance are reduced, and high-speed operation is enabled. In addition, the isolation insulating film 2 of the DRAM memory array section
The active region surrounded by is much finer than the logic region, and the contact hole 8a is opened by self-alignment using the nitride film sidewall 5 on the sidewall of the gate electrode 3. As a result, the contact hole 8a reaching the metal silicide layer 6a on the surface of the low-concentration diffusion layer 6 can be opened in a fine region with high reliability. Further, the nitride film side wall 5 also has a function of insulating the metal silicide layer 6a on the surface of the low concentration diffusion layer 6 from the gate electrode 3.

[0004]

By the way, the metal silicide layer 6a needs to have a certain thick film thickness in order to improve the morphology. However, in the conventional semiconductor device shown in FIG. 9, the low-concentration diffusion layer 6 is formed shallowly, and there is a concern that junction leakage may occur if the metal silicide layer 6a is thickened. On the contrary, if the low-concentration diffusion layer 6 is deepened, there is a problem that channel leak of the transistor increases and reliability deteriorates. In addition, the gate electrode 3
Since the nitride film side wall 5 is formed on the side wall,
The formation region of the metal silicide layer 6a in the fine active region of the DRAM memory array portion becomes a further fine region, and it is difficult to sufficiently obtain the effect of reducing the wiring resistance and the contact resistance.

The present invention has been made to solve the above-mentioned problems, and in the DRAM part,
A good metal silicide layer that can suppress junction leakage and transistor channel leakage is formed on the low-concentration diffusion layer, and the area of this metal silicide layer is increased to reduce wiring resistance and contact resistance. It is an object to obtain a high-speed and highly reliable DRAM embedded semiconductor device.

[0006]

[Means for Solving the Problems] Claim 1 according to the present invention
The semiconductor device described above is a DRAM-embedded semiconductor device in which a DRAM part and a logic part are formed on the same semiconductor substrate, and a metal silicide layer is formed on the surface of a diffusion layer serving as a source / drain region of a transistor in the DRAM part and the logic part. The metal silicide layer is a silicon epitaxial growth layer formed on the diffusion layer, which is silicided by salicide. A nitride film sidewall is provided, the metal silicide layer is provided outside the insulating film sidewall of the gate electrode and adjacent to the insulating film sidewall, and the nitride film sidewall is on the metal silicide layer. It is formed in.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the metal silicide layer is a silicide layer of cobalt, titanium or nickel.

A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first or second aspect, wherein an interlayer oxide film covering the transistor is formed on the semiconductor substrate, and the interlayer oxide film has a metal silicide layer on the diffusion layer. The contact hole provided so as to reach is a self-aligned opening using the nitride film sidewall of the gate electrode in the DRAM portion.

According to a fourth aspect of the present invention, in a method of manufacturing a semiconductor device, a step of forming a gate electrode on a semiconductor substrate, and an insulating film sidewall L on the sidewall of the gate electrode are provided.
A step of forming a thinner thickness than a normal thickness for forming a DD region, a step of forming diffusion layers to be source / drain regions on both sides of the gate electrode, and growing silicon on the surface of the semiconductor substrate by an epitaxial growth method. A step of forming a silicon epitaxial growth layer adjacent to the outside of the insulating film side wall of the gate electrode, and further forming a nitride film side wall for forming an LDD region on the gate electrode on which the insulating film side wall is formed. And a step of forming a metal film on the entire surface and then converting the silicon epitaxial growth layer and the metal film into a metal silicide layer by a salicide method.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. Embodiment 1 of the present invention will be described below with reference to the drawings. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention, and shows a structure of a DRAM embedded semiconductor device in which a DRAM portion and a logic portion are formed on the same semiconductor substrate. In the figure, 11 is a semiconductor substrate (hereinafter referred to as substrate 11
, 12 is an isolation insulating film for separating the elements,
Reference numeral 13 is a gate electrode formed on the substrate 11 via the gate insulating film 14, 15 is a thin oxide film side wall formed on the side wall of the gate electrode 14, and 16 is nitridation formed outside the oxide film side wall 15. Membrane sidewall, 1
Reference numerals 7a and 17b denote a low concentration diffusion layer and a high concentration diffusion layer which will be the source / drain regions.
Only a is formed. Further, 18 is a metal silicide layer made of CoSi formed on the source / drain regions 17a and 17b, 19 is an interlayer oxide film, and 20 is a contact hole provided in the interlayer oxide film 19 so as to reach the metal silicide layer 18. In particular, in the DRAM part, the self-aligned opening is performed using the nitride film side wall 16. Also, 21
a and 21b are plug electrodes formed by burying the contact holes 20 in the DRAM part and the logic part, and 2
2 is a nitride film, 23 is an oxide film, 24 is a Ti film 24a and Ru
A lower electrode of the capacitor composed of the film 24b, 25 an insulating film, 26 an upper electrode of the capacitor, 27 an oxide film, 28
Is a W plug formed by filling an opening 28a formed so as to reach the plug electrodes 21a and 21b, 29
a and 29b are the W plug 28 and the plug electrode 21a,
A metal wiring layer formed so as to be connected to the metal silicide layer 18 via 21b, and particularly 29a is a bit line in the DRAM portion.

A method of manufacturing a semiconductor device having such a structure will be described below with reference to FIGS. First, after forming an isolation insulating film 12 for element isolation on a substrate 11 made of silicon single crystal, a gate oxide film 13 is formed, and a conductive polysilicon film, a refractory metal film, and a nitride film are sequentially deposited. Then, patterning is performed to form a pattern of the gate electrode 14 on the substrate 11 via the gate oxide film 13. Subsequently, a TEOS film 15a is formed on the entire surface with a film thickness not exceeding 10 nm (FIG. 2), and then the TEOS film 15a is anisotropically etched to form a thin oxide film side wall 15 on the side wall of the gate electrode and the substrate. The silicon surface of 11 is exposed. The oxide film side wall 15 is a normal LD.
It is formed to be thinner than the thickness of the sidewall for forming the D region (FIG. 3). Next, silicon is selectively epitaxially grown by ultra-high pressure CVD to form a silicon epi layer 18a adjacent to the outside of the oxide film sidewall 15. At this time, the silicon epi layer 18 is formed on the isolation insulating film 12 and the nitride film of the gate electrode 13.
a is not formed. After that, a low concentration diffusion layer 17a to be the source / drain region is formed in the lower layer of the silicon epi layer 18a by ion implantation (FIG. 4).

Next, after depositing a nitride film on the entire surface, anisotropic etching is performed to further form a nitride film sidewall 16 outside the oxide film sidewall 15 on the side wall of the gate electrode. The nitride film side wall 16 is formed outside the oxide film side wall 15 and on the silicon epi layer 18a. After that, in the logic portion, the high concentration diffusion layer 17b is formed by ion implantation to form the source / drain regions 17a and 17b of the LDD structure (FIG. 5). Next, after forming a Co film as a metal film on the entire surface, a metal silicide layer 18 made of CoSi is formed by a salicide method. That is, the Co film is changed to the silicon epilayer 18 by heat treatment.
It reacts with a and is transformed into CoSi, and then the unreacted Co film is removed. As a result, the silicon epitaxial layer 18a and the Co film formed thereon are selectively transformed into the metal silicide layer 18. At this time, since the metal silicide layer 18 is formed by reacting the silicon epi layer 18a with the Co film formed thereon, the diffusion layer 17a below the silicon epi layer 18a,
The formation of the metal silicide layer 18 does not proceed up to 17b.
Further, the metal silicide layer 18 is the oxide film side wall 1.
It is insulated from the gate electrode 13 by 5 (FIG. 6).

Next, an interlayer oxide film 19 is deposited, and the source / drain region 1 is formed in a predetermined region of the interlayer oxide film 19.
A contact hole 20 reaching the metal silicide layer 18 on 7a and 17b is opened. At this time, in the DRAM part, it is necessary to open the contact hole 20 in a fine region, and the self-aligned opening using the nitride film sidewall 16 is performed. After that, a barrier metal such as a TiN film is deposited by a sputtering method so as to fill the contact hole 20 with a film thickness of 40 to 50 nm to form plug electrodes 21a and 21b made of the barrier metal. Next, a nitride film 22 and an oxide film 23 are sequentially deposited, an opening 30 is provided, and a Ti film 24a is vapor-deposited by a sputtering method, followed by CV.
The Ru film 24b is deposited by the D method and patterned to form the lower electrode 24 of the capacitor (FIG. 7).

After that, a Ta film is deposited by the CVD method and then oxidized by RTA to form an insulating film 2 made of Ta ₂ O _5.
5 is formed. Subsequently, a Ru film is deposited by the CVD method,
The upper electrode 26 of the capacitor is formed by patterning (FIG. 8). Next, the interlayer oxide film 27 is formed, and the bit line 2
Opening 28 for forming 9a and metal wiring layer 29b
a is formed so as to reach the plug electrodes 21a and 21b,
The W plug 28 is formed by filling the opening 28a. Further, by forming a metal film on the entire surface and patterning it, the W plug 28 and the plug electrodes 21a, 2
A bit line 29a and a metal wiring layer 29b connected to the metal silicide layer 18 via 1b are formed (see FIG. 1). After that, predetermined processing is performed to complete the semiconductor device.

In this embodiment, the silicon epitaxial layer 18a is formed after forming the oxide film sidewall 15 on the side wall of the gate electrode 13 and before forming the nitride film sidewall 16 on the outside thereof. Therefore, the metal silicide layer 18 transformed from the silicon epi layer 18a by the salicide method has a larger area than the conventional case where it is formed outside the nitride film side wall 16 for forming the LDD region, and the wiring resistance and the contact are reduced. The reduction of resistance can be effectively promoted. Further, since the silicon epi layer 18a is grown on the substrate 11 and silicidized into the metal silicide layer 18, the diffusion layer 1 below the silicon epi layer 18a is formed.
The formation of the metal silicide layer 18 does not proceed to 7a and 17b. Therefore, a junction leak does not occur, the depth of the low-concentration diffusion layer 17a is deepened, and the channel leak of the transistor does not increase, and a highly reliable semiconductor device with good characteristics can be obtained. Further, the metal silicide layer 18 is formed by the oxide film side wall 15 on the gate electrode 1.
Insulated with 3 reliability.

By the way, in the DRAM portion, it is necessary to form the contact hole 20 in a fine region, and the self-aligned opening is formed by using the nitride film side wall 16. However, when the contact hole diameter is smaller than 0.2 μm, It is not possible to satisfactorily embed W used for usual plug electrode formation. Therefore, as described above, the plug electrodes 21a and 21b are formed of only the barrier metal. For this reason, the contact resistance becomes high, and especially in the DRAM part, the source / drain regions are composed of only the low-concentration diffusion layer 17a, so that the source / drain resistance is also high. In this embodiment, since the metal silicide layer 18 formed on the low-concentration diffusion layer 17a can be formed wider than the conventional one,
In particular, in the low-concentration diffusion layer 17a in the DRAM portion where the increase in resistance is concerned, reduction of wiring resistance and contact resistance can be effectively promoted.

Although CoSi is used for the metal silicide layer 18 in the above-mentioned embodiment, a silicide of Ti or Ni may be used and can be similarly formed by the salicide method, and the same effect can be obtained. be able to. Further, the oxide film side wall 15 may be a side wall made of another insulating film.

[0018]

As described above, in the semiconductor device according to the first aspect of the present invention, the DRAM section and the logic section are formed on the same semiconductor substrate, and the source and drain regions of the transistors in the DRAM section and the logic section are formed. And a metal silicide layer formed on the surface of the diffusion layer, wherein the metal silicide layer is obtained by siliciding a silicon epitaxial growth layer formed on the diffusion layer by salicide. A thin insulating film sidewall and a nitride film sidewall formed outside thereof are provided on the side surface of the gate electrode, and the metal silicide layer is adjacent to the insulating film sidewall outside the insulating film sidewall of the gate electrode. And the nitride film sidewall is formed on the metal silicide layer. Therefore, the area of the metal silicide layer can be increased, the reduction of the wiring resistance and the contact resistance can be effectively promoted, and the metal silicide layer does not proceed to the diffusion layer region of the lower layer to be formed. It is possible to obtain a highly reliable semiconductor device having excellent characteristics by suppressing the channel leakage of the.

The semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the metal silicide layer is a silicide layer of cobalt, titanium or nickel. Can be formed, and the effect according to claim 1 can be reliably obtained.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, an interlayer oxide film covering the transistor is formed on the semiconductor substrate, and the metal oxide layer on the diffusion layer is formed in the interlayer oxide film. Since the contact hole provided to reach to is a self-aligned opening using the nitride film side wall of the gate electrode in the DRAM part, the contact hole can be opened in a fine region with high reliability and miniaturization is promoted. In addition to being able to increase the area of the metal silicide layer, it is possible to suppress an increase in wiring resistance and contact resistance due to miniaturization.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a step of forming a gate electrode on a semiconductor substrate and a step of forming an insulating film side wall on the side wall of the gate electrode for forming an LDD region are performed normally. A step of forming thinner than the thickness, a step of forming diffusion layers to be source / drain regions on both sides of the gate electrode, and growing silicon on the surface of the semiconductor substrate by an epitaxial growth method,
Forming a silicon epitaxial growth layer adjacent to the outside of the insulating film side wall of the gate electrode; and forming a nitride film side wall for forming an LDD region on the gate electrode on which the insulating film side wall is formed. And a step of forming a metal film on the entire surface and then transforming the silicon epitaxial growth layer and the metal film into a metal silicide layer by a salicide method, so that the area of the metal silicide layer can be easily increased, Reduction of wiring resistance and contact resistance can be effectively promoted, and since the metal silicide layer does not progress to the lower diffusion layer region to be formed, junction leakage and transistor channel leakage are suppressed, and reliability of good characteristics is improved. A high semiconductor device can be obtained easily and surely.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a cross sectional view showing a step in the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a cross sectional view showing a step in the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a cross sectional view showing a step in the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view showing the structure of a conventional semiconductor device.

[Explanation of symbols]

11 semiconductor substrate, 13 gate electrode, 15 oxide film sidewall, 16 nitride film sidewall, 17a
Low-concentration diffusion layer, 17b high-concentration diffusion layer, 18 metal silicide layer, 18a silicon epitaxial layer, 19 interlayer oxide film, 20 contact holes.

Continued front page    F term (reference) 5F048 AB01 AB03 AC01 BA01 BB05                       BF03 BF06 BF11 BF16 BG12                       DA23                 5F083 AD10 AD24 AD49 GA02 JA06                       JA19 JA32 JA35 JA38 JA39                       JA40 JA53 MA05 MA06 MA17                       MA20 PR25 PR29 PR34 PR43                       PR45 PR53 PR55 ZA11

Claims (4)

[Claims] 1. A DRAM-embedded semiconductor device in which a DRAM section and a logic section are formed on the same semiconductor substrate, and a metal silicide layer is formed on the surface of a diffusion layer serving as a source / drain region of a transistor in the DRAM section and the logic section. The metal silicide layer is obtained by siliciding a silicon epitaxial growth layer formed on the diffusion layer by salicide. A film sidewall is provided, the metal silicide layer is provided outside the insulating film sidewall of the gate electrode and adjacent to the insulating film sidewall, and the nitride film sidewall is formed on the metal silicide layer. A semiconductor device characterized in that. 2. The semiconductor device according to claim 1, wherein the metal silicide layer is a silicide layer of cobalt, titanium or nickel. 3. An interlayer oxide film covering a transistor is formed on a semiconductor substrate, and a contact hole is formed in the interlayer oxide film so as to reach a metal silicide layer on a diffusion layer. 3. The semiconductor device according to claim 1, which is a self-aligned opening using a nitride film sidewall. 4. A step of forming a gate electrode on a semiconductor substrate, and an insulating film sidewall L on the sidewall of the gate electrode.
A step of forming a thinner thickness than a normal thickness for forming a DD region, a step of forming diffusion layers to be source / drain regions on both sides of the gate electrode, and growing silicon on the surface of the semiconductor substrate by an epitaxial growth method. A step of forming a silicon epitaxial growth layer adjacent to the outside of the insulating film side wall of the gate electrode, and further forming a nitride film side wall for forming an LDD region on the gate electrode on which the insulating film side wall is formed. A method of manufacturing a semiconductor device, comprising: a forming step; and a step of forming a metal film on the entire surface and then converting the silicon epitaxial growth layer and the metal film into a metal silicide layer by a salicide method.