JPH11111974A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform acceleration and to lower power consumption, while keeping pose time as long as before in a semiconductor device, for which a memory cell and the peripheral circuit are constituted on a semiconductor substrate. SOLUTION: In a peripheral circuit region Rs, high density source/drain regions 7b, 8b, 9b and 10b are formed, etching is performed with resist used at the time of ion injection as a mask, and a first oxidized film 13 formed on the semiconductor substrate 1 is removed. A titan (Ti) film 53 is deposited on the semiconductor substrate 1 as a high-fusing point metallic film and is thermally treated, and a TiSi2 film 11 is formed on the source/drain region of the peripheral circuit region Rs as the silicide film of high-fusing point metal. Since the first oxidized film 13 is left in a memory cell region Rc, the TiSi2 film 11 is not formed. That is, the sheet resistance of the source/drain region of the peripheral circuit region Rs is reduced, while suppressing the increase of leakage current in a charge storage electrode connected to the low density drain region 6a of the memory cell region Rc.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a memory cell and its peripheral circuit are formed on a semiconductor substrate, and more particularly to a high speed and low power consumption by lowering the resistance of wirings and active regions. And a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, semiconductor memory devices, especially dynamic random access memories (hereinafter referred to as "DRAM").
In such a case, the integration degree, the speed, and the power consumption have been reduced by miniaturizing the processing dimensions (design rules).

FIG. 17 shows a DRAM as a conventional semiconductor device.
FIG. 3 is a cross-sectional view of a memory cell and its peripheral circuit region. In FIG. 17, Rc is a memory cell region, Rn and Rp are an NMOS region and a PMO of a peripheral circuit, respectively.
This is the S area. 61a and 61b are a p-type well region and an n-type well region of the p-type Si substrate 61, respectively, 62 is an element isolation insulating film, 63a, 63b and 63c.
Is a gate electrode made of polycrystalline silicon, 64 is a gate insulating film, and 65a and 66a are memory cell regions R, respectively.
c, the n-type lightly doped source region and lightly doped drain region 67a and 68a
N-type low-concentration source region and low-concentration drain region in S region Rn, 69a and 70a are p-type low-concentration source and low-concentration drain regions in peripheral circuit PMOS region Rp, 67b and 68b are peripheral circuit NMOS regions, respectively. N-type high concentration source region and high concentration drain region in Rn, 69b and 70b
Is a p-type high-concentration source region and a high-concentration drain region in the peripheral circuit PMOS region Rp, 73A is a sidewall of an oxide film, 74 is an oxide film, 81 is a charge storage electrode, 82 is a capacitance insulating film, and 83 is a plate electrode. , 84 are bit lines, 85a to 85e are first to fifth interlayer insulating films, 86a to 86c are first to third contact plugs, 87a is a first layer wiring, and 87b is a second layer wiring. .

According to a semiconductor device having a structure as shown in FIG. 17, a charge storage electrode 81 is formed in a memory cell region Rc.
The drain region connected to is formed only of the low-concentration region 66a, and the high-concentration region is not formed unlike the drain regions of the peripheral circuit regions Rn and Rp. For this reason, since the spread of the depletion layer on the drain side is large, the potential gradient is not steep, and since there are few injection defects, the junction leakage is low and the charge stored in the charge storage electrode 81 is small. The holding time (hereinafter referred to as “pause time”) is long.

On the other hand, gate electrodes 63a, 63b, 63c
Is formed of a polycrystalline silicon film, its sheet resistance is higher than that of metal or the like. Further, the sheet resistances of the high-concentration source regions 68a and 69a and the high-concentration drain regions 68b and 69b in the peripheral circuit regions Rn and Rp are also high.

Heretofore, the operating speed and power consumption of a transistor have been improved by reducing the resistance during operation of the transistor (hereinafter referred to as "on-resistance") by miniaturizing the gate length of the transistor. However, on the other hand, the gate electrode and source
The sheet resistance of the drain region increases with miniaturization,
The size has become almost equal to the on-resistance of the reduced transistor. For this reason, the sheet resistance of the gate electrode and the source / drain regions is becoming a major factor in determining the operating speed and power consumption of the transistor, and it is difficult to improve the operating speed and power consumption of the transistor even with further miniaturization. It has become to.

Recently, MPU (Micro Processing Un
It) has increased the demand for a DRAM-LOGIC mixed chip in which a high-speed LOGIC circuit such as a DRAM and a DRAM are formed on the same chip. However, if the above-described structure is used for the DRAM-LOGIC mixed chip, LOGI due to high sheet resistance of gate electrode and source / drain region
There is a problem that the operation speed of the C-system circuit cannot be sufficiently obtained.

On the other hand, conventionally, in order to improve the operation speed of a LOGIC circuit in a chip such as an MPU, a salicide film is formed on a gate electrode or a source / drain region to reduce the sheet resistance. Technology is used.

FIG. 18 shows such salicide technology in FIG.
FIG. 8 is a cross-sectional view in a region of a memory cell and its peripheral circuit when applied to the DRAM shown in FIG. 7 as it is. 18, the same components as those of the semiconductor device shown in FIG. 17 are denoted by the same reference numerals as in FIG. As shown in FIG. 18, a TiSi ₂ film 71 is formed on each gate electrode and each drain / source region.

A DRAM having a structure as shown in FIG.
A conventional example of the manufacturing method will be described with reference to the drawings. 19 and 20 show the DRA having the structure shown in FIG.
It is process sectional drawing which shows the conventional example of the manufacturing method of M.

First, as shown in FIG. 19A, a gate insulating film 64 and polycrystalline silicon are formed on a p-type Si substrate 61 on which a p-type well region 61a, an n-type well region 61b and an element isolation insulating film 62 are formed. Gate electrode 63 made of
a, 63b and 63c are formed. Thereafter, in the memory cell region Rc and the peripheral circuit NMOS region Rn, the n-type low concentration source / drain regions 65a, 66a, 67a, 6
8a, and p-type low-concentration source / drain regions 69a, 70a in the peripheral circuit PMOS region Rp.
Is formed, and an oxide film 73 is formed on the entire surface of the substrate by a low pressure chemical vapor deposition method (hereinafter, referred to as “LPCVD method”).

Thereafter, as shown in FIG. 19B, the oxide film 73 is removed by anisotropic dry etching, and the oxide film 73 is formed only on the side walls of the gate electrodes 63a, 63b and 63c.
Are left behind, so that the oxide film sidewalls 7
Form 3A.

Thereafter, as shown in FIG. 19C, a resist 91 covering the memory cell region Rc and the peripheral circuit PMOS region Rp is formed by photolithography, and the resist 91, the gate electrode 63b and the gate electrode 63b are formed. Using the side wall 73A formed on the side wall of the substrate as a mask, n-type high-concentration impurities such as arsenic As are ion-implanted to form high-concentration source / drain regions 67b and 68b.
Is formed, and the resist 91 is removed.

Next, as shown in FIG. 19D, a resist 92 covering the memory cell region Rc and the peripheral circuit NMOS region Rn is formed by photolithography, and the resist 92, the gate electrode 63c and the gate electrode are formed. Using the side wall 73A formed on the side wall of 63c as a mask, a p-type high concentration impurity such as boron B is added to BF ₂ ⁺
20a, and as shown in FIG.
Forming high concentration source / drain regions 69b and 70b,
The resist 92 is removed.

Thereafter, as shown in FIG. 20B, a titanium (Ti) film 93 is deposited on the entire surface of the substrate by a sputtering method, and a RTA (Rapid Thermal Anneal) is formed.
a) heat treatment and silicidation to form low concentration source / drain regions 65 in the memory cell region Rc on the gate electrodes 63a, 63b and 63c.
a, 65b, and high-concentration source / drain regions 67b, 68b, 69b, in peripheral circuit regions Rn, Rp.
A TiSi ₂ film 71 is formed on 70b, and the unreacted Ti film 93 and the titanium nitride (TiN) film formed on the surface of the Ti film 93 during heat treatment by the RTA method are removed.

Thereafter, a second oxide film 74 and a first interlayer insulating film 85a are formed on the entire surface of the substrate. Thereafter, a contact hole connected to the low-concentration drain region 66a in the memory cell region Rc is opened, and a charge storage electrode 81, a capacitor insulating film 82, and a plate electrode 83 are formed. At this time, a stacked film of a Si ₃ N ₄ film and a SiO ₂ film has been often used as the capacitance insulating film 82.

Thereafter, a second interlayer insulating film 85b is formed on the entire surface of the substrate, and the low concentration source region 65a in the memory cell region Rc and the high concentration source / drain regions 67b, 68b, 69b, in the peripheral circuit regions Rn, Rp.
A contact hole connected to 70b is opened, and a first contact plug 86a and a bit line 84 are formed.

Thereafter, a third interlayer insulating film 85c is formed on the entire surface of the substrate, and the high-concentration source / drain regions 67b, 68b, 69b, 70 in the peripheral circuit regions Rn, Rp are formed.
A contact hole connected to the gate electrode b or the gate electrodes 63b and 63c is opened, and a second contact plug 86b and a first layer wiring 87a are formed.

Thereafter, a fourth interlayer insulating film 85d is formed on the entire surface of the substrate, a contact hole connected to the first layer wiring 87a is opened, and a third contact plug 86c and a second layer wiring 87b are formed. A fifth interlayer insulating film 85e is formed on the entire surface.

[0020]

However, according to the structure of the conventional semiconductor device as described above, the low-concentration source / drain regions 65a, 65a in the memory cell region Rc.
The TiSi ₂ film 71 is formed on 6a. The junction depth of the low-concentration regions 65a and 66a is smaller than that of the high-concentration regions 67b, 68b, 69b and 70b in the peripheral circuit regions Rn and Rp, and Source when bias is applied
The depletion layer width on the drain side is also large. Therefore, TiSi
_{Even if the 2} film 71 is thicker than the junction depth and breaks through the junction, or the TiSi ₂ film 71 is thinner than the junction depth,
There is a disadvantage that the depletion layer extends to the TiSi ₂ film 71 due to the bias application, and the junction leakage increases.

Since the silicidation reaction involves the movement of Si atoms, defects such as vacancies are generated in the Si substrate. Also, the stress applied to the Si substrate changes,
Distortion also occurs in the crystal of the substrate. The occurrence of such defects and distortion causes an increase in junction leak. In particular, the increase in junction leak in the low-concentration drain region 66a connected to the charge storage electrode 81 in the memory cell region Rc is accumulated in the charge storage electrode 81. This causes an increase in the leaked charge, which causes a problem that the pause time is shortened.

In the conventional manufacturing method, the capacitance insulating film 8
As 2, a laminated film of a Si ₃ N ₄ film and a SiO ₂ film is used. However, the process temperature for forming the SiO ₂ film is 800
° C or higher, so in this SiO ₂ film forming process,
There is a problem that the TiSi ₂ film 71 formed in the previous step aggregates to increase the resistance.

In view of the above problems, the present invention provides a semiconductor device in which a memory cell and its peripheral circuits are formed on a semiconductor substrate, while maintaining a pause time as long as the conventional one, while achieving high speed and low power consumption. It is to realize the conversion.

[0024]

Means for Solving the Problems In order to solve the above-mentioned problems, means taken by the invention according to claim 1 is that a semiconductor substrate has
As a semiconductor device provided with both a memory cell including a MOS structure and a peripheral circuit, in a memory cell region,
A charge storage electrode connected to the drain region is formed, and a silicide film of a high melting point metal or a high melting point metal film is formed on the source / drain region in the peripheral circuit region, while the charge in the memory cell region is formed. The refractory metal silicide film and the refractory metal film are not provided on the drain region connected to the storage electrode.

According to the first aspect of the present invention, since the high melting point metal silicide film or the high melting point metal film is formed on the source / drain region in the peripheral circuit region, the sheet resistance of the source / drain region is low. As a result, high speed and low power consumption of the semiconductor device are realized. On the other hand, since a silicide film and a high-melting-point metal film of a high-melting-point metal are not provided on the drain region connected to the charge storage electrode in the memory cell region, the junction leak is as low as the conventional one, and the junction leak increases. Does not cause an increase in the leakage of electric charge, so that the pause time is not shortened. Therefore, high speed and low power consumption are realized while the pause time is kept as long as the conventional one.

According to a second aspect of the present invention, the high melting point metal silicide film or the high melting point metal film is formed on the gate electrode in the peripheral circuit region of the semiconductor device of the first aspect.

According to the second aspect of the present invention, since the refractory metal silicide film or the refractory metal film is formed on the gate electrode in the peripheral circuit region, the wiring resistance of the gate electrode is also reduced. Further higher speed and lower power consumption are realized while the pause time is kept as long as the conventional one.

According to the third aspect of the present invention, in the first aspect,
It is assumed that the gate electrode in the peripheral circuit region of the semiconductor device has a laminated structure of a polycrystalline silicon film and a refractory metal silicide film or a refractory metal film.

According to the third aspect of the present invention, since the gate electrode in the peripheral circuit region has a laminated structure of a polycrystalline silicon film and a high melting point metal silicide film or a high melting point metal film, the wiring resistance of the gate electrode is reduced. , The speed is further reduced and the power consumption is further reduced while the pause time is kept as long as the conventional one.

According to a fourth aspect of the present invention, in the memory cell region of the semiconductor device of the first aspect, a plate electrode is formed so as to cover the charge storage electrode and a drain region connected to the charge storage electrode. It is assumed that a silicide film or a high melting point metal film of the high melting point metal is formed on the plate electrode.

According to the fourth aspect of the present invention, the refractory metal silicide film or the refractory metal film is formed on the charge storage electrode and the plate electrode formed above the drain region connected to the charge storage electrode. Since it is formed, the resistance of the plate electrode can also be reduced, so that a higher speed and lower power consumption can be realized while the pause time is kept as long as the conventional one.

Further, in the invention of claim 5, according to claim 1,
In the memory cell region of the semiconductor device, a bit line connected to a source region is formed, and the refractory metal silicide film or the refractory metal film is formed on the source region connected to the bit line. It is assumed that

According to the fifth aspect of the present invention, in the memory cell region, the silicide film of the refractory metal or the refractory metal film is formed on the source region connected to the bit line. Since the reaction with the Si substrate can be prevented and a stable contact can be realized, a metal film such as Ti, W and Al which has low resistance but reacts with Si can be used as it is as a bit line material. In addition, the resistance of the wiring can be reduced.

According to a sixth aspect of the present invention, there is provided a semiconductor device manufacturing method for manufacturing a semiconductor device provided with a memory cell and a peripheral circuit both having a MOS structure on a semiconductor substrate. Forming a gate electrode thereon, forming a drain region on a surface of the semiconductor substrate in a memory cell region, forming an insulating film on the semiconductor substrate, and forming a memory cell region on the semiconductor substrate. Forming a resist to cover, in the peripheral circuit region, forming source / drain regions on the surface of the semiconductor substrate by ion implantation using the resist and the gate electrode as a mask, and etching the insulating film using the resist as a mask, Removing the resist, forming a refractory metal film on the semiconductor substrate and performing a heat treatment, Forming a silicide film of the refractory metal on a source / drain region in a peripheral circuit region where an edge film is not left; and forming a charge storage electrode connected to the drain region in a memory cell region. Shall be provided.

According to the present invention, the insulating film in the peripheral circuit region is etched using the resist used for ion implantation for forming the source / drain regions in the peripheral circuit region as a mask. The film is left only in the memory cell region, and the surface of the semiconductor substrate is exposed in the peripheral circuit region. Therefore, as a result of forming a refractory metal film on a semiconductor substrate and performing heat treatment, a silicide film of the refractory metal is formed on the source / drain regions in the peripheral circuit region, while the silicide film is formed in the memory cell region. It is not formed on the drain region covered with the insulating film. Therefore, a refractory metal silicide film is formed on the source / drain region in the peripheral circuit region, while a refractory metal silicide film is formed on the drain region connected to the charge storage electrode in the memory cell region. Unprocessed semiconductor devices can be manufactured in a small number of steps.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, instead of the step of forming a silicide film of a high melting point metal, a method of manufacturing the semiconductor device in the peripheral circuit region where the insulating film is not left is used. It is assumed that a step of forming a high melting point metal film on the source / drain region by a selective chemical vapor deposition method is provided.

According to the seventh aspect of the present invention, the refractory metal film is formed on the source / drain region in the peripheral circuit region, and is formed on the drain region covered with the insulating film in the memory cell region. Not done. Therefore, while the refractory metal film is formed on the source / drain region in the peripheral circuit region, the refractory metal film is not formed on the drain region connected to the charge storage electrode in the memory cell region. The device can be manufactured in a small number of steps.

According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, the gate electrode is made of a polycrystalline silicon film, and when the refractory metal silicide film is formed, the insulating film is formed. It is assumed that a silicide film of the refractory metal is formed on the gate electrode where no is left.

According to the ninth aspect of the present invention, the sixth aspect of the present invention is provided.
The method for manufacturing a semiconductor device according to
It has a laminated structure of a polycrystalline silicon film and a refractory metal silicide film or a refractory metal film, and an insulating film is formed on the gate electrode when the gate electrode is formed.

According to the ninth aspect of the present invention, when the wiring width of the gate electrode is reduced, the wiring resistance does not increase due to aggregation of the refractory metal silicide film, so that the gate electrode can be reduced in size.

According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, the step of forming a source / drain region in a peripheral circuit region and etching the insulating film includes forming a memory on a semiconductor substrate. Forming a first resist covering the cell region and the first conductivity type transistor region in the peripheral circuit region; anisotropically etching the insulating film to form a side wall of the gate electrode in the second conductivity type transistor region in the peripheral circuit region; Forming a sidewall by leaving the insulating film; and forming the first conductive layer in the second conductive transistor region of the peripheral circuit region.
Forming a source / drain region on the surface of the semiconductor substrate by ion implantation using the resist and the gate electrode as a mask, and removing the first resist; and forming a second region of the memory cell region and the peripheral circuit region on the semiconductor substrate. Forming a second resist covering the conductive type transistor region and isotropically etching and anisotropically etching the insulating film;
Forming a sidewall by leaving the insulating film on the side wall of the gate electrode of the first conductivity type transistor region in the peripheral circuit region; and forming the second resist in the first conductivity type transistor region in the peripheral circuit region. And forming a source / drain region on the surface of the semiconductor substrate by ion implantation using the gate electrode as a mask.
And a step of removing the resist.

According to the tenth aspect of the present invention, the peripheral circuit first
The etching of the insulating film in the conductive transistor region is performed by isotropic etching and anisotropic etching, while the etching of the insulating film in the peripheral circuit second conductive transistor region is performed by anisotropic etching. In the first conductivity type transistor region and the second conductivity type transistor region of the circuit, sidewalls having different thicknesses can be formed on the side walls of the gate electrode. Since the source / drain region in the peripheral circuit region is formed using the gate electrode as a mask, its dimensions can be changed depending on the thickness of the sidewall. Therefore, source / drain regions having dimensions suitable for the transistors of the first conductivity type and the second conductivity type can be formed.

According to another aspect of the present invention, there is provided a semiconductor device manufacturing method for manufacturing a semiconductor device provided with a memory cell and a peripheral circuit both having a MOS structure on a semiconductor substrate. Forming a gate electrode thereon, forming a drain region on the surface of the semiconductor substrate in the memory cell region, forming an insulating film on the semiconductor substrate, and forming the drain region in the memory cell region. Forming a connected charge storage electrode on the insulating film, laminating a capacitive insulating film and a conductive film on the semiconductor substrate, and forming a plate electrode on the conductive film to cover a predetermined region in a memory cell region; A resist is formed, the conductive film is etched using the plate electrode forming resist as a mask, and the charge storage electrode is replaced with the capacitor insulating film. Performing a step of forming a plate electrode to cover through, a step of etching the insulating film using the plate electrode forming resist or the plate electrode as a mask, and forming a refractory metal film on the semiconductor substrate and performing heat treatment. Forming a silicide film of the refractory metal on a source / drain region in a peripheral circuit region where the insulating film is not left.

According to the eleventh aspect of the present invention, a plate electrode that covers the charge storage electrode and a drain region connected to the charge storage electrode via a capacitor insulating film, or a plate electrode for forming the plate electrode Since the insulating film in the peripheral circuit region is etched using the resist as a mask, the insulating film is removed in a region other than the region covered by the plate electrode in the memory cell region, and the surface of the semiconductor substrate is exposed. Therefore, as a result of forming a refractory metal film on a semiconductor substrate and performing heat treatment, a silicide film of the refractory metal is formed on the source / drain regions in the peripheral circuit region, while the silicide film is formed in the memory cell region. It is not formed on the drain region covered with the plate electrode. Therefore, while the silicide film of the refractory metal is formed on the source / drain regions in the peripheral circuit region,
A semiconductor device in which a silicide film of a refractory metal is not formed on a drain region connected to a charge storage electrode in a memory cell region can be manufactured in a small number of steps. In addition, since the formation of the silicide film of the refractory metal is performed after the formation of the capacitive insulating film, the heat treatment of the capacitive insulating film does not cause the aggregation of the silicide film of the refractory metal. The same as described above can be used.

According to a twelfth aspect of the present invention, in the method of manufacturing a semiconductor device according to the eleventh aspect, before forming the silicide film of the refractory metal, the ion implantation is performed using the plate electrode and the gate electrode as a mask. And a step of forming source / drain regions on the surface of the semiconductor substrate.

According to a thirteenth aspect of the present invention, in the method of manufacturing the semiconductor device according to the eleventh aspect, the plate electrode is formed in the memory cell region so as to avoid a source region connected to a bit line. When forming the refractory metal silicide film, the refractory metal silicide film is formed on the source region connected to the bit line in the memory cell region.

According to a fourteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the eleventh aspect, the gate electrode is made of a polycrystalline silicon film, and the gate electrode is formed on the gate electrode when the silicide film is formed. It is assumed that a silicide film of a melting point metal is formed.

According to a fifteenth aspect of the present invention, in the method for manufacturing a semiconductor device according to the eleventh aspect, the conductive film is made of a polycrystalline silicon film, and is formed of the conductive film when the silicide film is formed. The refractory metal silicide film is formed on the plate electrode.

According to a sixteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the eleventh aspect, the insulating film etching step includes removing the plate electrode resist before etching the insulating film. Forming a second insulating film thereon, etching the second insulating film together with the insulating film, and forming a sidewall by leaving the second insulating film on a side wall of the plate electrode. And a process.

[0050]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a cross-sectional view of a memory cell of a dynamic random access memory (hereinafter referred to as "DRAM"), which is a semiconductor device according to a first embodiment of the present invention, and its peripheral circuits. FIG. In FIG. 1, Rc is a memory cell region in which a memory cell is formed, Rs is a peripheral circuit region in which a peripheral circuit is formed,
Both have a MOS structure. The peripheral circuit region Rs is N
It is divided into a MOS region Rn and a PMOS region Rp.

Reference numeral 1 denotes a p-type Si substrate as a semiconductor substrate, 1a and 1b denote a p-type well region and an n-type well region of the p-type Si substrate 1, 2 denotes an element isolation insulating film,
a, 3b, 3c are gate electrodes made of polycrystalline silicon;
4 is a gate insulating film, 5a and 6a are n-type lightly doped source and lightly doped drain regions in the memory cell region Rc, and 7a and 8a are peripheral circuits N respectively.
N-type low-concentration source region and low-concentration drain region in MOS region Rn; 7b and 8b are n-type high-concentration source and high-concentration drain regions in NMOS region Rn; 9a and 10a are peripheral circuit PMOS regions, respectively The p-type low-concentration source region and low-concentration drain region in Rp, 9b and 10b are the p-type high-concentration source region and high-concentration drain region in the peripheral circuit PMOS region Rp, respectively.

In the memory cell region Rc, the source region 5 is constituted by the n-type low-concentration source region 5a.
The low-concentration drain region 6a forms a drain region 6. In the peripheral circuit NMOS region Rn, a source region 7 is formed by the n-type low-concentration source region 7a and the high-concentration source region 7b, and a drain region 8 is formed by the n-type low-concentration drain region 8a and the high-concentration drain region 8b. It is configured. Further, in the peripheral circuit PMOS region Rp, the source region 9 is formed by the p-type low-concentration source region 9a and the high-concentration source region 9b.
And the drain region 10 is constituted by the p-type low-concentration drain region 10a and the high-concentration drain region 10b.

Reference numeral 11 denotes a TiSi ₂ film, 13 denotes a first oxide film, 13A and 13B denote sidewalls of the oxide film, 14 denotes a second oxide film, 21 denotes a charge storage electrode, 22 denotes a capacitance insulating film, and 23 denotes a capacitor insulating film. Is a plate electrode, 24 is a bit line, 2
5a to 25e are first to fifth interlayer insulating films, respectively.
a to 26c are first to third contact plugs, respectively.
27a is a first layer wiring, and 27b is a second layer wiring.

According to the semiconductor device having the structure as shown in FIG. 1, a silicide film of a refractory metal is not formed on the source / drain regions 5 and 6 in the memory cell region Rc. The junction leakage is as low as before and the pause time is as long as before.

On the other hand, a TiSi ₂ film 11 as a silicide film of a high melting point metal is formed on the source / drain regions 7, 8, 9 and 10 in the peripheral circuit region Rs. Since these source / drain regions 7, 8, 9, 10 have high concentration regions 7b, 8b, 9b, 10b, respectively,
Memory cell region Rc consisting only of low concentration regions 5a and 6a
The junction depth is deeper than the source / drain regions 5 and 6, and the width of the depletion layer on the source and drain sides is smaller. Therefore, there is no problem of junction leakage, and low resistance can be realized. Further, the gate electrodes 3b and 3c in the peripheral circuit region Rs
Since the TiSi ₂ film 11 is also formed thereon, it is possible to reduce the wiring resistance of the gate electrodes 3b and 3c.

Hereinafter, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings.

FIGS. 2 and 3 are sectional views showing a method of manufacturing the semiconductor device according to the first embodiment of the present invention, in which the method of manufacturing the semiconductor device shown in FIGS.

First, a gate insulating film 4 and gate electrodes 3a, 3b, 3c made of polycrystalline silicon are formed on a p-type Si substrate 1 on which a p-type well region 1a, an n-type well region 1b and an element isolation insulating film 2 are formed. Then, n-type low-concentration source regions 5a and n are formed in memory cell region Rc.
-Type low-concentration drain region 6a is formed, and a peripheral circuit NMOS is formed.
An n-type low-concentration source region 7a and an n-type low-concentration drain region 8a are formed in a region Rn, and a p-type low-concentration source region 9a and a p-type low-concentration drain region 10a are formed in a peripheral circuit PMOS region Rp. A first oxide film 13 as an insulating film is formed on the entire surface by low pressure chemical vapor deposition (hereinafter, referred to as "LPCVD").

Next, as shown in FIG. 2A, a resist 51 covering the memory cell region Rc and the peripheral circuit PMOS region Rp is formed by photolithography, and the resist 51, the gate electrode 3b and the gate electrode 3 are formed.
Using the first oxide film 13 on the side wall of b as a mask, ions of an n-type high-concentration impurity such as arsenic As are implanted to form an n-type high-concentration source region 7b and an n-type high-concentration drain region 8b. The drain region 8 in the peripheral circuit NMOS region Rn thus formed is located near the channel of the n-type high-concentration drain region 8b.
, An LDD (Lightly Doped Drain) structure is provided, so that the electric field near the drain is alleviated, and high reliability in drain withstand voltage and the like can be realized.

Next, as shown in FIG.
Using 1 as a mask, by anisotropic dry etching,
On the gate electrode 3b in the peripheral circuit NMOS region Rn,
In addition, the first oxide film 13 on the n-type high-concentration source region 7b and the n-type high-concentration drain region 8b is removed, and the first oxide film 13 is left only on the side wall of the gate electrode 3b to form a side wall 13A. I do. After that, the resist 51 is removed.

Next, as shown in FIG. 2C, a resist 52 covering the memory cell region Rc and the peripheral circuit NMOS region Rn is formed by photolithography, and the resist 52, the gate electrode 3c and the gate electrode 3 are formed.
Using the first oxide film 13 on the side wall of the mask c as a mask, a p-type high-concentration impurity, for example, boron B is implanted using BF ₂ ⁺ ions, and the p-type high-concentration source region 9b and the p-type high-concentration drain The region 10b is formed. The drain region 10 in the peripheral circuit PMOS region Rp thus formed
Is the drain region 8 in the peripheral circuit NMOS region Rn.
LDD in which a p-type low-concentration drain region 10a is provided near the channel of a p-type high-concentration drain region 10b
It has a structure.

Next, as shown in FIG.
Using 2 as a mask, anisotropic dry etching
On the gate electrode 3c in the peripheral circuit PMOS region Rp,
In addition, the first oxide film 13 on the p-type high-concentration source region 9b and the p-type high-concentration drain region 10b is removed, and the first oxide film 13 is left only on the side wall of the gate electrode 3c to form a sidewall 13B. I do. After that, the resist 52
Is removed.

Next, as shown in FIG. 3A, a titanium (Ti) film 53 is deposited on the entire surface of the substrate by a sputtering method, and RTA (Rapid Thermal Anneal).
1) Heat treatment is performed by the method. As a result, as shown in FIG. 3B, by the silicidation, TiSi ₂ is formed only on the gate electrodes 3b and 3c and the high concentration source / drain regions 7b, 8b, 9b and 10b in the peripheral circuit region Rs. The film 11 is formed. At this time, the low-concentration source / drain regions 5a and 6a in the memory cell region Rc
Above, since the first oxide film 13 is formed, RT
During the heat treatment by the method A, the Ti film 53 does not react with the Si substrate, and no silicide film is formed. Then, FIG.
As shown in (2), the unreacted Ti film 53 and the titanium nitride (TiN) film formed on the surface of the Ti film 53 during the heat treatment by the RTA method are removed.

Thereafter, although not shown, the second oxide film 14
In addition, a first interlayer insulating film 25a is formed on the entire surface of the substrate, and is planarized by a CMP (Chemical Mechanical Polishing) method. Next, a contact hole connected to the drain region 6 of the memory cell region Rc is opened, and a charge storage electrode 21, a capacitor insulating film 22, and a plate electrode 23 are formed. Next, a second interlayer insulating film 25b is formed on the entire surface of the substrate, and is planarized by the CMP method.
c and the source region 5 of the peripheral circuit region Rs.
A contact hole connected to the drain regions 7, 8, 9, 10 is opened, and a first contact plug 26a and a bit line 24 are formed.

After that, a third interlayer insulating film 25c is formed on the entire surface of the substrate, planarized by the CMP method, and the source / drain regions 7, 8, 9, 10 of the peripheral circuit region Rs are formed.
Alternatively, a contact hole connected to the gate electrodes 3b, 3c is opened, and a second contact plug 26b and a first layer wiring 27a are formed. Next, a fourth interlayer insulating film 25d is formed on the entire surface of the substrate, and is planarized by a CMP method.
A contact hole connected to the first layer wiring 27a is opened, a third contact plug 26c and a second layer wiring 27b are formed, and a fifth interlayer insulating film 25e is formed on the entire surface.

Here, in order to prevent the TiSi ₂ film 11 from aggregating and increasing the resistance, the process temperature after the formation of the TiSi ₂ film 11 needs to be 750 ° C. or less. Therefore, the second oxide film 14 and the first to fifth interlayer insulating films 2
The process temperature in the formation process and the planarization process of 5a to 25e is 750 ° C. or less, and the capacitance insulating film 22 is made of Ta.
It is assumed that the film can be formed at 750 ° C. or less, such as ₂ O ₅ or BST (BaSrTiO ₃ ).

As described above, according to the method of manufacturing the semiconductor device according to the first embodiment of the present invention, the peripheral circuit region Rs
The first oxide film 13 in the peripheral circuit region Rs is dry-etched while the resists 51 and 52 used for ion implantation for forming the high-concentration regions 7b, 8b, 9b, and 10b are used as masks, while the memory is The first oxide film 13 is left in the cell region Rc. Thereby, the source / drain regions 5, 6 of the memory cell region Rc
Without forming a silicide film thereon, the gate electrodes 3b and 3c of the peripheral circuit region Rs and the source / drain regions 7,
The TiSi ₂ film 11 can be formed on 8, 9, and 10.

In this embodiment, the case where the TiSi ₂ film 11 is formed as the silicide film of the high melting point metal has been described, but another high melting point metal film such as cobalt (Co) may be used instead of the Ti film 53. Accordingly, it is needless to say that this refractory metal silicide film can be formed instead of the TiSi ₂ film 11.

(Second Embodiment) A second embodiment of the present invention relates to a semiconductor device according to the first embodiment,
A W film is formed instead of the Si ₂ film 11. Hereinafter, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to the drawings.

FIG. 4 shows a method of manufacturing a semiconductor device according to a second embodiment of the present invention, in which a W film is formed instead of the TiSi ₂ film 11 in the semiconductor device shown in FIG. FIG.

FIGS. 2A to 2D according to the first embodiment.
As shown in FIG. 4A, the high-concentration source / drain regions 7b, 8b,
9b and 10b are formed, and the first is formed only in the memory cell region Rc.
Oxide film 13 is left, and the peripheral circuit region Rs
The sidewalls 13A and 13B are formed leaving the first oxide film 13 on the side walls of the gate electrodes 3b and 3c, and the resist 52 is removed.

Thereafter, as shown in FIG. 4B, the selective chemical vapor deposition method (selective CVD method) is performed on the gate electrodes 3b and 3c in the peripheral circuit region Rs and the high-concentration source / source.
On the drain regions 7b, 8b, 9b, 10b, a W film 12 is formed as a refractory metal film. At this time, since the first oxide film 13 is formed on the low-concentration source / drain regions 5a and 6a in the memory cell region Rc, the W film 12 is not formed.

Thereafter, as in the first embodiment, a second oxide film 14 and a first interlayer insulating film 25a are formed on the entire surface of the substrate, and are planarized by the CMP method. , Capacitive insulating film 22, plate electrode 23,
The bit line 24, the first layer wiring 27a and the like are formed.

Here, in order to prevent the W film 12 from reacting with the underlying polycrystalline silicon film or Si substrate to cause agglomeration or the like, the process temperature after the formation of the W film 12 must be 750 ° C. or less. There is. Therefore, the temperature in the step of forming and planarizing the second oxide film 14 and the first to fifth interlayer insulating films 25a to 25e is 750 ° C. or less,
The capacitance insulating film 22 is made of 750 ° C. such as Ta ₂ O ₅ or BST.
It is assumed that the film can be formed as follows.

As described above, according to the method of manufacturing the semiconductor device according to the second embodiment of the present invention, the W film 12 can be formed only in a desired region by using the selective CVD method. It can be significantly reduced.

Further, as shown in the first embodiment, a Ti film 53 is deposited on the entire surface of the substrate, and TiS is deposited by RTA.
In the method of forming the i ₂ film 11 in a desired region, Ti and S
During the reaction of i, the Si atoms of the Si substrate move to the Ti film 53 side, whereby the TiSi ₂ film 11 travels along the Ti film 53 formed on the entire surface of the substrate and the side wall 13 of the oxide film
A, 13B or the element isolation insulating film 2 will go up. Therefore, as device miniaturization progresses, TiSi on adjacent source, drain regions or gate electrodes
There is a possibility that the _two films 11 come into contact with each other and cause a short circuit. However, in the film formation method by the selective CVD method as shown in this embodiment, the W film 12 is formed only on the Si substrate and the gate electrode of polycrystalline silicon. The W films 12 on the region or the gate electrode do not contact with each other or short-circuit.

In this embodiment, the case where the refractory metal film formed by the selective CVD method is the W film 12 is shown, but instead of the W film 12, another refractory metal film or TiSi ₂
Needless to say, a silicide film such as a film or a WSi ₂ film can be formed.

(Third Embodiment) FIG. 5 is a sectional view of a memory cell of a DRAM, which is a semiconductor device according to a third embodiment of the present invention, and its peripheral circuits. The semiconductor device according to the present embodiment shown in FIG. 5 has the same configuration as the semiconductor device according to the first embodiment shown in FIG. 1, and the same components as those in FIG. doing. In FIG. 5, reference numerals 15a, 15b and 15c denote gate electrodes of a polycide film having a laminated structure of polycrystalline silicon and a silicide film, and reference numeral 16 denotes a third oxide film formed on the gate electrodes 15a, 15b and 15c.

According to the semiconductor device having the structure as shown in FIG. 5, no refractory metal silicide film is formed on the source / drain regions 5 and 6 in the memory cell region Rc. The junction leakage is as low as before and the pause time is as long as before.

On the other hand, a TiSi ₂ film 11 as a silicide film of a high melting point metal is formed on the source / drain regions 7, 8, 9 and 10 in the peripheral circuit region Rs. Since these source / drain regions 7, 8, 9, 10 have high concentration regions 7b, 8b, 9b, 10b, respectively,
Memory cell region Rc consisting only of low concentration regions 5a and 6a
The junction depth is deeper than the source / drain regions 5 and 6, and the width of the depletion layer on the source and drain sides is smaller. Therefore, there is no problem of junction leakage, and low resistance can be realized.

In memory cell region Rc and peripheral circuit region Rs, gate electrodes 15a, 15b, 15c
Is formed of a polycide film having a laminated structure of polycrystalline silicon and a silicide film, so that the wiring resistance of the gate electrodes 15a, 15b, and 15c can be reduced.

Hereinafter, a method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described with reference to the drawings.

FIGS. 6 and 7 are cross-sectional views showing a method of manufacturing the semiconductor device according to the third embodiment of the present invention, in the order of steps showing the method of manufacturing the semiconductor device shown in FIG.

First, on the p-type Si substrate on which the p-type well region 1a, the n-type well region 1b and the element isolation insulating film 2 are formed, a gate insulating film 4 and a polycide having a laminated structure of polycrystalline silicon and a silicide film are formed. A film and a third oxide film 16 are formed and patterned by photolithography and dry etching to form a gate electrode 15.
a, 15b and 15c are formed. At this time, the polycide film is formed by a CVD method or a sputtering method. Next, the memory cell region Rc and the peripheral circuit NMOS region R
n, n-type low concentration source / drain regions 5a, 6
a, 7a, 8a are formed, p-type low-concentration source / drain regions 9a, 10a are formed in the peripheral circuit PMOS region Rp, and a first oxide film 13 is formed on the entire surface of the substrate by LPCVD.

Next, as shown in FIG. 6A, the memory cell region Rc and the peripheral circuit PMOS region Rp are covered with a resist 51 by photolithography, and the resist 51, the gate electrode 15b, and the gate electrode 15b are covered.
Using the first oxide film 13 on the side wall of the substrate as a mask, n-type high-concentration impurities such as arsenic As are ion-implanted to form an n-type high-concentration source region 7b and an n-type high-concentration drain region 8b. The drain region 8 of the NMOS region Rn is set to L
It has a DD structure.

Next, as shown in FIG.
Using 1 as a mask, by anisotropic dry etching,
The first oxide film 13 on the gate electrode 15b and the n-type high-concentration source region 7b and the n-type high-concentration drain region 8b in the peripheral circuit NMOS region Rn is removed, and the first oxide film is formed only on the side wall of the gate electrode 15b. 13 are left to form side walls 13A. After that, resist 51
Is removed.

Next, as shown in FIG. 6C, the memory cell region Rc and the peripheral circuit NMOS region Rn are covered with a resist 52 by photolithography, and the resist 52, the gate electrode 15c and the gate electrode 15c are covered.
Using the first oxide film 13 on the side wall of the mask as a mask, a p-type high-concentration impurity such as boron B is implanted using BF ₂ ⁺ ions to form a p-type high-concentration source region 9 b and a p-type high-concentration drain region 10 b Is formed, and the drain region 10 of the peripheral circuit PMOS region Rp has an LDD structure.

Next, as shown in FIG.
Using 2 as a mask, anisotropic dry etching
The first oxide film 13 on the gate electrode 15c and the p-type high-concentration source region 9b and the p-type high-concentration drain region 10b in the peripheral circuit PMOS region Rp is removed, and the first oxide film is formed only on the side wall of the gate electrode 15c. 13
The side wall 13B is formed. Then, resist 5
Remove 2.

Next, as shown in FIG. 7A, a Ti film 53 is deposited on the entire surface of the substrate by sputtering, and is heat-treated by RTA. As a result, as shown in FIG. 7B, the TiSi ₂ film 11 is formed only on the high-concentration source / drain regions 7b, 8b, 9b, 10b in the peripheral circuit region Rs by silicidation. At this time, the low-concentration source / drain regions 5a and 6a in the memory cell region Rc
Since the first oxide film 13 is formed thereon, the RTA
The Ti film 53 and the Si substrate do not react during the heat treatment by the method, and no silicide film is formed. Then, FIG.
As shown in (2), the unreacted Ti film 53 and the TiN film formed on the surface of the Ti film 53 during the heat treatment by the RTA method are removed.

Thereafter, as in the first embodiment, a second oxide film 14 and a first interlayer insulating film 25a are formed on the entire surface of the substrate, and are planarized by the CMP method. The insulating film 22, the plate electrode 23, the bit line 24, the first layer wiring 27a and the like are formed.

In order to prevent the TiSi ₂ film 11 from aggregating and increasing the resistance, the process temperature after the formation of the TiSi ₂ film 11 needs to be 750 ° C. or less. Therefore, the second oxide film 14 and the first to fifth interlayer insulating films 2
The process temperature in the formation process and the planarization process of 5a to 25e is 750 ° C. or less, and the capacitance insulating film 22 is made of Ta.
It is assumed that the film can be formed at 750 ° C. or lower such as ₂ O ₅ or BST.

As described above, according to the method of manufacturing the semiconductor device according to the third embodiment of the present invention, the peripheral circuit region Rs
The first oxide film 13 in the peripheral circuit region Rs is dry-etched while the resists 51 and 52 used in the ion implantation for forming the high-concentration regions 7b, 8b, 9b and 10b are used as a mask, while the memory is The first oxide film 13 is left in the cell region Rc. Thereby, the source / drain regions 5, 6 of the memory cell region Rc
The TiSi ₂ film 11 can be formed on the source / drain regions 7, 8, 9, and 10 in the peripheral circuit region Rs without forming a silicide film thereon.

The gate electrode 15 in the peripheral circuit region Rs
Since the gate electrode 15a of the memory cell region Rc as well as the gate electrodes 15a and 15c are formed of the polycide film, the wiring resistance can be reduced.

Also, as in the first embodiment, the gate electrodes 3a, 3b, 3c are formed of a polycrystalline silicon film,
A Ti film 53 is formed thereon, and TiSi is formed by RTA.
_In the method of forming the _two films 11, the gate electrodes 3a, 3b,
When the wiring width of 3c is reduced, the TiSi ₂ film 11 aggregates and the wiring resistance increases. However,
As in the present embodiment, the gate electrodes 15a, 15b, 15
According to the method of forming a third oxide film 16 thereon using a polycide film formed by a CVD method or a sputtering method as c, the above problem does not occur and the gate is increased without increasing the wiring resistance. The electrodes 15a,
15b and 15c can be miniaturized.

(Fourth Embodiment) FIG. 8 is a sectional view showing a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention, showing a method of manufacturing the semiconductor device shown in FIG. .

First, a gate insulating film 4 and gate electrodes 3a, 3b, 3c made of polycrystalline silicon are formed on a p-type Si substrate 1 on which a p-type well region 1a, an n-type well region 1b and an element isolation insulating film 2 are formed. And then n in the memory cell region Rc and the peripheral circuit NMOS region Rn.
-Type low concentration source / drain regions 5a, 6a, 7a, 8a
And p-type low-concentration source / drain regions 9a, 10a are formed in the peripheral circuit PMOS region Rp, and a first oxide film 13 is formed on the entire surface of the substrate by LP.
It is formed by a CVD method.

Next, as shown in FIG. 8A, a memory cell region Rc and a peripheral circuit NMO as a peripheral circuit first conductivity type transistor region are formed by photolithography.
Resist 52 as first resist covering S region Rn
To form

Then, as shown in FIG. 8B, the first oxide film 13 in the peripheral circuit PMOS region Rp as the peripheral circuit second conductivity type transistor region is subjected to anisotropic dry etching using the resist 52 as a mask. Is removed, and is left only on the side wall of the gate electrode 3c.
Form 3B. Using the resist 52, the gate electrode 3c and the side wall 13B as a mask, p
High-concentration impurity such as boron B is implanted using BF ₂ ⁺ ions, and p-type high-concentration source / drain regions 9b and 10 are implanted.
b is formed. The peripheral circuit PMO thus formed
The drain region 10 in the S region Rp has an LDD structure. After that, the resist 52 is removed.

Next, as shown in FIG. 8C, a resist 51 as a second resist covering the memory cell region Rc and the peripheral circuit PMOS region Rp is formed by photolithography.

Next, as shown in FIG.
Using 1 as a mask, the first oxide film 13 in the peripheral circuit NMOS region Rn is removed by anisotropic dry etching and isotropic etching, and is left only on the side wall of the gate electrode 3b to form a side wall 13A. . The side wall 13A formed at this time is finished to a thickness different from that of the side wall 13B by isotropic etching. The isotropic etching may be either dry etching or wet etching.

Thereafter, using the resist 51, the gate electrode 3b and the side wall 13A as a mask, n-type high-concentration impurities, for example, arsenic As are ion-implanted to form n-type high-concentration source / drain regions 7b and 8b. The drain region 8 of the peripheral circuit NMOS region Rn thus formed
Has an LDD structure.

At this time, the side wall 13A of the gate electrode 3b in the peripheral circuit NMOS region Rn and the side wall 13B of the gate electrode 3c in the peripheral circuit PMOS region Rp have different thicknesses. The width of the lower n-type lightly doped drain region 8a in the gate length direction is equal to the peripheral circuit PMO.
The p-type low-concentration drain region 10a under the sidewall 13B in the S region Rp is formed so as to have a different width in the gate length direction. Thereafter, as shown in FIG. 8E, the resist 51 is removed.

Thereafter, as in the first embodiment, a Ti film 53 is deposited on the entire surface of the substrate, and TiS is deposited by RTA.
i ₂ film 11 is formed, unreacted Ti film 53 and RTA
Formed on the surface of the Ti film 53 during the heat treatment by the TiN method
Remove the film. After that, a second oxide film 14 and a first interlayer insulating film 25a are formed on the entire surface of the substrate, planarized by a CMP method, and the charge storage electrode 21 and the capacitor insulating film 2 are formed.
2, plate electrode 23, bit line 24, first layer wiring 27
a etc. are formed.

Here, in order to prevent the TiSi ₂ film 11 from aggregating and increasing the resistance, the process temperature after forming the TiSi ₂ film 11 needs to be 750 ° C. or less. Therefore, the second oxide film 14 and the first to fifth interlayer insulating films 2
The process temperature in the formation process and the planarization process of 5a to 25e is 750 ° C. or less, and the capacitance insulating film 22 is made of Ta.
It is assumed that the film can be formed at 750 ° C. or lower such as ₂ O ₅ or BST.

As described above, according to the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention, the peripheral circuit NMOS
In the region Rn and the peripheral circuit PMOS region Rp, the low-concentration drain regions 8a, 10b under the oxide film sidewalls 13A, 13B on the side walls of the respective gate electrodes 3b, 3c.
Since the width of “a” can be freely changed, an optimum width and an optimum LDD structure can be formed for each of the NMOS and PMOS transistors, so that high reliability in drain withstand voltage and the like can be realized.

In this embodiment, the sidewall is formed by anisotropic etching in the peripheral circuit PMOS region Rp, while the sidewall is formed by isotropic etching and anisotropic etching in the peripheral circuit NMOS region Rn. On the other hand, on the contrary, in the peripheral circuit PMOS region Rp, sidewalls are formed by isotropic etching and anisotropic etching,
Sidewalls may be formed in the peripheral circuit NMOS region Rn by anisotropic etching.

(Fifth Embodiment) FIG. 9 is a sectional view of a memory cell of a DRAM, which is a semiconductor device according to a fifth embodiment of the present invention, and its peripheral circuits. 9, the same components as those of the semiconductor device according to the first embodiment shown in FIG. 1 are denoted by the same reference numerals as those in FIG. In FIG. 9, 5b is an n-type high-concentration source region in the memory cell region Rc, 31 is a charge storage electrode, 32 is a capacitor insulating film, 33 is a plate electrode made of polycrystalline silicon, 34
Is a bit line, 35a to 35d are first to fourth interlayer insulating films, 36a and 36b are first and second contact plugs, 37a is a first layer wiring, and 37b is a second layer wiring.

According to the semiconductor device having the structure shown in FIG. 9, no silicide film is formed on the drain region 6 in contact with the charge storage electrode 31 in the memory cell region Rc. Leakage is as low as before, and pause time is as long as before.

On the other hand, TiS is formed on source / drain regions 7, 8, 9, 10 in peripheral circuit region Rs and on source region 5 in contact with bit line 34 in memory cell region Rc.
An i ₂ film 11 is formed. These source / drain regions 5, 7, 8, 9, and 10 are high-concentration regions 5b, 7b,
8B, 9B, and 10B, the junction depth is deeper than the drain region 6 of the memory cell region Rc including only the low concentration region 6a, and the width of the depletion layer on the source and drain sides is smaller. Therefore, there is no problem of junction leakage, and low resistance can be realized. Further, the peripheral circuit region R
Since the TiSi ₂ film 11 is also formed on the s gate electrodes 3b and 3c, the wiring resistance of the gate electrodes 3b and 3c can be reduced.

Since the TiSi ₂ film 11 is also formed on the plate electrode 33 made of polycrystalline silicon,
A reduction in the wiring resistance of the plate electrode 33 can also be realized.

Hereinafter, a method for manufacturing a semiconductor device according to the fifth embodiment of the present invention will be described with reference to the drawings.

FIG. 10 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the fifth embodiment of the present invention, which illustrates a method of manufacturing the semiconductor device shown in FIG.

First, a gate insulating film 4 and gate electrodes 3a, 3b, 3c made of polycrystalline silicon are formed on a p-type Si substrate 1 on which a p-type well region 1a, an n-type well region 1b and an element isolation insulating film 2 are formed. And then n in the memory cell region Rc and the peripheral circuit NMOS region Rn.
-Type low concentration source / drain regions 5a, 6a, 7a, 8a
And p-type low-concentration source / drain regions 9a, 10a are formed in the peripheral circuit PMOS region Rp, and a first oxide film 13 is formed on the entire surface of the substrate by LP.
It is formed by a CVD method.

Next, by photolithography, the memory cell region Rc and the peripheral circuit NMOS region Rn are covered with a resist, and the resist, the gate electrode 3c and the first oxide film 13 on the side wall thereof are used as a mask to form a p-type. High-concentration impurities such as boron B are implanted using BF ₂ ⁺ ions to form p-type high-concentration source / drain regions 9b and 10b. The drain region 10 in the peripheral circuit PMOS region Rp formed in this manner is located near the channel of the p-type high-concentration drain region 10b.
0a is provided.

Next, as shown in FIG. 10A, a resist 54 having a pattern in which the peripheral circuit NMOS region Rn and the source region of the memory cell region Rc are opened is formed by photolithography, and the resist 54 and the gate are formed. Using the electrodes 3a and 3b and the first oxide film 13 on the side walls thereof as a mask, n-type high-concentration impurities such as arsenic As are ion-implanted. Then, as shown in FIG. 10B, an n-type high-concentration source / drain region 7 is formed in the peripheral circuit NMOS region Rn.
b, 8b are formed. The drain region 8 in the peripheral circuit NMOS region Rn thus formed has an LDD structure in which the n-type low-concentration drain region 8a is provided near the channel of the n-type high-concentration drain region 8b. At this time, also in the memory cell region Rc, the bit line 3
The n-type high-concentration source region 5b is formed in the source region 5 which is in contact with 4.

Thereafter, a contact hole connected to the n-type low-concentration drain region 6a is formed in the memory cell region Rc, and the charge storage electrode 31 is formed. Next, a capacitor insulating film and a polycrystalline silicon film are formed, and heat treatment for activating impurities in the source and drain regions is performed at a process temperature of 850 ° C. for 30 minutes.

Thereafter, as shown in FIG. 10C, a predetermined region to be a plate electrode is covered with a plate electrode forming resist 55 by photolithography, and the polycrystalline silicon film and the capacitor insulating film are etched by dry etching. And the plate electrode 33 and the capacitance insulating film 3
Form 2 At this time, the resist 55 for forming the plate electrode forms the n of the charge storage electrode 31 and the memory cell region Rc.
The plate electrode 33 is not formed in the peripheral circuit region Rs, but is formed in the memory cell region Rc in the memory cell region Rc.
It is formed in a region excluding a contact region connecting the high-concentration source region 5b.

Then, as shown in FIG. 10D, the first oxide film 13 is removed using the plate electrode forming resist 55 or the plate electrode 33 as a mask. The first oxide film 13 left on the side walls of the gate electrodes 3b and 3c in the peripheral circuit region Rs causes the side walls 13A and 13A.
Form B. At this time, the first oxide film 13 is left under the plate electrode 33. After that, the plate electrode forming resist 55 is removed.

Next, as shown in FIG. 10E, a Ti film 56 as a refractory metal film is deposited on the entire surface of the substrate by a sputtering method, and is heat-treated by an RTA method. As a result, the gate electrodes 3b, 3c and the high concentration regions 7b, 8b, 9 in the peripheral circuit region Rs are formed by silicidation.
The TiSi ₂ film 11 is formed on the high concentration source region 5b which contacts the plate electrodes 33 and the bit line 34 to be formed later in the memory cell region Rc. At this time, since the first oxide film 13 and the plate electrode 33 are formed on the drain region 6 of the memory cell region Rc, the Ti film 56 does not react with the Si substrate during the heat treatment by the RTA method, and the silicide film Is not formed. Thereafter, the unreacted Ti film 56 and RT
Ti formed on the surface of the Ti film 56 during the heat treatment by the A method
The N film is removed.

Thereafter, although not shown, the second oxide film 14
Then, a first interlayer insulating film 35a is formed on the entire surface of the substrate, and is planarized by a CMP method. Next, the high concentration source region 5b of the memory cell region Rc and the peripheral circuit region Rs
High concentration source / drain regions 7b, 8b, 9b, 10
Then, a contact hole connected to b is opened, and a bit line 34 is formed.

After that, a second interlayer insulating film 35b is formed on the entire surface of the substrate, planarized by the CMP method, and the high-concentration source / drain regions 7b and 8 in the peripheral circuit region Rs are formed.
b, 9b, 10b or the contact holes connected to the gate electrodes 3b, 3c are opened.
a and the first layer wiring 37a are formed.

Thereafter, a third interlayer insulating film 35c is formed on the entire surface of the substrate, and is planarized by the CMP method.
A contact hole connected to the layer wiring 37a is opened, a second contact plug 36b and a second layer wiring 37b are formed, and a fourth interlayer insulating film 35d is formed on the entire surface.

As described above, according to the method of manufacturing the semiconductor device according to the fifth embodiment of the present invention, the plate electrode 33
Has a shape that covers the charge storage electrode 31 and the drain region 6 of the memory cell region Rc and excludes a contact region connected to the bit line 34 on the high-concentration source region 5b. The first oxide film 13 is dry-etched using the resist itself or the plate electrode forming resist 55 for forming the same as a mask to expose the Si substrate and the gate electrode made of polycrystalline silicon only in a desired region. By depositing the Ti film 56, the first oxide film 13 and the plate electrode 33 left on the side wall of the gate electrode are used as a mask, and the Ti film 56, the Si substrate, and the polycrystalline silicon are formed only in the desired region. Contact and react with the gate electrode to make Ti
An Si ₂ film 11 is formed. Thus, a silicide film is not formed on the drain region 6 of the memory cell region Rc, but on the gate electrodes 3b and 3c and the source / drain regions 7, 8, 9, and 10 of the peripheral circuit region Rs, and on the memory cell region Rs. The TiSi ₂ film 11 can be formed on the high-concentration source region 5b in contact with the bit line 34 in Rc.

Conventionally, only a low concentration layer is formed in the source region of the memory cell region Rc, so that the junction depth is small and the width of the depletion layer toward the source is large.
For this reason, if a low-resistance refractory metal or a silicide film used as a bit line material is directly contacted with the Si substrate, it reacts with the Si substrate by a later heat treatment or the like, thereby breaking the junction or reducing junction leakage. There was a problem of increasing.

In order to solve this problem, conventionally, Si
A method in which polycrystalline silicon that does not react with the substrate is formed as a contact plug, and a bit line made of a low-resistance refractory metal or a silicide film is formed thereon in a separate process,
A multilayer wiring (polycide or the like) of polycrystalline silicon and a low-resistance refractory metal or silicide film is formed as a bit line,
A method of contacting with a Si substrate via polycrystalline silicon on the lower layer side of the laminated wiring has been used.

However, according to the manufacturing method of this embodiment, the memory cell region Rc and the peripheral circuit region Rc are formed on the Si substrate and the gate electrode which are in contact with the bit line 34.
s together TiSi ₂ film 11 is formed, the TiSi ₂
In order for the film 11 to prevent the reaction between the bit line material and the Si substrate,
A stable contact can be realized, and a metal film of Ti, W, Al, etc., which has low resistance but reacts with Si, can be used as a bit line material as it is. Wiring can be realized.

Further, since the formation of the TiSi ₂ film 11 is performed after the formation of the capacitance insulating film 32, the film formation temperature (heat treatment) of the capacitance insulating film 32 does not affect the TiSi ₂ film 11 and does not cause aggregation or the like. . Therefore, a film having a high film forming temperature such as a laminated film of a SiO ₂ film and a Si ₃ N ₄ film conventionally used as a capacitor insulating film can be used as the capacitor insulating film in the present embodiment. High reliability and low manufacturing cost of the insulating film can be realized, and the effect is large.

Although a polycrystalline silicon film is used as the plate electrode 32, this does not involve an increase in the number of steps, and the TiSi ₂ film 11 is formed on the plate electrode 32. Its own resistance can be reduced, and the effect is great.

The heat treatment for activating the impurities in the source and drain regions is performed after the plate electrode is formed and before the Ti film 56 is formed.
Aggregation of the iSi ₂ film 11 does not occur, and a desired heat treatment can be applied. Furthermore, during this heat treatment, the source and drain regions are covered with the first oxide film 13 and the like and are not exposed, so that outward diffusion of impurities can be prevented, and the effect is large.

(Sixth Embodiment) The sixth embodiment of the present invention relates to a method for manufacturing the semiconductor device shown in FIG. 9, as in the fifth embodiment.

FIGS. 11 and 12 are sectional views showing a method of manufacturing the semiconductor device according to the sixth embodiment of the present invention, in which the method of manufacturing the semiconductor device shown in FIGS.

First, as shown in FIG. 11A, a gate insulating film 4 and polycrystalline silicon are formed on a p-type Si substrate 1 on which a p-type well region 1a, an n-type well region 1b and an element isolation insulating film 2 are formed. Gate electrodes 3a, 3b, 3c
Then, n-type low-concentration source / drain regions 5a, 6a, 7a, 8a are formed in the memory cell region Rc and the peripheral circuit NMOS region Rn, and p-type low-concentration source / drain regions are formed in the peripheral circuit PMOS region Rp. Regions 9a and 10a are formed, and a first oxide film 13 is formed on the entire surface of the substrate by LPCVD.

Thereafter, as shown in FIG. 11B, a contact hole connected to the drain region 6 of the memory cell region Rc is formed, and a charge storage electrode 31 is formed. Next, a capacitor insulating film and a polycrystalline silicon film are formed, a region to be a plate electrode is covered with a plate electrode forming resist 55 by a photolithography method, and the polycrystalline silicon film and the capacitor insulating film are etched by dry etching. The plate electrode 33 and the capacitance insulating film 32 are formed. At this time, the plate electrode forming resist 55 has a shape covering the charge storage electrode 31 and the drain region 6 of the memory cell region Rc, and the plate electrode 33 is not formed in the peripheral circuit region Rs.
It is formed in a region excluding a contact region connecting the bit line 34 to be formed later and the source region 5.

Next, as shown in FIG. 11C, the first oxide film 13 is removed using the plate electrode forming resist 55 or the plate electrode 33 as a mask. Peripheral circuit area R
The side walls 13A and 13B are formed by the first oxide film 13 left on the side walls of the s gate electrodes 3b and 3c. At this time, the first oxide film 13 is also left under the plate electrode 33.

Next, as shown in FIG. 11D, the peripheral circuit PMOS region Rp is covered with a resist 57 by photolithography, and the resist 57, the plate electrode 33, the gate electrode 3b, and the gate electrode 3b are formed. Using the side wall 13A as a mask, an n-type high-concentration impurity such as arsenic As is ion-implanted to form an n-type high-concentration source.
Drain regions 7b and 8b are formed. The drain region 8 of the peripheral circuit NMOS region Rn thus formed is
The LDD structure has a low concentration region 8a provided near the channel of the high concentration region 8b. At this time, also in the memory cell region Rc, a bit line 34 formed later is formed.
An n-type high-concentration source region 5b is formed in the source region 5 in contact with the substrate.

Next, after removing the resist 57, FIG.
As shown in (a), by photolithography,
The memory cell region Rc and the peripheral circuit NMOS region Rp are covered with a resist 58, and the resist 58 and the gate electrode 3 are covered.
c and the side wall 13B of the gate electrode 3c as a mask, p-type high-concentration impurities such as boron B
Implantation is performed using F ₂ ⁺ ions to form p-type high-concentration source / drain regions 9b and 10b. The drain region 10 of the peripheral circuit PMOS region Rp thus formed is
Similarly to the peripheral circuit NMOS region Rn, the high concentration region 10b
LDD provided with low concentration region 10a near the channel of
It has a structure.

Next, after removing the resist 58, FIG.
As shown in (b), a Ti film 56 is deposited on the entire surface of the substrate by sputtering, and is heat-treated by RTA.
As a result, due to the silicidation, the gate electrode 3b, 3c and the high concentration source / drain regions 7b, 8b, 9b, 10b in the peripheral circuit region Rs, the plate electrode 33 in the memory cell region Rc, and the bit line formed later The TiSi ₂ film 11 is formed on the high-concentration source region 5b in contact with. At this time,
Since the first oxide film 13 and the plate electrode 33 are formed on the low-concentration drain region 6a in the memory cell region Rc, the Ti film 56 and the Si substrate do not react during the heat treatment by the RTA method, and the silicide film is formed. Not formed. Thereafter, the unreacted Ti film 56 and the TiN film formed on the surface of the Ti film 56 during the heat treatment by the RTA method are removed.

Thereafter, although not shown, the second oxide film 14
Then, a first interlayer insulating film 35a is formed on the entire surface of the substrate, and is planarized by a CMP method. Next, the high concentration source region 5b of the memory cell region Rc and the peripheral circuit region Rs
High concentration source / drain regions 7b, 8b, 9b, 10
Then, a contact hole connected to b is opened, and a bit line 34 is formed.

Thereafter, a second interlayer insulating film 35b is formed on the entire surface of the substrate, planarized by the CMP method, and the high-concentration source / drain 7b, 8b, 9 in the peripheral circuit region Rs is formed.
A contact hole connected to the gate electrodes b, 10b or the gate electrodes 3b, 3c is opened, and a first contact plug 36a and a first layer wiring 37a are formed.

Thereafter, a third interlayer insulating film 35c is formed on the entire surface of the substrate, and is planarized by the CMP method.
A contact hole connected to the layer wiring 37a is opened, a second contact plug 36b and a second layer wiring 37b are formed, and a fourth interlayer insulating film 35d is formed on the entire surface.

As described above, according to the method of manufacturing the semiconductor device according to the sixth embodiment of the present invention, the plate electrode 33
Has a shape that covers the charge storage electrode 31 and the drain region 6 of the memory cell region Rc and excludes a contact region connected to the bit line 34 on the high-concentration source region 5b. The first oxide film 13 is dry-etched using the resist itself or the plate electrode forming resist 55 for forming the same as a mask to expose the Si substrate and the gate electrode made of polycrystalline silicon only in a desired region. By depositing the Ti film 56, the first oxide film 13 and the plate electrode 33 left on the side wall of the gate electrode are used as a mask, and the Ti film 56, the Si substrate, and the polycrystalline silicon are formed only in the desired region. Contact and react with the gate electrode to make Ti
An Si ₂ film 11 is formed. Thus, a silicide film is not formed on the drain region 6 of the memory cell region Rc, but on the gate electrodes 3b and 3c and the source / drain regions 7, 8, 9, and 10 of the peripheral circuit region Rs, and on the memory cell region Rs. The TiSi ₂ film 11 can be formed on the high-concentration source region 5b in contact with the bit line 34 in Rc.

The Si contacting the bit line 34
A TiSi ₂ film 11 is formed on both the memory cell region Rc and the peripheral circuit region Rs on the substrate and the gate electrode,
Since the TiSi ₂ film 11 prevents a reaction between the bit line material and the Si substrate, a stable contact can be realized, and a metal film of Ti, W, Al, etc., which has a low resistance but reacts with Si, is directly used as the bit line material. Therefore, the number of steps can be reduced, and a low-resistance contact and a low-resistance wiring can be realized.

Since the formation of the TiSi ₂ film 11 is performed after the formation of the capacitance insulating film 32, the film formation temperature (heat treatment) of the capacitance insulating film 32 does not affect the TiSi ₂ film 11 and aggregation does not occur. . Therefore, a film having a high film forming temperature such as a laminated film of a SiO ₂ film and a Si ₃ N ₄ film conventionally used as a capacitor insulating film can be used as the capacitor insulating film in the present embodiment. High reliability and low manufacturing cost of the insulating film can be realized, and the effect is large.

Although the polycrystalline silicon film is used as the plate electrode 32, this does not involve an increase in the number of steps, and the TiSi ₂ film 11 is formed on the plate electrode 32. Its own resistance can be reduced, and the effect is great.

The heat treatment for activating the impurities in the source and drain regions is performed after the plate electrode is formed and before the Ti film 56 is formed.
Aggregation of the iSi ₂ film 11 does not occur, and a desired heat treatment can be applied. Furthermore, during this heat treatment, the source and drain regions are covered with the first oxide film 13 and the like and are not exposed, so that outward diffusion of impurities can be prevented, and the effect is large.

Since the size of the n-type high-concentration source region 5b in the memory cell region Rc is fine, a resist mask for ion-implanting the n-type high-concentration impurity into the source region 5 is patterned by photolithography. In some cases, high precision was required for alignment and dimensions. However, in the present embodiment, since the plate electrode 33 formed earlier is used as it is as a mask for implanting n-type high-concentration impurity ions in the memory cell region Rc, there is no need to form a highly accurate resist mask pattern, so that the effect is large. .

(Seventh Embodiment) FIGS. 13 and 14 are sectional views in the order of steps in a method for manufacturing a semiconductor device according to a seventh embodiment of the present invention.

First, as shown in FIG. 13A, a plate electrode 33 and a capacitor insulating film 32 are formed according to the steps shown in FIGS. 11A and 11B of the sixth embodiment, and The resist 55 is removed.

Thereafter, as shown in FIG.
A third oxide film 41 as an insulating film is formed on the entire surface of the substrate. At this time, the third oxide film 41 is formed with a small thickness so as not to bury a contact hole between the bit line 34 to be formed later and the source region 5 of the memory cell region Rc.

Thereafter, as shown in FIG. 13C, the first oxide film 13 and the third oxide film 41 are removed by anisotropic etching. At this time, the first oxide film 13 is formed under the plate electrode 33 using the plate electrode 33 as a mask.
And the first oxide film 13 is left on the side walls of the gate electrodes 3b and 3c in the peripheral circuit region Rs to form the sidewall 13E. Further, the third oxide film 41 is formed on the side wall of the plate electrode 33 and the peripheral circuit region R.
The sidewalls 41A and 41B are formed by being left on the s gate electrodes 3b and 3c.

Thereafter, as shown in FIG. 13D, the peripheral circuit PMOS region Rp is formed by photolithography.
Is formed, the resist 57, the plate electrode 33, the side wall 41A formed on the side wall of the plate electrode 33, the gate electrode 3b and the side wall 13E formed on the side wall of the gate electrode 3b. Using the mask 41B as a mask, high-concentration source / drain regions 7b and 8b are formed in the peripheral circuit NMOS region Rn by ion-implanting n-type high-concentration impurities such as arsenic As. The peripheral circuit NMOS region Rn thus formed
The drain region 8 has an LDD structure in which a low concentration region 8b is provided near the channel of the high concentration region 8a.
In the memory cell region Rc, an n-type high-concentration source region 5b is also formed in the source region 5 in contact with a bit line 34 to be formed later.

Next, after removing the resist 57, FIG.
As shown in (a), by photolithography,
A resist 58 covering the memory cell region Rc and the peripheral circuit NMOS region Rn is formed, and the resist 57 and the gate electrode 3c are formed.
Using the side walls 13E and 41B formed on the side walls of the gate electrode 3c as a mask, a p-type high-concentration impurity such as boron B is implanted by using BF ₂ ⁺ ions.
High-concentration source / drain regions 9b and 10b are formed in the peripheral circuit PMOS region Rp. The drain region 10 of the peripheral circuit PMOS region Rp thus formed has an LDD structure in which a low-concentration region 10a is provided near the channel of the high-concentration region 10b, similarly to the drain region 8 of the peripheral circuit NMOS region Rn. ing.

Next, after removing the resist 58, FIG.
As shown in (b), a Ti film 56 is deposited on the entire surface of the substrate by sputtering, and is heat-treated by RTA.
As a result, the gate electrodes 3b and 3c and the high concentration regions 7b and 8 in the peripheral circuit region Rs are formed by silicidation.
b, 9b, and 10b, the plate electrode 33 in the memory cell region Rc, and the bit line 3 to be formed later.
TiS on the high-concentration source region 5b in contact with
An i ₂ film 11 is formed. At this time, the plate electrode 33
Since the sidewall 41A of the oxide film is formed on the side wall portion, the TiSi ₂ film 11 is not formed. At this time, since the first oxide film 13 and the plate electrode 33 are formed on the drain region 6 of the memory cell region Rc, the Ti film 58 and the Si film are not heat-treated by the RTA method.
It does not react with the substrate and no silicide film is formed. Thereafter, the unreacted Ti film 58 and the TiN film formed on the surface of the Ti film 58 during the heat treatment by the RTA method are removed.

Thereafter, a second oxide film 14 and a first interlayer insulating film 35a are formed on the entire surface of the substrate, and are planarized by the CMP method. Next, a contact hole connecting to the high-concentration source region 5b of the memory cell region Rc and the high-concentration source / drain regions 7b, 8b, 9b, 10b of the peripheral circuit region Rs is opened, and the bit line 34 is formed. Thereafter, a second interlayer insulating film 35b is formed on the entire surface of the substrate,
The planarization is performed by the CMP method, and the high concentration source / drain regions 7b, 8b, 9b, 1 in the peripheral circuit region Rs are formed.
0b or a contact hole connected to the gate electrodes 3b and 3c is opened.
The layer wiring 37a is formed. After that, the third interlayer insulating film 3
5c is formed on the entire surface of the substrate, planarized by a CMP method, a contact hole connected to the first-layer wiring 37a is opened, a second contact plug 36b and a second-layer wiring 37b are formed, and the entire surface is formed. The fourth interlayer insulating film 35
forming d.

Here, as shown in FIG. 15A, the plate electrode 33 has a structure that covers the entire charge storage electrode 31. However, miniaturization has progressed and misalignment of photolithography at the time of forming the plate electrode 33 has occurred. If the dimensional deviation or the dimensional deviation during etching cannot be sufficiently controlled within an allowable range, as shown in FIG. 15B, the end of the plate electrode 33 is flush with the end of the charge storage electrode 31, There is a case where it is closer to the drain region than the end of the storage electrode 31.

In this case, since the underlying charge storage electrode 31 is also etched during the dry etching of the plate electrode 33, the charge storage electrode 31 is exposed below the plate electrode 33. If the Ti film 56 is formed as it is in this state, the exposed portion of the charge storage electrode 31 contacts the Ti film 56 as shown in FIG.
After that, when the heat treatment by the RTA method is performed, the plate electrode 3
3 on the surface of TiS by a silicidation reaction with the Ti film 56.
The i ₂ film 11 is formed. At the same time, a silicidation reaction occurs between the exposed portion of the charge storage electrode 31 and the Ti film 56, and the TiSi ₂ film 11 is formed also in this portion.
In this silicidation reaction, the silicon atoms of the polycrystalline silicon diffuse to the Ti film 56 side, so that the TiSi ₂ film 11 travels along the Ti film 56 and rises. Here, since the thickness of the capacitor insulating film 32 is as thin as about 1 to 20 nm, FIG.
As shown in (c), will be a TiSi ₂ film 11 formed on the TiSi ₂ film 11 and the plate electrode 33 crawls up from the charge storage electrode 31 side come into contact on the capacitor insulating film 32, The capacitance insulating film 32 does not function as a capacitance.

However, in the method of manufacturing a semiconductor device according to the present embodiment, after the plate electrode 33 is formed, the side wall 41A of the oxide film is formed on the side wall of the plate electrode 33, as shown in FIG. If the charge storage electrode 31 is misaligned due to misalignment of photolithography, etc.
Is exposed, a sidewall 41A of an oxide film is also formed on the exposed side wall of the charge storage electrode 31. Therefore, as shown in FIG. 16B, the Ti film 56 does not directly contact the charge storage electrode 31 when the Ti film 56 is deposited. Therefore, as shown in FIG.
The problem that the capacitance insulating film 32 does not function as a capacitance as described above does not occur, and only the T
Since the iSi ₂ film 11 is formed, the same effect as in the sixth embodiment can be obtained reliably.

[0159]

As described above, according to the semiconductor device of the present invention, the refractory metal silicide film or the refractory metal film is formed on the source / drain region of the peripheral circuit region, while the memory cell region is formed. Since the refractory metal silicide film and refractory metal film are not formed on the drain region connected to the charge storage electrode, the pause time is maintained as long as before, and the sheet of the source / drain region is maintained. Higher speed and lower power consumption can be achieved by lowering the resistance.

Further, according to the method of manufacturing a semiconductor device according to the present invention, the insulating film formed on the semiconductor substrate can be formed by resist or charge used for ion implantation for forming source / drain regions in the peripheral circuit region. The surface of the semiconductor substrate in the peripheral circuit region is exposed by etching using the plate electrode covering the storage electrode and the drain region connected to the charge storage electrode as a mask, thereby forming a high melting point metal silicide film or a high melting point metal film. Is formed, the semiconductor device as described above can be manufactured in a small number of steps.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A to 2D are cross-sectional views in the order of steps in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIGS. 3A to 3C are cross-sectional views in the order of steps in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIGS. 4A and 4B are cross-sectional views in the order of steps in a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

FIGS. 6A to 6D are cross-sectional views in the order of steps in a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIGS. 7A to 7C are cross-sectional views in the order of steps in a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIGS. 8A to 8E are cross-sectional views in the order of steps in a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 9 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.

FIGS. 10A to 10E are cross-sectional views in the order of steps in a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

FIGS. 11A to 11D are cross-sectional views in a process order in a method for manufacturing a semiconductor device according to a sixth embodiment of the present invention.

12A and 12B are cross-sectional views in a process order in a method for manufacturing a semiconductor device according to a sixth embodiment of the present invention.

13A to 13D are cross-sectional views in a process order in a method for manufacturing a semiconductor device according to a seventh embodiment of the present invention.

14A and 14B are cross-sectional views in the order of steps in a method for manufacturing a semiconductor device according to a seventh embodiment of the present invention.

FIGS. 15A to 15C are enlarged cross-sectional views showing a silicidation process when a side wall of a charge storage electrode is exposed during dry etching of a plate electrode when no side wall is formed on the plate electrode.

FIGS. 16A to 16C are enlarged cross-sectional views showing a silicidation process when a side wall of a charge storage electrode is exposed during dry etching of a plate electrode when a side wall is formed on the plate electrode.

FIG. 17 is a cross-sectional view of a conventional semiconductor device.

FIG. 18 is a cross-sectional view when a salicide technique is applied to a conventional semiconductor device as it is.

FIGS. 19A to 19D are cross-sectional views in the order of steps in the case where the salicide technique is applied to a conventional semiconductor device as it is.

20 (a) and (b) are cross-sectional views in the order of steps in the case where the salicide technique is applied to a conventional semiconductor device as it is.

[Explanation of symbols]

Rc memory cell region Rs peripheral circuit region Rn peripheral circuit NMOS region (peripheral circuit first conductivity type transistor region) Rp peripheral circuit PMOS region (peripheral circuit second conductivity type transistor region) 1 semiconductor substrate 3a, 3b, 3c gate electrode 5 memory Source region in cell region Rc 6 Drain region in memory cell region Rc 7 Source region in peripheral circuit NMOS region Rn 8 Drain region in peripheral circuit NMOS region Rn 9 Source region in peripheral circuit PMOS region Rp 10 Drain region in peripheral circuit PMOS region Rp Reference Signs List 11 TiSi ₂ film (silicide film of high melting point metal) 12 W film (high melting point metal film) 13 First oxide film (insulating film) 13A, 13B Side walls 15a, 15b, 15c Gate electrode 21, 31 Charge storage electrode 32 Capacity Film 33 Plate electrode 34 Bit line 41 Third oxide film (second insulating film) 41A Side wall 51 Resist (second resist) 52 Resist (first resist) 53, 56 Ti film (high melting point metal film) 55 Plate electrode forming resist

Claims (16)

[Claims] 1. A semiconductor device provided with a memory cell and a peripheral circuit both having a MOS structure on a semiconductor substrate, wherein a charge storage electrode connected to a drain region is formed in a memory cell region. A high-melting-point metal silicide film or a high-melting-point metal film is formed on the source / drain regions in the peripheral circuit region, while a high-melting-point metal is formed on the drain region connected to the charge storage electrode in the memory cell region. Wherein the silicide film and the refractory metal film are not provided. 2. The semiconductor device according to claim 1, wherein a silicide film or a high-melting-point metal film of said high-melting-point metal is formed on a gate electrode in a peripheral circuit region. 3. The semiconductor device according to claim 1, wherein the gate electrode in the peripheral circuit region has a laminated structure of a polycrystalline silicon film and a refractory metal silicide film or a refractory metal film. Semiconductor device. 4. The semiconductor device according to claim 1, wherein in the memory cell region, the charge storage electrode and a drain region connected to the charge storage electrode are covered.
A semiconductor device, comprising: a plate electrode; and a refractory metal silicide film or a refractory metal film formed on the plate electrode. 5. The semiconductor device according to claim 1, wherein a bit line connected to a source region is formed in the memory cell region, and the high melting point metal is formed on the source region connected to the bit line. A semiconductor device comprising a silicide film or the refractory metal film formed thereon. 6. A method of manufacturing a semiconductor device in which a memory cell and a peripheral circuit both having a MOS structure are provided on a semiconductor substrate, the method comprising: forming a gate electrode on the semiconductor substrate; Forming a drain region on the surface of the memory cell region of the semiconductor substrate; forming an insulating film on the semiconductor substrate; forming a resist covering the memory cell region on the semiconductor substrate; Forming a source / drain region on the surface of a semiconductor substrate by ion implantation using the resist and a gate electrode as a mask, etching the insulating film using the resist as a mask, and removing the resist; and A peripheral circuit in which a refractory metal film is formed on a substrate and heat-treated, and the insulating film is not left Forming a silicide film of the refractory metal on a source / drain region in a region, and forming a charge storage electrode connected to the drain region in a memory cell region. A method for manufacturing a semiconductor device. 7. The method of manufacturing a semiconductor device according to claim 6, wherein, instead of the step of forming a silicide film of a high melting point metal, the step of forming a silicide film on the source / drain region in the peripheral circuit region where the insulating film is not left. By selective chemical vapor deposition,
A method for manufacturing a semiconductor device, comprising a step of forming a high melting point metal film. 8. The method of manufacturing a semiconductor device according to claim 6, wherein said gate electrode is made of a polycrystalline silicon film, and said insulating film is not left when forming a refractory metal silicide film. A method for manufacturing a semiconductor device, wherein a silicide film of the refractory metal is formed thereon. 9. The method of manufacturing a semiconductor device according to claim 6, wherein the gate electrode has a laminated structure of a polycrystalline silicon film and a high melting point metal silicide film or a high melting point metal film,
A method of manufacturing a semiconductor device, comprising forming an insulating film on a gate electrode when forming the gate electrode. 10. The method of manufacturing a semiconductor device according to claim 6, wherein the step of forming a source / drain region in a peripheral circuit region and etching the insulating film comprises: forming a memory cell region and a peripheral circuit first on a semiconductor substrate. Forming a first resist covering the conductive transistor region, anisotropically etching the insulating film, and leaving the insulating film on the side wall of the gate electrode in the peripheral circuit second conductive transistor region to form a side resist; Forming a source / drain region on the surface of the semiconductor substrate by ion implantation using the first resist and a gate electrode as a mask in the peripheral circuit second conductivity type transistor region; Removing the memory cell region and the peripheral circuit second conductivity type transistor region on the semiconductor substrate. A second resist is formed to cover the insulating film, and the insulating film is isotropically and anisotropically etched to leave the insulating film on the side wall of the gate electrode in the peripheral circuit first conductivity type transistor region. Forming a source / drain region on the surface of the semiconductor substrate by ion implantation using the second resist and the gate electrode as a mask in the peripheral circuit first conductivity type transistor region; and forming the second resist A method of manufacturing a semiconductor device, comprising: 11. A semiconductor device manufacturing method for manufacturing a semiconductor device in which a memory cell and a peripheral circuit both having a MOS structure are provided on a semiconductor substrate, comprising: a step of forming a gate electrode on the semiconductor substrate; Forming a drain region on a surface of a memory cell region of the semiconductor substrate; forming an insulating film on the semiconductor substrate; forming a charge storage electrode connected to the drain region in the memory cell region on the insulating film; Forming a capacitor insulating film and a conductive film on the semiconductor substrate;
A resist for forming a plate electrode covering a predetermined area in the memory cell region is formed on the conductive film, the conductive film is etched using the resist for forming the plate electrode as a mask, and the charge storage electrode and the charge storage electrode are etched. Forming a plate electrode that covers the drain region connected to the semiconductor substrate via a capacitor insulating film; etching the insulating film using the plate electrode forming resist or the plate electrode as a mask; and Forming a high-melting-point metal film and performing a heat treatment to form a silicide film of the high-melting-point metal on source / drain regions in a peripheral circuit region where the insulating film is not left. Manufacturing method of a semiconductor device. 12. The method for manufacturing a semiconductor device according to claim 11, wherein before forming the silicide film of the refractory metal, a source electrode is formed on the surface of the semiconductor substrate by ion implantation using the plate electrode and the gate electrode as a mask. A method for manufacturing a semiconductor device, comprising a step of forming a drain region. 13. The method for manufacturing a semiconductor device according to claim 11, wherein the plate electrode is formed in a memory cell region so as to avoid over a source region connected to a bit line. A method of manufacturing a semiconductor device, comprising: forming a silicide film of the refractory metal on a source region connected to the bit line in a memory cell region. 14. The method for manufacturing a semiconductor device according to claim 11, wherein said gate electrode is made of a polycrystalline silicon film, and said silicide film of said high melting point metal is formed on said gate electrode when said silicide film is formed. A method for manufacturing a semiconductor device, characterized by being formed. 15. The method of manufacturing a semiconductor device according to claim 11, wherein said conductive film is made of a polycrystalline silicon film, and said high conductive film is formed on a plate electrode formed of said conductive film when said silicide film is formed. A method for manufacturing a semiconductor device, comprising forming a silicide film of a melting point metal. 16. The method of manufacturing a semiconductor device according to claim 11, wherein, in the step of etching the insulating film, the resist for forming a plate electrode is removed before etching the insulating film. Forming an insulating film, and etching the second insulating film together with the insulating film;
Forming a side wall by leaving the second insulating film on a side wall of the plate electrode.