JP2007201370A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a drive current by strengthening a stress to be applied to a channel region. <P>SOLUTION: Gate electrodes 15, 25 and side walls 16, 26 are formed on a silicon substrate 1, dummy gate patterns 6, 7 are formed so as to cover the upper surfaces of gate electrodes 15, 25 and one part the upper surfaces of the side walls 16, 26, and a stress control insulating film 8 for covering the surface thereof is formed. The application of the stress of the insulating film 8 from above the dummy gate patterns 6, 7 can strengthen the stress in the same way as in a case where the gate electrodes 15, 25 are increased in height. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a gate length of 100 nm or less and a manufacturing method thereof.

  With the progress of miniaturization of semiconductor devices, development of 65 nm node processes and 45 nm node processes has become an urgent task. It has been found that the mobility of electrons and holes in the channel region is greatly affected by the stress applied to the channel region of the MOSFET with the miniaturization of the element. Utilizing this, a technique for improving the drive current by coating a MOSFET with a silicon nitride film (SiN) having a high stress in the film and applying an appropriate stress to the MOSFET has been studied. For example, Patent Document 1 discloses that SiN having compressive stress is used for a p-channel MOSFET and SiN having tensile stress is used for an n-channel MOSFET to increase the drive current.

  FIG. 15 is a cross-sectional view of a conventional semiconductor device described in Patent Document 1. In FIG. On the silicon substrate 1, a p-channel MOSFET 10 and an n-channel MOSFET 20 separated by element isolation 2 are formed.

  The p-channel MOSFET 10 includes an n-well 11, p-type source / drain regions 12 and 13, a gate insulating film 14, a gate electrode 15, and sidewalls 16 formed on a silicon substrate 1. A silicide layer 17 is formed on the surface 13. The upper surface is mainly made of SiN and is covered with a stress control insulating film 19 having compressive stress.

  On the other hand, the n-channel MOSFET 20 has a p-well 21, n-type source / drain regions 22, 23, a gate insulating film 24, a gate electrode 25, and sidewalls 26 formed on the silicon substrate 1. A silicide layer 27 is formed on the surface of the drain region 23. The upper surface is mainly made of SiN and is covered with a stress control insulating film 29 having a tensile stress.

  Patent Document 1 describes that the drive current of the p-channel MOSFET 10 increases due to compressive stress and decreases due to tensile stress. On the other hand, it is described that the drive current of the n-channel MOSFET 20 increases with tensile stress and decreases with compressive stress.

  Non-Patent Document 1 discloses that the stress on the surface of the channel region of an NMOSFET having a gate length of 45 nm varies with the height of the polysilicon gate and the thickness of the SiN film. FIG. 16 shows the structure of a conventional NMOSFET 30 described in Non-Patent Document 1. On the silicon substrate 1, a gate insulating film, a polysilicon gate 31, and sidewalls 32 (not shown) are formed, and a SiN cap layer 33 is provided as a whole.

  FIG. 17 is a graph showing the result of examining the stress on the surface of the channel region for the NMOSFET 30. It is shown that the tensile stress (Tensil Strain) on the surface of the channel region tends to increase as the polysilicon gate 31 increases in height and the thickness of the SiN cap layer 33 increases. On the other hand, the compressive stress tends to increase as the thickness of the SiN cap layer 33 increases. However, the tensile stress increases significantly with respect to the height of the polysilicon gate 31. Not shown.

FIG. 18 is a graph showing the _IDSAT improvement rate with respect to the thickness of the SiN cap layer 33 having compressive stress for the NMOSFET 30. It is shown that the current drive capability _IDSAT improves as the thickness of the SiN cap layer 33 increases, but is saturated at 80 nm or more. In other words, _{I DSAT} of NMOSFET30 the compressive stress is high it can be seen that there is a tendency to be improved to some extent.
JP 2003-86708 A S. Pidin et al. “MOSFET Current Drive Optimization Using Silicon Nitride Coupling Layer for 65-nm Technology Node” 2004 Symposium on VLSI Technology Dielectric Technology

  At a gate length of 100 nm or less, it is considered that by applying an optimal stress to the MOSFET, the mobility of the channel region can be improved and the drive current can be increased. According to the above-described method, the stress is applied to the MOSFET by covering the MOSFET with the SiN film having the film stress. In order to further improve the drive current, it is necessary to further increase the film stress of the SiN film. However, the above-described conventional technique has a limit in increasing the drive current. The reason is described below.

According to Non-Patent Document 1, as shown in Figure 18, when the thickness of the SiN cap layer 33 is equal to or higher than a certain degree _{I DSAT} improvement rate _(I DSAT Improvement) is saturated, the SiN cap layer 33 It has been suggested that there is a limit to improving the drive current only by increasing the thickness. Further, according to this document, as shown in FIG. 17, the tensile stress increases as the height of the polysilicon gate 31 increases. Whether or not the drive current is improved at this time is not shown, but there is a possibility that the drive current can be improved by increasing the height of the polysilicon gate 31. However, as the gate length becomes as fine as 65 nm, 45 nm or less, the height of the polysilicon gate 31 must be lowered in order to process with high dimensional accuracy. This is because the processing accuracy and the aspect ratio are in a trade-off relationship, and the trade-off becomes stronger as the gate length becomes finer. Therefore, as the gate length becomes finer, the effect of improving the drive current by the SiN cap layer 33 becomes smaller.

  In Patent Document 1, the stress control films 19 and 29 are formed by chemical vapor deposition (CVD) or sputtering. In order to further increase the film stress of the SiN film, it is conceivable to raise the film formation temperature. However, in a fine LSI, a shallow junction or silicide electrode that is vulnerable to heat is essential. Therefore, even if the deposition temperature of the SiN film is raised, it must be suppressed to 400 to 500 ° C. or less, and the obtained film stress has a limit.

  In the present invention, a gate electrode and a sidewall are formed on a semiconductor substrate, a dummy gate pattern is formed so as to cover the upper surface of the gate electrode and a part of the upper surface of the sidewall, and the surface of the dummy gate pattern and the sidewall This is characterized by the formation of a stress-controlling insulating film that covers the film. The stress control insulating film is preferably a SiN film that can obtain a large film stress. By providing the dummy gate pattern on the gate electrode and the sidewall, the aspect ratio of the gate electrode can be increased in a pseudo manner. Since the dummy gate pattern is formed so that the edges are positioned on the sidewalls on both sides, the processing accuracy is not as high as that of the gate electrode. Therefore, it is easier to artificially increase the height of the gate electrode using the dummy gate pattern than to increase the height of the gate electrode itself.

  According to the present invention, it is possible to easily increase the stress applied to the channel region as compared with the conventional case, so that the drive current can be further improved. This is because by forming the dummy gate pattern, the stress of the stress control insulating film is applied from above the dummy gate pattern, so that the stress can be increased as in the case where the gate electrode is raised.

  Hereinafter, by forming a dummy gate pattern on the gate electrode, the stress on the channel region is increased by artificially increasing the aspect ratio of the gate electrode, and an embodiment of the semiconductor device of the present invention that improves the drive current, This will be described with reference to the drawings.

  1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. A p-channel MOSFET 40 and an n-channel MOSFET 50 separated by element isolation 2 are formed on the silicon substrate 1.

  The p-channel MOSFET 40 includes an n-well 11, a p-type source / drain region 4, a gate insulating film 14, a gate electrode 15, and sidewalls 16. The surface of the gate electrode 15 and the p-type source / drain region 4 is formed. A silicide layer 17 is formed on the substrate. Hereinafter, for simplicity, the gate electrode 15 and the silicide layer 17 are referred to as the gate electrode 15.

  A p-well 21, an n-type source / drain region 5, a gate insulating film 24, a gate electrode 25, and a sidewall 26 are formed in the n-channel MOSFET 50, and on the surface of the gate electrode 25 and the n-type source / drain region 5 A silicide layer 27 is formed. Hereinafter, for simplicity, the gate electrode 25 and the silicide layer 27 are referred to as the gate electrode 25.

  In the p-channel MOSFET 40, a dummy gate pattern 6 is formed so as to cover a part of the upper surface of the gate electrode 15 and the upper surface of the sidewall 16. On the other hand, in the n-channel MOSFET 50, the dummy gate pattern 7 is formed so as to cover a part of the upper surface of the gate electrode 25 and the upper surface of the sidewall 26. As the material of the dummy gate patterns 6 and 7, an insulating film such as a silicon oxide film or a SiN film, polysilicon, or the like can be used. The dummy gate patterns 6 and 7 do not need to have a film stress. The whole is covered with a stress control insulating film 8 having a tensile stress, and a stress is applied to the channel region of each MOSFET. A SiN film is effective for the stress control insulating film 8. The stress control insulating film 8 can be formed by a CVD method or a sputtering method as in Patent Document 1, and a plasma CVD method is preferably used because of easy control. Further, the whole is covered with an interlayer insulating film 3, and a semiconductor device is formed in the same manner as a normal LSI.

  For example, the gate electrode 15 has a gate length of 10 to 150 nm, the gate electrode 15 has a height of 50 to 200 nm, the sidewalls 16 and 26 have a width of 40 to 100 nm, and the dummy gate patterns 6 and 7 have a width of The height of the dummy gate patterns 6 and 7 is 20 to 100 nm, and the thickness of the stress control insulating film 8 is 20 to 100 nm. The pseudo aspect ratio of the gate electrode is 0.5 to 2.0, which is the height of the gate electrode 15 and the dummy gate pattern 6 with respect to the width of the sidewalls 16 and 26 and the gate electrode 15. In addition, a numerical value is an example and is not restricted to these.

  Here, the influence of stress on the p-channel MOSFET 40 and the n-channel MOSFET 50 will be described. FIG. 2 is a perspective view for explaining a stress direction in which the drive current is improved. The left is a p-channel MOSFET 40 and the right is an n-channel MOSFET 50. In both cases, a drive current is applied when a stress (tensile stress) is applied in the extending direction relative to the gate width direction (X direction) and a downward stress (compressive stress) is applied in the height direction (Z direction) of the gate electrode. Will increase. On the other hand, in the gate length direction (Y direction), in the case of the p-channel MOSFET 40, the drive current increases when stress in the extending direction (compressive stress) is applied, and in the case of the n-channel MOSFET 50, the stress in the reverse contraction direction. The drive current increases when (compressive stress) is applied.

  For the n-channel MOSFET 50, the effect of increasing the drive current in all directions can be obtained by forming a stress control insulating film having a tensile stress. On the other hand, for the p-channel MOSFET 40, the effect is canceled in the gate width direction (X direction), the height direction of the gate electrode (Z direction), and the gate length direction (Y direction). The increase in drive current cannot be expected. Since the influence of stress in the gate length direction (Y direction) is greater than in other directions, it is better to form a stress control insulating film having a compressive stress if the maximum effect of increasing the drive current is to be obtained.

  The structure of FIG. 1 shows an example in which a stress control insulating film 8 having a tensile stress is formed. Although the drive current of the p-channel MOSFET 40 is slightly sacrificed, the drive current of the n-channel MOSFET 50 is improved and the stress control insulating film 8 is made a single unit, thereby reducing the cost.

  According to the first embodiment, the drive current can be improved by providing the dummy gate pattern and artificially increasing the height of the gate electrode. This is particularly effective when the gate length of the gate electrode is 10 to 150 nm. Further, when the ratio (aspect ratio) between the gate length and the total height of the gate electrode and the dummy gate pattern is set to 2 to 15, this is particularly effective.

  Here, if the dummy gate pattern is made higher, even if the height of the gate electrode is lowered by that amount, it is possible to obtain a further effect that the drive current can be maintained without reducing the stress. That is, the height of the gate electrode can be reduced without reducing the drive current. If the height of the gate electrode can be reduced, a finer gate length can be realized without developing an advanced processing apparatus. Therefore, miniaturization of the MOSFET can be promoted, and a higher performance device can be realized. In other words, by using the technical idea of the present invention, device design that maximizes stress and obtains drive current and device design that improves MOSFET performance by further miniaturizing the gate electrode without damaging the stress This will greatly contribute to the improvement of the degree of freedom in device design.

  Next, the manufacturing method of the semiconductor device of Example 1 mentioned above is demonstrated using drawing. First, as shown in FIG. 3, on a silicon substrate 1, an element isolation 2, an n-well 11 of a p-channel MOSFET 40, a p-type source / drain region 4, a gate insulating film 14, a gate electrode 15, sidewalls 16 and The silicide layer 17, the p-well 21 of the n-channel MOSFET 50, the n-type source / drain region 5, the gate insulating film 24, the gate electrode 25, the sidewall 26 and the silicide layer 17 are formed. These can be formed using conventional methods.

  Next, as shown in FIG. 4, a dummy gate formation film 34 is formed on the entire surface. As the dummy gate formation film 34, various insulating films such as a silicon oxide film, a SiN film, and a SiON film, polysilicon, and the like can be used. The dummy gate formation film 34 does not need to have a film stress. Since the dummy gate formation film 34 is processed into the dummy gate patterns 6 and 7 by using dry etching, if inconvenience occurs when the underlying sidewalls 16 and 26 are etched, contact with the underlying sidewalls 16 and 26 is achieved. It is recommended to select a material that can provide an etching selectivity.

  Next, as shown in FIG. 5, dummy gate resists 35 and 36 are formed on the gate electrodes 15 and 25 and the sidewalls 16 and 26 with a photoresist. The dummy gate resists 35 and 36 may be formed by alignment exposure and designed so that the edge comes near the center of the sidewalls 16 and 26.

  Next, as shown in FIG. 6, using the dummy gate resists 35 and 36 as a mask, the dummy gate formation film 34 is processed by dry etching to form dummy gate patterns 6 and 7. The dummy gate patterns 6 and 7 are formed so as to cover the upper surfaces of the gate electrodes 15 and 25 and a part of the upper surfaces of the dummy gate patterns 6 and 7. Ideally, the centers of the dummy gate patterns 6 and 7 and the centers of the gate electrodes 15 and 25 are ideal, but some misalignment can be allowed, and the dummy gate pattern only needs to cover the gate electrode.

  Next, as shown in FIG. 7, a stress control insulating film 8 is formed. In order to prevent the deposition temperature from exceeding 400 to 500 ° C., a plasma CVD method or a sputtering method is preferably used. The plasma CVD method is superior in terms of coverage. The stress is controlled by controlling the pressure and the gas flow rate as in the known technique.

  Thereafter, an interlayer insulating film 3 is formed (see FIG. 1). Thereafter, a semiconductor device is formed in the same manner as a normal LSI.

  The second embodiment is an embodiment in which compressive stress is applied to the p-channel MOSFET 60 and tensile stress is applied to the n-channel MOSFET 70. FIG. 8 is a sectional view of the semiconductor device according to the second embodiment of the present invention. The p-channel MOSFET 60 has an n-well 11, a p-type source / drain region 4, a gate insulating film 14, a gate electrode 15, a sidewall 16 and a silicide layer 17, and the n-channel MOSFET 70 has a p-well 21. The process up to the point where the n-type source / drain region 5, the gate insulating film 24, the gate electrode 25, the sidewall 26 and the silicide layer 27 are formed is the same as in the first embodiment.

In the p-channel MOSFET 60, a tensile stress control insulating film 41 and an insulating film 42 having the same shape are formed so as to cover a part of the upper surface of the gate electrode 15 and the upper surface of the sidewall 16, and the dummy gate pattern 6 functions. Here, since the tensile stress control insulating film 41 to be the dummy gate pattern 6 does not cover the entire p-channel MOSFET 60, the tensile stress caused by this hardly affects. Although the insulating film 42 is not essential, the provision of the insulating film 42 has an effect that the pseudo height of the gate electrode 15 of the p-channel MOSFET 60 can be increased. The insulating film 42 can also be used as an etching stopper when the compressive stress control insulating film 43 is removed from the n-channel MOSFET 70 as will be described later. A compressive stress control insulating film 43 is formed so as to cover the p-type source / drain regions 4, the sidewalls 16, and the dummy gate patterns 6. Therefore, compressive stress is applied to the p-channel MOSFET 60.

  On the other hand, in the n-channel MOSFET 70, a tensile stress control insulating film 41 and an insulating film 42 are formed so as to cover the n-type source / drain region 5, the gate electrode 25, and the sidewall 26. The compressive stress control insulating film 43 is not formed. Then, the whole is covered with an interlayer insulating film 3, and a semiconductor device is formed in the same manner as a normal LSI. Accordingly, a tensile stress is applied to the n-channel MOSFET 70.

  In the second embodiment, the height of the gate electrode 25 is not increased in a pseudo manner for the n-channel MOSFET 70, but the p-channel MOSFET 60 is formed by using the tensile stress control insulating film 41 for the dummy gate pattern 6. This shows a practical structure in which a structure for applying a tensile stress to the n-channel MOSFET 70 while increasing the applied compressive stress is formed by a small number of processes. Of course, the height of the gate electrode 25 can be increased in a pseudo manner in the n-channel MOSFET 70 as well. At that time, after providing the dummy gates 6 and 7 as in the first embodiment, the compressive stress control insulating film 43 is formed on the p-channel MOSFET 60, and the tensile stress control insulating film 41 is formed on the n-channel MOSFET 70. The method of doing is conceivable.

  Next, the manufacturing method of the semiconductor device of Example 2 mentioned above is demonstrated using drawing. The structure up to FIG. 9 is the same as that of the first embodiment. Next, as shown in FIG. 10, a tensile stress control insulating film 41 and an insulating film 42 are formed on the entire surface. The tensile stress control insulating film 41 applies a tensile stress to the n-channel MOSFET 70, and a SiN film may be used as in the first embodiment. As the insulating film 42, a low-temperature grown silicon oxide film or the like is preferably used. In a later step, it is preferable to select a material having an etching selectivity with respect to the compressive stress control film 63 so that it becomes an etching stopper when the compressive stress control insulating film 43 is removed from the n-channel MOSFET 70.

  Next, as shown in FIG. 11, a patterning resist 45 that covers the gate electrode 15 and the side wall 16 of the p-channel MOSFET 60 and the n-channel MOSFET 70 is formed with a photoresist. A planar layout of the patterning resist 45 is shown in FIG. The cross-sectional view of FIG. 11 corresponds to the AA cross section of FIG. A plurality of p-channel MOSFETs 60 are formed on the left side of FIG. 12, and a plurality of n-channel MOSFETs 70 are formed on the right side. FIG. 12 illustrates a plurality of gate electrodes 15 and 25, a p-type source / drain region 4 and an n-type source / drain region 5. Sidewalls 16 and 26 are omitted. The patterning resist 45 is formed so as to cover the entire n-channel MOSFET 70 and to cover part of the gate electrode 15 and the side wall 16 (not shown) of the p-channel MOSFET 60. A patterning resist 45 is also preferably provided on the left side of the p-channel MOSFET 60 (on the extension of the gate electrode 15 in the gate width direction). This is because the drive current is improved by applying a tensile stress in the gate width direction, so it is preferable to leave the tensile stress control insulating film 41 here.

  Next, the insulating film 42 and the tensile stress control insulating film 41 are dry-etched using the patterning resist 45 as a mask. Next, as shown in FIG. 13, a compressive stress control insulating film 43 is formed on the entire surface. The compressive stress control insulating film 43 can be formed by controlling the pressure and the gas flow rate as in the known technique.

  Next, as shown in FIG. 14, a patterning resist 46 that covers the p-channel MOSFET 60 is formed with a photoresist. Thereafter, the compressive stress control insulating film 43 is dry-etched using the patterning resist 46 as a mask. At this time, the insulating film 42 functions as an etching stopper when the compressive stress control insulating film 43 is removed by etching, and the tensile stress control insulating film 41 on the n-channel MOSFET 70 is not damaged by etching. Thereafter, an interlayer insulating film 3 is formed (see FIG. 8), and then a semiconductor device is formed in the same manner as a normal LSI.

  According to the second embodiment, although the drive current of the n-channel MOSFET 70 is slightly lower than that of the first embodiment, the drive current of the p-channel MOSFET 60 can be improved.

  In the second embodiment, the n-channel MOSFET 70 is not provided with a dummy gate pattern, and a tensile stress is applied by the tensile stress control insulating film 41, and the p-channel MOSFET 60 is a dummy using the tensile stress control insulating film 41. The example which provided the gate pattern 6 and improved the compressive-stress application effect of the compressive-stress control insulating film 43 was shown. As a result, the patterning process may be performed twice, i.e., the patterning process of the dummy gate pattern 6 and the patterning process of the compressive stress control insulating film 43, and the manufacturing cost can be suppressed. In contrast, a dummy gate pattern using the compressive stress control insulating film 43 in the n-channel MOSFET 70 is provided without applying a dummy gate pattern to the p-channel MOSFET 60 and applying a compressive stress in the compressive stress control insulating film 43. May be provided.

  Further, similarly to the first embodiment, dummy gate patterns are provided in both the p-channel MOSFET 60 and the n-channel MOSFET 70, the compressive stress control insulating film 43 is provided in the p-channel MOSFET 60, and the tensile stress control insulating film 41 is provided in the n-channel MOSFET 70. May be formed. In this case, the patterning process requires three times, that is, the dummy gate pattern patterning process, the compressive stress control insulating film 43 patterning process, and the tensile stress control insulating film 41 patterning process, and the manufacturing cost increases.

  As described above, according to the present invention, the stress applied to the channel region by the stress control insulating film is formed by forming the dummy gate pattern so as to cover a part of the upper surface of the gate electrode and the upper surface of the sidewall. The drive current can be improved. The above-described embodiment is merely an example, and various modifications can be made without departing from the spirit of the present invention.

  The present invention can be applied to a semiconductor device in which carrier mobility changes depending on stress applied to a channel region.

It is sectional drawing of the semiconductor device of Example 1 of this invention. It is a perspective view for demonstrating the stress direction which a drive current improves. 7 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device of Example 1. FIG. 7 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device of Example 1. FIG. 7 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device of Example 1. FIG. 7 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device of Example 1. FIG. 7 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device of Example 1. FIG. It is sectional drawing of the semiconductor device of Example 2 of this invention. 10 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device of Example 2. FIG. 12 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device according to Example 2. FIG. 12 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device according to Example 2. FIG. 4 is a planar layout of a patterning resist 45 of Example 2. 12 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device according to Example 2. FIG. 12 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device according to Example 2. FIG. 10 is a cross-sectional view of a conventional semiconductor device described in Patent Document 1. FIG. This is the structure of a conventional NMOSFET 30 described in Non-Patent Document 1. It is the graph which showed the result of having investigated the stress in the channel area | region surface about NMOSFET30. It is the graph which showed the _IDSAT improvement rate with respect to the thickness of the SiN cap layer 33 which has compressive stress about NMOSFET30.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 6, 7 Dummy gate pattern 8 Stress control insulating film 15, 25 Gate electrode 16, 26 Side wall 40 p channel type MOSFET
50 n-channel MOSFET

Claims (14)

A gate electrode formed on a semiconductor substrate;
A sidewall formed on a side surface of the gate electrode;
A dummy gate pattern formed so as to cover a part of the upper surface of the gate electrode and the upper surface of the sidewall;
A semiconductor device comprising: the dummy gate pattern; and a stress control insulating film that covers a surface of the sidewall. The semiconductor device according to claim 1,
The gate length of the gate electrode is 10 to 150 nm. The semiconductor device according to claim 1 or 2,
A ratio of the gate length of the gate electrode to the total height of the gate electrode and the dummy gate pattern (aspect ratio) is 2 to 15. The semiconductor device according to any one of claims 1 to 3,
2. The semiconductor device according to claim 1, wherein the stress control insulating film is a silicon nitride (SiN) film. The semiconductor device according to claim 1,
The semiconductor device is at least one of a p-channel MOSFET and an n-channel MOSFET. The semiconductor device according to claim 5,
The p-channel MOSFET and the n-channel MOSFET,
The semiconductor device, wherein the p-channel MOSFET and the n-channel MOSFET are covered with the stress control insulating film having a tensile stress. The semiconductor device according to claim 5,
The p-channel MOSFET and the n-channel MOSFET,
The p-channel MOSFET is covered with the stress control insulating film having compressive stress;
The semiconductor device, wherein the n-channel MOSFET is covered with the stress control insulating film having a tensile stress. The semiconductor device according to claim 5,
A semiconductor device further comprising a MOSFET not having the dummy gate pattern. The semiconductor device according to claim 8,
A semiconductor device, wherein the MOSFET is an n-channel MOSFET covered with the stress control insulating film having a tensile stress. Forming a gate electrode on a semiconductor substrate via a gate insulating film;
Forming a sidewall on a side surface of the gate electrode;
Forming an insulating film over the entire surface, and processing into a dummy gate pattern that covers a part of the upper surface of the gate electrode and the upper surface of the sidewall;
A method of manufacturing a semiconductor device, comprising: forming a first stress control insulating film covering a surface of the dummy gate pattern and the sidewall. In the manufacturing method of the semiconductor device according to claim 10,
The method of manufacturing a semiconductor device, wherein the first stress control insulating film is a silicon nitride (SiN) film formed by a plasma CVD method. In the manufacturing method of the semiconductor device according to claim 10,
The method of manufacturing a semiconductor device, wherein the semiconductor device is at least one of a p-channel MOSFET and an n-channel MOSFET. In the manufacturing method of the semiconductor device according to claim 12,
Forming a second stress control insulating film having a tensile stress on the p-channel MOSFET and the n-channel MOSFET;
Forming the dummy gate pattern in the p-channel MOSFET;
Forming the first stress control insulating film having compressive stress on the p-channel MOSFET and the n-channel MOSFET;
And a step of removing the first stress control insulating film on the n-channel MOSFET. In the manufacturing method of the semiconductor device according to claim 13,
An insulating film having an etching rate different from that of the first stress control insulating film is provided on the second stress control insulating film,
The step of removing the first stress control insulating film comprises etching the first stress control insulating film using the insulating film as a stopper.

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