JP3061118B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device characterized by a connection between a gate electrode and a source or drain diffusion layer and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a semiconductor device using a MOSFET as a circuit element, a gate electrode may be directly connected to a source diffusion layer or a drain diffusion layer, such as a flip-flop. In order to realize such a configuration, several structures and manufacturing methods can be considered.
When a so-called salicide structure in which metal silicide is formed in the source diffusion layer and the drain diffusion layer in a self-aligning manner is used, the following example is known.

FIG. 14 is a longitudinal sectional view showing this conventional semiconductor device.

On a p-type silicon substrate 1, a field oxide film 2, a polysilicon gate electrode 4a, 4b via a gate oxide film 3, and a gate sidewall 13b of the oxide film formed on the side surface of the gate electrode 4b. N-type high-concentration diffusion layers 7a, 7b formed in a self-aligned manner on gate electrodes 4a, 4b.
And the gate electrode 4a lacking the gate side wall and the high concentration diffusion layer 7
a and a metal silicide layer 14 for connecting to the metal silicide layer 14a.

FIGS. 15 and 16 are longitudinal sectional views showing a method of manufacturing the semiconductor device of FIG. 14 in the order of main steps. FIG.
4 to 16, the steps proceed in the order of (a) to (e).

First, as shown in FIG. 15A, a field oxide film 2 is formed on a p-type silicon substrate 1, and a polycrystalline silicon gate electrode 4 a,
4b is formed. Next, as shown in FIG. 15B, n-type high concentration diffusion layers 7a and 7b are formed in a self-aligned manner around the gate electrodes 4a and 4b by ion implantation. Next, as shown in FIG. 16C, the gate electrodes 4a, 4b
Gate sidewalls 13a and 13b of a silicon oxide film are formed on the side surfaces of. Next, as shown in FIG. 16D, a photoresist 9 is applied, an opening is formed on the gate side wall 6a and a region around the gate side wall 6a, and the gate side wall 6a in this region is removed. Next, as shown in FIG. 14E, a metal film is deposited on the entire surface, and heat treatment is performed to thereby form the gate electrode 4a.
Then, a metal silicidation reaction is caused on the surface of the high concentration diffusion layer 7a, and subsequently, the unreacted metal is removed, thereby forming a metal silicide layer 14 connecting the gate electrode 4a and the high concentration diffusion layer 7a. The gate electrode 4a
The gate oxide film 3 is interposed between the metal silicide layer 7a and the high-concentration diffusion layer 7a, but the metal silicide formed by each protrudes from each other, so that both metal silicide layers 14 are connected.

[0007]

The problem of the prior art shown in FIGS. 14 to 16 is that short circuits or leaks are likely to occur between the gate electrode 4a and the high concentration diffusion layer 7a and the silicon substrate 1. is there.

Since the high concentration diffusion layer 7a is formed in a self-aligned manner with the gate electrode 4a by ion implantation, the overlap between the gate electrode 4a and the high concentration diffusion layer 7a is small. However, in order to form a fine MOSFET, from the viewpoint of preventing the short channel effect and reducing the overlap capacitance, by reducing the heat treatment in a later step, the distance between the gate electrode 4a and the high concentration diffusion layer 7a is reduced. It is desirable to minimize the overlap. on the other hand,
Under these circumstances, when the gate electrode 4a and the high-concentration diffusion layer 7a are converted to metal silicide, these connection portions 12a
In this case, the metal silicide layer 14 reaches or approaches the junction surface of the high concentration diffusion layer 7a, and a short circuit or a leak occurs between the metal silicide layer 14 and the silicon substrate 1. This means that the gate electrode 4a and the high concentration diffusion layer 7a
Means that a short circuit or a leak occurs between the semiconductor device 1 and the silicon substrate 1, which causes a malfunction of the circuit.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to prevent a short circuit or a leak between a gate electrode, a source diffusion layer and a drain diffusion layer and a silicon substrate when connecting the gate electrode to the source diffusion layer or the drain diffusion layer. To prevent it. Also,
An object of the present invention is to reliably connect a gate electrode to a source diffusion layer or a drain diffusion layer without significantly increasing the number of steps.

[0010]

According to the present invention, there is provided a semiconductor device comprising: a gate electrode formed on a silicon substrate via an insulating film; a gate side wall made of an insulating film formed on a side surface of the gate electrode; A diffusion layer formed in a self-aligned manner on the silicon substrate around the gate sidewall or the gate electrode; and a metal silicide layer connecting the gate electrode and the diffusion layer via the gate sidewall. It is a thing. Further, the gate electrode may be made of silicon, and the gate sidewall may be made of a silicon nitride film.

A method of manufacturing a semiconductor device according to the present invention basically includes the following steps (1) to (4). . Forming a gate electrode made of silicon on the silicon substrate via an insulating film; . Forming a gate sidewall made of a first insulating film on a side surface of the gate electrode. . Forming a diffusion layer in a self-aligning manner on the gate side wall or the silicon substrate around the gate electrode. . A step of depositing a second insulating film on the entire surface of the silicon substrate, and then removing the second insulating film from a region on and around the gate sidewall. . In the area where the second insulating film is removed,
A step of selectively growing silicon. . A step of connecting the gate electrode and the diffusion layer via the side wall of the gate by converting the surfaces of the selectively grown silicon, the gate electrode, and the diffusion layer into metal silicide. Further, the first insulating film is a silicon nitride film,
The second insulating film may be a silicon oxide film.

When the gate electrode is connected to the source diffusion layer or the drain diffusion layer, the gate electrode and the high-concentration diffusion layer are connected by a metal silicide so as to straddle the gate side wall. A short circuit or a leak between the layer and the drain diffusion layer and the silicon substrate can be prevented. The reason is that an extra distance between the junction surface of the metal silicide layer and the diffusion layer can be secured by the width of the gate side wall in the lateral direction. In addition, an additional distance between the metal silicide layer and the bonding surface of the diffusion layer can be secured in the vertical direction by the thickness of the selectively grown silicon.

[0013]

1 and 5 show a first embodiment of a semiconductor device according to the present invention. FIG. 1 is a vertical sectional view taken along the line GG in FIG. 5, and FIG. 5 is a plan view.

The semiconductor device according to the present embodiment has a field oxide film 2 and a gate oxide film 3 on a p-type silicon substrate 1.
Self-alignment with gate electrodes 4a, 4b of polycrystalline silicon, gate sidewalls 6a, 6b of silicon nitride film formed on side surfaces of gate electrodes 4a, 4b, and silicon substrate 1 around gate electrodes 4a, 4b. N-type high-concentration diffusion layers 7a and 7b, and a titanium silicide layer 11 connecting the gate electrode 4a and the high-concentration diffusion layer 7a over the gate sidewall 6a.

FIGS. 2 to 4 and FIGS. 6 to 8 show a first embodiment of a method of manufacturing a semiconductor device according to the present invention.
4 to 4 are longitudinal sectional views taken along lines aa to ff in FIGS. 6 to 8, and FIGS. 6 to 8 are plan views. 1 to 8, each step proceeds in the order of (a) to (g).

First, as shown in FIGS. 2A and 6A, a field oxide film 2 having a thickness of 300 nm is formed on a p-type silicon substrate 1 by a selective oxidation method.
Through the gate oxide film 3, gate electrodes 4a and 4b of polycrystalline silicon having a thickness of 200 nm are formed by CVD, lithography and anisotropic etching.

Next, as shown in FIGS. 2 (b) and 6 (b), arsenic ions are converted to 3 × at an acceleration energy of 40 keV.
By implanting 10 ¹⁵ cm ^-2 , the gate electrodes 4a, 4
The n-type high-concentration diffusion layers 7a and 7b are formed in a self-aligned manner on the silicon substrate 1 around b.

Next, as shown in FIGS. 3C and 7C, gate sidewalls 6a, 6b of a silicon nitride film having a width of 100 nm are formed on the side surfaces of the gate electrodes 4a, 4b by CVD and anisotropic etching. And formed.

Next, as shown in FIGS. 3D and 7D, the entire surface of the silicon substrate 1 is covered with a 10 nm-thick silicon oxide film 8 formed by a CVD method. However, for convenience,
7D to 8F, the silicon oxide film 8 is omitted. Thereafter, as shown in FIGS. 4E and 8E, a photoresist 9 is applied and the gate side wall 6a is formed.
An opening is provided in the upper and peripheral regions, and the silicon oxide film 8 in this region is removed by anisotropic etching. FIG.
In (e), the hatched portion shows the photoresist 9 after the opening is provided.

Next, after the photoresist 9 is removed, as shown in FIGS. 4F and 8F, the silicon oxide film 8 is removed by UHV-CVD using silane or disilane as a reaction gas. The silicon 10 having a thickness of 30 nm is selectively grown on the silicon nitride film and the silicon in the region thus formed. In FIG. 4F, the hatched portion indicates the selectively grown silicon 10.

Here, in order to selectively grow silicon only on the silicon nitride film and only on the silicon, as shown in FIG. 9, the growth time is longer than the incubation time on the silicon nitride film and the silicon oxide film is formed. What is necessary is just to set it shorter than the incubation time on a film.

Next, as shown in FIGS. 1G and 5G, the remaining portion of the silicon oxide film 8 is removed by anisotropic etching, and a 30 nm-thick titanium film is formed on the entire surface by sputtering. And a heat treatment at 700 ° C. for 20 seconds to cause a titanium silicidation reaction on the surface of the selectively grown silicon 10, gate electrode 4a and high concentration diffusion layer 7a, followed by ammonium hydroxide and peroxide. By removing the unreacted titanium by immersing it in a mixed solution with hydrogen water, a titanium silicide layer 11 having a thickness of 45 nm connecting the gate electrode 4a and the high-concentration diffusion layer 7a is formed so as to extend over the gate side wall 6a. I do. In FIG. 5G, a hatched portion indicates the titanium silicide layer 11. Thereafter, a heat treatment is performed at 850 ° C. for 20 seconds to cause a phase transition, and the titanium silicide layer 1
1 lower the resistivity.

Although titanium silicide is used as the metal silicide in this embodiment, other metal silicides such as cobalt silicide and nickel silicide can be used only by slightly changing the process conditions.

FIG. 10 is a longitudinal sectional view showing a second embodiment of the semiconductor device according to the present invention.

The semiconductor device of the present embodiment has a field oxide film 2 and a gate oxide film 3 on a p-type silicon substrate 1.
Self-alignment with gate electrodes 4a, 4b of polycrystalline silicon, gate sidewalls 6a, 6b of silicon nitride film formed on side surfaces of gate electrodes 4a, 4b, and silicon substrate 1 around gate electrodes 4a, 4b. N-type low-concentration diffusion layers 5a and 5b, n-type high-concentration diffusion layers 7a and 7b formed in a self-aligned manner on silicon substrate 1 around gate sidewalls 6a and 6b, and gate sidewalls There is provided a titanium silicide layer 11 that connects the gate electrode 4a and the high concentration diffusion layer 7a so as to straddle over the portion 6a.

FIGS. 11 to 13 are vertical sectional views showing a second embodiment of the method for manufacturing a semiconductor device according to the present invention.
10 to 13, each step proceeds in the order of (a) to (g). Although plan views corresponding to these drawings are omitted, they are based on FIGS. 5 to 8A to 8G.

First, as shown in FIG. 11A, a field oxide film 2 having a thickness of 300 nm is formed on a p-type silicon substrate 1 by a selective oxidation method, and is interposed via a gate oxide film 3 having a thickness of 5 nm. And 200 nm thick polycrystalline silicon gate electrodes 4a and 4b are formed by CVD, lithography and anisotropic etching.

Next, as shown in FIG. 11 (b), arsenic ions are accelerated to 3 × 10 ¹³ cm ⁻² at an acceleration energy of 20 keV.
By implantation, n-type low concentration diffusion layers 5a, 5a are self-aligned with silicon substrate 1 around gate electrodes 4a, 4b.
5b is formed.

Next, as shown in FIG. 12C, gate sidewalls 6a and 6b of a silicon nitride film having a width of 100 nm are formed on the side surfaces of the gate electrodes 4a and 4b by CVD and anisotropic etching.

Next, as shown in FIG. 12 (d), after suffering a silicon oxide film 8 having a thickness of 10nm was formed on the entire surface by CVD, arsenic ions at an acceleration energy of 40keV 3 × 10 ¹⁵ cm ^{- By} implanting ^two , the gate sidewall 6
n-type high concentration diffusion layers 7a, 7b
To form

Next, as shown in FIG. 13E, a photoresist 9 is applied, an opening is formed on the gate side wall 6a and a region around the gate side wall 6a, and the silicon oxide film 8 in this region is anisotropically etched. Remove.

Next, after the photoresist 9 is removed, as shown in FIG. 13 (f), the silicon nitride film in the region where the silicon oxide film 8 has been removed by UHV-CVD using silane or disilane as a reaction gas. A 30 nm thick silicon 10 is selectively grown on the top and the silicon.

Here, in order to selectively grow silicon only on the silicon nitride film and the silicon, FIG.
As shown in (1), the growth time may be set longer than the incubation time on the silicon nitride film and shorter than the incubation time on the silicon oxide film.

Next, as shown in FIG. 10 (g), the remaining portion of the silicon oxide film 8 is removed by anisotropic etching, and a titanium film having a thickness of 30 nm is deposited on the entire surface by a sputtering method. Heat treatment at 20 ° C. for 20 seconds to cause a titanium silicidation reaction on the surface of the selectively grown silicon 10, gate electrode 4 a and high concentration diffusion layer 7 a, followed by a mixed solution of ammonium hydroxide and hydrogen peroxide solution To remove unreacted titanium
A titanium silicide layer 11 having a thickness of 45 nm connecting the gate electrode 4a and the high-concentration diffusion layer 7a is formed so as to straddle the gate side wall 6a. Thereafter, a heat treatment is performed at 850 ° C. for 20 seconds to cause a phase transition and lower the resistivity of the titanium silicide layer 11.

Although titanium silicide is used as the metal silicide in this embodiment, other metal silicides such as cobalt silicide and nickel silicide can be used only by slightly changing the process conditions.

The difference between this embodiment and the first embodiment is that
In the structure of the source diffusion layer and the drain diffusion layer. In an actual fine MOSFET, from the viewpoint of suppressing a short channel effect and improving hot carrier resistance, a so-called L having a low concentration diffusion layer and a high concentration diffusion layer as in this embodiment is used.
In many cases, a source / drain having a DD structure is employed. Even in such a case, according to the present invention, it is apparent that a short circuit or a leak between the titanium silicide layer 11 and the silicon substrate 1 can be prevented.

[0037]

The effect of the present invention is that when the gate electrode is connected to the source diffusion layer or the drain diffusion layer, short-circuit or leakage between the gate electrode, the source diffusion layer and the drain diffusion layer and the silicon substrate is prevented. That can be prevented. The first reason is that it straddles over the gate sidewall,
This is because the gate electrode and the high concentration diffusion layer are connected by metal silicide. Therefore, an extra distance between the metal silicide layer and the junction surface of the diffusion layer can be secured by the width of the gate side wall in the lateral direction. The second reason is that a gate sidewall is formed of a silicon nitride film, silicon is selectively grown so as to include the silicon nitride film, and the surfaces of the selectively grown silicon, the gate electrode, and the diffusion layer are made of metal silicide. Because you do. For this reason, at the connection between the gate electrode and the high-concentration diffusion layer, the selectively grown silicon is converted into metal silicide. An extra distance from the surface can be secured.

An advantage of the present invention is that the gate electrode can be reliably connected to the source diffusion layer or the drain diffusion layer without significantly increasing the number of steps.
The reason is that the gate sidewall is formed of a silicon nitride film, silicon is selectively grown so as to include the silicon nitride film, and the surface of the selectively grown silicon, the gate electrode, and the diffusion layer are converted into metal silicide. It is. For this reason,
The newly added step is basically only selective growth of silicon, and in order to convert the selectively grown silicon into metal silicide, it is necessary to surely connect the gate electrode to the source diffusion layer or the drain diffusion layer. Will be able to

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a vertical cross-sectional view showing the method for manufacturing the semiconductor device of FIG. 1, and the process proceeds in the order of FIG. 2 (a) and FIG. 2 (b).

FIG. 3 is a vertical cross-sectional view showing the method for manufacturing the semiconductor device of FIG. 1, and the process proceeds in the order of FIG. 3 (c) and FIG. 3 (d).

FIG. 4 is a vertical cross-sectional view showing the method for manufacturing the semiconductor device of FIG. 1, and the process proceeds in the order of FIG. 4 (e) and FIG. 4 (f).

FIG. 5 is a plan view showing a first embodiment of the semiconductor device of the present invention.

FIG. 6 is a plan view showing the method for manufacturing the semiconductor device of FIG. 1, and the process proceeds in the order of FIGS. 6 (a) and 6 (b).

FIG. 7 is a plan view showing the method for manufacturing the semiconductor device of FIG. 1, and the process proceeds in the order of FIGS. 7 (c) and 7 (d).

FIG. 8 is a plan view showing the method for manufacturing the semiconductor device of FIG. 1, and the process proceeds in the order of FIGS. 8 (e) and 8 (f).

FIG. 9 is a graph showing the relationship between the thickness of selective growth silicon and the growth time.

FIG. 10 is a longitudinal sectional view showing a second embodiment of the semiconductor device of the present invention.

11 is a longitudinal sectional view showing the method of manufacturing the semiconductor device of FIG. 10, and the process proceeds in the order of FIG. 11 (a) and FIG. 11 (b).

12 is a longitudinal sectional view showing the method of manufacturing the semiconductor device of FIG. 10, and the process proceeds in the order of FIG. 12 (c) and FIG. 12 (d).

FIG. 13 is a longitudinal sectional view showing the method for manufacturing the semiconductor device of FIG. 10, and the process proceeds in the order of FIGS. 13 (e) and 13 (f).

FIG. 14 is a longitudinal sectional view showing a conventional semiconductor device.

15 is a longitudinal sectional view showing the method of manufacturing the semiconductor device of FIG. 14, and the process proceeds in the order of FIGS. 15 (a) and 15 (b).

FIG. 16 is a longitudinal sectional view showing the method of manufacturing the semiconductor device of FIG. 14, and the process proceeds in the order of FIG. 16 (c) and FIG. 16 (d).

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 field oxide film 3 gate oxide film 4a, 4b gate electrode 5a, 5b low concentration diffusion layer 6a, 6b gate side wall 7a, 7b high concentration diffusion layer 8 silicon oxide film 9 photoresist 10 selective growth silicon 11 titanium silicide layer 12 Connection between gate electrode and diffusion layer 13a, 13b Gate side wall 14 Metal silicide layer

Claims (4)

(57) [Claims] A gate electrode formed on a silicon substrate with an insulating film interposed therebetween; a gate side wall made of an insulating film formed on a side surface of the gate electrode; A semiconductor device comprising: a diffusion layer formed in a silicon substrate in a self-aligned manner; and a metal silicide layer connecting the gate electrode and the diffusion layer via the gate sidewall. 2. The semiconductor device according to claim 1, wherein said gate electrode is made of silicon, and said gate side wall is made of a silicon nitride film. A step of forming a gate electrode made of silicon on a silicon substrate via an insulating film; a step of forming a gate side wall made of a first insulating film on a side surface of the gate electrode; A step of forming a diffusion layer in a self-aligned manner on the silicon substrate around the gate electrode, and after depositing a second insulating film on the entire surface of the silicon substrate,
Removing the second insulating film from a region on and around the gate sidewall; selectively growing silicon in a region from which the second insulating film has been removed; and selectively growing the silicon. Connecting the gate electrode and the diffusion layer via the gate side wall by converting the surfaces of the gate electrode and the diffusion layer into metal silicide. 4. The method according to claim 3, wherein the first insulating film is a silicon nitride film, and the second insulating film is a silicon oxide film.