JP3676276B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a silicide layer formed by siliciding a metal.
[0002]
[Prior art]
  In recent years, with the miniaturization and high integration of semiconductor devices, as a method for reducing the resistance of gate electrodes and diffusion layers of MIS type semiconductor devices, cobalt (Co), titanium (Ti), tungsten (W), etc. A so-called salicide process in which a silicide film is formed on a gate electrode or a diffusion layer in a self-aligning manner using a metal film is well known. Hereinafter, a method of manufacturing a semiconductor device using a conventional salicide process will be described.
[0003]
  FIG. 10A to FIG. 10E are cross-sectional views showing a manufacturing process of a semiconductor device using a conventional salicide process.
[0004]
  First, in the step shown in FIG. 10A, a trench type element isolation insulating film 102 surrounding the active region is formed on the semiconductor substrate 101, and then a gate insulating film made of a silicon oxide film on the active region of the semiconductor substrate 101. 103 is formed. Thereafter, after depositing a polysilicon film on the substrate, the polysilicon film is patterned by lithography and dry etching to form the gate electrode 104 on the gate insulating film 103. After that, low concentration impurity ions are implanted into the active region using the gate electrode 104 and the element isolation insulating film 102 as a mask to form the LDD region 105 in a self-aligned manner with respect to the gate electrode 104. Thereafter, an oxide film is deposited on the substrate by a CVD method, and this oxide film is etched back to form a sidewall 106 made of an oxide film on the side surface of the gate electrode 104. Thereafter, high concentration impurity ions are implanted into the active region using the gate electrode 104, the sidewall 106 and the element isolation insulating film 102 as a mask, so that the high concentration source / drain region 107 is self-aligned with the gate electrode 104. Form.
[0005]
  Next, in the step shown in FIG. 10B, a cobalt film 108 is deposited on the substrate by sputtering, and then a titanium nitride film 109 is deposited on the cobalt film 108.
[0006]
  Next, in the step shown in FIG. 10C, the semiconductor substrate 101 is subjected to a first short-time heat treatment (RTA) at a temperature of about 400 to 500 ° C. in a nitrogen gas atmosphere, and the gate electrode 104 and the high-concentration source. In the exposed portion of the drain region 107, silicon (Si) and cobalt (Co) are reacted to form a cobalt-rich first cobalt silicide film 110a (CoSi and Co₂ A mixture with Si). At this time, portions of the cobalt film 108 located on the insulating films such as the sidewall 106 and the element isolation insulating film 102 are not silicided, and the unreacted cobalt film 108a remains.
[0007]
  Next, in the step shown in FIG. 10D, the titanium nitride film 109 and the unreacted cobalt film 108a are selectively removed using a solution such as a mixed solution of sulfuric acid and hydrogen peroxide solution. Thus, the polycrystalline first cobalt silicide film 110a is selectively left on the gate electrode 104 and the high concentration source / drain region 107.
[0008]
  Next, in the step shown in FIG. 10E, the semiconductor substrate 101 is subjected to a second short-time heat treatment (RTA) at a temperature of about 800 to 900 ° C. in a nitrogen gas atmosphere, and the first cobalt silicide film 110a. The structurally stable second cobalt silicide film 110b (CoSi₂ Film). As a result, the sheet resistance of the second cobalt silicide film 110b becomes smaller than the sheet resistance of the first cobalt silicide film 110a, and the resistance of the gate electrode 104 and the high concentration source / drain region 107 can be reduced.
[0009]
[Problems to be solved by the invention]
  However, the conventional method for manufacturing a semiconductor device using the salicide process as described above has a problem that it is easily affected by the aggregation of the silicide film and the resistance value of the silicide film is increased. Cobalt silicide crystal grains formed by a silicidation reaction on the gate electrode and the source / drain regions have a property of aggregating when subjected to heat treatment at 650 ° C. or higher. Therefore, when the second short-time heat treatment (800 to 900 ° C.) necessary for forming a stable cobalt silicide film is performed, a part of the cobalt silicide film is broken or extremely thin due to agglomeration of crystal grains. The phenomenon of becoming was seen.
[0010]
  11A and 11B are cross-sectional views showing the shape of the semiconductor device in the steps of FIGS. 10C and 10E, respectively. As shown in FIG. 11A, the cobalt silicide film 110a formed by removing the unreacted cobalt film after the first short-time heat treatment has a thickness in which many crystals having a relatively small grain size are continuous. It is a uniform film. However, as shown in FIG. 11 (b), the cobalt crystal grains agglomerate and coalesce by the second short-time heat treatment, and the grain size of each crystal increases, so that the film thickness becomes partially extremely thin. The uniformity of the thickness of the second cobalt silicide film 110b may be lost, or the dividing portion 111 of the second cobalt silicide film 110b may be generated and the continuity of the cobalt silicide film may be lost. As a result, the conductivity of the second cobalt silicide film 110b is deteriorated and the resistance value is greatly increased. Therefore, it is difficult to reduce the resistance of the gate electrode 104 and the high concentration source / drain region 107.
[0011]
  The cause of such agglomeration of crystal grains in the silicide film is considered as follows. When the cobalt silicide film reaches a temperature of 650 ° C. or higher, the cobalt atoms in each crystal grain begin to diffuse, and each crystal grain moves so that the interfacial energy is minimized according to the movement of the cobalt atom. The entire structure changes as a result. In other words, it is thought that agglomeration of crystal grains occurs, for example, when a plurality of crystal grains having close crystal orientations are combined into one crystal grain, or a certain crystal grain takes in the grain boundary portion and grows into a large crystal grain. ing.
[0012]
  In particular, since the gate electrode and wiring dimensions have been thinned recently, for example, the gate length has become about 0.1 μm, when the above aggregation occurs, not only the resistance value increases but also the silicide wiring is disconnected. May also cause. In addition, recently, the source / drain regions are also shallowed and become shallow, so that when a part of a crystal grain becomes coarse due to agglomeration of crystal grains, a part of a silicide film is extremely extended to a PN junction. There is also a possibility that junction leakage increases by approaching.
[0013]
  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a low-resistance and high-reliability silicide film and a method for manufacturing the same by taking measures to suppress coarsening and non-uniformity of crystal grains due to aggregation of crystal grains in the silicide film Is to provide.
[0014]
[Means for Solving the Problems]
  A first method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a partly silicided member, the step (a) of forming a metal film on a semiconductor layer of a substrate; A step (b) of causing a silicidation reaction between the metal film and the semiconductor layer by a first heat treatment to form a first silicide film having a polycrystalline structure on the semiconductor layer; After the step (b), a step (c) of removing an unreacted portion of the metal film, and an impurity ion is implanted into the first silicide film, so that the first silicide film has an amorphous structure. And changing the second silicide film from an amorphous structure to a third silicide film having a polycrystalline structure by the step (d) of changing to a second silicide film and a second heat treatment, and changing the third silicide film to the member Steps to at least part of ( ) AndIn the step (d), the impurity ions are implanted into the semiconductor layer below the first silicide film to make the surface portion of the semiconductor layer amorphous.
[0015]
  By this method, the polycrystalline structure is destroyed once the first silicide film becomes the second silicide film in the amorphous state, so that the crystal grains in the third silicide film grown thereafter are the first silicide film. Newly grown independently of the crystal grains of the film. Therefore, the coarsening due to the aggregation of crystal grains in the third silicide film can be suppressed, and a semiconductor device having a continuous silicide film having a substantially uniform thickness without a parting portion can be formed.Then, in the step (d), the impurity ions are implanted into the semiconductor layer to make the surface portion of the semiconductor layer amorphous, so that the crystal grains of the third silicide film grow more uniformly. When the semiconductor layer is a gate electrode, the gate resistance can be further reduced, and when the semiconductor layer is a source / drain region, a spike reaction is suppressed and a semiconductor device with small junction leakage can be obtained.
[0016]
  The semiconductor layer is a part of a gate electrode of a MISFET, a step of depositing a polysilicon film before the step (a), and a gate electrode that becomes the semiconductor layer before or after the step (a) In addition, a MISFET having a low-resistance gate electrode without disconnection can be formed.
[0017]
  Forming the semiconductor layer as a part of a source / drain region of a MISFET, forming a gate insulating film and a gate electrode on the active region including the semiconductor layer before the step (a), and the gate A step of forming an insulator sidewall on the side surface of the electrode, and a step of forming source / drain regions to be the semiconductor layer in regions of the active region located on both sides of the gate electrode. A silicide layer can be provided in the source / drain region in a self-aligned manner with respect to the gate electrode.
[0018]
  The method further includes a step of forming a protective film on the substrate after the step (c) and before the step (d). In the step (d), ions are implanted into the silicide film through the protective film. As a result, the function of suppressing the flow of silicide crystal grains by the protective film is further added, so that the above-described effect can be more reliably exhibited.
[0019]
  In that case, the step of forming the protective film is preferably performed at a temperature at which the silicide film does not aggregate.
[0020]
  Moreover, it is preferable that the process of forming the said protective film is performed at the temperature below the temperature at the said 1st heat processing.
[0021]
UpIn the step (d), the aboveImpurity ionsBy using silicon ions, the consumption of silicon due to the silicidation reaction can be supplemented, and the required effect of the spike reaction can be exhibited more remarkably.
[0022]
  A second method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a partly silicided member, and a step of forming a first metal film on a semiconductor layer of a substrate ( a) and a step of causing a silicidation reaction between the first metal film and the semiconductor layer by a first heat treatment to form a metal-rich first silicide film on the semiconductor layer. (B) After the step (b), after removing the unreacted portion of the first metal film (c) and after the step (c), the first metal film is formed on the substrate. Depositing a thin second metal film (d),After the step (d), the second metal film is formed and the temperature is higher than that of the first heat treatment.Second heat treatmentBy doingForming a second silicide film composed of a portion where the first silicide film is changed to a silicon-rich structure and a portion where the second metal film is silicided, and the second silicide film is formed as described above. Step (e) for forming at least part of memberThe first heat treatment is performed at a temperature of 400 to 500 ° C., and the second heat treatment is performed at a temperature of 800 to 900 ° C.
[0023]
  By this method, since the second metal film is thinner than the first metal film, problems such as a short circuit due to penetration of the silicide film into a region of the second metal film that is not in contact with the semiconductor layer can be avoided. .
[0024]
  According to a third method of manufacturing a semiconductor device of the present invention, the first metal film and the semiconductor layer are formed by a step (a) of forming a first metal film on a semiconductor layer of a substrate and a first heat treatment. (B) forming a metal-rich first silicide film on the semiconductor layer by performing a silicidation reaction between the first metal film and the first metal film after the process (b). After the step (c) of removing the unreacted portion, the step (d) of changing the first silicide film to the silicon-rich second silicide film by the second heat treatment, and the step (d), A step (e) of depositing a second metal film on the substrate and a third heat treatment cause a silicidation reaction between the second metal film and the semiconductor layer to form a top surface of the semiconductor layer. Forming a metal-rich third silicide film (f) and a fourth heat treatment. Ri, the third silicide film by changing the silicon-rich fourth silicide film, the second silicide layer and the fourth silicide film and step (g) to at least a portion of the memberThe first metal film is a titanium film, The second metal film is a cobalt film, the first silicide film and the second silicide film are titanium silicide films, and the third silicide film and the fourth silicide film are cobalt silicide films. Is.
[0025]
  According to this method, even if crystal grains aggregate in the second silicide film in the second heat treatment and a divided portion is generated, the divided portion is supplemented by the fourth silicide film in which the second metal film is silicided. As a result, a semiconductor device having a continuous silicide film without a dividing portion can be obtained. In addition, since the second metal film is thinner than the first metal film, problems such as a short circuit due to penetration of the silicide film into a region of the second metal film that is not in contact with the semiconductor layer can be avoided.In the step (a), a titanium film is formed as the first metal film, and in the step (g), a cobalt film is formed as the second silicide film. The third and fourth heat treatments can be performed without affecting the crystal grains in the second silicide film.
[0026]
  A first semiconductor device of the present invention includes a substrate having a semiconductor layer, a silicide layer formed on the semiconductor layer, and formed by integrating a first metal silicide film and a second metal silicide film; WithThe silicide film of the first metal is a titanium silicide film, the silicide film of the second metal is a cobalt silicide film, and the first metal silicide film has a divided portion due to agglomeration of crystal grains. The silicide film of the second metal is formed at least on a part of the silicide film of the first metal..
[0027]
  As a result, even if the crystal grains in the second silicide film are aggregated, the fourth silicide film compensates for the deviation of the presence of crystal grains due to the aggregation, for example, a divided part or a thinned part. A continuous silicide layer having a uniform target thickness can be obtained.Since the first metal silicide film is a titanium silicide film and the second metal silicide film is a cobalt silicide film, the difference in silicidation reaction temperature is utilized to facilitate the manufacture. Can do.
[0028]
  The semiconductor layer and the silicide layer can constitute a gate electrode of MISFET and source / drain regions.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0030]
    (First embodiment)
  FIG. 1A to FIG. 1C and FIG. 2A to FIG. 2C are cross-sectional views showing the manufacturing steps of the semiconductor device of the first embodiment of the present invention.
[0031]
  First, in the step shown in FIG. 1A, a trench type element isolation insulating film 2 surrounding an active region is formed on a p type semiconductor substrate 1 and then a silicon oxide film is formed on the active region of the semiconductor substrate 1. A gate insulating film 3 is formed. Thereafter, after depositing a polysilicon film on the substrate, the polysilicon film is patterned by lithography and dry etching to form a gate electrode 4 on the gate insulating film 3. Thereafter, n-type low-concentration impurity ions are implanted into the active region using the gate electrode 4 and the element isolation insulating film 2 as a mask to form the LDD region 5 in a self-aligned manner with respect to the gate electrode 4. Thereafter, an oxide film is deposited on the substrate by the CVD method, and the oxide film is etched back to form the sidewall 6 made of the oxide film on the side surface of the gate electrode 4. Thereafter, n-type high-concentration impurity ions are implanted into the active region using the gate electrode 4, the side wall 6 and the element isolation insulating film 2 as a mask, so that the high-concentration source / drain region 7 can be Form consistently.
[0032]
  In this step, after the impurity implanted into the high-concentration source / drain region 7 is activated, nitrogen ions (N) are substituted for the arsenic ion implantation shown in FIG.⁺ Or N₂ ⁺) Injection can also suppress the separation of the silicide film and the occurrence of large irregularities due to the agglomeration of the silicide film.
[0033]
  Further, instead of performing ion implantation of nitrogen, when performing a preclean process, which is a pretreatment for sputtering of the cobalt film, plasma is generated in an atmosphere containing nitrogen, and the nitrogen plasma is converted into the gate electrode 4 or the high concentration source. -It may be introduced into the drain region 7. This pre-clean process is generally a process in which Ar ions are irradiated onto the underlayer to reverse-sputter the substance in the underlayer. Prior to the silicide process, this preclean process is performed for the purpose of removing the oxide film on the surface of the semiconductor layer (gate electrode 4 and high-concentration source / drain region 7) on which the silicide layer is formed.
[0034]
  Next, in the step shown in FIG. 1B, a cobalt film 8 having a thickness of about 8 nm is deposited on the substrate by sputtering, and then a titanium nitride film 9 having a thickness of about 20 nm is formed on the cobalt film 8 as a protective film. To deposit.
[0035]
  In this step, before or after the deposition of the titanium nitride film 9, instead of the arsenic ion implantation shown in FIG.⁺ Or N₂ ⁺) Injection can also suppress the separation of the silicide film and the occurrence of large irregularities due to the agglomeration of the silicide film.
[0036]
  Next, in the step shown in FIG. 1C, the semiconductor substrate 1 is subjected to a first short-time heat treatment (RTA) for about 60 seconds at a temperature of about 400 to 500 ° C. in a nitrogen gas atmosphere, and the gate electrode 4 and the exposed portions of the high-concentration source / drain regions 7 are reacted with silicon (Si) and cobalt (Co) to form a cobalt-rich first cobalt silicide film 10a (Co₂ A mixture of Si and CoSi). The first silicide film 10a is considered to be an aggregate of microcrystals, and actually a clear crystal grain boundary as shown in FIG. 1C does not always appear. At this time, portions of the cobalt film 8 located on the insulating films such as the sidewalls 6 and the element isolation insulating film 2 are not silicided, and the unreacted cobalt film 8a remains. Note that the first short-time heat treatment may be performed in a vacuum or an argon atmosphere instead of in a nitrogen gas atmosphere.
[0037]
  In this step, arsenic ions (As) are used instead of the arsenic ion implantation shown in FIG.⁺ ) Implantation or nitrogen ions (N⁺ Or N₂ ⁺) Injection can also suppress the separation of the silicide film and the occurrence of large irregularities due to the agglomeration of the silicide film.
[0038]
  Next, in the step shown in FIG. 2A, the titanium nitride film 9 and the unreacted cobalt film 8a are selectively removed using a solution such as a mixed solution of sulfuric acid and hydrogen peroxide. Thus, the polycrystalline first cobalt silicide film 10a is selectively left on the gate electrode 4 and the high-concentration source / drain region 7.
[0039]
  Next, in the step shown in FIG. 2B, n-type impurity ions such as arsenic ions (As⁺ ) Dose amount 1 × 10¹⁴atoms / cm² Implanting into the first cobalt silicide film 10a under such conditions, at least the first cobalt silicide film 10a is amorphized to form a second cobalt silicide film 10b having an amorphous structure. At this time, the gate electrode 4 located under the first cobalt silicide film 10a and the surface portions of the high-concentration source / drain regions 7 are also deeply converted into a cobalt silicide film by the second second short-time heat treatment. It is preferable to make polysilicon or silicon amorphous by ion implantation.
[0040]
  In this process, instead of arsenic ions, nitrogen ions (N⁺ Or N₂ ⁺) Injection can also suppress the separation of the silicide film and the occurrence of large irregularities due to the agglomeration of the silicide film. At this time, N as nitrogen ions⁺ Than N₂ ⁺Is preferable because it is easy to make the silicide film and the underlying polysilicon or silicon amorphous.
[0041]
  Next, in the step shown in FIG. 2 (c), the semiconductor substrate 1 is subjected to a second short-time heat treatment (RTA) for about 10 seconds at a temperature of about 800 to 900 ° C. in a nitrogen gas atmosphere, so that an amorphous structure is obtained. The second cobalt silicide film 10b is converted into a third cobalt silicide film 10c (CoSi) having a structurally stable polycrystalline structure.₂ ). Note that the second short-time heat treatment may be performed in a vacuum or an argon atmosphere instead of in a nitrogen gas atmosphere.
[0042]
  When arsenic ions are implanted in the process of FIG. 1C or FIG. 2B described above, the third cobalt silicide film 10c has a lateral direction as shown in FIG. However, instead of the arsenic ion implantation, the steps shown in FIGS. 1 (a), 1 (b), 1 (c), and 2 (b) are used. When nitrogen ions are implanted in any one of the steps, as shown in the upper right of FIG. 2 (c), a polycrystal having a grain boundary in the lateral direction is formed, and a substantially stacked structure in which crystal grains overlap each other. It becomes.
[0043]
  14A and 14B are TEM photographs of bright and dark fields of a silicide layer formed by implanting nitrogen ions. FIGS. 14C and 14D are TEM photographs of bright and dark fields of a conventional silicide film without nitrogen ion implantation. 14 (a) to 14 (d) show N₂ Ions with acceleration energy of 20 keV and dose of 1 × 10¹⁵・ Cm_-23 shows the structure of a third cobalt silicide film obtained by implanting the first cobalt silicide film after annealing for activating the impurities in the source / drain regions under the above conditions.
[0044]
  As shown in FIGS. 14 (a) and 14 (b), by implanting nitrogen ions, a silicide film having a grain boundary in the lateral direction, that is, a polycrystalline structure, is formed instead of the so-called bamboo structure. Yes. Also, the grain size is small and CoSi₂ Grains are stacked one above the other. Furthermore, the upper surface of the cobalt silicide film is smooth. That is, the upper layer of CoSi is formed by heat treatment.₂ CoSi below the grain boundary₂ Grain enters and the underlying CoSi₂ There is no aggregation (agglomeration) in the membrane.
[0045]
  On the other hand, as shown in FIGS. 14C and 14D, the cobalt silicide film formed without nitrogen ion implantation has a so-called bamboo structure and has no grain boundaries in the lateral direction. Moreover, the grain size is large and agglomeration occurs. Furthermore, the upper surface of the cobalt silicide film and the interface between the cobalt silicide film and the underlying layer are rough.
[0046]
  According to the manufacturing process of the present embodiment, arsenic ions are implanted into the polycrystalline first cobalt silicide film 10a in the process shown in FIG. 2B, and the first cobalt silicide film 10a is transformed into the amorphous structure. After forming the second cobalt silicide film 10b, the third cobalt silicide film 10c having a polycrystalline structure is formed by the second short-time heat treatment in the step shown in FIG. The entire region of the second cobalt silicide film 10b having an amorphous structure is converted to a stable third cobalt silicide film 10c made of substantially uniform polycrystal without causing aggregation of crystal grains by the second short-time heat treatment. Accordingly, the cobalt silicide film 10c that is finally formed is not likely to be partially divided, and the third cobalt silicide film 10c, which is one continuous film having a uniform thickness, can be formed. Therefore, the resistance of the gate electrode 4 and the high concentration source / drain region 7 can be reliably reduced. Further, even when the gate electrode or the gate wiring is thinned, it is possible to avoid a situation in which a part of the gate electrode or the gate wiring is disconnected. Even if the high concentration source / drain region 7 is shallowed, relatively uniform crystal grains By obtaining a silicide film having a uniform thickness depending on the diameter, junction leakage can be suppressed.
[0047]
  Further, when ion implantation is performed on the first cobalt silicide film 10a, the surface of the gate electrode 4 and the high concentration source / drain region 7 located below the first cobalt silicide film 10a is made amorphous. The crystal grains of the third cobalt silicide film 10c grow uniformly during the second short-time heat treatment. Therefore, the resistance of the gate electrode 4 can be reduced more effectively, and the spike reaction is less likely to occur below the high concentration source / drain region 7, thereby suppressing junction leakage abnormality.
[0048]
  In the above embodiment, arsenic is ion-implanted in the step shown in FIG. 2B to change the first cobalt silicide film 10a to an amorphous structure. However, silicon (Si) is ion-implanted instead of arsenic. Then, it may be made amorphous. When silicon is ion-implanted in this way, the silicon consumption of the gate electrode 4 and the high-concentration source / drain region 7 in the second short-time heat treatment reaction can be compensated, so that junction leakage due to the spike reaction is suppressed. can do. As a result, the sheet resistance of the third cobalt silicide film 10c is lowered, and the resistance of the gate electrode 4 and the high concentration source / drain region 7 can be reduced. Alternatively, instead of arsenic, an element such as argon (Ar), germanium (Ge), tin (Sn), etc. that is electrically neutral and capable of amorphizing the first cobalt silicide film 10a may be implanted. . In this case, as in the case of arsenic ion implantation, it is possible to suppress separation of the silicide film and occurrence of large unevenness due to the aggregation of the silicide film.
[0049]
  In addition, when an impurity serving as a dopant for generating carriers is ion-implanted into the silicide film on the source / drain region, it is preferable to implant an impurity having the same conductivity type as that of the source / drain region. For example, gallium (Ga) or indium (In) is implanted when the source / drain region is p-type, and arsenic (As) or antimony (Sb) is implanted when the source / drain region is n-type. To do. The same applies to the case where ions are implanted into a silicide film on a gate electrode having a dual gate structure.
[0050]
  Here, the timing of implanting arsenic ions is not limited to the step shown in FIG. 2C, and may be the step shown in FIG.
[0051]
  Further, instead of arsenic ions, nitrogen is used in the semiconductor layer (the gate electrode 4 or the high-concentration source) in the step shown in FIG. 1A or 1B (that is, before forming the first cobalt silicide film 10a). The drain region 7) can be introduced into a portion where a silicide film is formed. Further, nitrogen can be introduced into the semiconductor layer (the gate electrode 4 or the high concentration source / drain region 7) in the step shown in FIG. 1B or 2B.
[0052]
  When nitrogen ions are implanted, a polycrystalline multi-layer structure shown in the upper right of FIG. 2C and FIG. 14 appears by the second short-time heat treatment. In that case, it has been confirmed that even if the second short-time heat treatment is performed, the conventional aggregation of cobalt silicide crystal grains hardly occurs. Therefore, it is possible to form a MIS transistor having a continuous silicide film having a substantially uniform thickness without a parting portion. Therefore, the resistance of the gate electrode 4 and the high concentration source / drain region 7 can be reduced.
[0053]
  The reason is not completely elucidated, but for example, the following mechanism can be considered. In the case of the polycrystalline layered structure shown in the upper right of FIG. 2 (c), diffusion is hindered by the reverse diffusion of atoms in the upper and lower crystals at the grain boundaries occurring in the lateral direction, As a result of the suppression of atomic diffusion itself due to the presence of nitrogen, it can be considered that aggregation is hindered. It can be considered that the aggregation of the crystal is caused by a driving force that reduces the surface area of the crystal grain by diffusing atoms such as metal atoms and silicon atoms in each crystal grain in a certain direction (for example, clockwise). Because.
[0054]
  When nitrogen is introduced into the silicide film, there is an advantage that the influence on the carrier concentration of the semiconductor layer is small as in the case of introducing arsenic.
[0055]
  FIG. 12 shows a conventional MISFET having a silicide film (without nitrogen implantation) and nitrogen ions (N₂ ⁺Is a diagram showing the result of measuring the junction leak with a MISFET having a silicide film introduced with a). Here, nitrogen ions are accelerated at an energy of 20 keV and a dose of 1 × 10.¹⁵・ Cm^-2The condition is injected. As shown in the figure, in a MIS transistor formed by a conventional method in which nitrogen is not introduced into a silicide film, there is a large variation in junction leakage, whereas in a MIS transistor having a silicide film into which nitrogen is introduced. It can also be seen that the variation in the junction leakage value is small. As a result, CoSi₂ Even if the film formation temperature or the heat treatment temperature after this step is about 650 ° C. to 700 ° C., junction leakage does not increase. Therefore, heat treatment can be performed at about 700 ° C. without deteriorating the short channel characteristics of the transistor.
[0056]
  In that case, the nitrogen ion implantation condition is N₂ Dose amount 2 × 10¹⁴~ 2x10¹⁵・ Cm^-2It is preferable to carry out within the range. Dose amount is 2 × 10¹⁴・ Cm^-2If it is less than 1, the effect of suppressing the agglomeration of silicide crystals cannot be sufficiently obtained, and the dose amount is 2 × 10.¹⁵・ Cm^-2Exceeds CoSi₂ This is because the interface resistance at the / Si interface increases.
[0057]
  Further, the introduced nitrogen is introduced not only into the silicide film but also into the semiconductor layer (in this embodiment, the gate electrode 4, the high concentration source / drain region 7, the LDD region 5, etc.). The nitrogen concentration in the layers (gate electrode 4, high-concentration source / drain region 7 and LDD region 5) is 1 × 10 after forming the third cobalt silicide film 10c.¹⁷cm^-3The following is preferable. In other words, 1x10¹⁷cm^-3It is preferable to limit the region containing nitrogen exceeding the limit to the silicide film. If the nitrogen concentration is high, impurities (arsenic, phosphorus, boron, etc.) in the semiconductor layer may not be activated sufficiently. As a result, the drain current of the MIS transistor decreases, the gate electrode, and the gate wiring This is because the resistance may increase excessively.
[0058]
  FIG. 13 is data showing the difference in sheet resistance between the gate electrode and the gate wiring depending on the presence or absence of nitrogen. As shown in the figure, when nitrogen is not introduced, a sample having a large sheet resistance value appears with a considerable probability. On the other hand, acceleration energy 10 keV, dose amount 6 × 10¹⁴・ Cm^-2Nitrogen ions (N₂ ⁺), A sample having a large sheet resistance value does not appear, and a stable sheet resistance value is obtained. That is, the effect of the present invention is shown.
[0059]
  In this embodiment and each embodiment described later, the silicide film to be formed is not necessarily a cobalt silicide film, and various metal silicides such as a titanium silicide film, a tungsten silicide film, a nickel silicide film, a molybdenum silicide film, and a tantalum silicide film are used. The present invention can be applied to a film. However, in the case of a cobalt silicide film, the silicidation reaction can be performed at a lower temperature than the titanium silicide film, and thus has an advantage that the influence on the impurity profile in the semiconductor substrate is small.
[0060]
    (Second Embodiment)
  FIG. 3A to FIG. 3C and FIG. 4A to FIG. 4C are cross-sectional views showing the manufacturing steps of the semiconductor device of the second embodiment of the present invention.
[0061]
  First, in the step shown in FIG. 3A, a trench type element isolation insulating film 2 surrounding an active region is formed on a p type semiconductor substrate 1 and then a silicon oxide film is formed on the active region of the semiconductor substrate 1. A gate insulating film 3 is formed. Thereafter, after depositing a polysilicon film on the substrate, the polysilicon film is patterned by lithography and dry etching to form a gate electrode 4 on the gate insulating film 3. Thereafter, n-type low-concentration impurity ions are implanted into the active region using the gate electrode 4 and the element isolation insulating film 2 as a mask to form the LDD region 5 in a self-aligned manner with respect to the gate electrode 4. Thereafter, an oxide film is deposited on the substrate by the CVD method, and the oxide film is etched back to form the sidewall 6 made of the oxide film on the side surface of the gate electrode 4. Thereafter, n-type high-concentration impurity ions are implanted into the active region using the gate electrode 4, the side wall 6 and the element isolation insulating film 2 as a mask, so that the high-concentration source / drain region 7 is self-aligned with respect to the gate electrode 4. Form consistently.
[0062]
  In this step, after the impurity implanted into the high concentration source / drain region 7 is activated, nitrogen ions (N) are substituted for the arsenic ion implantation shown in FIG.⁺ Or N₂ ⁺) Injection can also suppress the separation of the silicide film and the occurrence of large irregularities due to the agglomeration of the silicide film.
[0063]
  Further, instead of performing ion implantation of nitrogen, when performing a preclean process, which is a pretreatment for sputtering of the cobalt film, plasma is generated in an atmosphere containing nitrogen, and the nitrogen plasma is converted into the gate electrode 4 or the high concentration source. -It may be introduced into the drain region 7.
[0064]
  3B, a cobalt film 8 having a thickness of about 8 nm is deposited on the substrate by sputtering, and then a titanium nitride film 9 having a thickness of about 20 nm is formed on the cobalt film 8 as a protective film. To deposit.
[0065]
  In this step, before or after the deposition of the titanium nitride film 9, instead of the arsenic ion implantation shown in FIG.⁺ Or N₂ ⁺) Injection can also suppress the separation of the silicide film and the occurrence of large irregularities due to the agglomeration of the silicide film.
[0066]
  Next, in the step shown in FIG. 3C, the semiconductor substrate 1 is subjected to a first short-time heat treatment (RTA) for about 60 seconds at a temperature of about 400 to 500 ° C. in a nitrogen gas atmosphere, so that the gate electrode 4 and the exposed portions of the high-concentration source / drain regions 7 are reacted with silicon (Si) and cobalt (Co) to form a cobalt-rich first cobalt silicide film 10a (Co₂ A mixture of Si and CoSi). The first silicide film 10a is considered to be an aggregate of microcrystals, and actually a clear crystal grain boundary as shown in FIG. 3C does not always appear. At this time, portions of the cobalt film 8 located on the insulating films such as the sidewalls 6 and the element isolation insulating film 2 are not silicided, and the unreacted cobalt film 8a remains. Note that the first short-time heat treatment may be performed in a vacuum or an argon atmosphere instead of in a nitrogen gas atmosphere.
[0067]
  In this step, arsenic ions (As) are used instead of the arsenic ion implantation shown in FIG.⁺ ) Implantation or nitrogen ions (N⁺ Or N₂ ⁺) Injection can also suppress the separation of the silicide film and the occurrence of large irregularities due to the agglomeration of the silicide film.
[0068]
  Next, in the step shown in FIG. 4A, the titanium nitride film 9 and the unreacted cobalt film 8a are selectively removed using a solution such as a mixed solution of sulfuric acid and hydrogen peroxide solution. Thus, the polycrystalline first cobalt silicide film 10a is selectively left on the gate electrode 4 and the high-concentration source / drain region 7. Thereafter, a protective film 12 made of a CVD oxide film having a thickness of about 20 nm is deposited on the substrate. At this time, the deposition temperature of the protective film 12 is preferably lower than the temperature at which the first silicide film aggregates, for example, 650 ° C. or lower when a cobalt silicide film is used as in this embodiment. Further, it is more preferable that the deposition temperature of the protective film 12 is the same as or lower than the temperature of the first short-time heat treatment. As the protective film 12, an insulating film such as a plasma oxide film or a plasma nitride film, or a conductive film of a titanium nitride film may be used in addition to the CVD oxide film.
[0069]
  Next, in the step shown in FIG. 4B, n-type impurity ions such as arsenic ions (As⁺ ) Dose of about 1 × 10¹⁴atoms / cm² Under the above conditions, the protective film 12 is passed through the first cobalt silicide film 10a and implanted, and at least the first cobalt silicide film 10a is amorphized to form a second cobalt silicide film 10b having an amorphous structure. At this time, the gate electrode 4 located under the first cobalt silicide film 10a and the surface portions of the high-concentration source / drain regions 7 are also deeply converted into a cobalt silicide film by the second second short-time heat treatment. It is preferable to make polysilicon or silicon amorphous by ion implantation.
[0070]
  In this process, instead of arsenic ions, nitrogen ions (N⁺ Or N₂ ⁺) Injection can also suppress the separation of the silicide film and the occurrence of large irregularities due to the agglomeration of the silicide film. At this time, N as nitrogen ions⁺ Than N₂ ⁺Is preferable because it is easy to make the silicide film and the underlying polysilicon or silicon amorphous.
[0071]
  Next, in the step shown in FIG. 4C, the semiconductor substrate 1 is subjected to a second short-time heat treatment (RTA) for about 10 seconds at a temperature of about 800 to 900 ° C. in a nitrogen gas atmosphere, so that an amorphous structure is obtained. The second cobalt silicide film 10b is converted into a third cobalt silicide film 10c (CoSi) having a structurally stable polycrystalline structure.₂ ). Note that the second short-time heat treatment may be performed in a vacuum or an argon atmosphere instead of in a nitrogen gas atmosphere.
[0072]
  When arsenic ions are implanted in the above-described step of FIG. 3C or FIG. 4B, the third cobalt silicide film 10c is formed in the lateral direction as shown in FIG. However, instead of the arsenic ion implantation, the steps shown in FIGS. 3 (a), 3 (b), 3 (c) and 4 (b) are used. When nitrogen ions are implanted in any one of the steps, as shown in the upper right of FIG. 4 (c), a polycrystal having a grain boundary in the lateral direction is formed, and the substantially laminated structure in which the crystal grains overlap each other. It becomes.
[0073]
  Thereafter, when the protective film 12 is an insulating film, it may be left as it is, and an interlayer insulating film may be formed on the protective film 12. When the protective film 12 is a conductor film such as a titanium nitride film, the interlayer insulating film may be formed after the protective film 12 is selectively removed.
[0074]
  According to the manufacturing process of the present embodiment, after the protective film 12 is deposited on the first cobalt silicide film 10a in the process shown in FIG. 4A, the protective film 12 is processed in the process shown in FIG. Then, ions are implanted into the first cobalt silicide film 10a to form a second amorphous cobalt silicide film 10b having an amorphous structure, and a second structure having a polycrystalline structure is formed by a second short-time heat treatment in the step shown in FIG. 3 is formed, the fluidization of the cobalt silicide crystal grains is suppressed by the protective film 12. In addition, since it is in an amorphous state, the entire region of the second cobalt silicide film 10b having an amorphous structure is substantially uniform without causing aggregation of crystal grains by the second short-time heat treatment as in the conventional manufacturing process. It is converted into a stable third cobalt silicide film 10c made of polycrystal. Therefore, the third cobalt silicide film 10c is unlikely to be partially divided, and the third cobalt silicide film 10c, which is one continuous film having a uniform thickness, can be formed. Therefore, the resistance of the gate electrode 4 and the high concentration source / drain region 7 can be reliably reduced. Further, even when the gate electrode or the gate wiring is thinned, it is possible to avoid a situation in which a part of the gate electrode or the gate wiring is disconnected. Even if the high concentration source / drain region 7 is shallowed, relatively uniform crystal grains By obtaining a silicide film having a uniform thickness depending on the diameter, junction leakage can be suppressed.
[0075]
  Further, when ion implantation is performed on the first cobalt silicide film 10a, the surface of the gate electrode 4 and the high concentration source / drain region 7 located below the first cobalt silicide film 10a is made amorphous. The crystal grains of the third cobalt silicide film 10c grow uniformly during the second short-time heat treatment. Therefore, the resistance of the gate electrode 4 can be reduced more effectively, and the spike reaction is less likely to occur below the high concentration source / drain region 7, thereby suppressing junction leakage abnormality.
[0076]
  In the above embodiment, arsenic is ion-implanted in the step shown in FIG. 4B to form the first cobalt silicide film 10a in an amorphous structure, but silicon (Si) is ion-implanted instead of arsenic. It may be made amorphous. When silicon is ion-implanted in this way, the silicon consumption of the gate electrode 4 and the high-concentration source / drain region 7 in the second short-time heat treatment reaction can be compensated, so that junction leakage due to the spike reaction is suppressed. can do. As a result, the sheet resistance of the third cobalt silicide film 10c is lowered, and the resistance of the gate electrode 4 and the high concentration source / drain region 7 can be reduced. Alternatively, instead of arsenic, an element such as argon (Ar), germanium (Ge), or tin (Sn) that is electrically neutral and capable of amorphizing the first cobalt silicide film 10a may be implanted. . In this case, as in the case of arsenic ion implantation, it is possible to suppress separation of the silicide film and occurrence of large unevenness due to the aggregation of the silicide film.
[0077]
  Here, the timing of implanting arsenic ions is not limited to the step shown in FIG. 4C, and may be the step shown in FIG.
[0078]
  When nitrogen ions are implanted, a polycrystalline laminated structure shown in the upper right of FIG. 4C appears by the second short-time heat treatment. In that case, it has been confirmed that even if the second short-time heat treatment is performed, coalescence due to agglomeration of cobalt crystal grains as in the conventional case hardly occurs. The reason is as already described in the first embodiment.
[0079]
  In that case, the implantation condition of nitrogen ions is set to a dose amount of 2 × 10.¹⁴~ 2x10¹⁵・ Cm^-2It is preferable to carry out within the range. Dose amount is 2 × 10¹⁴・ Cm^-2If it is below, the effect of suppressing the agglomeration of silicide crystals cannot be sufficiently obtained, and the dose amount is 2 × 10¹⁵cm^-2Exceeds CoSi₂ This is because the interface resistance at the / Si interface increases.
[0080]
  Further, the introduced nitrogen is introduced not only into the silicide film but also into the semiconductor layer (in this embodiment, the gate electrode 4, the high concentration source / drain region 7, the LDD region 5, etc.). The nitrogen concentration in the layers (gate electrode 4, high-concentration source / drain region 7 and LDD region 5) is 1 × 10 after forming the third cobalt silicide film 10c.¹⁷・ Cm^-3The following is preferable. In other words, 1x10¹⁷・ Cm^-3It is preferable to limit the region containing nitrogen exceeding the limit to the silicide film. If the nitrogen concentration is high, impurities (arsenic, phosphorus, boron, etc.) in the semiconductor layer may not be activated sufficiently. As a result, the drain current of the MIS transistor decreases, the gate electrode, and the gate wiring This is because the sheet resistance may increase excessively.
[0081]
  (Third embodiment)
  FIG. 5A to FIG. 5C and FIG. 6A to FIG. 6C are cross-sectional views showing the manufacturing steps of the semiconductor device of the third embodiment of the present invention.
[0082]
  First, in the step shown in FIG. 5A, a trench type element isolation insulating film 2 surrounding the active region is formed on the p type semiconductor substrate 1, and then a silicon oxide film is formed on the active region of the semiconductor substrate 1. A gate insulating film 3 is formed. Thereafter, after depositing a polysilicon film on the substrate, the polysilicon film is patterned by lithography and dry etching to form a gate electrode 4 on the gate insulating film 3. Thereafter, n-type low-concentration impurity ions are implanted into the active region using the gate electrode 4 and the element isolation insulating film 2 as a mask to form the LDD region 5 in a self-aligned manner with respect to the gate electrode 4. Thereafter, an oxide film is deposited on the substrate by the CVD method, and the oxide film is etched back to form the sidewall 6 made of the oxide film on the side surface of the gate electrode 4. Thereafter, n-type high-concentration impurity ions are implanted into the active region using the gate electrode 4, the side wall 6 and the element isolation insulating film 2 as a mask, so that the high-concentration source / drain region 7 is self-aligned with respect to the gate electrode 4. Form consistently.
[0083]
  Next, in the step shown in FIG. 5B, a cobalt film 8 having a thickness of about 8 nm is deposited on the substrate by sputtering, and then a titanium nitride film 9 having a thickness of about 20 nm is deposited on the cobalt film 8.
[0084]
  Next, in the step shown in FIG. 5C, the semiconductor substrate 1 is subjected to a first short-time heat treatment (RTA) for about 60 seconds at a temperature of about 400 to 500 ° C. in a nitrogen gas atmosphere, so that the gate electrode 4 and the exposed portions of the high-concentration source / drain regions 7 are reacted with silicon (Si) and cobalt (Co) to form a cobalt-rich first cobalt silicide film 20a (Co₂ A mixture of Si and CoSi). At this time, portions of the cobalt film 8 located on the insulating films such as the sidewalls 6 and the element isolation insulating film 2 are not silicided, and the unreacted cobalt film 8a remains. Note that the first short-time heat treatment may be performed in a vacuum or an argon atmosphere instead of in a nitrogen gas atmosphere.
[0085]
  Next, in the step shown in FIG. 6A, the titanium nitride film 9 and the unreacted cobalt film 8a are selectively removed using a solution such as a mixed solution of sulfuric acid and hydrogen peroxide solution. Thus, the first cobalt silicide film 20a having a polycrystalline structure is selectively left on the gate electrode 4 and the high concentration source / drain region 7. Thereafter, a cobalt film having a thickness of about 2 nm is formed on the substrate as a second metal film having a thickness smaller than that of the cobalt film 8 which is the first metal film used for forming the first cobalt silicide film 20a on the substrate. After the film 13 is deposited, a titanium nitride film 14 having a thickness of about 20 nm is deposited continuously on the cobalt film 13 as a second protective film.
[0086]
  Next, in the step shown in FIG. 6B, the semiconductor substrate 1 is subjected to a second short-time heat treatment (RTA) for about 10 seconds at a temperature of about 800 to 900 ° C. in a nitrogen gas atmosphere, so that the metal rich state is obtained. The first cobalt silicide film 20a is silicon-rich and structurally stable second cobalt silicide film 20b (CoSi₂ ). By this second short-time heat treatment, silicidation reaction proceeds between the first cobalt silicide film 20a and the cobalt film 13 thereon, but the side wall 6 and the element isolation insulating film 2 of the cobalt film 13 are advanced. The silicidation reaction does not occur in the portion located on the upper part, and the unreacted cobalt film 13a remains. Here, since the temperature of the second short-time heat treatment is higher than the temperature of the first short-time heat treatment, when the second short-time heat treatment is performed continuously with the first short-time heat treatment, the first short-time heat treatment is performed. During the time heat treatment, the silicide film may erode to the unreacted cobalt film 8a, and the gate electrode 4 and the high-concentration source / drain region 7 may be conducted through the silicide film. On the other hand, in the present embodiment, the cobalt film 13 as the second metal film has a thickness of only about 2 nm and is thin. Therefore, the entire unreacted cobalt film 13a is silicided by the second short-time heat treatment. Absent. Note that the second short-time heat treatment may be performed in a vacuum or an argon atmosphere instead of in a nitrogen gas atmosphere.
[0087]
  Next, in the step shown in FIG. 6C, the titanium nitride film 14 and the unreacted cobalt film 13a are selectively removed using a solution such as a mixed solution of sulfuric acid and hydrogen peroxide solution. Thus, the second cobalt silicide film 20 b can be selectively left on the gate electrode 4 and the high concentration source / drain region 7.
[0088]
  According to the manufacturing process of this embodiment, after depositing the thin cobalt film 13 on the first cobalt silicide film 20a in the process shown in FIG. 6A, the cobalt film is processed in the process shown in FIG. 6B. Since the second short-time heat treatment is performed in a state where 13 is formed on the entire surface, even during the second short-time heat treatment, the second cobalt silicide film 20b is partially divided as in the conventional manufacturing process. Thus, a stable second cobalt silicide film 20b in which the entire region is continuous is obtained. Therefore, the resistance of the gate electrode 4 and the high concentration source / drain region 7 can be reliably reduced. Further, even when the gate electrode or the gate wiring is thinned, it is possible to avoid a situation in which a part of the gate electrode or the gate wiring is disconnected. By obtaining a silicide film, junction leakage can be suppressed.
[0089]
  Also in this embodiment, by applying the second embodiment and depositing the second metal film and then implanting impurity ions into the first silicide film, there is an effect that the crystal grains can be further refined. is there.
[0090]
    (Fourth embodiment)
  FIG. 7A to FIG. 7C, FIG. 8A to FIG. 8C, FIG. 9A and FIG. 9B show the manufacture of the semiconductor device of the fourth embodiment of the present invention. It is sectional drawing which shows a process.
[0091]
  First, in the step shown in FIG. 7A, a trench type element isolation insulating film 2 surrounding an active region is formed on a p type semiconductor substrate 1 and then a silicon oxide film is formed on the active region of the semiconductor substrate 1. A gate insulating film 3 is formed. Thereafter, after depositing a polysilicon film on the substrate, the polysilicon film is patterned by lithography and dry etching to form a gate electrode 4 on the gate insulating film 3. Thereafter, n-type low-concentration impurity ions are implanted into the active region using the gate electrode 4 and the element isolation insulating film 2 as a mask to form the LDD region 5 in a self-aligned manner with respect to the gate electrode 4. Thereafter, an oxide film is deposited on the substrate by the CVD method, and the oxide film is etched back to form the sidewall 6 made of the oxide film on the side surface of the gate electrode 4. Thereafter, n-type high-concentration impurity ions are implanted into the active region using the gate electrode 4, the side wall 6 and the element isolation insulating film 2 as a mask, so that the high-concentration source / drain region 7 is self-aligned with respect to the gate electrode 4. Form consistently.
[0092]
  Next, in the step shown in FIG. 7B, a cobalt film 8 having a thickness of about 8 nm is deposited on the substrate by sputtering, and then a titanium nitride film 9 having a thickness of about 20 nm is deposited on the cobalt film 8.
[0093]
  Next, in the step shown in FIG. 7C, the semiconductor substrate 1 is subjected to a first short-time heat treatment (RTA) for about 60 seconds at a temperature of about 400 to 500 ° C. in a nitrogen gas atmosphere, and the gate electrode 4 and the exposed portions of the high-concentration source / drain regions 7 are reacted with silicon (Si) and cobalt (Co) to form a cobalt-rich first cobalt silicide film 20a (Co₂ A mixture of Si and CoSi). At this time, portions of the cobalt film 8 located on the insulating films such as the sidewalls 6 and the element isolation insulating film 2 are not silicided, and the unreacted cobalt film 8a remains. Note that the first short-time heat treatment may be performed in a vacuum or an argon atmosphere instead of in a nitrogen gas atmosphere.
[0094]
  Next, in the step shown in FIG. 8A, the titanium nitride film 9 and the unreacted cobalt film 8a are selectively removed using a solution such as a mixed solution of sulfuric acid and hydrogen peroxide solution. Thus, the first cobalt silicide film 20 a is selectively left on the gate electrode 4 and the high concentration source / drain region 7. Thereafter, the semiconductor substrate 1 is subjected to a second short-time heat treatment (RTA) at about 800 to 900 ° C. in a nitrogen gas atmosphere, so that the first cobalt silicide film 20a is structurally stable. (CoSi₂ ). At this time, agglomeration of crystal grains due to movement of cobalt atoms occurs due to the second short-time heat treatment, and the crystal grain size increases, so that the film thickness becomes partially extremely thin, or the second cobalt silicide film 20b. In some cases, a split portion 15 is formed, and the underlying silicon layer is exposed at the split portion.
[0095]
  Next, in the step shown in FIG. 8B, after depositing a cobalt film 16 having a thickness of about 6 nm as a second metal film on the substrate by sputtering, a second protective film is formed on the cobalt film 16. As a result, a titanium nitride film 17 having a thickness of about 20 nm is deposited.
[0096]
  Next, in the step shown in FIG. 8C, a third short-time heat treatment (RTA) is performed on the semiconductor substrate 1 at a temperature of about 400 to 500 ° C. for about 60 seconds in a nitrogen gas atmosphere. As a result, in the gate electrode 4 and the high concentration source / drain region 7, silicon (Si) and cobalt (Co) in a portion exposed in the divided portion 15 of the second cobalt silicide film 20 b react to react with cobalt. Third cobalt silicide film 18a (Co₂ Si or CoSi) is formed. At this time, the silicidation reaction also proceeds between the second cobalt silicide film 20b and the cobalt film 16, but compared with the reaction between the cobalt film 16 and the silicon layer in the divided portion 15 of the second cobalt silicide film 20b. The reaction is slight. Note that in the portion of the cobalt film 16 located on the sidewalls 6 and the element isolation insulating film 2, no silicidation reaction occurs and the unreacted cobalt film 16a remains. Note that the third short-time heat treatment may be performed in a vacuum or an argon atmosphere instead of in a nitrogen gas atmosphere.
[0097]
  Next, in the step shown in FIG. 9A, the titanium nitride film 17 and the unreacted cobalt film 16a are selectively removed using a solution such as a mixed solution of sulfuric acid and hydrogen peroxide solution. Thus, the third cobalt silicide film 18a is selectively left on the gate electrode 4 and the high concentration source / drain region 7 together with the second cobalt silicide film 20b.
[0098]
  Next, in the step shown in FIG. 9B, the semiconductor substrate 1 is subjected to a fourth short-time heat treatment (RTA) for about 10 seconds at a temperature of about 800 to 900 ° C. in a nitrogen gas atmosphere. The cobalt silicide film 18a is structurally stable as a fourth cobalt silicide film 18b (CoSi).₂ ). Note that the fourth short-time heat treatment may be performed in a vacuum or an argon atmosphere instead of in a nitrogen gas atmosphere.
[0099]
  According to the manufacturing process of the present embodiment, after forming the structurally stable second cobalt silicide film 20b in the process shown in FIGS. 7B, 7C, and 8A, FIG. (B), FIG. 8 (c), FIG. 9 (a), and FIG. 9 (b), even if the divided portion 15 is formed when the second cobalt silicide film 20b is formed, the process is finally performed. Since the structurally stable fourth cobalt silicide film 18b is formed in the divided portion 15, a continuous silicide film composed of the second cobalt silicide film 20b and the fourth cobalt silicide film 18b is formed. Can do. As a result, the sheet resistance of the entire silicide film composed of the second and fourth cobalt silicide films 20b and 18b is reduced, and the resistance of the gate electrode 4 and the high concentration source / drain region 7 can be reduced.
[0100]
  In the above embodiment, both the first and second metal films have been described using a cobalt film. However, a titanium film is used as the first metal film, a cobalt film is used as the second metal film, and titanium silicide is used. A silicide film made of a film and a cobalt silicide film may be formed. At this time, if the titanium silicide film is first formed and then the cobalt silicide film is formed, the temperature at which the titanium silicide film aggregates is higher than that of the cobalt silicide film. A cobalt silicide film can be formed in the divided portion where the is exposed.
[0101]
    (Other embodiments)
  In the first to fourth embodiments, the titanium nitride film is used on the cobalt film, but a nitride film or an oxide film may be used.
[0102]
  Further, as the semiconductor substrate, not only a bulk semiconductor substrate but also an SOI substrate may be used, and a semiconductor substrate other than a silicon substrate may be used. Further, for example, it may have a heterojunction in which a SiGe layer and a SiGeC layer are provided on a silicon substrate.
[0103]
  Further, the target member for forming the silicide layer may be only the gate electrode and the gate wiring. In that case, the following two cases can be considered. The first method is a method of first performing a silicidation process after patterning a polysilicon film to form a gate electrode and a gate wiring. In the second method, a polysilicon film and a metal film are stacked, the metal film is silicided to form a first silicide film, and then the polycide film is patterned to form a gate electrode and a gate wiring. Is the method. In the case of this second method, the step of forming the second and third silicide films of the present invention from the first silicide film may be performed before the patterning of the polycide film or after the patterning of the polycide film. Also good.
[0104]
  The target member for forming the silicide layer is not limited to the gate electrode and the gate wiring, but may be another member made of a material capable of silicidation of metal such as a polysilicon wiring or a polysilicon electrode (pad). . For example, in a DRAM memory cell transistor, a silicide layer may be provided only on the gate electrode and the gate wiring (word line). Even in general wiring and electrodes (pads), if gaps or high resistance portions are partially generated due to agglomeration of silicide crystal grains, there is a problem in electrical connection with the members themselves or contact members connected to the portions. Therefore, by applying the present invention, the effects described in the embodiments can be obtained. The same applies to the electrode of the capacitor and the contact portion with the wiring of the resistance element.
[0105]
  However, particularly in a miniaturized member, the influence of local voids or thinning of the silicide layer is large, so this is necessary when forming a silicide layer on the gate electrode, gate wiring, source / drain region of the MISFET. It can be said that the significance of applying the invention is great. Of course, in this case, it goes without saying that the present invention may be applied to a process of forming a silicide layer only on the gate electrode and the gate wiring, and a process of forming a silicide layer only on the source / drain regions.
[0106]
  In addition, as a result of the present inventors examining the cutting phenomenon of the gate wiring, the silicide crystal (cobalt silicide crystal) in the vicinity of the cut portion is CoSi.₂ It was found that it is configured by. Therefore, in the present invention, the second short-time heat treatment is performed using CoSi.₂ The conditions are such that crystal grains are not easily generated, that is, a temperature of 725 ° C. or lower (however, a temperature higher than the first short-time heat treatment temperature). Thereby, cutting | disconnection (disconnection) of a gate electrode, gate wiring, etc. can be suppressed.
[0107]
  However, when the second short-time heat treatment is performed under a low temperature condition of 725 ° C. or lower, there may be problems such as an increase in junction leakage of the MIS transistor and occurrence of spikes. Therefore, after the second short-time heat treatment, the silicide film is covered with a protective film such as an oxide film, and then the third short-time heat treatment is performed under conditions of, for example, 850 ° C. and 30 sec. The third short-time heat treatment is, for example, a heat treatment performed for the purpose of reflowing the interlayer insulating film after depositing a BPSG film as an interlayer insulating film on the substrate after the step shown in FIG. Can be used in combination.
[0108]
  Thereby, it is possible to suppress the junction leakage of the MIS transistor while suppressing the cutting due to the thinning of the gate electrode, the gate wiring, and the like.
[0109]
【The invention's effect】
  According to the present invention, it is possible to prevent a resistance increase due to a divided portion generated in a silicide film, and to form a semiconductor device having a silicide film having a low resistance even when a gate electrode or a source / drain region is miniaturized. it can.
[Brief description of the drawings]
FIGS. 1A to 1C are cross-sectional views illustrating steps up to forming a first silicide film in the manufacturing steps of the semiconductor device of the first embodiment. FIGS.
FIGS. 2A to 2C are cross-sectional views showing steps from the removal of the unreacted cobalt film to the formation of a third silicide film in the manufacturing process of the semiconductor device of the first embodiment; FIG.
FIGS. 3A to 3C are cross-sectional views showing steps up to forming a first silicide film in the manufacturing steps of the semiconductor device of the second embodiment. FIGS.
FIGS. 4A to 4C are cross-sectional views showing steps from the removal of an unreacted cobalt film to the formation of a third silicide film in the manufacturing process of the semiconductor device of the second embodiment. FIG.
FIGS. 5A to 5C are cross-sectional views showing steps up to forming a first silicide film in the manufacturing steps of the semiconductor device of the third embodiment. FIGS.
FIGS. 6A to 6C are steps from the formation of the second metal film and the protective film to the formation of the second silicide film in the manufacturing process of the semiconductor device of the third embodiment. FIG.
FIGS. 7A to 7C are cross-sectional views illustrating steps up to forming a first silicide film in the manufacturing steps of the semiconductor device of the fourth embodiment. FIGS.
FIGS. 8A to 8C are cross-sectional views showing processes from the formation of the second silicide film to the formation of the third silicide film in the manufacturing process of the semiconductor device of the fourth embodiment. FIG.
FIGS. 9A to 9C are processes from the removal of the unreacted second cobalt film to the formation of the fourth silicide film in the manufacturing process of the semiconductor device of the fourth embodiment; FIG.
FIGS. 10A to 10E are cross-sectional views showing a manufacturing process of a semiconductor device having a conventional salicide structure. FIGS.
11 (a) and 11 (b) are enlarged views of the cross-sectional views shown in FIGS. 10 (d) and 10 (e), respectively.
FIG. 12 is a diagram showing a result of measuring a junction leak between a MISFET having a silicide film by a conventional method and a MISFET having a silicide film into which nitrogen ions are introduced.
FIG. 13 is data showing differences in resistance of gate electrodes, gate wirings, and the like depending on the presence or absence of nitrogen.
14A and 14B are TEM photographs of bright and dark fields of a silicide layer formed by implanting nitrogen ions, respectively. (C), (d) is a TEM photograph of a bright field and a dark field of a conventional silicide film without nitrogen ion implantation.
[Explanation of symbols]
  1 Semiconductor substrate
  2 Insulating film for element isolation
  3 Gate insulation film
  4 Gate electrode
  5 LDD region (low concentration source / drain region)
  6 Sidewall
  7 High concentration source / drain regions
  8 Cobalt film
  9 Titanium nitride film
  10a First cobalt silicide film
  10b Second cobalt silicide film
  10c Third cobalt silicide film
  12 Protective film
  13 Cobalt film
  14 Titanium nitride film
  15 Dividing part
  16 Cobalt film
  17 Titanium nitride film
  18 Cobalt silicide film
  18a Third cobalt silicide film
  18b Fourth cobalt silicide film
  20a First cobalt silicide film
  20b Second cobalt silicide film

Claims (16)

A method of manufacturing a semiconductor device including a partly silicided member,
Forming a metal film on the semiconductor layer of the substrate;
A step (b) of forming a first silicide film having a polycrystalline structure on the semiconductor layer by causing a silicidation reaction between the metal film and the semiconductor layer by a first heat treatment;
After the step (b), a step (c) of removing an unreacted portion of the metal film;
A step (d) of implanting nitrogen ions into the first silicide film to change the first silicide film into a second silicide film having an amorphous structure;
A step (e) of changing the second silicide film from an amorphous structure to a third silicide film having a polycrystalline structure by the second heat treatment, and using the third silicide film as at least a part of the member; Including
In the step (d), the nitrogen ions are implanted into the semiconductor layer under the first silicide film to make the surface portion of the semiconductor layer amorphous. In the manufacturing method of the semiconductor device according to claim 1,
The semiconductor layer is a part of the gate electrode of the MISFET,
Before the step (a), depositing a polysilicon film;
And a step of forming the gate electrode before or after the step (a). In the manufacturing method of the semiconductor device of Claim 1 or 2,
The semiconductor layer is a part of the source / drain region of the MISFET,
Before step (a) above,
Forming a gate insulating film and a gate electrode on the active region including the semiconductor layer;
Forming an insulator sidewall on the side surface of the gate electrode;
Forming a source / drain region in a region located on both sides of the gate electrode in the active region. In the manufacturing method of the semiconductor device as described in any one of Claims 1-3,
The method further includes a step of forming a protective film on the substrate after the step (c) and before the step (d),
In the step (d), an ion implantation is performed on the silicide film through the protective film. In the manufacturing method of the semiconductor device according to claim 4,
The method of manufacturing a semiconductor device, wherein the step of forming the protective film is performed at a temperature at which the silicide film does not aggregate. In the manufacturing method of the semiconductor device according to claim 4,
The method of manufacturing a semiconductor device, wherein the step of forming the protective film is performed at a temperature equal to or lower than the temperature during the first heat treatment. A method of manufacturing a semiconductor device including a partly silicided member,
Forming a first metal film on the semiconductor layer of the substrate;
(B) forming a metal-rich first silicide film on the semiconductor layer by causing a silicidation reaction between the first metal film and the semiconductor layer by a first heat treatment; ,
After the step (b), a step (c) of removing an unreacted portion of the first metal film;
After the step (c), a step (d) of depositing a second metal film thinner than the first metal film on the substrate;
After the step (d), the second silicide film is silicon-rich by performing a second heat treatment having a temperature higher than that of the first heat treatment in a state where the second metal film is formed. Forming a second silicide film comprising a portion changed to a structure and a portion in which the second metal film is silicided, and using the second silicide film as at least a part of the member (e) Including
The first heat treatment is performed at a temperature of 400 to 500 ° C.
The method for manufacturing a semiconductor device, wherein the second heat treatment is performed at a temperature of 800 to 900 ° C. The method of manufacturing a semiconductor device according to claim 7 .
The semiconductor layer is a part of the gate electrode of the MISFET,
Before the step (a), depositing a polysilicon film;
And a step of forming the gate electrode before or after the step (a). In the manufacturing method of the semiconductor device according to claim 7 or 8 ,
The semiconductor layer is a part of the source / drain region of the MISFET,
Before step (a) above,
Forming a gate insulating film and a gate electrode on the substrate region including the semiconductor layer;
Forming an insulator sidewall on the side surface of the gate electrode;
Forming a source / drain region in a region located on both sides of the gate electrode in the substrate region. A method of manufacturing a semiconductor device including a partly silicided member,
Forming a first metal film on the semiconductor layer of the substrate;
(B) forming a metal-rich first silicide film on the semiconductor layer by causing a silicidation reaction between the first metal film and the semiconductor layer by a first heat treatment; ,
After the step (b), a step (c) of removing an unreacted portion of the first metal film;
A step (d) of changing the first silicide film into a silicon-rich second silicide film by a second heat treatment;
After the step (d), a step (e) of depositing a second metal film on the substrate;
A step (f) of causing a silicidation reaction between the second metal film and the semiconductor layer by a third heat treatment to form a metal-rich third silicide film on the semiconductor layer; ,
A step (g) of changing the third silicide film into a silicon-rich fourth silicide film by a fourth heat treatment so that the second silicide film and the fourth silicide film are at least part of the member (g) ) And
The first metal film is a titanium film, and the second metal film is a cobalt film;
The first silicide film and the second silicide film are titanium silicide films,
The method of manufacturing a semiconductor device, wherein the third silicide film and the fourth silicide film are cobalt silicide films. The method of manufacturing a semiconductor device according to claim 10 .
The semiconductor layer is a part of the gate electrode of the MISFET,
Before the step (a), depositing a polysilicon film;
And a step of forming the gate electrode before or after the step (a). In the manufacturing method of the semiconductor device according to claim 10 or 11 ,
The semiconductor layer is a part of the source / drain region of the MISFET,
Before step (a) above,
Forming a gate insulating film and a gate electrode on the substrate region including the semiconductor layer;
Forming an insulator sidewall on the side surface of the gate electrode;
Forming a source / drain region in a region located on both sides of the gate electrode in the substrate region. In the manufacturing method of the semiconductor device according to any one of claims 10 to 12 ,
In the step (f), when the first silicide film is changed to the second silicide film, a divided portion is generated in the second silicide film, and a part of the semiconductor layer is exposed,
In the step (g), a silicidation reaction is caused between the exposed part of the semiconductor layer and the second metal film. A substrate having a semiconductor layer;
A silicide layer formed on the semiconductor layer and formed by integrating a silicide film of a first metal and a silicide film of a second metal;
The silicide film of the first metal is a titanium silicide film,
The second metal silicide film is a cobalt silicide film,
The silicide film of the first metal has a parted portion due to agglomeration of crystal grains,
2. The semiconductor device according to claim 1, wherein the second metal silicide film is formed at least in a divided portion of the first metal silicide film. The semiconductor device according to claim 14 .
A semiconductor device, wherein the semiconductor layer and the silicide layer constitute a gate electrode of a MISFET. The semiconductor device according to claim 14 or 15 ,
A semiconductor device, wherein the semiconductor layer and the silicide layer constitute a source / drain region of a MISFET.

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