JP2003224133A - Diode and its manufacturing method - Google Patents
Diode and its manufacturing methodInfo
- Publication number
- JP2003224133A JP2003224133A JP2002020135A JP2002020135A JP2003224133A JP 2003224133 A JP2003224133 A JP 2003224133A JP 2002020135 A JP2002020135 A JP 2002020135A JP 2002020135 A JP2002020135 A JP 2002020135A JP 2003224133 A JP2003224133 A JP 2003224133A
- Authority
- JP
- Japan
- Prior art keywords
- concentration diffusion
- diffusion region
- type
- opening
- openings
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 79
- 230000001681 protective effect Effects 0.000 claims abstract description 74
- 238000002844 melting Methods 0.000 claims abstract description 50
- 230000008018 melting Effects 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 13
- 238000009792 diffusion process Methods 0.000 claims description 323
- 239000010410 layer Substances 0.000 claims description 98
- 239000011229 interlayer Substances 0.000 claims description 26
- 239000012535 impurity Substances 0.000 claims description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000009413 insulation Methods 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 18
- 239000010703 silicon Substances 0.000 description 18
- 239000005380 borophosphosilicate glass Substances 0.000 description 12
- 230000015556 catabolic process Effects 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 11
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 5
- 230000007257 malfunction Effects 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000006378 damage Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PNDPGZBMCMUPRI-UHFFFAOYSA-N iodine Chemical compound II PNDPGZBMCMUPRI-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- NLYAJNPCOHFWQQ-UHFFFAOYSA-N kaolin Chemical compound O.O.O=[Al]O[Si](=O)O[Si](=O)O[Al]=O NLYAJNPCOHFWQQ-UHFFFAOYSA-N 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ダイオードおよび
その製造方法に関するもので、特に半導体装置の入出力
保護に用いられるＰＮ接合ダイオードとその製造方法に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diode and a manufacturing method thereof, and more particularly to a PN junction diode used for input / output protection of a semiconductor device and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】半導体装置では、静電気放電（ElectroS
tatic Discharge、ＥＳＤ）やサージ電圧・電流によっ
て半導体装置が破壊されるのを防止するため、半導体装
置の入出力保護素子として、従来、主にＰＮ接合ダイオ
ードが使用されてきた。この種のＰＮ接合ダイオードに
は、例えば図１４に示すようなＰＮ接合ダイオードがあ
る。2. Description of the Related Art In semiconductor devices, electrostatic discharge (ElectroS
In order to prevent the semiconductor device from being destroyed by tatic discharge (ESD) or surge voltage / current, a PN junction diode has been mainly used as an input / output protection element of the semiconductor device. An example of this type of PN junction diode is a PN junction diode as shown in FIG.
【０００３】図１４（ａ）は従来のＰＮ接合ダイオード
の平面図であり、図１４（ｂ）は図１４（ａ）における
Ａ−Ａ’線に沿った拡大断面図である。FIG. 14 (a) is a plan view of a conventional PN junction diode, and FIG. 14 (b) is an enlarged sectional view taken along the line AA 'in FIG. 14 (a).
【０００４】図１４（ａ），（ｂ）に示す従来のＰＮ接
合ダイオードでは、図１４（ｂ）からわかるように、低
濃度Ｎ型シリコン（半導体）基板１にベースとなるＰ型
高濃度拡散領域２が配置され、そのベースの両側にエミ
ッタとなるＮ型高濃度拡散領域３ａ，３ｂが配置されて
おり、ベースとエミッタの間の半導体部分がＰＮ接合領
域４ａ，４ｂとなって、ＰＮ接合ダイオードが構成され
ている。図１４（ａ）の平面図においては、Ｐ型高濃度
拡散領域２とＮ型高濃度拡散領域３ａ，３ｂは、それぞ
れ破線で示されている。In the conventional PN junction diode shown in FIGS. 14A and 14B, as can be seen from FIG. 14B, the P-type high-concentration diffusion serving as the base is formed on the low-concentration N-type silicon (semiconductor) substrate 1. The region 2 is arranged, and the N-type high-concentration diffusion regions 3a and 3b serving as emitters are arranged on both sides of the base, and the semiconductor portion between the base and the emitter becomes the PN junction regions 4a and 4b to form the PN junction. A diode is constructed. In the plan view of FIG. 14A, the P-type high-concentration diffusion region 2 and the N-type high-concentration diffusion regions 3a and 3b are indicated by broken lines.
【０００５】Ｐ型高濃度拡散領域２とＮ型高濃度拡散領
域３ａ，３ｂには、それぞれ、図１４（ｂ）に示すよう
に、ＢＰＳＧからなる層間絶縁膜５の開口部を介して、
Ａｌ電極７ａ，７ｂが接続されている。図１４（ａ）の
平面図に示すように、Ｐ型の高濃度拡散領域２に接続す
るベース電極は７ａであり、Ｎ型の高濃度拡散領域３
ａ，３ｂはエミッタ電極７ｂで互いに接続されている。
図１４（ａ）の平面図において、各電極７ａ，７ｂは実
線で示されており、各高濃度拡散領域２，３ａ，３ｂと
各電極７ａ，７ｂのコンタクト領域７１，７２，７３
は、点線で示されている。また、ダイオード全体は窒化
珪素（ＳｉＮ）からなる保護膜１０によって被覆され、
保護膜１０の開口部に形成された図１４（ａ）に実線で
示すパッド７０ａ，７０ｂを介して、外部に接続され
る。As shown in FIG. 14B, the P-type high-concentration diffusion region 2 and the N-type high-concentration diffusion regions 3a and 3b are respectively passed through an opening of an interlayer insulating film 5 made of BPSG.
The Al electrodes 7a and 7b are connected. As shown in the plan view of FIG. 14A, the base electrode connected to the P-type high-concentration diffusion region 2 is 7a, and the N-type high-concentration diffusion region 3 is included.
a and 3b are connected to each other by an emitter electrode 7b.
In the plan view of FIG. 14A, the electrodes 7a and 7b are shown by solid lines, and the high-concentration diffusion regions 2, 3a and 3b and the contact regions 71, 72 and 73 of the electrodes 7a and 7b are shown.
Are indicated by dotted lines. The entire diode is covered with a protective film 10 made of silicon nitride (SiN),
It is connected to the outside through pads 70a and 70b shown in solid lines in FIG. 14A formed in the openings of the protective film 10.
【０００６】図１４（ａ）の平面図において、各高濃度
拡散領域２，３ａ，３ｂは約１０μｍ×５００μｍの矩
形状である。半導体装置の入出力保護素子としてのＰＮ
接合ダイオードでは、大きなサージ電流に対応するため
に、通常は図１４に示すＰＮ接合ダイオードが数１０個
並列接続される。In the plan view of FIG. 14A, each of the high concentration diffusion regions 2, 3a and 3b has a rectangular shape of about 10 μm × 500 μm. PN as an input / output protection element for semiconductor devices
In the junction diode, several PN junction diodes shown in FIG. 14 are normally connected in parallel in order to handle a large surge current.
【０００７】次に、図１４に示したＰＮ接合ダイオード
の製造方法を、図１５に従って説明する。図１５は、図
１４（ａ）におけるＡ−Ａ’線に沿った拡大断面を、製
造工程順に示したものである。Next, a method of manufacturing the PN junction diode shown in FIG. 14 will be described with reference to FIG. FIG. 15 shows an enlarged cross section taken along the line AA ′ in FIG. 14A in the order of manufacturing steps.
【０００８】図１５（ａ）に示すように、低濃度Ｎ型シ
リコン（半導体）基板１上に、ベースに対応した第１の
マスク１００を形成し、Ｐ型の不純物を高濃度にイオン
注入して、ベースとなるＰ型高濃度拡散領域２を形成す
る。As shown in FIG. 15A, a first mask 100 corresponding to a base is formed on a low-concentration N-type silicon (semiconductor) substrate 1, and P-type impurities are ion-implanted at a high concentration. Thus, the P-type high-concentration diffusion region 2 serving as the base is formed.
【０００９】次に、図１５（ｂ）に示すように、ベース
に対応した第１のマスク１００を除去した後、エミッタ
に対応した第２のマスク１０１を形成し、Ｎ型の不純物
を高濃度にイオン注入して、エミッタとなるＮ型高濃度
拡散領域３ａ，３ｂを、ベースとなるＰ型高濃度拡散領
域２の両側に形成する。これにより、Ｐ型高濃度拡散領
域２とＮ型高濃度拡散領域３ａ，３ｂの間の半導体部分
が、ＰＮ接合領域４ａ，４ｂとなる。Next, as shown in FIG. 15 (b), after removing the first mask 100 corresponding to the base, a second mask 101 corresponding to the emitter is formed to increase the concentration of N-type impurities. Are ion-implanted into the substrate to form N-type high-concentration diffusion regions 3a and 3b which serve as emitters on both sides of the P-type high-concentration diffusion region 2 which serves as a base. As a result, the semiconductor portion between the P-type high-concentration diffusion region 2 and the N-type high-concentration diffusion regions 3a and 3b becomes the PN junction regions 4a and 4b.
【００１０】次に、図１５（ｃ）に示すように、エミッ
タに対応した第２のマスク１０１を除去した後、層間絶
縁膜５としてＢＰＳＧ膜を全面に積層し、Ｐ型高濃度拡
散領域２とＮ型高濃度拡散領域３ａ，３ｂに接続するた
めの開口部６１，６２，６３を形成する。Next, as shown in FIG. 15C, after removing the second mask 101 corresponding to the emitter, a BPSG film is laminated on the entire surface as an interlayer insulating film 5, and the P-type high concentration diffusion region 2 is formed. And openings 61, 62, 63 for connecting to the N-type high-concentration diffusion regions 3a, 3b are formed.
【００１１】次に、図１５（ｄ）に示すように、全面に
Ａｌ膜を積層した後、所定形状にパターニングして、ベ
ース電極７ａおよびエミッタ電極７ｂを形成する。Then, as shown in FIG. 15D, an Al film is laminated on the entire surface and then patterned into a predetermined shape to form a base electrode 7a and an emitter electrode 7b.
【００１２】次に、図１５（ｅ）に示すように、全面に
保護膜１０としてのＳｉＮ膜を積層した後、外部に接続
するためのパッド用開口部を形成して、図１４に示した
ＰＮ接合ダイオードが完成する。Next, as shown in FIG. 15 (e), after a SiN film as the protective film 10 is laminated on the entire surface, an opening for a pad for connecting to the outside is formed, and as shown in FIG. The PN junction diode is completed.
【００１３】[0013]
【発明が解決しようとする課題】ＥＳＤのようなサージ
がエミッタである図１４のＮ型高濃度拡散領域３ａ，３
ｂに印加されると、即座にＰＮ接合領域４ａ，４ｂが逆
バイアスされてアバランシェが発生し、サージ電流がエ
ミッタであるＮ型高濃度拡散領域３ａ，３ｂからベース
であるＰ型高濃度拡散領域２に流れる。図１４の構造の
ＰＮ接合ダイオードでは、ベースのＰ型高濃度拡散領域
２とエミッタのＮ型高濃度拡散領域３ａ，３ｂが分離さ
れているため、その断面においてＰＮ接合領域４ａ，４
ｂに幅Ｌca，Ｌcbがある。この幅Ｌca，Ｌcbは、設計段
階においては、等しく設定される。The N-type high-concentration diffusion regions 3a, 3 of FIG. 14 in which a surge such as ESD is the emitter
When applied to b, the PN junction regions 4a and 4b are immediately reverse-biased to generate avalanche, and a surge current flows from the N-type high-concentration diffusion regions 3a and 3b which are the emitters to the P-type high-concentration diffusion regions which are the bases. It flows to 2. In the PN junction diode having the structure shown in FIG. 14, the P-type high-concentration diffusion region 2 of the base and the N-type high-concentration diffusion regions 3a and 3b of the emitter are separated from each other.
b has widths L ca and L cb . The widths L ca and L cb are set equal in the design stage.
【００１４】しかしながら、図１４の構造のＰＮ接合ダ
イオードでは、図１５に示したように、Ｐ型高濃度拡散
領域２とＮ型高濃度拡散領域３ａ，３ｂを、それぞれ専
用のホトマスクを使って、別々にイオン注入して形成し
ている。従って、マスクのアラインメントずれが起きる
と、図１４（ｂ）に示したように、ＰＮ接合領域４ａ，
４ｂの幅Ｌca，Ｌcbが異なってしまう（図では、Ｌca＜
Ｌcb）。その結果、幅の狭いＰＮ接合領域４ａの接合耐
圧が、幅の広いＰＮ接合領域４ｂの接合耐圧より低くな
る。また図中の矢印の太さの違いで示したように、幅の
狭いＰＮ接合領域４ａでは、幅の広いＰＮ接合領域４ｂ
より、大きなサージ電流が流れる。つまり、製造過程で
図１４（ｂ）のように幅Ｌca，Ｌcbが異なってしまった
ダイオードでは、接合耐圧の低いＰＮ接合領域のほうに
サージ電流が偏るので、素子のサージに対する耐量が、
マスクのアラインメントずれのない設計どおりのダイオ
ードに比べて低下してしまう。また、図１４のダイオー
ドを複数個並列接続したダイオードにおいても、ＰＮ接
合領域の幅が製造過程で異なってしまうと、ダイオード
の特性は実質的に一番狭い幅のＰＮ接合領域の特性に支
配されてしまい、大きなサージ電流に対応するために並
列接続した効果が得られなくなってしまう。However, in the PN junction diode having the structure shown in FIG. 14, as shown in FIG. 15, the P-type high-concentration diffusion region 2 and the N-type high-concentration diffusion regions 3a and 3b are respectively provided with dedicated photomasks. It is formed by ion implantation separately. Therefore, when the mask misalignment occurs, as shown in FIG. 14B, the PN junction region 4a,
4b has different widths L ca and L cb (in the figure, L ca <
L cb ). As a result, the junction breakdown voltage of the narrow PN junction region 4a becomes lower than the junction breakdown voltage of the wide PN junction region 4b. Further, as indicated by the difference in the thickness of the arrows in the figure, in the narrow PN junction region 4a, the wide PN junction region 4b is formed.
Therefore, a large surge current flows. That is, in a diode in which the widths L ca and L cb are different from each other as shown in FIG. 14B during the manufacturing process, the surge current is biased toward the PN junction region having a low junction breakdown voltage, so that the surge withstand capability of the element is
It is lower than the designed diode with no mask misalignment. In addition, even in a diode in which a plurality of diodes shown in FIG. 14 are connected in parallel, if the width of the PN junction region is different in the manufacturing process, the characteristics of the diode are substantially controlled by the characteristics of the PN junction area having the narrowest width. As a result, the effect of parallel connection to cope with a large surge current cannot be obtained.
【００１５】さらに、図１４の構造のＰＮ接合ダイオー
ドにおいては、層間絶縁膜５がＢＰＳＧ膜で形成されて
いるが、大きなサージ電流が流れるとサージのエネルギ
ーでＰＮ接合領域４ａ，４ｂが約９００℃の高温にな
り、ＢＰＳＧ膜が部分的に溶け出すといった問題点を有
している。ＢＰＳＧ膜が一旦溶けると、サージ電流がな
くなり常温に戻って固化した後のＢＰＳＧ膜は、絶縁作
用が劣化し、ＰＮ接合領域４ａ，４ｂでリーク電流が発
生し易くなる。Further, in the PN junction diode having the structure of FIG. 14, the interlayer insulating film 5 is formed of the BPSG film, but when a large surge current flows, the PN junction regions 4a and 4b are heated to about 900 ° C. due to the energy of the surge. There is a problem that the BPSG film is partially melted due to the high temperature. Once the BPSG film is melted, the surge current disappears and the BPSG film after returning to room temperature and solidifying deteriorates the insulating action, and a leak current is easily generated in the PN junction regions 4a and 4b.
【００１６】また、図１４の構造のＰＮ接合ダイオード
においては、図１４（ａ）の平面図に示したように、各
高濃度拡散領域２，３ａ，３ｂに接続するＡｌ配線７
ａ，７ｂの幅が広くとれないため、大きなサージ電流に
対しては配線幅が十分でなく、配線が焼き切れるといっ
た問題点もある。Further, in the PN junction diode having the structure of FIG. 14, as shown in the plan view of FIG. 14A, the Al wiring 7 connected to each of the high concentration diffusion regions 2, 3a and 3b.
Since the widths of a and 7b cannot be made wide, there is a problem that the wiring width is not sufficient for a large surge current and the wiring is burnt out.
【００１７】そこで、本発明の目的は、サージ電流を均
一に流すことができ、サージ耐量の高いＰＮ接合ダイオ
ードおよびその製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a PN junction diode having a high surge withstand capability and a method of manufacturing the same, which allows a surge current to flow uniformly.
【００１８】[0018]
【課題を解決するための手段】請求項１に記載の発明
は、半導体上に配置され、２本の等幅ブリッジ部で分割
される３個の開口部を備える高融点絶縁保護膜と、前記
３個の開口部の中央の開口部を介して半導体中に配置さ
れ、Ｐ型またはＮ型からなる第１高濃度拡散領域と、前
記３個の開口部の両端の開口部を介して半導体中に配置
され、前記第１高濃度拡散領域とは逆型のＰ型またはＮ
型からなる２個の第２高濃度拡散領域とを有し、前記２
本の等幅ブリッジ部の下に配置され、前記第１高濃度拡
散領域と前記第２高濃度拡散領域の間の半導体からなる
ＰＮ接合領域が、等幅に２本形成され、前記２個の第２
高濃度拡散領域同士が電極を介して互いに接続されるこ
とを特徴とするダイオードとしている。According to a first aspect of the present invention, there is provided a high melting point insulating protective film having three openings arranged on a semiconductor and divided by two equal-width bridge portions, and In the semiconductor through the first high-concentration diffusion region of P-type or N-type, which is arranged in the semiconductor through the central opening of the three openings, and through the openings at both ends of the three openings. And is of a P-type or N-type which is opposite to the first high-concentration diffusion region.
A second high-concentration diffusion region of a mold,
Two PN junction regions, which are arranged below the equal-width bridge portion and are made of a semiconductor between the first high-concentration diffusion region and the second high-concentration diffusion region, are formed in the same width, and the two PN junction regions are formed. Second
The diode is characterized in that the high-concentration diffusion regions are connected to each other via electrodes.
【００１９】これによれば、第１高濃度拡散領域および
第２高濃度拡散領域を形成するためのマスクとして、共
通の高融点絶縁保護膜を用いるため、第１高濃度拡散領
域の両側に、幅が等しいＰＮ接合領域を形成することが
できる。このため、並列接続されているＰＮ接合の一方
にサージ電流が偏ることがなく、ダイオードのサージ耐
量を実質的に高めることができる。According to this, since the common high melting point insulating protective film is used as a mask for forming the first high concentration diffusion region and the second high concentration diffusion region, both sides of the first high concentration diffusion region are formed. PN junction regions of equal width can be formed. Therefore, the surge current is not biased to one of the PN junctions connected in parallel, and the surge resistance of the diode can be substantially increased.
【００２０】ＰＮ接合領域に隣接して配置される高融点
絶縁保護膜は、ＢＰＳＧ膜のような融点が１０００℃以
下の膜ではなく、シリコン（Ｓｉ、融点１４２０℃）よ
りも高い融点を持つ絶縁膜とする。これによれば、ＰＮ
接合領域に大きなサージ電流が流れてＰＮ接合部が発熱
しても、高融点絶縁保護膜の融点が基板となるＳｉより
高い融点を持つため、高融点絶縁保護膜が基板のＳｉよ
り先に溶け出すことはない。従って、一度大きなサージ
電流が流れると、絶縁作用が劣化してその後使用できな
くなるといったことがなく、サージ電流に対する保護作
用を持続することができる。The high melting point insulating protective film disposed adjacent to the PN junction region is not a film having a melting point of 1000 ° C. or lower like a BPSG film, but an insulating film having a melting point higher than silicon (Si, melting point 1420 ° C.). The film. According to this, PN
Even if a large surge current flows in the junction region and the PN junction heats up, the high melting point insulating protective film has a melting point higher than that of the substrate Si, so that the high melting point insulating protective film melts before the substrate Si. I will not put it out. Therefore, once a large surge current flows, the insulating action does not deteriorate and the device cannot be used thereafter, and the protective action against the surge current can be continued.
【００２１】請求項２に記載の発明は、半導体上に配置
され、２本の等幅ブリッジ部で分割される３個の開口部
を１組の開口群として、前記開口群をｍ組備える高融点
絶縁保護膜と、前記ｍ組の開口群の各々の中央の開口部
を介して半導体中に配置され、Ｐ型またはＮ型のどちら
か１つの型からなるｍ個の第１高濃度拡散領域と、前記
ｍ組の開口群の各々の両端の開口部を介して半導体中に
配置され、前記第１高濃度拡散領域とは逆型のＰ型また
はＮ型からなる２ｍ個の第２高濃度拡散領域とを有し、
前記ｍ組の各々の開口群の２本の等幅ブリッジ部の下に
配置され、前記第１高濃度拡散領域と前記第２高濃度拡
散領域の間の半導体からなるＰＮ接合領域が、等幅に２
ｍ本形成され、前記ｍ個の第１高濃度拡散領域同士が電
極を介して互いに接続され、前記２ｍ個の第２高濃度拡
散領域同士が電極を介して互いに接続されることを特徴
とするダイオードとしている。According to a second aspect of the present invention, three opening portions arranged on a semiconductor and divided by two equal-width bridge portions are set as one opening group, and m openings are provided. A melting point insulating protective film and m first high-concentration diffusion regions which are arranged in the semiconductor through the central opening of each of the m sets of opening groups and which are either P-type or N-type And 2m second high-concentrations of P-type or N-type, which are arranged in the semiconductor through the openings at both ends of each of the m sets of openings and are of the opposite type to the first high-concentration diffusion region. And a diffusion region,
A PN junction region made of a semiconductor, which is disposed below the two equal-width bridge portions of each of the m sets of opening groups and has a uniform width between the first high-concentration diffusion region and the second high-concentration diffusion region, To 2
m pieces are formed, the m first high-concentration diffusion regions are connected to each other via electrodes, and the 2m second high-concentration diffusion regions are connected to each other via electrodes. It is a diode.
【００２２】これによれば、２ｍ本のＰＮ接合を並列接
続することで大きなサージ電流に対しても必要なサージ
耐量を確保することができると共に、高融点絶縁保護膜
の開口部を介して、ＰＮ接合領域の幅が全てのＰＮ接合
にわたって等しく配置されるため、ＰＮ接合のどれか1
個にサージ電流が偏ることがなく、サージ電流に対する
ダイオードのサージ耐量を実質的にも高めることができ
る。また、ＰＮ接合領域に隣接して高融点絶縁保護膜が
配置されているので、前記のようにサージ電流に対する
保護作用を持続することができる。According to this, by connecting the PN junctions of 2 m in parallel, it is possible to secure the necessary surge withstanding capability against a large surge current, and at the same time, through the opening of the high melting point insulating protective film, One of the PN junctions because the width of the PN junction region is evenly distributed over all PN junctions.
There is no bias in the surge current, and the surge resistance of the diode against the surge current can be substantially increased. Further, since the high melting point insulating protective film is disposed adjacent to the PN junction region, the protective action against the surge current can be maintained as described above.
【００２３】請求項３に記載の発明は、半導体上に配置
され、ｎ本の等幅ブリッジ部で分割される（ｎ＋１）個
の開口部を備える高融点絶縁保護膜と、前記（ｎ＋１）
個の開口部のうち、１つおきに位置する開口部からなる
第１の開口群の各々の開口部を介して半導体中に配置さ
れ、Ｐ型またはＮ型のどちらか１つの型からなる複数個
の第１高濃度拡散領域の組と、前記第１の開口群の各々
の開口部に隣接する、１つおきに位置する開口部からな
る第２の開口群の各々の開口部を介して半導体中に配置
され、前記第１高濃度拡散領域とは逆型のＰ型またはＮ
型からなる複数個の第２高濃度拡散領域の組とを有し、
前記ｎ本の各々の等幅ブリッジ部の下に配置され、前記
第１高濃度拡散領域と前記第２高濃度拡散領域の間の半
導体からなるＰＮ接合領域が、等幅にｎ本形成され、前
記複数個の第１高濃度拡散領域同士が電極を介して互い
に接続され、前記複数個の第２高濃度拡散領域同士が電
極を介して互いに接続されることを特徴とするダイオー
ドとしている。According to a third aspect of the present invention, there is provided a high melting point insulating protective film which is disposed on a semiconductor and has (n + 1) openings divided by n equal-width bridge portions, and the (n + 1).
A plurality of P-type or N-type ones of the P-type and N-type, which are arranged in the semiconductor through the respective openings of the first opening group including the openings located at every other openings. Via a set of the first high-concentration diffusion regions and each opening of the second opening group, which is adjacent to each of the openings of the first opening group and is arranged at every other opening. A P-type or N-type that is arranged in a semiconductor and is of an opposite type to the first high-concentration diffusion region.
A plurality of second high-concentration diffusion regions of a mold,
N PN junction regions made of a semiconductor, which are arranged under each of the n equal-width bridge portions and are formed between the first high-concentration diffusion region and the second high-concentration diffusion region, are formed in equal widths, The diode is characterized in that the plurality of first high-concentration diffusion regions are connected to each other via electrodes and the plurality of second high-concentration diffusion regions are connected to each other via electrodes.
【００２４】これによれば、第１高濃度拡散領域と第２
高濃度拡散領域を隣り合って交互に配置し、ｎ個のＰＮ
接合を並列接続することで、必要なサージ耐量を確保す
ると共に、ダイオードを小型化することができる。ま
た、高融点絶縁保護膜の開口部を介して、ＰＮ接合領域
の幅が全てのＰＮ接合にわたって等しく配置されるた
め、ＰＮ接合のどれか1個にサージ電流が偏ることがな
く、サージ電流に対するダイオードのサージ耐量を実質
的にも高めることができる。また、ＰＮ接合領域に隣接
して高融点絶縁保護膜が配置されているので、前記のよ
うにサージ電流に対する保護作用を持続することができ
る。According to this, the first high concentration diffusion region and the second high concentration diffusion region
High-concentration diffusion regions are alternately arranged next to each other, and n PN
By connecting the junctions in parallel, it is possible to secure the necessary surge withstand capability and reduce the size of the diode. In addition, since the width of the PN junction region is evenly arranged over all PN junctions through the opening of the high melting point insulating protective film, the surge current is not biased to any one of the PN junctions, The surge resistance of the diode can be substantially increased. Further, since the high melting point insulating protective film is disposed adjacent to the PN junction region, the protective action against the surge current can be maintained as described above.
【００２５】請求項４に記載の発明は、前記高融点絶縁
保護膜の開口部の平面形状を、前記等幅ブリッジ部を長
辺とする矩形としたことを特徴としている。これによ
り、その開口部を介して半導体中に配置される前記第１
高濃度拡散領域と前記第２高濃度拡散領域の平面形状も
前記等幅ブリッジ部に沿った方向が長手となる矩形状に
形成される。これによれば、ＰＮ接合領域が、隣り合う
矩形の第１高濃度拡散領域と第２高濃度拡散領域の間に
おいて、それらの長手方向全域にわたって等幅に形成さ
れるため、長手方向の全域にわたってサージ電流を均等
に流すことができる。従って、ダイオードのサージ耐量
を実質的に高めることができる。The invention according to claim 4 is characterized in that the plane shape of the opening of the high-melting-point insulating protective film is a rectangle having the equal width bridge portion as a long side. As a result, the first portion arranged in the semiconductor through the opening is formed.
The planar shapes of the high-concentration diffusion region and the second high-concentration diffusion region are also formed in a rectangular shape whose longitudinal direction is along the constant width bridge portion. According to this, the PN junction region is formed to have the same width over the entire area in the longitudinal direction between the rectangular first high-concentration diffusion area and the second high-concentration diffusion area adjacent to each other. Surge current can be evenly flowed. Therefore, the surge resistance of the diode can be substantially increased.
【００２６】請求項５に記載の発明は、前記第１高濃度
拡散領域を形成するための開口部と前記第２高濃度拡散
領域を形成するための開口部とは、前記等幅ブリッジに
沿った方向の長さが異なることを特徴としている。これ
により、前記第１項高濃度拡散領域と前記第２高濃度拡
散領域との長手方向の長さが異なることとなり、第１高
濃度拡散領域と第２高濃度拡散領域の角部同士の距離
は、ＰＮ接合領域の幅より長くなる。隣り合う第１項高
濃度拡散領域と第２高濃度拡散領域の長手方向の長さが
等しい場合には角部同士でサージ電流が集中し易いが、
前記のように長手方向の長さが異なるように配置するこ
とによって、角部同士では電流経路の抵抗が大きくな
り、角部同士でサージ電流の集中を回避することができ
る。According to a fifth aspect of the present invention, the opening for forming the first high-concentration diffusion region and the opening for forming the second high-concentration diffusion region are along the equal-width bridge. It is characterized by different lengths in different directions. As a result, the first term high-concentration diffusion region and the second high-concentration diffusion region have different lengths in the longitudinal direction, and the distance between the corners of the first high-concentration diffusion region and the second high-concentration diffusion region is large. Is longer than the width of the PN junction region. When the lengths of the first term high-concentration diffusion region and the second high-concentration diffusion region adjacent to each other are equal, the surge current tends to concentrate at the corners,
By arranging so that the lengths in the longitudinal direction are different as described above, the resistance of the current path between the corners becomes large, and the concentration of the surge current can be avoided between the corners.
【００２７】請求項６に記載の発明は、前記高融点絶縁
保護膜の矩形状の開口部の角部が丸められ、略矩形状に
形成されることを特徴としている。これにより、開口部
を介して形成される第１高濃度拡散領域と第２高濃度拡
散領域も、角部が丸められた略矩形状に形成されるた
め、両者の長手方向端部間の距離は、ＰＮ接合領域の幅
より長くなる。このため、第１高濃度拡散領域と第２高
濃度拡散領域の端部間でのサージ電流の集中を回避する
ことができる。The invention according to claim 6 is characterized in that the corners of the rectangular opening of the high-melting-point insulating protective film are rounded to form a substantially rectangular shape. As a result, the first high-concentration diffusion region and the second high-concentration diffusion region formed through the opening are also formed in a substantially rectangular shape with rounded corners. Is longer than the width of the PN junction region. Therefore, it is possible to avoid the concentration of the surge current between the ends of the first high concentration diffusion region and the second high concentration diffusion region.
【００２８】請求項７に記載の発明は、前記矩形の開口
部を介して矩形状に形成される第１高濃度拡散領域、第
２高濃度拡散領域の少なくとも一方の高濃度拡散領域に
おいて、長手方向における両端部の周囲に、前記一方の
高濃度拡散領域と同型の不純物によって当該一方の高濃
度拡散領域よりも低濃度の低濃度拡散領域を形成したこ
とを特徴としている。これによれば、長手方向における
両端部の周囲に同型の低濃度拡散領域を形成すること
で、当該両端部の耐圧が上り、両端部でのサージ電流の
集中を回避することができる。According to a seventh aspect of the present invention, at least one of the first high-concentration diffusion region and the second high-concentration diffusion region formed in a rectangular shape through the rectangular opening is elongated in the longitudinal direction. A low-concentration diffusion region having a lower concentration than the one high-concentration diffusion region is formed around the both ends in the direction by impurities of the same type as the one high-concentration diffusion region. According to this, by forming the low-concentration diffusion regions of the same type around the both ends in the longitudinal direction, the breakdown voltage of the both ends is increased, and the concentration of the surge current at both ends can be avoided.
【００２９】請求項８に記載の発明は、前記矩形開口部
の内側に形成され前記第１高濃度拡散領域および前記第
２高濃度拡散領域に接触するそれぞれの電極のコンタク
ト面の形状は、前記開口部の長辺をなす前記等幅ブリッ
ジ部との間隔よりも、前記開口部の短辺との間隔のほう
が大きいことを特徴としている。第１高濃度拡散領域お
よび第２高濃度拡散領域に接触する電極のコンタクト面
と高融点絶縁保護膜との間隔が、等幅ブリッジ部より矩
形の端部で大きくなっているため、端部までの電流経路
の抵抗が大きくなり、端部に流れ込む電流が減って、端
部でサージ電流の集中を回避することができる。According to an eighth aspect of the present invention, the shape of the contact surface of each electrode formed inside the rectangular opening is in contact with the first high concentration diffusion region and the second high concentration diffusion region, It is characterized in that the distance from the short side of the opening is larger than the distance from the constant width bridge portion forming the long side of the opening. Since the distance between the contact surface of the electrode in contact with the first high-concentration diffusion region and the second high-concentration diffusion region and the high-melting-point insulating protective film is larger at the rectangular end than at the equal-width bridge, The resistance of the current path is increased, the current flowing into the end portion is reduced, and the concentration of surge current can be avoided at the end portion.
【００３０】請求項９に記載の発明は、前記高融点絶縁
保護膜の開口部が、同心円状に形成されたことを特徴と
している。これにより、第１および第２の高濃度拡散領
域も同心円状に形成され、ＰＮ接合領域の幅は、隣り合
った第１高濃度拡散領域と第２高濃度拡散領域の円周の
全てにわたって等しくなり、円周の全域にわたってサー
ジ電流を半径方向に均等に流すことができる。このよう
に、ＰＮ接合領域を無駄なく配置することでダイオード
の占有面積が小さくなり、ダイオードを小型化すること
ができる。The invention according to claim 9 is characterized in that the openings of the high-melting-point insulating protective film are formed concentrically. As a result, the first and second high-concentration diffusion regions are also formed concentrically, and the width of the PN junction region is equal over the entire circumferences of the adjacent first and second high-concentration diffusion regions. Therefore, the surge current can be evenly distributed in the radial direction over the entire circumference. Thus, by arranging the PN junction region without waste, the area occupied by the diode is reduced, and the diode can be downsized.
【００３１】請求項１０に記載の発明は、前記第１高濃
度拡散領域と前記第２高濃度拡散領域を形成するための
前記高融点絶縁保護膜の開口部上に第１高濃度拡散領域
と第２高濃度拡散領域の各々に対応して形成した第1下
層電極および第２下層電極が設けられ、前記第1下層電
極および第２下層電極上に層間絶縁膜が形成され、当該
層間絶縁膜において、第1下層電極に対応して第1層間絶
縁膜開口部が形成され、第２下層電極に対応して第２層
間絶縁膜開口部が形成され、前記層間絶縁膜上に第1上
層電極および第２上層電極が形成され、第1上層電極は
前記第1層間絶縁膜開口部を介して第１高濃度拡散領域
に対応する第1下層電極に接続され、第２上層電極は前
記第２層間絶縁膜開口部を介して第２高濃度拡散領域に
対応する第２下層電極に接続されたことを特徴としてい
る。According to a tenth aspect of the present invention, a first high-concentration diffusion region is formed on an opening of the high-melting-point insulating protective film for forming the first high-concentration diffusion region and the second high-concentration diffusion region. A first lower-layer electrode and a second lower-layer electrode formed corresponding to each of the second high-concentration diffusion regions are provided, and an interlayer insulating film is formed on the first lower-layer electrode and the second lower-layer electrode. A first interlayer insulating film opening is formed corresponding to the first lower layer electrode, a second interlayer insulating film opening is formed corresponding to the second lower layer electrode, and a first upper layer electrode is formed on the interlayer insulating film. And a second upper layer electrode is formed, the first upper layer electrode is connected to the first lower layer electrode corresponding to the first high-concentration diffusion region through the first interlayer insulating film opening, and the second upper layer electrode is the second upper layer electrode. Contact the second lower layer electrode corresponding to the second high-concentration diffusion region through the interlayer insulating film opening. It is characterized in that it is.
【００３２】このように電極を２層構成にすることで、
個々の拡散領域に接続した幅の狭い下層電極に対して、
上層電極から垂直方向にサージ電流を流すことができ
る。これによって配線抵抗を十分に低減することがで
き、大きなサージ電流に対しても対応することができ、
配線が焼き切れるといった問題も発生しない。By thus forming the electrode in two layers,
For the narrow lower electrode connected to each diffusion region,
A surge current can flow vertically from the upper layer electrode. As a result, the wiring resistance can be sufficiently reduced and a large surge current can be accommodated.
The problem that the wiring is burnt out does not occur.
【００３３】請求項１１に記載の発明は、前記第1上層
電極、第２上層電極における平面内の最短幅は、それぞ
れ、前記第1下層電極、第２下層電極における平面内の
最短幅より大きいことを特徴としている。このように第
1上層電極、第２上層電極の幅を、第1下層電極、第２下
層電極より広くしてベタ形状に近づけることで、上層電
極の配線抵抗を十分に低減することができ、大きなサー
ジ電流に対しても対応することができる上層電極が得ら
れる。According to an eleventh aspect of the invention, the shortest width in the plane of the first upper layer electrode and the second upper layer electrode is larger than the shortest width in the plane of the first lower layer electrode and the second lower layer electrode, respectively. It is characterized by that. Like this
By making the widths of the 1st upper layer electrode and the 2nd upper layer electrode wider than the 1st lower layer electrode and the 2nd lower layer electrode and making them close to a solid shape, the wiring resistance of the upper layer electrode can be sufficiently reduced, and a large surge current can be obtained. As a result, an upper layer electrode that can be used is obtained.
【００３４】請求項１２に記載の発明は、前記第1上層
電極および前記第２上層電極上に保護膜が形成され、前
記第１上層電極に対応して前記保護膜に開口を形成し、
この開口部により露出される前記第１上層電極により第
1パッドを形成し、前記第２上層電極に対応して前記保
護膜に開口を形成し、この開口部により露出される前記
第２上層電極により第２パッドを形成し、前記第1パッ
ドと前記第２パッドが前記高融点絶縁保護膜の開口部を
間に挟んでその両側に配置され、前記第1上層電極と前
記第２上層電極の幅を、それぞれ、第1パッドと第２パ
ッドに近くなるほど大きくしたことを特徴としている。According to a twelfth aspect of the present invention, a protective film is formed on the first upper layer electrode and the second upper layer electrode, and an opening is formed in the protective film corresponding to the first upper layer electrode,
By the first upper layer electrode exposed by this opening,
1 pad is formed, an opening is formed in the protective film corresponding to the second upper layer electrode, and a second pad is formed by the second upper layer electrode exposed by the opening, and the first pad and the The second pads are arranged on both sides of the opening of the high melting point insulating protective film, and the widths of the first upper layer electrode and the second upper layer electrode are close to those of the first pad and the second pad, respectively. The feature is that the size is increased.
【００３５】サージ電流は一方のパッドから流入し、も
う一方のパッドから流出していくので、上層電極におい
てはそれぞれのパッドに近いほど大きなサージ電流が流
れる。従って、上層電極においてパッドに近い部分ほど
幅を大きくきくすることでサージ電流を均一に流すこと
ができ、パッド近くでのサージ電流による破壊を防ぐこ
とができる。Since the surge current flows in from one pad and flows out from the other pad, a larger surge current flows in the upper layer electrode closer to each pad. Therefore, by increasing the width of the upper electrode closer to the pad, the surge current can be made to flow uniformly, and damage due to the surge current near the pad can be prevented.
【００３６】請求項１３に記載の発明は、半導体中に配
置された前記第１高濃度拡散領域、前記第２高濃度拡散
領域、前記ＰＮ接合領域を、Ｐ型の第３高濃度拡散領域
で取り囲み、前記第３高濃度拡散領域を電極を介して接
地したことを特徴としている。これによれば、サージ電
流が大きくてＰＮ接合領域では吸収できず溢れ出た状態
になっても、ダイオードを取り囲んだＰ型の第３高濃度
拡散領域が、溢れ出たサージ電流を流す回路となる。従
って、ダイオードの周辺に形成された半導体装置におい
て、溢れ出たサージ電流によって発生する誤動作を防止
することができる。According to a thirteenth aspect of the present invention, the first high-concentration diffusion region, the second high-concentration diffusion region, and the PN junction region arranged in a semiconductor are formed by a P-type third high-concentration diffusion region. The third high-concentration diffusion region is surrounded and grounded via an electrode. According to this, even if the surge current is so large that it cannot be absorbed in the PN junction region and overflows, the P-type third high-concentration diffusion region surrounding the diode functions as a circuit for flowing the overflow surge current. Become. Therefore, in the semiconductor device formed around the diode, it is possible to prevent a malfunction caused by an overflow surge current.
【００３７】請求項１４に記載の発明は、半導体中に配
置された前記第１高濃度拡散領域、前記第２高濃度拡散
領域、前記ＰＮ接合領域を、絶縁領域で取り囲んだこと
を特徴としている。これによれば、サージ電流が大きく
てＰＮ接合領域では吸収できず溢れ出た状態になって
も、ダイオードを取り囲んだ絶縁領域が溢れ出たサージ
電流を完全に遮断する。従って、ダイオードの周辺に形
成された半導体装置において、溢れ出たサージ電流によ
って発生する誤動作を防止することができる。According to a fourteenth aspect of the present invention, the first high concentration diffusion region, the second high concentration diffusion region, and the PN junction region arranged in the semiconductor are surrounded by an insulating region. . According to this, even when the surge current is so large that it cannot be absorbed in the PN junction region and overflows, the insulating region surrounding the diode completely blocks the overflow surge current. Therefore, in the semiconductor device formed around the diode, it is possible to prevent a malfunction caused by an overflow surge current.
【００３８】請求項１５に記載の発明は、前記高融点絶
縁保護膜が、ＬＯＣＯＳ酸化膜、酸化シリコン膜、窒化
シリコン膜のいずれか１つの膜、もしくはそれらの積層
膜よりなることを特徴としている。これによれば、これ
らの高融点絶縁保護膜は、基板となるＳｉ（融点１４２
０℃）よりも高い融点を持つため、大きなサージ電流が
流れてＰＮ接合部が発熱しても、基板のＳｉより先に溶
け出すことはない。従って、一度大きなサージ電流が流
れると、絶縁作用が劣化してその後使用できなくなると
いったことがなく、サージ電流に対する保護作用を持続
することができる。According to a fifteenth aspect of the present invention, the refractory insulating protective film is formed of any one film of a LOCOS oxide film, a silicon oxide film, a silicon nitride film, or a laminated film thereof. . According to this, these high melting point insulating protective films are formed of Si (melting point 142) which becomes a substrate.
Since it has a melting point higher than 0 ° C.), even if a large surge current flows and the PN junction section generates heat, it does not melt before Si of the substrate. Therefore, once a large surge current flows, the insulating action does not deteriorate and the device cannot be used thereafter, and the protective action against the surge current can be continued.
【００３９】請求項１６に記載の発明は、半導体上に配
置され、２本の等幅ブリッジ部で分割される３個の開口
部を備える高融点絶縁保護膜を設ける工程と、前記３個
の開口部の中央の開口部を介して半導体中に不純物をイ
オン注入して、Ｐ型またはＮ型からなる第１高濃度拡散
領域を形成する工程と、前記３個の開口部の両端の開口
部を介して半導体中に不純物をイオン注入して、第１高
濃度拡散領域とは逆型の、Ｐ型またはＮ型からなる第２
高濃度拡散領域を２個形成する工程と、前記２個の第２
高濃度拡散領域同士を電極を介して互いに接続する工程
とを有することを特徴としている。According to a sixteenth aspect of the present invention, there is provided a step of providing a high melting point insulating protective film having three openings arranged on a semiconductor and divided by two equal-width bridge portions, and the three steps. A step of ion-implanting impurities into a semiconductor through an opening at the center of the opening to form a P-type or N-type first high-concentration diffusion region; and openings at both ends of the three openings. An impurity is ion-implanted into the semiconductor via the second impurity of the P-type or N-type, which is the opposite type to the first high-concentration diffusion region.
A step of forming two high-concentration diffusion regions, and a step of forming the two second
And a step of connecting the high-concentration diffusion regions to each other via electrodes.
【００４０】この製造方法によれば、第1高濃度拡散領
域の形成工程とその両側に配置される第２高濃度拡散領
域の形成工程において、同じ高融点絶縁保護膜がイオン
注入のマスクとして用いられるので、２枚のマスクを使
用した際に起きる位置合わせずれの問題が発生しない。
従って、第1高濃度拡散領域と第２高濃度拡散領域の間
に形成される２本のＰＮ接合領域の幅も、設計どおりに
等しく形成することができる。これにより、並列接続さ
れているＰＮ接合の一方にサージ電流が偏ることがな
く、サージ耐量の高いダイオードを製造することができ
る。According to this manufacturing method, the same high melting point insulating protective film is used as a mask for ion implantation in the step of forming the first high-concentration diffusion region and the step of forming the second high-concentration diffusion regions arranged on both sides thereof. Therefore, the problem of misalignment that occurs when two masks are used does not occur.
Therefore, the widths of the two PN junction regions formed between the first high concentration diffusion region and the second high concentration diffusion region can also be formed equal as designed. As a result, the surge current is not biased to one of the PN junctions connected in parallel, and a diode having a high surge resistance can be manufactured.
【００４１】また、半導体上に形成された高融点絶縁保
護膜の３個の開口部に、Ｐ型不純物とＮ型不純物をイオ
ン注入して第１高濃度拡散領域と第２高濃度拡散領域を
形成しているので、第１高濃度拡散領域と第２高濃度拡
散領域の間の半導体からなるＰＮ接合領域には、高融点
絶縁保護膜が隣接して配置されることになる。このよう
にして製造されたダイオードにおいては、ＰＮ接合領域
に大きなサージ電流が流れても、高融点絶縁保護膜が基
板となるＳｉより先に溶け出すことはない。従って、一
度大きなサージ電流が流れても高融点絶縁保護膜の絶縁
作用が劣化することがなく、繰り返し使用が可能なダイ
オードを製造することができる。Further, P-type impurities and N-type impurities are ion-implanted into the three openings of the high melting point insulating protective film formed on the semiconductor to form the first high concentration diffusion region and the second high concentration diffusion region. Since it is formed, the high melting point insulating protective film is arranged adjacent to the PN junction region made of the semiconductor between the first high concentration diffusion region and the second high concentration diffusion region. In the diode manufactured in this manner, even if a large surge current flows in the PN junction region, the high-melting point insulating protective film does not melt out before Si serving as the substrate. Therefore, even if a large surge current flows once, the insulating action of the high melting point insulating protective film does not deteriorate, and a diode that can be repeatedly used can be manufactured.
【００４２】請求項１７に記載の発明は、半導体上に配
置され、２本の等幅ブリッジ部で分割される３個の開口
部を１組の開口群として、前記開口群をｍ組備える高融
点絶縁保護膜を設ける工程と、前記ｍ組の開口群の各々
の中央の開口部を介して半導体中に不純物をイオン注入
して、Ｐ型またはＮ型からなる第１高濃度拡散領域をｍ
個形成する工程と、前記ｍ組の開口群の各々の両端の開
口部を介して半導体中に不純物をイオン注入して、第１
高濃度拡散領域とは逆型の、Ｐ型またはＮ型からなる第
２高濃度拡散領域を２ｍ個形成する工程と、前記ｍ個の
第１高濃度拡散領域同士を電極を介して互いに接続する
工程と、前記２ｍ個の第２高濃度拡散領域同士を電極を
介して互いに接続する工程とを有することを特徴として
いる。According to a seventeenth aspect of the present invention, a set of three openings arranged on a semiconductor and divided by two equal-width bridge portions is one set of opening groups, and m sets of the opening groups are provided. A step of providing a melting point insulating protective film and ion implantation of impurities into the semiconductor through the central opening of each of the m sets of openings to form a first high-concentration diffusion region of P type or N type.
A step of individually forming and ion-implanting impurities into the semiconductor through the openings at both ends of each of the m sets of openings,
A step of forming 2m second P-type or N-type second high-concentration diffusion regions opposite to the high-concentration diffusion regions, and connecting the m first high-concentration diffusion regions to each other through electrodes. The method is characterized by including a step and a step of connecting the 2m second high-concentration diffusion regions to each other through an electrode.
【００４３】この製造方法によれば、第1高濃度拡散領
域と第２高濃度拡散領域の間に形成される２ｍ本の並列
接続されたＰＮ接合領域の幅を、全て設計どおりに等し
く形成することができる。これにより、並列接続されて
いるＰＮ接合のどれか１本にサージ電流が偏ることがな
く、大きなサージ電流に対しても必要なサージ耐量をも
ったダイオードを製造することができる。また、ＰＮ接
合領域には高融点絶縁保護膜が隣接して配置されるた
め、一度大きなサージ電流が流れても高融点絶縁保護膜
の絶縁作用が劣化することがなく、繰り返し使用が可能
なダイオードを製造することができる。According to this manufacturing method, the widths of the 2m parallel-connected PN junction regions formed between the first high concentration diffusion region and the second high concentration diffusion region are all made equal as designed. be able to. As a result, the surge current is not biased to any one of the PN junctions connected in parallel, and it is possible to manufacture a diode having a necessary surge withstand capability even for a large surge current. Further, since the high melting point insulating protective film is arranged adjacent to the PN junction region, the insulating action of the high melting point insulating protective film does not deteriorate even if a large surge current flows once, and the diode can be used repeatedly. Can be manufactured.
【００４４】請求項１８に記載の発明は、半導体上に配
置され、ｎ本の等幅ブリッジ部で分割される（ｎ＋１）
個の開口部を備える高融点絶縁保護膜を設ける工程と、
前記（ｎ＋１）個の開口部のうち、１つおきに位置する
開口部からなる第１の開口群の各々の開口部を介して半
導体中に不純物をイオン注入して、Ｐ型またはＮ型から
なる第１高濃度拡散領域を複数個形成する工程と、前記
第１の開口群の各々の開口部に隣接する、１つおきに位
置する開口部からなる第２の開口群の各々の開口部を介
して半導体中に不純物をイオン注入して、第１高濃度拡
散領域とは逆型の、Ｐ型またはＮ型からなる第２高濃度
拡散領域を複数個形成する工程と、前記複数個の第１高
濃度拡散領域同士を電極を介して互いに接続する工程
と、前記複数個の第２高濃度拡散領域同士を電極を介し
て互いに接続する工程とを有することを特徴としてい
る。The invention described in claim 18 is arranged on a semiconductor and divided by n equal-width bridge portions (n + 1).
A step of providing a high melting point insulating protective film having individual openings,
Impurities are ion-implanted into the semiconductor through each opening of the first opening group consisting of the openings located at every other opening out of the (n + 1) openings, Forming a plurality of the first high-concentration diffusion regions, and each opening of the second opening group, which is adjacent to each of the openings of the first opening group and is formed of every other opening. Forming a plurality of second high-concentration diffusion regions of P-type or N-type opposite to the first high-concentration diffusion region by ion implantation of impurities into the semiconductor via The method is characterized by including a step of connecting the first high-concentration diffusion regions to each other via electrodes and a step of connecting the plurality of second high-concentration diffusion regions to each other via electrodes.
【００４５】この製造方法によれば、隣り合って交互に
配置された第１高濃度拡散領域と第２高濃度拡散領域で
形成されるＰＮ接合領域の幅を、全て設計どおりに等し
く形成することができる。これにより、並列接続されて
いるＰＮ接合のどれか１個にサージ電流が偏ることがな
く、大きなサージ電流に対しても必要なサージ耐量をも
った小型のダイオードを製造することができる。また、
ＰＮ接合領域には高融点絶縁保護膜が隣接して配置され
るため、一度大きなサージ電流が流れても高融点絶縁保
護膜の絶縁作用が劣化することがなく、繰り返し使用が
可能なダイオードを製造することができる。According to this manufacturing method, the widths of the PN junction regions formed by the first high-concentration diffusion regions and the second high-concentration diffusion regions that are alternately arranged adjacent to each other are all formed as designed. You can As a result, the surge current is not biased to any one of the PN junctions connected in parallel, and it is possible to manufacture a small-sized diode having a necessary surge withstanding capability even for a large surge current. Also,
Since the high melting point insulating protective film is placed adjacent to the PN junction region, the insulation function of the high melting point insulating protective film does not deteriorate even if a large surge current flows once, and a diode that can be used repeatedly is manufactured. can do.
【００４６】請求項１９に記載の発明は、前記高融点絶
縁保護膜が、ＬＯＣＯＳ酸化膜、酸化シリコン膜、窒化
シリコン膜のいずれか１つの膜、もしくはそれらの積層
膜よりなることを特徴としている。これによれば、これ
らの高融点絶縁保護膜が基板となるＳｉ（融点１４２０
℃）よりも高い融点を持つため、大きなサージ電流が流
れてＰＮ接合部が発熱しても、基板のＳｉより先に溶け
出すことがない。このため、サージ耐量の高いダイオー
ドを製造することができる。According to the nineteenth aspect of the present invention, the refractory insulating protective film is formed of any one film of a LOCOS oxide film, a silicon oxide film, a silicon nitride film, or a laminated film thereof. . According to this, Si (melting point 1420) on which these high melting point insulating protective films serve as a substrate
Since it has a melting point higher than (.degree. C.), even if a large surge current flows and the PN junction section generates heat, it does not melt before Si of the substrate. Therefore, it is possible to manufacture a diode having a high surge resistance.
【００４７】[0047]
【発明の実施の形態】以下、本発明の実施の形態を、図
に基づいて説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.
【００４８】（第１の実施形態）図１に、第1の実施形
態におけるＰＮ接合ダイオードを示す。図１（ａ）は本
実施形態におけるＰＮ接合ダイオードの平面図であり、
図１（ｂ）は、図１（ａ）におけるＡ−Ａ’線に沿った
拡大断面図である。尚、図１４に示した従来のＰＮ接合
ダイオードと同様の部分については同一の符号をつけ、
その説明を省略する。(First Embodiment) FIG. 1 shows a PN junction diode according to the first embodiment. FIG. 1A is a plan view of the PN junction diode according to the present embodiment,
FIG. 1B is an enlarged cross-sectional view taken along the line AA ′ in FIG. Incidentally, the same parts as those of the conventional PN junction diode shown in FIG.
The description is omitted.
【００４９】図１に示すＰＮ接合ダイオードにおいて
も、図１４に示した従来のＰＮ接合ダイオードと同様
に、低濃度Ｎ型シリコン（半導体）基板１にベースとな
るＰ型高濃度拡散領域２が配置され、そのベースの両側
にエミッタとなるＮ型高濃度拡散領域３ａ，３ｂが配置
されている。低濃度Ｎ型シリコン（半導体）基板１の不
純物はリン（Ｐ）で、濃度は約１×１０15ｃｍ-3であ
る。また、図１（ａ）の平面図において各高濃度拡散領
域２，３ａ，３ｂは約１０μｍ×５００μｍの矩形状で
ある。ベースとエミッタの間の半導体部分がＰＮ接合領
域４ａ，４ｂとなってＰＮ接合ダイオードが構成される
点も、従来と同様である。In the PN junction diode shown in FIG. 1 as well, as in the conventional PN junction diode shown in FIG. 14, a P type high concentration diffusion region 2 serving as a base is arranged on a low concentration N type silicon (semiconductor) substrate 1. The N-type high-concentration diffusion regions 3a and 3b serving as emitters are arranged on both sides of the base. The impurity of the low-concentration N-type silicon (semiconductor) substrate 1 is phosphorus (P), and the concentration is about 1 × 10 15 cm −3 . Further, in the plan view of FIG. 1A, each of the high-concentration diffusion regions 2, 3a, 3b has a rectangular shape of about 10 μm × 500 μm. The semiconductor portion between the base and the emitter serves as the PN junction regions 4a and 4b to form a PN junction diode, which is also similar to the conventional case.
【００５０】一方、図１に示す本実施形態のＰＮ接合ダ
イオードにおいては、図１４に示す従来のＰＮ接合ダイ
オードと異なり、ＰＮ接合領域４ａ，４ｂが高融点絶縁
保護膜であるＬＯＣＯＳ酸化膜のブリッジ部５００ａ，
５００ｂの下に配置されている。また、ブリッジ部５０
０ａ，５００ｂの幅Ｌ1a，Ｌ1bは等しく形成され、その
下に配置されたＰＮ接合領域４ａ，４ｂの幅Ｌca，Ｌcb
も等しく形成されている。図１（ａ）の平面図におい
て、３個のＬＯＣＯＳ開口部５０は、実線で示されてい
る。図１に示すＬＯＣＯＳ酸化膜のブリッジ部の幅
Ｌla，Ｌlbは、通常Ｌ la＝Ｌlb＝３μｍ程度に設定す
る。On the other hand, the PN junction device of this embodiment shown in FIG.
In iodine, the conventional PN junction die shown in FIG.
Unlike ode, PN junction regions 4a and 4b have high melting point insulation
A bridge portion 500a of a LOCOS oxide film which is a protective film,
It is located below 500b. Also, the bridge section 50
Width L of 0a and 500b1a, L1bAre formed equally and their
The width L of the PN junction regions 4a and 4b arranged belowca, Lcb
Are also formed equally. The plan view of Figure 1 (a)
The three LOCOS openings 50 are shown in solid lines.
It Width of bridge part of LOCOS oxide film shown in FIG.
Lla, LlbIs usually L la= Llb= Set to about 3 μm
It
【００５１】また、Ｐ型高濃度拡散領域２とＮ型高濃度
拡散領域３ａ，３ｂには、それぞれ、図１（ｂ）に示す
ように、ＢＰＳＧからなる下層の層間絶縁膜５の開口部
を介して、Ａｌからなる下層電極７ａ，７ｂが接続され
るが、各々の下層電極７ａ，７ｂは、それぞれＴＥＯＳ
からなる上層の層間絶縁膜８の開口部を介して、Ａｌか
らなる上層電極９ａ，９ｂに接続される。Further, in the P-type high-concentration diffusion region 2 and the N-type high-concentration diffusion regions 3a and 3b, as shown in FIG. 1B, the openings of the lower interlayer insulating film 5 made of BPSG are formed. The lower layer electrodes 7a and 7b made of Al are connected to each other via the lower layer electrodes 7a and 7b.
Is connected to upper layer electrodes 9a and 9b made of Al through an opening of an upper interlayer insulating film 8 made of.
【００５２】図１（ａ）の平面図において、下層電極７
ａ，７ｂと上層電極９ａ，９ｂは、それぞれ実線で示さ
れている。また、各高濃度拡散領域と各下層電極のコン
タクト領域７１，７２，７３、および下層電極と上層電
極のコンタクト領域９１，９２，９３は、それぞれ点線
で示されている。各高濃度拡散領域と各下層電極のコン
タクト領域７１，７２，７３は、ＬＯＣＯＳ開口部５０
との間隔（Ｌx，Ｌy）が、全周に渡って等しくなるよう
に（Ｌx＝Ｌy）配置されている。In the plan view of FIG. 1A, the lower layer electrode 7
a and 7b and upper layer electrodes 9a and 9b are shown by solid lines, respectively. Further, the contact regions 71, 72, 73 of the high-concentration diffusion regions and the lower-layer electrodes, and the contact regions 91, 92, 93 of the lower-layer electrodes and the upper-layer electrodes are respectively indicated by dotted lines. The contact regions 71, 72, 73 of the high-concentration diffusion regions and the lower-layer electrodes are formed in the LOCOS openings 50.
Are arranged so that the distances (L x , L y ) between and are equal over the entire circumference (L x = L y ).
【００５３】図１（ａ）に示すように、Ｐ型の高濃度拡
散領域２に対応する下層電極７ａはベースの上層電極９
ａに接続されており、Ｎ型の高濃度拡散領域３ａ，３ｂ
に対応する下層電極７ｂは、エミッタの上層電極９ｂに
接続されている。また、ダイオード全体はＳｉＮからな
る保護膜１０によって被覆され、保護膜１０の開口部に
形成された図１（ａ）に実線で示すパッド９０ａ，９０
ｂを介して、外部に接続される。As shown in FIG. 1A, the lower layer electrode 7a corresponding to the P type high concentration diffusion region 2 is the upper layer electrode 9 of the base.
N-type high-concentration diffusion regions 3a and 3b connected to a
The lower layer electrode 7b corresponding to is connected to the upper layer electrode 9b of the emitter. The entire diode is covered with a protective film 10 made of SiN, and pads 90a, 90 shown by solid lines in FIG. 1A are formed in the openings of the protective film 10.
It is connected to the outside through b.
【００５４】尚、上層電極９ａ，９ｂは矩形形状で電極
幅Ｌea，Ｌebが等しく設定されており（Ｌea＝Ｌeb）、
３個並んだＬＯＣＯＳ開口部５０を横断して、ＬＯＣＯ
Ｓ開口部５０を等しく２分するように配置されている。
また、パッド９０ａ，９０ｂは、３個並んだＬＯＣＯＳ
開口部５０の一方の端の開口部の外側に、並んで配置さ
れている。The upper-layer electrodes 9a and 9b have a rectangular shape and the electrode widths L ea and L eb are set to be equal (L ea = L eb ).
Cross the three LOCOS openings 50,
The S openings 50 are arranged so as to equally divide them into two.
In addition, the pads 90a and 90b are three LOCOSs arranged side by side.
The openings 50 are arranged side by side outside the opening at one end of the opening 50.
【００５５】次に、図１に示したＰＮ接合ダイオードの
製造方法を、図２に従って説明する。図２は、図１
（ａ）におけるＡ−Ａ’線に沿った拡大断面を、製造工
程順に示したものである。また、図２に示すＰＮ接合ダ
イオードの製造は、同じ基板の別位置に形成されるＣＭ
ＯＳ半導体装置の製造と同時に行なわれるので、図３に
示したＣＭＯＳ半導体装置の製造工程を参照しながら、
図２のＰＮ接合ダイオードの製造工程を説明する。Next, a method for manufacturing the PN junction diode shown in FIG. 1 will be described with reference to FIG. 2 is shown in FIG.
The enlarged cross section along the line AA ′ in (a) is shown in the order of manufacturing steps. Further, the PN junction diode shown in FIG. 2 is manufactured by using a CM formed on another position of the same substrate.
Since it is performed at the same time as the manufacturing of the OS semiconductor device, referring to the manufacturing process of the CMOS semiconductor device shown in FIG.
The manufacturing process of the PN junction diode of FIG. 2 will be described.
【００５６】最初に、図２（ａ）に示す低濃度Ｎ型シリ
コン（半導体）基板１を用意する。低濃度Ｎ型シリコン
（半導体）基板１は、不純物としてリン（Ｐ）を含有し
ており、その濃度は１×１０15ｃｍ-3程度である。一
方、図３（ａ）に示すように、ＣＭＯＳ形成位置では、
最初に、ＮチャンネルＭＯＳ部に１×１０13ｃｍ-2の条
件でボロン（Ｂ）をイオン注入して、Ｐ型ウェル領域２
０１を形成しておく。また、同様にして、Ｐチャンネル
ＭＯＳ部に１×１０13ｃｍ-2の条件でリン（Ｐ）をイオ
ン注入して、Ｎ型ウェル領域３０１を形成しておく。First, a low concentration N-type silicon (semiconductor) substrate 1 shown in FIG. 2A is prepared. The low-concentration N-type silicon (semiconductor) substrate 1 contains phosphorus (P) as an impurity, and its concentration is about 1 × 10 15 cm −3 . On the other hand, as shown in FIG. 3A, at the CMOS formation position,
First, boron (B) is ion-implanted into the N-channel MOS portion under the condition of 1 × 10 13 cm −2 to form the P-type well region 2
01 is formed. Further, similarly, phosphorus (P) is ion-implanted into the P-channel MOS portion under the condition of 1 × 10 13 cm −2 to form the N-type well region 301.
【００５７】次に、図２（ｂ）と図３（ｂ）に示すよう
に、高融点絶縁保護膜となる所定の開口部を有するＬＯ
ＣＯＳ酸化膜５００，５００ａ，５００ｂを形成する。
ＬＯＣＯＳ酸化膜５００，５００ａ，５００ｂの形成
は、通常用いられている以下の手順で行なう。最初に、
低濃度Ｎ型シリコン（半導体）基板１上の全面に熱酸化
時のマスクとなるＳｉＮ膜を積層し、所定の開口部を形
成したレジストをマスクにしてＳｉＮ膜をエッチング
し、ＬＯＣＯＳ形成部に対応する部分を開口させる。つ
いで、ＳｉＮ膜の開口部に露出したシリコン表面を熱酸
化させてＬＯＣＯＳ酸化膜を形成し、最後にＳｉＮ膜を
除去する。ＬＯＣＯＳ酸化膜の厚さは、約０．６μｍで
ある。図３（ｂ）に示すように、ＣＭＯＳ形成位置では
ＬＯＣＯＳ酸化膜５００を形成した後、さらに酸化シリ
コン膜からなるゲート酸化膜６０１とポリシリコン膜か
らなるゲート電極６０２を、通常用いられる方法で形成
する。Next, as shown in FIGS. 2 (b) and 3 (b), the LO having a predetermined opening serving as a high melting point insulating protective film is formed.
COS oxide films 500, 500a and 500b are formed.
The LOCOS oxide films 500, 500a and 500b are formed by the following procedure which is usually used. At first,
A SiN film serving as a mask at the time of thermal oxidation is laminated on the entire surface of the low-concentration N-type silicon (semiconductor) substrate 1, and the SiN film is etched by using a resist having a predetermined opening as a mask to correspond to a LOCOS forming portion. Open the part to be opened. Then, the silicon surface exposed in the opening of the SiN film is thermally oxidized to form a LOCOS oxide film, and finally the SiN film is removed. The LOCOS oxide film has a thickness of about 0.6 μm. As shown in FIG. 3B, after the LOCOS oxide film 500 is formed at the CMOS formation position, a gate oxide film 601 made of a silicon oxide film and a gate electrode 602 made of a polysilicon film are further formed by a commonly used method. To do.
【００５８】次に、図２（ｃ）に示すように、エミッタ
に対応したＬＯＣＯＳ酸化膜の開口部を第1のレジスト
１０２により覆った後、ＬＯＣＯＳ酸化膜を実質的なマ
スクとして、ベースに対応した開口部から２×１０14ｃ
ｍ-2の条件でボロン（Ｂ）をイオン注入する。その後、
１０００℃以上で数時間熱処理して、ベースとなるＰ型
高濃度拡散領域２を形成する。Ｐ型高濃度拡散領域２の
拡散深さは、約３μｍである。これと同時に、図３
（ｃ）に示すように、ＣＭＯＳ形成位置ではＰチャンネ
ルに対応したＰ型高濃度拡散領域２１，２２を形成す
る。Next, as shown in FIG. 2C, after covering the opening of the LOCOS oxide film corresponding to the emitter with the first resist 102, the LOCOS oxide film is used as a substantial mask to correspond to the base. 2 × 10 14 c from the opening
Boron (B) is ion-implanted under the condition of m −2 . afterwards,
A heat treatment is performed at 1000 ° C. or higher for several hours to form a P-type high concentration diffusion region 2 serving as a base. The diffusion depth of the P-type high concentration diffusion region 2 is about 3 μm. At the same time, as shown in FIG.
As shown in (c), P-type high-concentration diffusion regions 21 and 22 corresponding to P-channels are formed at the CMOS formation positions.
【００５９】次に、図２（ｄ）に示すように、第１のレ
ジスト１０２を除去した後、ベースに対応したＬＯＣＯ
Ｓ酸化膜の開口部を第２のレジスト１０３によりにより
覆った後、ＬＯＣＯＳ酸化膜を実質的なマスクとして、
エミッタに対応した開口部から４×１０16ｃｍ-2の条件
でリン（Ｐ）をイオン注入する。その後、１０００℃以
上で１時間程度熱処理して、エミッタとなるＮ型高濃度
拡散領域３ａ，３ｂをベースとなるＰ型高濃度拡散領域
２の両側に形成する。Ｎ型高濃度拡散領域３ａ，３ｂの
拡散深さは、約２μｍである。これにより、Ｐ型高濃度
拡散領域２とＮ型高濃度拡散領域３ａ，３ｂの間の半導
体部分が、ＰＮ接合領域４ａ，４ｂとなる。これと同時
に、図３（ｄ）に示すように、ＣＭＯＳ形成位置ではＮ
チャンネルに対応したＮ型高濃度拡散領域３１，３２を
形成する。Next, as shown in FIG. 2D, after removing the first resist 102, the LOCO corresponding to the base is removed.
After covering the opening of the S oxide film with the second resist 103, the LOCOS oxide film is used as a substantial mask.
Phosphorus (P) is ion-implanted from the opening corresponding to the emitter under the condition of 4 × 10 16 cm −2 . Then, heat treatment is performed at 1000 ° C. or higher for about 1 hour to form the N-type high-concentration diffusion regions 3a and 3b serving as emitters on both sides of the P-type high-concentration diffusion region 2 serving as a base. The diffusion depth of the N-type high concentration diffusion regions 3a and 3b is about 2 μm. As a result, the semiconductor portion between the P-type high-concentration diffusion region 2 and the N-type high-concentration diffusion regions 3a and 3b becomes the PN junction regions 4a and 4b. At the same time, as shown in FIG. 3D, at the CMOS formation position, N
N-type high concentration diffusion regions 31 and 32 corresponding to the channels are formed.
【００６０】次に、図２（ｅ）に示すように、第２のレ
ジスト１０３を除去した後、下層の層間絶縁膜５として
ＢＰＳＧ膜を全面に積層し、Ｐ型高濃度拡散領域２とＮ
型高濃度拡散領域３ａ，３ｂに接続するための開口部６
１，６２，６３を形成する。ＢＰＳＧ膜の厚さは、約
０．６μｍである。Next, as shown in FIG. 2E, after removing the second resist 103, a BPSG film is laminated as the lower interlayer insulating film 5 on the entire surface, and the P-type high concentration diffusion region 2 and the N-type high concentration diffusion region 2 are formed.
Opening 6 for connecting to the high-concentration diffusion regions 3a and 3b
1, 62, 63 are formed. The thickness of the BPSG film is about 0.6 μm.
【００６１】次に、図２（ｆ）に示すように、Ａｌ膜を
全面に約１μｍの厚さで積層した後、所定形状にパター
ニングして、下層電極７ａ，７ｂを形成する。Next, as shown in FIG. 2F, an Al film is laminated on the entire surface to a thickness of about 1 μm, and then patterned into a predetermined shape to form lower layer electrodes 7a and 7b.
【００６２】図３（ｅ）に示すＣＭＯＳ形成位置におい
ても、図２（ｅ）と図２（ｆ）の工程により、ＢＰＳＧ
膜からなる下層の層間絶縁膜５とＡｌからなる下層電極
７を形成する。Also in the CMOS formation position shown in FIG. 3E, the BPSG is performed by the steps of FIG. 2E and FIG.
A lower interlayer insulating film 5 made of a film and a lower electrode 7 made of Al are formed.
【００６３】次に、図２（ｇ）に示すように、上層の層
間絶縁膜８としてのＴＥＯＳ膜を積層した後、各々の下
層電極７ａ，７ｂに対応した開口部を形成し、全面にＡ
ｌ膜を積層する。その後、Ａｌ膜を所定形状にパターニ
ングして、上層電極９ａ，９ｂを形成する。最後に、全
面に保護膜１０としてのＳｉＮ膜を積層した後、外部に
接続するためのパッド用開口部を形成して、図１に示し
たＰＮ接合ダイオードが完成する。尚、図３に示すＣＭ
ＯＳ形成位置においては、図３（ｅ）に示す工程以降、
図２（ｇ）と同様の工程を経て、ＣＭＯＳ半導体装置が
完成される（図は省略）。Next, as shown in FIG. 2G, after a TEOS film as an upper interlayer insulating film 8 is laminated, openings corresponding to the lower layer electrodes 7a and 7b are formed, and A is formed on the entire surface.
1 film is laminated. Then, the Al film is patterned into a predetermined shape to form upper layer electrodes 9a and 9b. Finally, after depositing a SiN film as the protective film 10 on the entire surface, a pad opening for connecting to the outside is formed, and the PN junction diode shown in FIG. 1 is completed. The CM shown in FIG.
At the OS formation position, after the step shown in FIG.
A CMOS semiconductor device is completed (illustration is omitted) through the same steps as those in FIG.
【００６４】以上の図２に示した製造方法によれば、ベ
ースであるＰ型高濃度拡散領域２とエミッタであるＮ型
高濃度拡散領域３ａ，３ｂが、同じＬＯＣＯＳをマスク
にしてイオン注入される。このように、図２の工程では
マスクのアライメント操作がないため、図１５の従来の
工程で起こり得るマスクのアライメントずれは存在しな
い。従って、ＬＯＣＯＳの左右ブリッジ部５００ａ，５
００ｂの幅Ｌ1a，Ｌ1bを同じに設定しておけば、不純物
拡散後の左右のＰＮ接合領域の幅Ｌca，Ｌcbも同じにな
る。これによって、左右のＰＮ接合領域４ａ，４ｂの耐
圧も均一になる。また、左右のＰＮ接合領域４ａ，４ｂ
は融点の高いＬＯＣＯＳ酸化膜下に形成されることにな
るので、サージ印加時に起きるＰＮ接合領域４ａ，４ｂ
の温度上昇にも耐えることができる。According to the manufacturing method shown in FIG. 2, the P-type high-concentration diffusion region 2 as the base and the N-type high-concentration diffusion regions 3a and 3b as the emitters are ion-implanted using the same LOCOS as a mask. It As described above, since there is no mask alignment operation in the process of FIG. 2, there is no mask misalignment that may occur in the conventional process of FIG. Therefore, the left and right bridge portions 500a, 5 of the LOCOS
If the widths L 1a and L 1b of 00b are set to be the same, the widths L ca and L cb of the left and right PN junction regions after impurity diffusion are also the same. As a result, the breakdown voltages of the left and right PN junction regions 4a and 4b also become uniform. Also, the left and right PN junction regions 4a and 4b
Is formed under the LOCOS oxide film having a high melting point, so that the PN junction regions 4a and 4b that occur at the time of applying a surge are formed.
It can withstand the temperature rise.
【００６５】（第２の実施形態）第１の実施形態では、
ＰＮ接合領域を覆う等幅のブリッジ部を持つＬＯＣＯＳ
酸化膜を基礎として、ベースとなるＰ型高濃度拡散領域
の両側にエミッタとなるＮ型高濃度拡散領域が配置され
たＰＮ接合ダイオードの構造、およびその製造方法を示
した。半導体装置の入出力保護素子としてのＰＮ接合ダ
イオードでは、大きなサージ電流に対応するために、通
常は図１に示すＰＮ接合ダイオードが数１０個並列接続
される。第２の実施形態では、前記第１の実施形態のＰ
Ｎ接合ダイオードが複数個並列接続された構造を持つＰ
Ｎ接合ダイオードに関する。以下、第１の実施形態のＰ
Ｎ接合ダイオードが３個並列配置されたＰＮ接合ダイオ
ードを一例として、本実施形態について図に基づいて説
明する。(Second Embodiment) In the first embodiment,
LOCOS with a bridge of equal width covering the PN junction region
The structure of a PN junction diode in which an N-type high-concentration diffusion region serving as an emitter is arranged on both sides of a P-type high-concentration diffusion region serving as a base on the basis of an oxide film, and a manufacturing method thereof are shown. In a PN junction diode as an input / output protection element of a semiconductor device, several tens of PN junction diodes shown in FIG. 1 are usually connected in parallel in order to cope with a large surge current. In the second embodiment, P of the first embodiment is used.
P having a structure in which a plurality of N-junction diodes are connected in parallel
It relates to an N-junction diode. Hereinafter, P of the first embodiment
This embodiment will be described with reference to the drawings by taking a PN junction diode in which three N junction diodes are arranged in parallel as an example.
【００６６】図４は、本実施形態におけるＰＮ接合ダイ
オードの平面図である。第１の実施形態と同様の部分に
ついては、同一の符号をつけ、その説明を省略する。FIG. 4 is a plan view of the PN junction diode according to this embodiment. The same parts as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.
【００６７】図４に示すように、第２の実施形態では、
３個のＰ型高濃度拡散領域２１，２２，２３の各々を中
心として、その両側に各々２個のＮ型高濃度拡散領域３
１ａ，３１ｂ，３２ａ，３２ｂ，３３ａ，３３ｂが配置
されており、図中のＬＯＣＯＳ酸化膜のブリッジ部５０
１ａ，５０１ｂ，５０２ａ，５０２ｂ，５０３ａ，５０
３ｂの幅Ｌ1a，Ｌ1b，Ｌ2a，Ｌ2b，Ｌ3a，Ｌ3bは、全て
等しく設定されている。また、３個のＰ型高濃度拡散領
域２１，２２，２３同士は上層電極９ａによって接続さ
れており、６個のＮ型高濃度拡散領域３１ａ，３１ｂ，
３２ａ，３２ｂ，３３ａ，３３ｂ同士は上層電極９ｂに
よって接続されている。本実施形態の図４に示すＰＮ接
合ダイオードは、第１実施形態の図２に示した製造方法
によって、同じように製造することができる。As shown in FIG. 4, in the second embodiment,
Each of the three P-type high-concentration diffusion regions 21, 22, and 23 is centered, and two N-type high-concentration diffusion regions 3 are provided on each side of the center.
1a, 31b, 32a, 32b, 33a, 33b are arranged, and the bridge portion 50 of the LOCOS oxide film in the figure is arranged.
1a, 501b, 502a, 502b, 503a, 50
The widths L 1a , L 1b , L 2a , L 2b , L 3a and L 3b of 3b are all set to be equal. Further, the three P-type high-concentration diffusion regions 21, 22, 23 are connected to each other by the upper layer electrode 9a, and the six N-type high-concentration diffusion regions 31a, 31b,
32a, 32b, 33a and 33b are connected to each other by the upper layer electrode 9b. The PN junction diode of this embodiment shown in FIG. 4 can be similarly manufactured by the manufacturing method shown in FIG. 2 of the first embodiment.
【００６８】本実施形態においても、高融点絶縁保護膜
であるＬＯＣＯＳ酸化膜において、ＰＮ接合領域を覆う
６本のブリッジ部の幅Ｌ1a，Ｌ1b，Ｌ2a，Ｌ2b，Ｌ3a，
Ｌ3bが等しく設定されているので、同じＬＯＣＯＳ酸化
膜をマスクにしてイオン注入により形成された６本のＰ
Ｎ接合領域の幅も、全てに渡って等しくなる。これによ
って、６本のＰＮ接合領域の耐圧も全てに渡って等しく
なり、このような耐圧の等しいＰＮ接合領域を６個並列
接続した図４のＰＮ接合ダイオードは、図１に示したＰ
Ｎ接合ダイオードに比べて、サージ電流に対して３倍の
許容量を確保することができる。Also in the present embodiment, in the LOCOS oxide film which is the high melting point insulating protective film, the widths L 1a , L 1b , L 2a , L 2b , L 3a , of the six bridge portions covering the PN junction region,
Since L 3b is set to be equal, 6 Ps formed by ion implantation using the same LOCOS oxide film as a mask
The width of the N-junction region is also the same throughout. As a result, the breakdown voltages of the six PN junction regions become equal over all, and the PN junction diode of FIG. 4 in which six PN junction regions having the same breakdown voltage are connected in parallel is the same as the P diode shown in FIG.
As compared with the N-junction diode, it is possible to secure a tolerable amount three times as large as the surge current.
【００６９】図４に例示したＰＮ接合ダイオードでは、
６本のＰＮ接合領域を並列接続した。半導体装置の入出
力保護素子としてのＰＮ接合ダイオードでは、サージ電
流に対する必要な許容量を確保するために、通常は図４
に示したＰＮ接合領域が数１０本並列接続される。この
ように、ＰＮ接合領域を覆うＬＯＣＯＳ酸化膜のブリッ
ジ部の本数を増大した場合においても、等幅に形成され
たブリッジ部をもとにしてＰＮ接合領域の幅が全てに渡
って等しく形成でき、ブリッジ部の本数に比例してサー
ジ電流に対する許容量を増大することができる。In the PN junction diode illustrated in FIG. 4,
Six PN junction regions were connected in parallel. A PN junction diode as an input / output protection element for a semiconductor device is normally designed to ensure a necessary allowable amount of surge current.
Several ten PN junction regions shown in are connected in parallel. As described above, even when the number of bridge portions of the LOCOS oxide film covering the PN junction region is increased, the width of the PN junction region can be formed to be equal over all the bridge portions having the same width. The allowable amount for surge current can be increased in proportion to the number of bridge portions.
【００７０】（第３の実施形態）第２の実施形態では、
ＰＮ接合領域を覆う等幅のブリッジ部を持つＬＯＣＯＳ
酸化膜を基礎として、ベースとなるＰ型高濃度拡散領域
の両側にエミッタとなるＮ型高濃度拡散領域が配置され
たＰＮ接合ダイオードが３個並列配置された構造を持つ
ＰＮ接合ダイオードを示した。第３の実施形態は、ベー
スとなる複数個のＰ型高濃度拡散領域とエミッタとなる
複数個のＮ型高濃度拡散領域が交互に配置された構造を
持つＰＮ接合ダイオードに関する。以下、ベースとなる
４個のＰ型高濃度拡散領域とエミッタとなる５個のＮ型
高濃度拡散領域が交互に配置され、８本のＰＮ接合領域
を形成したＰＮ接合ダイオードを一例として、本実施形
態について図に基づいて説明する。(Third Embodiment) In the second embodiment,
LOCOS with a bridge of equal width covering the PN junction region
A PN junction diode having a structure in which three PN junction diodes in which N-type high-concentration diffusion regions serving as emitters are arranged on both sides of a P-type high-concentration diffusion region serving as a base are arranged in parallel based on an oxide film is shown. . The third embodiment relates to a PN junction diode having a structure in which a plurality of P-type high-concentration diffusion regions serving as a base and a plurality of N-type high-concentration diffusion regions serving as an emitter are alternately arranged. In the following, as an example, a PN junction diode in which four P-type high-concentration diffusion regions serving as bases and five N-type high-concentration diffusion regions serving as emitters are alternately arranged to form eight PN junction regions will be described. An embodiment will be described with reference to the drawings.
【００７１】図５は、本実施形態におけるＰＮ接合ダイ
オードの平面図である。第１の実施形態と同様の部分に
ついては同一の符号をつけ、その説明を省略する。FIG. 5 is a plan view of the PN junction diode according to this embodiment. The same parts as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.
【００７２】図５に示すように、第３の実施形態では、
４個のＰ型高濃度拡散領域２１，２２，２３，２４と５
個のＮ型高濃度拡散領域３１，３２，３３，３４，３５
が交互に配置されており、図中のＬＯＣＯＳ酸化膜のブ
リッジ部５０１，５０２，５０３，５０４，５０５，５
０６，５０７，５０８の幅Ｌ1，Ｌ2，Ｌ3，Ｌ4，Ｌ5，
Ｌ6，Ｌ7，Ｌ8は、全て等しく設定されている。また、
４個のＰ型高濃度拡散領域２１，２２，２３，２４同士
は上層電極９ａによって接続されており、５個のＮ型高
濃度拡散領域３１，３２，３３，３４，３５同士は上層
電極９ｂによって接続されている。本実施形態の図５に
示すＰＮ接合ダイオードは、第１実施形態の図２に示し
た製造方法によって、同じように製造することができ
る。As shown in FIG. 5, in the third embodiment,
Four P-type high concentration diffusion regions 21, 22, 23, 24 and 5
N-type high-concentration diffusion regions 31, 32, 33, 34, 35
Are alternately arranged, and bridge portions 501, 502, 503, 504, 505, 5 of the LOCOS oxide film in the figure are arranged.
Widths L 1 , L 2 , L 3 , L 4 , L 5 , of 06, 507, 508,
L 6 , L 7 , and L 8 are all set to be equal. Also,
The four P-type high-concentration diffusion regions 21, 22, 23, and 24 are connected to each other by the upper-layer electrode 9a, and the five N-type high-concentration diffusion regions 31, 32, 33, 34, and 35 are connected to the upper-layer electrode 9b. Connected by. The PN junction diode of this embodiment shown in FIG. 5 can be manufactured in the same manner by the manufacturing method shown in FIG. 2 of the first embodiment.
【００７３】本実施形態においても、ＰＮ接合領域を覆
うブリッジ部が等幅に設定された高融点絶縁保護膜であ
るＬＯＣＯＳ酸化膜を基礎としているので、ＰＮ接合領
域の幅も全てのＰＮ接合に渡って等しくなり、その結
果、全てのＰＮ接合領域の耐圧が等しくなる点は第２実
施形態と同様である。一方、第２実施形態の図４のＰＮ
接合ダイオードにおいてはＰＮ接合領域が６本形成され
ているが、同じ占有面積であるにもかかわらず、本実施
形態の図５のＰＮ接合ダイオードにおいては、ＰＮ接合
領域が８本形成されている。従って、図５のＰＮ接合ダ
イオードは図４のＰＮ接合ダイオードに比べ、４／３倍
のサージ電流に対する許容量を持っている。逆に言え
ば、同じサージ電流許容量であれば、図５のＰＮ接合ダ
イオードは図４のＰＮ接合ダイオードに比べ、ダイオー
ド占有面積を３／４に縮小することができる。Also in the present embodiment, since the bridge portion covering the PN junction region is based on the LOCOS oxide film which is a high melting point insulating protective film having an equal width, the width of the PN junction region also covers all PN junctions. It is the same as that of the second embodiment in that the breakdown voltages are the same over the entire area, and as a result, the breakdown voltages of all the PN junction regions are the same. On the other hand, the PN of FIG. 4 of the second embodiment.
Although six PN junction regions are formed in the junction diode, eight PN junction regions are formed in the PN junction diode of this embodiment shown in FIG. 5 despite having the same occupied area. Therefore, the PN junction diode shown in FIG. 5 has an allowable amount of surge current that is 4/3 times that of the PN junction diode shown in FIG. Conversely, if the surge current tolerance is the same, the PN junction diode of FIG. 5 can reduce the diode occupation area to 3/4 as compared with the PN junction diode of FIG.
【００７４】図５に例示したＰＮ接合ダイオードでは、
８本のＰＮ接合領域を並列接続した。サージ電流に対す
る必要な許容量を確保するために、図５に示したＰＮ接
合領域を数１０本並列接続した場合においても、ＬＯＣ
ＯＳ酸化膜のブリッジ部の本数に比例してサージ電流に
対する許容量を増大させることができる点は、第２実施
形態と同様である。In the PN junction diode illustrated in FIG. 5,
Eight PN junction regions were connected in parallel. In order to secure a necessary allowable amount of surge current, even when several PN junction regions shown in FIG. 5 are connected in parallel, the LOC
As in the second embodiment, the allowable amount for the surge current can be increased in proportion to the number of bridge portions of the OS oxide film.
【００７５】（第４の実施形態）第１〜３の実施形態で
は、ベースとなるＰ型高濃度拡散領域とエミッタとなる
Ｎ型高濃度拡散領域が、全て同じ大きさで矩形状である
ＰＮ接合ダイオードであった。第４の実施形態は、Ｐ型
高濃度拡散領域とＮ型高濃度拡散領域が、矩形状ではあ
るが、大きさが異なる構造を持つＰＮ接合ダイオードに
関する。以下、本実施形態について図に基づいて説明す
る。(Fourth Embodiment) In the first to third embodiments, the P-type high-concentration diffusion region serving as the base and the N-type high-concentration diffusion region serving as the emitter are all the same size and are rectangular. It was a junction diode. The fourth embodiment relates to a PN junction diode having a structure in which the P-type high-concentration diffusion region and the N-type high-concentration diffusion region are rectangular but have different sizes. Hereinafter, the present embodiment will be described with reference to the drawings.
【００７６】図６は、本実施形態におけるＰＮ接合ダイ
オードの平面図である。第３の実施形態と同様の部分に
ついては同一の符号をつけ、その説明を省略する。FIG. 6 is a plan view of the PN junction diode according to this embodiment. The same parts as those in the third embodiment are designated by the same reference numerals and the description thereof will be omitted.
【００７７】図６に示すように、本実施形態においても
Ｐ型高濃度拡散領域２１，２２，２３，２４とＮ型高濃
度拡散領域３１，３２，３３，３４，３５が交互に配置
され、ＬＯＣＯＳ酸化膜のブリッジ部５０１，５０２，
５０３，５０４，５０５，５０６，５０７，５０８の幅
Ｌ1，Ｌ2，Ｌ3，Ｌ4，Ｌ5，Ｌ6，Ｌ7，Ｌ8が全て等しく
設定されている点は、第３実施形態の図５のＰＮ接合ダ
イオードと同様である。一方、Ｐ型高濃度拡散領域に対
応する４個のＬＯＣＯＳ開口部５２，５４，５６，５８
の長さＬPとＮ型高濃度拡散領域に対応する５個のＬＯ
ＣＯＳ開口部５１，５３，５５，５７，５９の長さＬN
を異なった値にしている点で、図５のＰＮ接合ダイオー
ドと異なっている。As shown in FIG. 6, also in this embodiment, the P-type high-concentration diffusion regions 21, 22, 23, 24 and the N-type high-concentration diffusion regions 31, 32, 33, 34, 35 are alternately arranged. LOCOS oxide film bridge portions 501, 502,
The third embodiment is that the widths L 1 , L 2 , L 3 , L 4 , L 5 , L 6 , L 7 , and L 8 of 503, 504, 505, 506, 507, and 508 are all set to be equal. 5 is similar to the PN junction diode of FIG. On the other hand, four LOCOS openings 52, 54, 56, 58 corresponding to the P-type high-concentration diffusion region
Length L P and 5 LO corresponding to the N-type high-concentration diffusion region
Length L N of COS openings 51, 53, 55, 57, 59
Is different from the PN junction diode of FIG.
【００７８】同じ大きさの矩形状のＰ型高濃度拡散領域
とＮ型高濃度拡散領域が図５のように並んで配置される
と、隣り合ったのＰ型高濃度拡散領域とＮ型高濃度拡散
領域の角部同士では、隣り合った辺の中央部同士よりも
電界が集中する。このため、許容量を越えた大きなサー
ジ電流が発生すると、図５に示すＰＮ接合ダイオードで
は、角部が破壊され易い。一方、本実施形態の図６に示
すＰＮ接合ダイオードにおいては、隣り合って配置され
るＰ型高濃度拡散領域とＮ型高濃度拡散領域の各々に対
応したＬＯＣＯＳ開口部の長さＬp，ＬNを異にして、角
部同士の距離をブリッジ部の幅Ｌ1＝Ｌ2＝Ｌ3＝Ｌ4＝Ｌ
5＝Ｌ6＝Ｌ7＝Ｌ8より長くしている。従って、隣り合っ
て配置されるＰ型高濃度拡散領域とＮ型高濃度拡散領域
の角部同士での電流経路の抵抗は、ＰＮ接合領域の幅で
の電流経路の抵抗より大きい。このようにして角部同士
の電界集中を緩和し、サージ電流の角部での集中を回避
することで、角部での破壊を低減することができる。When the rectangular P-type high-concentration diffusion region and the N-type high-concentration diffusion region of the same size are arranged side by side as shown in FIG. 5, the adjacent P-type high-concentration diffusion region and N-type high-concentration diffusion region are arranged. At the corners of the concentration diffusion region, the electric field is more concentrated than at the center of adjacent sides. Therefore, when a large surge current exceeding the allowable amount occurs, the corner portion of the PN junction diode shown in FIG. 5 is easily broken. On the other hand, in the PN junction diode shown in FIG. 6 of the present embodiment, the lengths L p and L of the LOCOS openings corresponding to the P-type high-concentration diffusion region and the N-type high-concentration diffusion region which are arranged adjacent to each other. With N different, the distance between the corner portions is determined by the width of the bridge portion L 1 = L 2 = L 3 = L 4 = L
5 = is longer than L 6 = L 7 = L 8 . Therefore, the resistance of the current path between the corners of the P-type high-concentration diffusion region and the N-type high-concentration diffusion region arranged adjacent to each other is larger than the resistance of the current path in the width of the PN junction region. In this way, the concentration of the electric field between the corners is relaxed and the surge current is prevented from being concentrated at the corners, so that the breakdown at the corners can be reduced.
【００７９】Ｐ型高濃度拡散領域の長さＬPとＮ型高濃
度拡散領域の長さＬNを変えるに際して、基板がＮ型の
場合は、Ｐ型高濃度拡散領域の角部が破壊し易いので、
角部の電流集中を避けるにはベースとなるＰ型高濃度拡
散領域の長さＬPをエミッタとなるＮ型高濃度拡散領域
の長さＬNより長くすることが望ましい。逆に、基板が
Ｐ型の場合は、Ｎ型高濃度拡散領域の角部が破壊し易い
ので、エミッタとなるＮ型高濃度拡散領域の長さＬNを
ベースとなるＰ型高濃度拡散領域の長さＬPより長くす
ることが望ましい。[0079] In changing the length L N of the length L P and N-type high concentration diffusion region of the P-type high concentration diffusion region, if the substrate is N-type, and destroyed the corners of the P-type high concentration diffusion region Because it ’s easy
In order to avoid current concentration at the corners, it is desirable to make the length L P of the P-type high-concentration diffusion region serving as the base longer than the length L N of the N-type high-concentration diffusion region serving as the emitter. On the other hand, when the substrate is P-type, the corners of the N-type high-concentration diffusion region are easily broken, so that the length L N of the N-type high-concentration diffusion region serving as the emitter serves as the base of the P-type high-concentration diffusion region. It is desirable to make it longer than the length L P.
【００８０】（第５の実施形態）第１〜第４の実施形態
のＰＮ接合ダイオードは、高濃度拡散領域に対する下層
電極のコンタクト領域とＬＯＣＯＳ開口部との間隔が、
全周に渡って等しく配置されたＰＮ接合ダイオードであ
った。第５の実施形態では、コンタクト領域とＬＯＣＯ
Ｓ開口部との間隔が、矩形の等幅ブリッジ部と両端部で
異なるＰＮ接合ダイオードに関する。以下、本実施形態
について図に基づいて説明する。(Fifth Embodiment) In the PN junction diodes of the first to fourth embodiments, the distance between the contact region of the lower layer electrode and the LOCOS opening with respect to the high concentration diffusion region is
It was a PN junction diode which was arranged equally over the entire circumference. In the fifth embodiment, the contact region and the LOCO
The present invention relates to a PN junction diode in which the distance to the S opening is different from that of the rectangular equal-width bridge portion at both ends. Hereinafter, the present embodiment will be described with reference to the drawings.
【００８１】図７は、本実施形態におけるＰＮ接合ダイ
オードの平面図である。第３の実施形態と同様の部分に
ついては同一の符号をつけ、その説明を省略する。FIG. 7 is a plan view of the PN junction diode according to this embodiment. The same parts as those in the third embodiment are designated by the same reference numerals and the description thereof will be omitted.
【００８２】図７に示すように、本実施形態におけるＰ
Ｎ接合ダイオードは、各高濃度拡散領域２１，２２，２
３，２４，３１，３２，３３，３４，３５に対する各下
層電極のコンタクト領域７１，７２，７３，７４，７
５，７６，７７，７８，７９とＬＯＣＯＳ開口部５０と
の間隔に関して、矩形の両端部での間隔Ｌyが、等幅ブ
リッジ部での間隔Ｌxより大きくなるように（Ｌx＜
Ｌy）配置されている。As shown in FIG. 7, P in the present embodiment
The N-junction diode is formed in each of the high concentration diffusion regions 21, 22, 2
Contact regions 71, 72, 73, 74, 7 of the respective lower layer electrodes for 3, 24, 31, 32, 33, 34, 35
Regarding the distance between the LOCOS openings 50 and 5, 76, 77, 78, 79, the distance L y at both ends of the rectangle is set to be larger than the distance L x at the constant width bridge portion (L x <
L y ) are arranged.
【００８３】各高濃度拡散領域２１，２２，２３，２
４，３１，３２，３３，３４，３５と下層電極７ａ，７
ｂでは下層電極のほうが比抵抗が小さいため、等幅ブリ
ッジ部での間隔Ｌxより矩形の両端部での間隔Ｌyを大き
くすることで、端部までの電流経路の抵抗が大きくな
る。従って、端部に流れ込む電流が減って、端部でサー
ジ電流の集中を回避することができる。High-concentration diffusion regions 21, 22, 23, 2
4, 31, 32, 33, 34, 35 and lower layer electrodes 7a, 7
In b, since the lower layer electrode has a smaller specific resistance, the resistance of the current path to the ends becomes larger by making the interval L y at both ends of the rectangle larger than the interval L x at the constant width bridge portion. Therefore, the current flowing into the end portion is reduced and the surge current can be prevented from being concentrated at the end portion.
【００８４】（第６の実施形態）第１〜３の実施形態で
は、ベースとなるＰ型高濃度拡散領域とエミッタとなる
Ｎ型高濃度拡散領域が、全て同じ大きさで矩形状である
ＰＮ接合ダイオードであった。第６の実施形態は、Ｐ型
高濃度拡散領域とＮ型高濃度拡散領域が、同じ大きさで
はあるが、略矩形状で角部が丸められている構造を持つ
ＰＮ接合ダイオードに関する。以下、本実施形態につい
て図に基づいて説明する。(Sixth Embodiment) In the first to third embodiments, the P-type high-concentration diffusion region serving as the base and the N-type high-concentration diffusion region serving as the emitter are all the same size and are rectangular. It was a junction diode. The sixth embodiment relates to a PN junction diode having a structure in which the P-type high-concentration diffusion region and the N-type high-concentration diffusion region have the same size, but have substantially rectangular shapes and rounded corners. Hereinafter, the present embodiment will be described with reference to the drawings.
【００８５】図８は、本実施形態におけるＰＮ接合ダイ
オードの平面図である。第３の実施形態と同様の部分に
ついては同一の符号をつけ、その説明を省略する。FIG. 8 is a plan view of the PN junction diode in this embodiment. The same parts as those in the third embodiment are designated by the same reference numerals and the description thereof will be omitted.
【００８６】図８に示すように、本実施形態においても
Ｐ型高濃度拡散領域２１，２２，２３，２４とＮ型高濃
度拡散領域３１，３２，３３，３４，３５が交互に配置
され、ＬＯＣＯＳ酸化膜のブリッジ部５０１，５０２，
５０３，５０４，５０５，５０６，５０７，５０８の幅
Ｌ1，Ｌ2，Ｌ3，Ｌ4，Ｌ5，Ｌ6，Ｌ7，Ｌ8が全て等しく
設定されている点は、第３実施形態の図５のＰＮ接合ダ
イオードと同様である。一方、Ｐ型高濃度拡散領域とＮ
型高濃度拡散領域に対応する９個のＬＯＣＯＳ開口部５
０の矩形の角部が丸められている点で、図５のＰＮ接合
ダイオードと異なっている。As shown in FIG. 8, also in this embodiment, the P-type high-concentration diffusion regions 21, 22, 23, 24 and the N-type high-concentration diffusion regions 31, 32, 33, 34, 35 are alternately arranged. LOCOS oxide film bridge portions 501, 502,
The third embodiment is that the widths L 1 , L 2 , L 3 , L 4 , L 5 , L 6 , L 7 , and L 8 of 503, 504, 505, 506, 507, and 508 are all set to be equal. 5 is similar to the PN junction diode of FIG. On the other hand, a P-type high-concentration diffusion region and N
Nine LOCOS openings 5 corresponding to the high concentration diffusion region
This is different from the PN junction diode in FIG. 5 in that the corners of the rectangle 0 are rounded.
【００８７】本実施形態においては、隣り合って配置さ
れるＰ型高濃度拡散領域とＮ型高濃度拡散領域に対応す
るＬＯＣＯＳ開口部の矩形の角部を丸めることで、角部
同士の距離をブリッジ部の幅Ｌ1＝Ｌ2＝Ｌ3＝Ｌ4＝Ｌ5
＝Ｌ6＝Ｌ7＝Ｌ8より長くしている。これにより、第４
実施形態と同様に、サージ電流の角部での集中を回避
し、図５のＰＮ接合ダイオードで起きる角部での破壊を
低減することができる。In the present embodiment, the corners of the rectangle of the LOCOS opening corresponding to the P-type high-concentration diffusion region and the N-type high-concentration diffusion region arranged adjacent to each other are rounded so that the distance between the corners is increased. Width of bridge portion L 1 = L 2 = L 3 = L 4 = L 5
= Is longer than L 6 = L 7 = L 8 . As a result, the fourth
Similar to the embodiment, it is possible to avoid the concentration of the surge current at the corners and reduce the breakdown at the corners that occurs in the PN junction diode of FIG.
【００８８】また、図６に示すＰＮ接合ダイオードのＰ
Ｎ接合領域の実質的な長さがＬNであるのに対し、図８
に示すＰＮ接合ダイオードのＰＮ接合領域の長さはＬPN
となる（ＬPN＝ＬP＞ＬN）。従って、図８のＰＮ接合ダ
イオードは、図６のＰＮ接合ダイオードに比べ、サージ
電流に対してより大きな許容量を持っている。Further, the P of the PN junction diode shown in FIG.
The substantial length of the N-junction region is L N , while FIG.
The length of the PN junction region of the PN junction diode shown in the L PN
(L PN = L P > L N ). Therefore, the PN junction diode of FIG. 8 has a larger tolerance to surge current than the PN junction diode of FIG.
【００８９】尚、図８に示すＰＮ接合ダイオードではＬ
ＯＣＯＳ開口部５０の矩形の角部が丸められており、一
方高濃度拡散領域２１，３１に対するコンタクト領域７
１，７２は矩形形状のままで、コンタクト領域７１，７
２とＬＯＣＯＳ開口部５０との間隔に関して、矩形の両
端部での間隔が、等幅ブリッジ部での間隔より大きくな
るように配置されている。従って、第５の実施形態と同
様に、端部に流れ込む電流が減って、端部でサージ電流
の集中を回避する効果も有する。In the PN junction diode shown in FIG.
The rectangular corners of the OCOS opening 50 are rounded, while the contact region 7 for the high-concentration diffusion regions 21 and 31 is formed.
1, 72 remain rectangular and contact regions 71, 7
Regarding the distance between 2 and the LOCOS opening 50, the distance between both ends of the rectangle is larger than the distance between the constant width bridge portions. Therefore, similarly to the fifth embodiment, the current flowing into the end portion is reduced, and the effect of avoiding the concentration of the surge current at the end portion is also obtained.
【００９０】（第７の実施形態）第４の実施形態は、ベ
ースとなるＰ型高濃度拡散領域とエミッタとなるＮ型高
濃度拡散領域が矩形状で大きさの異なるＰＮ接合ダイオ
ードであった。また、第６の実施形態は、ベースとなる
Ｐ型高濃度拡散領域とエミッタとなるＮ型高濃度拡散領
域が、同じ大きさではあるが角部が丸められた略矩形状
のＰＮ接合ダイオードであった。第７の実施形態では、
Ｐ型高濃度拡散領域とＮ型高濃度拡散領域が、大きさの
異なる略矩形状であることに加え、各拡散領域の略矩形
状の終端部に、各拡散領域と同型の低濃度拡散ウェルを
形成した構造を持つＰＮ接合ダイオードに関する。以
下、本実施形態について図に基づいて説明する。(Seventh Embodiment) The fourth embodiment is a PN junction diode in which the P-type high-concentration diffusion region serving as the base and the N-type high-concentration diffusion region serving as the emitter are rectangular and have different sizes. . The sixth embodiment is a substantially rectangular PN junction diode in which the P-type high-concentration diffusion region serving as the base and the N-type high-concentration diffusion region serving as the emitter have the same size but have rounded corners. there were. In the seventh embodiment,
In addition to the P-type high-concentration diffusion region and the N-type high-concentration diffusion region having substantially rectangular shapes of different sizes, a low-concentration diffusion well of the same type as each diffusion region is provided at the substantially rectangular end portion of each diffusion region. The present invention relates to a PN junction diode having a structure formed with. Hereinafter, the present embodiment will be described with reference to the drawings.
【００９１】図９（ａ）は本実施形態におけるＰＮ接合
ダイオードの平面図であり、図９（ｂ）は、図９（ａ）
におけるＡ−Ａ’線に沿った拡大断面図である。第４の
実施形態と同様の部分については同一の符号をつけ、そ
の説明を省略する。FIG. 9A is a plan view of the PN junction diode in this embodiment, and FIG. 9B is a plan view of FIG. 9A.
3 is an enlarged cross-sectional view taken along line AA ′ in FIG. The same parts as those in the fourth embodiment are designated by the same reference numerals, and the description thereof will be omitted.
【００９２】図９（ａ）に示すように、本実施形態にお
いては、Ｐ型高濃度拡散領域２１，２２，２３，２４と
Ｎ型高濃度拡散領域３１，３２，３３，３４，３５が交
互に配置され、４個のＬＯＣＯＳ開口部５２，５４，５
６，５８の長さＬPとＮ型高濃度拡散領域に対応する５
個のＬＯＣＯＳ開口部５１，５３，５５，５７，５９の
長さＬNは異なった値となっている。また、図中、ＬＯ
ＣＯＳ酸化膜のブリッジ部５０１，５０２，５０３，５
０４，５０５，５０６，５０７，５０８の幅Ｌ 1，Ｌ2，
Ｌ3，Ｌ4，Ｌ5，Ｌ6，Ｌ7，Ｌ8は全て等しく設定されて
いるが、Ｐ型高濃度拡散領域に対応するＬＯＣＯＳ開口
部５２，５４，５６，５８とＮ型高濃度拡散領域に対応
するＬＯＣＯＳ開口部５１，５３，５５，５７，５９
は、いずれも角部が丸めらた略矩形状となっている。本
実施形態においては、さらに、略矩形状の各拡散領域の
終端部の周囲に各拡散領域と同型の低濃度拡散ウェル２
０２〜２０９，３０２〜３１１が形成されている。低濃
度拡散ウェル２０２〜２０９，３０２〜３１１の拡散深
さは、約５μｍである。As shown in FIG. 9A, in this embodiment,
The P-type high-concentration diffusion regions 21, 22, 23, 24
N-type high-concentration diffusion regions 31, 32, 33, 34, 35 intersect.
Four LOCOS openings 52, 54, 5 arranged one above the other
Length L of 6,58PAnd 5 corresponding to N-type high concentration diffusion region
Of the individual LOCOS openings 51, 53, 55, 57, 59
Length LNHave different values. In the figure, LO
Bridge portions 501, 502, 503, 5 of COS oxide film
Width L of 04, 505, 506, 507, 508 1, L2，
L3, LFour, LFive, L6, L7, L8Are all set equal
However, the LOCOS opening corresponding to the P-type high concentration diffusion region
Corresponding to parts 52, 54, 56, 58 and N type high concentration diffusion region
LOCOS openings 51, 53, 55, 57, 59
Has a substantially rectangular shape with rounded corners. Book
In the embodiment, further, each of the substantially rectangular diffusion regions
A low-concentration diffusion well 2 of the same type as each diffusion region around the end portion
02-209 and 302-311 are formed. Low concentration
Diffusion depth of the diffusion wells 202 to 209 and 302 to 311
The length is about 5 μm.
【００９３】本実施形態のＰＮ接合ダイオードの製造工
程においては、最初に低濃度拡散ウェル２０２〜２０
９，３０２〜３１１を形成した後、第１実施形態の図２
に示した製造工程によって、同じように製造することが
できる。低濃度拡散ウェル２０２〜２０９，３０２〜３
１１の形成は、ダイオードと共に形成されるＣＭＯＳ製
造工程の図３（ａ）に示したＰ型ウェル領域とＮ型ウェ
ル領域の形成と同じ条件であれば、同時に行なうことが
できる。In the manufacturing process of the PN junction diode of this embodiment, first, the low-concentration diffusion wells 202 to 20 are formed.
After forming 9,302 to 311 of FIG.
The same manufacturing process can be performed by the manufacturing process shown in FIG. Low concentration diffusion wells 202-209, 302-3
The formation of 11 can be performed simultaneously under the same conditions as the formation of the P-type well region and the N-type well region shown in FIG. 3A in the CMOS manufacturing process for forming with the diode.
【００９４】本実施形態においては、各拡散領域の終端
部の周囲に同型の低濃度拡散ウェルを形成しているの
で、終端部の耐圧が上り、終端部でのサージ電流の集中
を回避することができる。また、図９のＰＮ接合ダイオ
ードにおいては、終端部での低濃度拡散ウェルの形成に
加えて、第６実施形態と同様にＰ型高濃度拡散領域とＮ
型高濃度拡散領域を角部が丸められた略矩形状にしてお
り、第４実施形態と同様にＰ型高濃度拡散領域とＮ型高
濃度拡散領域の大きさが異なったものにしている。従っ
て、大きなサージ電流が発生した際の角部での電界集中
による破壊に対しては、図９のＰＮ接合ダイオードで
は、図６や図８のＰＮ接合ダイオードに比べ、さらにサ
ージ耐量がより大きくなっている。In the present embodiment, since the same type of low-concentration diffusion well is formed around the terminal end of each diffusion region, the breakdown voltage of the terminal end rises and the concentration of surge current at the terminal end is avoided. You can Further, in the PN junction diode of FIG. 9, in addition to the formation of the low-concentration diffusion well at the terminal end, the P-type high-concentration diffusion region and the N-type diffusion well are formed similarly to the sixth embodiment.
The type high-concentration diffusion region has a substantially rectangular shape with rounded corners, and the P-type high-concentration diffusion region and the N-type high-concentration diffusion region are different in size, as in the fourth embodiment. Therefore, with respect to destruction due to electric field concentration at the corners when a large surge current occurs, the PN junction diode of FIG. 9 has a larger surge withstand capability than the PN junction diode of FIGS. 6 and 8. ing.
【００９５】尚、各拡散領域の終端部の周囲に低濃度拡
散ウェルを形成することは、第１〜第６の実施形態で説
明したＰＮ接合ダイオードに適用しても良いことは、言
うまでもない。Needless to say, forming the low-concentration diffusion well around the end of each diffusion region may be applied to the PN junction diode described in the first to sixth embodiments.
【００９６】（第８の実施形態）第１〜第７の実施形態
は、上層電極が矩形形状であり、上層電極の電極幅が一
定のＰＮ接合ダイオードであった。第８の実施形態で
は、上層電極が矩形形状ではなく、並んだＬＯＣＯＳ開
口部を横断して配置される上層電極の電極幅が、パッド
に近くなるほど大きく設定されているＰＮ接合ダイオー
ドに関する。以下、本実施形態について図に基づいて説
明する。(Eighth Embodiment) In the first to seventh embodiments, the upper-layer electrode has a rectangular shape, and the upper-layer electrode has a constant electrode width. The eighth embodiment relates to a PN junction diode in which the upper layer electrode is not in a rectangular shape, and the electrode width of the upper layer electrode arranged across the aligned LOCOS openings is set larger as it gets closer to the pad. Hereinafter, the present embodiment will be described with reference to the drawings.
【００９７】図１０は、本実施形態におけるＰＮ接合ダ
イオードの平面図である。第３の実施形態と同様の部分
については同一の符号をつけ、その説明を省略する。図
１０に示すように、本実施形態におけるＰＮ接合ダイオ
ードは、パッド９０ａ，９０ｂがＬＯＣＯＳ開口部５０
を間に挟んでその両側に配置されており、各上層電極９
ａ，９ｂの電極幅Ｌea，Ｌebが、それぞれ、パッド９０
ａ，９０ｂに近くなるほど大きく設定されている。これ
に従って、下層電極７ａに接続する上層電極９ａのコン
タクト領域９２，９４，９６，９８の長さもパッド９０
ａに近くなるほど長く設定されており、下層電極７ｂに
接続する上層電極９ｂのコンタクト領域９１，９３，９
５，９７，９９の長さもパッド９０ｂに近くなるほど長
く設定されている。FIG. 10 is a plan view of the PN junction diode in this embodiment. The same parts as those in the third embodiment are designated by the same reference numerals and the description thereof will be omitted. As shown in FIG. 10, in the PN junction diode according to the present embodiment, the pads 90a and 90b have LOCOS openings 50.
Are arranged on both sides of the upper electrode 9 with the upper electrode 9 interposed therebetween.
The electrode widths L ea and L eb of a and 9b are respectively the pad 90
It is set larger as it gets closer to a and 90b. Accordingly, the lengths of the contact regions 92, 94, 96, 98 of the upper layer electrode 9a connected to the lower layer electrode 7a are also the pad 90.
It is set longer as it gets closer to a, and the contact regions 91, 93, 9 of the upper layer electrode 9b connected to the lower layer electrode 7b.
The lengths of 5, 97 and 99 are set longer as they are closer to the pad 90b.
【００９８】サージ電流は一方のパッドから流入し，も
う一方のパッドから流出していくので、それぞれ、対応
する下層電極７ａ，７ｂを並列接続している上層電極９
ａ，９ｂにおいては、それぞれのパッド９０ａ，９０ｂ
に近いほど大きなサージ電流が流れる。従って、上層電
極９ａ，９ｂにおいてそれぞれパッド９０ａ，９０ｂに
近い部分ほど幅を大きくきくすることで、サージ電流を
均一に流すことができ、パッド近くでのサージ電流によ
る破壊を防止することができる。Since the surge current flows in from one pad and flows out from the other pad, the upper layer electrode 9 in which the corresponding lower layer electrodes 7a and 7b are connected in parallel, respectively.
a and 9b, pads 90a and 90b respectively
Larger surge current flows closer to. Therefore, by making the widths of the upper electrode 9a, 9b closer to the pads 90a, 90b, respectively, the surge current can be made to flow uniformly, and the damage due to the surge current near the pad can be prevented.
【００９９】（第９の実施形態）第６の実施形態は、Ｐ
型高濃度拡散領域とＮ型高濃度拡散領域が、同じ大きさ
で矩形の角部が丸められたＰＮ接合ダイオードであっ
た。第９の実施形態では、Ｐ型高濃度拡散領域とＮ型高
濃度拡散領域が、同心円状に等間隔に配置されている構
造を持つＰＮ接合ダイオードに関する。以下、本実施形
態について図に基づいて説明する。(Ninth Embodiment) In the sixth embodiment, P
The high-concentration type diffusion region and the N-type high concentration diffusion region were PN junction diodes having the same size and rounded corners. The ninth embodiment relates to a PN junction diode having a structure in which P-type high-concentration diffusion regions and N-type high-concentration diffusion regions are concentrically arranged at equal intervals. Hereinafter, the present embodiment will be described with reference to the drawings.
【０１００】図１１に、本実施形態におけるＰＮ接合ダ
イオードを示す。図１１（ａ）は本実施形態におけるＰ
Ｎ接合ダイオードの平面図であり、図１１（ｂ）は図１
１（ａ）におけるＡ−Ａ’線に沿った拡大断面図であ
る。尚、第６の実施形態と同様の部分については同一の
符号をつけその説明を省略するが、図１１では、図１で
示したＴＥＯＳからなる上層の層間絶縁膜８、Ａｌから
なる上層電極９ａ，９ｂ、ＳｉＮからなる保護膜１０は
図示を省略した。FIG. 11 shows a PN junction diode according to this embodiment. FIG. 11A shows P in the present embodiment.
FIG. 11B is a plan view of the N-junction diode, and FIG.
It is an expanded sectional view which followed the AA 'line in 1 (a). The same parts as those of the sixth embodiment are designated by the same reference numerals and the description thereof is omitted. However, in FIG. 11, the upper interlayer insulating film 8 made of TEOS and the upper electrode 9a made of Al shown in FIG. , 9b and the protective film 10 made of SiN are not shown.
【０１０１】図１１に示すように、本実施形態では、３
個のＰ型高濃度拡散領域２１，２２，２３と２個のＮ型
高濃度拡散領域３１，３２が、交互に等間隔に同心円状
に配置されている。図中のＬＯＣＯＳ酸化膜のブリッジ
部５０１，５０２，５０３，５０４の幅Ｌ1，Ｌ2，
Ｌ3，Ｌ4は、全て等しく設定されている。As shown in FIG. 11, in this embodiment, 3
The P-type high-concentration diffusion regions 21, 22, 23 and the two N-type high-concentration diffusion regions 31, 32 are alternately arranged at equal intervals in a concentric pattern. The widths L 1 , L 2 , of the bridge portions 501, 502, 503, 504 of the LOCOS oxide film in the figure,
L 3 and L 4 are all set to be equal.
【０１０２】図１１に示すＰＮ接合ダイオードおいて
は、５個のＬＯＣＯＳ開口部５１，５２，５３，５４，
５５とそれに対応したＰ型高濃度拡散領域およびＮ型高
濃度拡散領域が円形状になっているので、矩形状の拡散
領域のような角部が存在しない。従って、角部同士での
サージ電流の集中といったことも起こり得ず、円周の全
域にわたってサージ電流を半径方向に均等に流すことが
できる。このように、図１１に示したＰＮ接合ダイオー
ドはＰＮ接合領域が無駄なく配置されており、第６の実
施形態である図８のＰＮ接合ダイオードと比べても、さ
らに小型化されたＰＮ接合ダイオードとなっている。In the PN junction diode shown in FIG. 11, five LOCOS openings 51, 52, 53, 54,
Since 55 and the corresponding P-type high-concentration diffusion region and N-type high-concentration diffusion region are circular, there are no corners such as a rectangular diffusion region. Therefore, concentration of the surge current between the corners does not occur, and the surge current can be evenly distributed in the radial direction over the entire circumference. As described above, in the PN junction diode shown in FIG. 11, the PN junction region is arranged without waste, and the PN junction diode is further downsized as compared with the PN junction diode of FIG. 8 which is the sixth embodiment. Has become.
【０１０３】（第１０の実施形態）第１〜９の実施形態
は、いずれも、ベースとなるＰ型高濃度拡散領域とエミ
ッタとなるＮ型高濃度拡散領域の形状と配置を最適にし
て、サージ耐量を高めたものであった。第１０の実施形
態では、Ｐ型高濃度拡散領域とＮ型高濃度拡散領域の形
状と配置に加えて、ＰＮ接合ダイオードの周囲をＰ型の
第３高濃度拡散領域で取り囲み、電極を介して接地した
構造に関する。以下、本実施形態について図に基づいて
説明する。(Tenth Embodiment) In any of the first to ninth embodiments, the shape and arrangement of the P-type high-concentration diffusion region serving as the base and the N-type high-concentration diffusion region serving as the emitter are optimized. It was a high surge resistance. In the tenth embodiment, in addition to the shapes and arrangements of the P-type high-concentration diffusion region and the N-type high-concentration diffusion region, the periphery of the PN junction diode is surrounded by the P-type third high-concentration diffusion region, and the electrodes are interposed. Regarding the grounded structure. Hereinafter, the present embodiment will be described with reference to the drawings.
【０１０４】図１２に、本実施形態におけるＰＮ接合ダ
イオードを示す。図１２（ａ）は本実施形態におけるＰ
Ｎ接合ダイオードの平面図であり、図１２（ｂ）は図１
２（ａ）におけるＡ−Ａ’線に沿った拡大断面図であ
る。尚、第４の実施形態と同様の部分については同一の
符号をつけその説明を省略するが、図１２では、図１で
示したＴＥＯＳからなる上層の層間絶縁膜８、Ａｌから
なる上層電極９ａ，９ｂ、ＳｉＮからなる保護膜１０は
図示を省略した。FIG. 12 shows a PN junction diode according to this embodiment. FIG. 12A shows P in the present embodiment.
FIG. 12B is a plan view of the N-junction diode, and FIG.
It is an expanded sectional view which followed the AA 'line in 2 (a). The same parts as those in the fourth embodiment are designated by the same reference numerals and the description thereof is omitted. However, in FIG. 12, the upper interlayer insulating film 8 made of TEOS and the upper electrode 9a made of Al shown in FIG. , 9b and the protective film 10 made of SiN are not shown.
【０１０５】図１２に示す本実施形態のＰＮ接合ダイオ
ードでは、２個のＰ型高濃度拡散領域２１，２２と３個
のＮ型高濃度拡散領域３１，３２，３３が交互に配置さ
れているが、これら５個の拡散領域２１，２２，３１，
３２，３３の下にＰ型の第３高濃度拡散領域２２０を配
し、さらに５個の拡散領域２１，２２，３１，３２，３
３の周りを、ＬＯＣＯＳ酸化膜の外周部５００ｒ，５０
１ｒに形成した開口部５０ｒとそれに対応したＰ型の第
３高濃度拡散領域２２１で取り囲んだ構造となってい
る。Ｐ型の第３高濃度拡散領域２２０，２２１は、図１
２（ｂ）に示すように接続しており、コンタクト部７０
ｒと電極７ｒを介して接地されている。In the PN junction diode of this embodiment shown in FIG. 12, two P-type high-concentration diffusion regions 21, 22 and three N-type high-concentration diffusion regions 31, 32, 33 are alternately arranged. However, these five diffusion regions 21, 22, 31,
A P-type third high-concentration diffusion region 220 is arranged under 32, 33, and five diffusion regions 21, 22, 31, 32, 3 are further arranged.
3 around the outer periphery 500r, 50 of the LOCOS oxide film.
The structure is surrounded by the opening 50r formed in 1r and the corresponding P-type third high-concentration diffusion region 221. The P-type third high-concentration diffusion regions 220 and 221 are shown in FIG.
2 (b), the contact portion 70 is connected.
It is grounded via r and the electrode 7r.
【０１０６】図１２に示すＰＮ接合ダイオードの製造方
法は、最初に、低濃度Ｎ型シリコン（半導体）基板１１
に酸化シリコン膜を積層した後に所定部分を開口し、１
×１０13ｃｍ-2の条件でボロン（Ｂ）をイオン注入し
て、Ｐ型の埋め込み層である第３高濃度拡散領域２２０
を形成しておく。次に、酸化シリコン膜を除去した後、
低濃度Ｎ型シリコン層１を１０μｍエピタキシャル成長
する。その後、所定部分に１×１０13ｃｍ-2の条件でボ
ロン（Ｂ）をイオン注入して、アイソレーション層であ
るＰ型の第３高濃度拡散領域２２１を形成する。これに
より、ダイオード形成位置を取り囲んだ構造の第３高濃
度拡散領域２２０，２２１が完成する。その後は、第１
実施形態の図２に示した製造工程に従い、本実施形態の
ＰＮ接合ダイオードを製造することができる。In the method of manufacturing the PN junction diode shown in FIG. 12, first, the low concentration N type silicon (semiconductor) substrate 11 is used.
After stacking a silicon oxide film on the
Boron (B) is ion-implanted under the condition of × 10 13 cm -2 , and the third high-concentration diffusion region 220 which is a P-type buried layer is implanted.
Is formed. Next, after removing the silicon oxide film,
The low concentration N-type silicon layer 1 is epitaxially grown to a thickness of 10 μm. Then, boron (B) is ion-implanted into a predetermined portion under the condition of 1 × 10 13 cm −2 to form a P-type third high concentration diffusion region 221 which is an isolation layer. As a result, the third high-concentration diffusion regions 220 and 221 having a structure surrounding the diode formation position are completed. After that, the first
The PN junction diode of this embodiment can be manufactured according to the manufacturing process shown in FIG. 2 of the embodiment.
【０１０７】本実施形態においては、ＰＮ接合ダイオー
ドを接地されたＰ型の第３高濃度拡散領域２２０，２２
１で取り囲んでいるので、サージ電流が大きくてＰＮ接
合領域では吸収できず溢れ出た状態になっても、ダイオ
ードを取り囲んだＰ型の第３高濃度拡散領域２２０，２
２１が溢れ出たサージ電流であるノイズ（注入された電
子、ホール）を吸収する。従って、ダイオードの周辺に
形成された半導体装置において、サージ電流によって発
生したノイズによるＬＯＧＩＣ回路の誤動作を防止する
ことができる。In this embodiment, the P-type third high-concentration diffusion regions 220 and 22 in which the PN junction diode is grounded.
Since it is surrounded by 1, even if the surge current is so large that it cannot be absorbed in the PN junction region and overflows, the P-type third high-concentration diffusion regions 220, 2 surrounding the diode are formed.
21 absorbs noise (injected electrons, holes) which is a surge current overflowing. Therefore, in the semiconductor device formed around the diode, it is possible to prevent malfunction of the LOGIC circuit due to noise generated by the surge current.
【０１０８】（第１１の実施形態）第１０の実施形態
は、ＰＮ接合ダイオードの周囲をＰ型の第３高濃度拡散
領域で取り囲んで、サージ電流が大きな場合におけるダ
イオードの周辺に形成された半導体装置の誤動作を防止
するものであった。第１１の実施形態では、Ｐ型の第３
高濃度拡散領に変えて、ＰＮ接合ダイオードの周囲を絶
縁領域で取り囲んだ構造に関する。以下、本実施形態に
ついて図に基づいて説明する。(Eleventh Embodiment) In the tenth embodiment, a semiconductor formed around a PN junction diode is surrounded by a P-type third high-concentration diffusion region and the surge current is large. It was intended to prevent malfunction of the device. In the eleventh embodiment, the P-type third
The present invention relates to a structure in which a PN junction diode is surrounded by an insulating region in place of a high concentration diffusion region. Hereinafter, the present embodiment will be described with reference to the drawings.
【０１０９】図１３に、本実施形態におけるＰＮ接合ダ
イオードを示す。図１３（ａ）は本実施形態におけるＰ
Ｎ接合ダイオードの平面図であり、図１３（ｂ）は図１
３（ａ）におけるＡ−Ａ’線に沿った拡大断面図であ
る。尚、第１０の実施形態と同様の部分については同一
の符号をつけその説明を省略するが、図１３では、図１
で示したＴＥＯＳからなる上層の層間絶縁膜８、Ａｌか
らなる上層電極９ａ，９ｂ、ＳｉＮからなる保護膜１０
は図示を省略した。FIG. 13 shows a PN junction diode according to this embodiment. FIG. 13A shows P in the present embodiment.
FIG. 13B is a plan view of the N-junction diode, and FIG.
It is an expanded sectional view which followed the AA 'line in 3 (a). The same parts as those in the tenth embodiment are designated by the same reference numerals and the description thereof will be omitted.
The upper interlayer insulating film 8 made of TEOS, the upper electrodes 9a and 9b made of Al, and the protective film 10 made of SiN shown in FIG.
Are not shown.
【０１１０】図１３に示す本実施形態では、２個のＰ型
高濃度拡散領域２１，２２と３個のＮ型高濃度拡散領域
３１，３２，３３が交互に配置されているが、これら５
個の拡散領域２１，２２，３１，３２，３３の周りを、
ＬＯＣＯＳ酸化膜の外周部５００ｒの下にある絶縁領域
４０１，４０２で取り囲んだ構造のＰＮ接合ダイオード
となっている。In the present embodiment shown in FIG. 13, two P-type high-concentration diffusion regions 21, 22 and three N-type high-concentration diffusion regions 31, 32, 33 are alternately arranged.
Around the individual diffusion regions 21, 22, 31, 32, 33,
It is a PN junction diode having a structure surrounded by insulating regions 401 and 402 below the outer peripheral portion 500r of the LOCOS oxide film.
【０１１１】図１３に示すＰＮ接合ダイオードの製造方
法は、最初に低濃度Ｎ型シリコン（半導体）基板１１を
２枚用意し、一方の基板表面を酸化して酸化シリコン膜
４０２を形成する。次に、通常の方法で、２枚の基板を
貼り合わせて、貼り合わせ基板を形成する。その後、酸
化したほうの基板を研磨して、１０μｍ厚の低濃度Ｎ型
シリコン層１に加工する。次に、レジストあるいは酸化
膜をマスクにして、埋め込み酸化シリコン膜４０２に到
達するまで低濃度Ｎ型シリコン層１をほぼ垂直にドライ
エッチングし、溝を形成する。次に、溝の側壁を熱酸化
して酸化シリコン（ＳｉＯ2）膜４０１を形成した後、
ポリシリコン（Ｓｉ）７００を積層して、溝を塞ぐ。そ
の後、表面に残ったポリシリコンをエッチバックし、化
学機械研磨で表面を平らにする。これにより、ダイオー
ド形成位置を取り囲んだ構造の絶縁領域４０１，４０２
が完成する。その後は、第１実施形態の図２に示した製
造工程に従い、本実施形態のＰＮ接合ダイオードを製造
することができる。図１３（ａ）の平面図においては、
酸化シリコン（ＳｉＯ2）膜４０１とポリシリコン（Ｓ
ｉ）７００は、それぞれ実線で示した。In the method of manufacturing the PN junction diode shown in FIG. 13, first, two low-concentration N-type silicon (semiconductor) substrates 11 are prepared, and the surface of one substrate is oxidized to form a silicon oxide film 402. Next, the two substrates are bonded together by a normal method to form a bonded substrate. Then, the oxidized substrate is polished and processed into a low-concentration N-type silicon layer 1 having a thickness of 10 μm. Next, using the resist or the oxide film as a mask, the low-concentration N-type silicon layer 1 is dry-etched substantially vertically until the buried silicon oxide film 402 is reached to form a groove. Next, after thermally oxidizing the side wall of the groove to form a silicon oxide (SiO 2 ) film 401,
Polysilicon (Si) 700 is laminated to close the groove. After that, the polysilicon remaining on the surface is etched back and the surface is flattened by chemical mechanical polishing. As a result, the insulating regions 401, 402 having a structure surrounding the diode formation position are formed.
Is completed. After that, the PN junction diode of the present embodiment can be manufactured according to the manufacturing process shown in FIG. 2 of the first embodiment. In the plan view of FIG. 13 (a),
Silicon oxide (SiO 2 ) film 401 and polysilicon (S
i) 700 is shown by a solid line.
【０１１２】本実施形態においては、ＰＮ接合ダイオー
ドを絶縁領域４０１，４０２で取り囲んでいるので、サ
ージ電流が大きくてＰＮ接合領域から溢れ出た状態にな
っても、ダイオードを取り囲んだ絶縁領域４０１，４０
２が溢れ出たサージ電流を完全に遮断する。従って、ダ
イオードの周辺に形成された半導体装置において、溢れ
出たサージ電流によって発生するノイズによる誤動作を
防止することができる。In this embodiment, since the PN junction diode is surrounded by the insulating regions 401 and 402, even if the surge current is large and overflows from the PN junction region, the insulating region 401, which surrounds the diode, 40
Completely cut off the surge current that 2 overflows. Therefore, in the semiconductor device formed around the diode, malfunction due to noise generated by the overflow surge current can be prevented.
【０１１３】（他の実施形態）上記各実施形態において
は、高融点絶縁保護膜としてＬＯＣＯＳ酸化膜を用いた
が、これに限らず、酸化シリコン（ＳｉＯ）膜であって
もよいし、窒化シリコン（ＳｉＮ）膜であってもよい。
また、これらの膜を積層して使用することも可能であ
る。(Other Embodiments) In each of the above embodiments, the LOCOS oxide film is used as the high melting point insulating protective film, but the invention is not limited to this, and a silicon oxide (SiO) film or a silicon nitride film may be used. It may be a (SiN) film.
It is also possible to stack these films and use them.
【０１１４】さらに、これら高融点絶縁保護膜の形成方
法としては、物理的あるいは化学的な気相成長により膜
形成してもよいし、ＬＯＣＯＳ酸化膜の形成で用いられ
たように、基板の酸化処理や窒化処理によって膜形成し
てもよい。Further, as the method of forming these high melting point insulating protective films, the film may be formed by physical or chemical vapor deposition, or the substrate may be oxidized as used in forming the LOCOS oxide film. The film may be formed by treatment or nitriding treatment.
【０１１５】また、上記実施形態において、基板として
低濃度Ｎ型シリコン基板を用いたが、これに限らず、低
濃度Ｐ型シリコン基板であってもよい。さらに、任意の
シリコン基板上に、厚さ１０μｍ以上でＮ型あるいはＰ
型の不純物を低濃度に含有するエピタキシャル膜を形成
した基板を用いてもよい。Although the low concentration N-type silicon substrate is used as the substrate in the above embodiment, the present invention is not limited to this, and a low concentration P-type silicon substrate may be used. Furthermore, it is N-type or P-type with a thickness of 10 μm or more on any silicon substrate.
A substrate on which an epitaxial film containing a low-type impurity is formed may be used.
【０１１６】以上述べたように、本案によれば容易にサ
ージ耐量の高い保護素子を実現でき、ＩＣ設計技術向上
に寄与するところ大である。As described above, according to the present invention, it is possible to easily realize a protection element having a high surge resistance, which greatly contributes to the improvement of IC design technology.
【図１】（ａ）は本発明における第１の実施形態のダイ
オードの構造を示す平面図であり、（ｂ）はその拡大断
面図である。FIG. 1A is a plan view showing a structure of a diode according to a first embodiment of the present invention, and FIG. 1B is an enlarged sectional view thereof.
【図２】本発明におけるダイオードの概略の製造工程を
示す工程別の断面図である。FIG. 2 is a sectional view for each step showing a schematic manufacturing process of a diode according to the present invention.
【図３】本発明のダイオードと共に同じ基板の別位置に
形成されるＣＭＯＳ半導体装置の概略の製造工程を示す
工程別の断面図である。FIG. 3 is a sectional view for each step showing a schematic manufacturing step of a CMOS semiconductor device formed at another position on the same substrate together with the diode of the present invention.
【図４】本発明における第２の実施形態のダイオードの
構造を示す平面図である。FIG. 4 is a plan view showing a structure of a diode according to a second embodiment of the present invention.
【図５】本発明における第３の実施形態のダイオードの
構造を示す平面図である。FIG. 5 is a plan view showing a structure of a diode according to a third embodiment of the present invention.
【図６】本発明における第４の実施形態のダイオードの
構造を示す平面図である。FIG. 6 is a plan view showing the structure of a diode according to a fourth embodiment of the present invention.
【図７】本発明における第５の実施形態のダイオードの
構造を示す平面図である。FIG. 7 is a plan view showing the structure of a diode according to a fifth embodiment of the present invention.
【図８】本発明における第６の実施形態のダイオードの
構造を示す平面図である。FIG. 8 is a plan view showing a structure of a diode according to a sixth embodiment of the present invention.
【図９】（ａ）は本発明における第７の実施形態のダイ
オードの構造を示す平面図であり、（ｂ）はその拡大断
面図である。9A is a plan view showing the structure of a diode according to a seventh embodiment of the present invention, and FIG. 9B is an enlarged sectional view thereof.
【図１０】本発明における第８の実施形態のダイオード
の構造を示す平面図である。FIG. 10 is a plan view showing the structure of a diode according to an eighth embodiment of the present invention.
【図１１】（ａ）は本発明における第９の実施形態のダ
イオードの構造を示す平面図であり、（ｂ）はその拡大
断面図である。FIG. 11A is a plan view showing a structure of a diode according to a ninth embodiment of the present invention, and FIG. 11B is an enlarged sectional view thereof.
【図１２】（ａ）は本発明における第１０の実施形態の
ダイオードの構造を示す平面図であり、（ｂ）はその拡
大断面図である。FIG. 12A is a plan view showing the structure of a diode according to a tenth embodiment of the present invention, and FIG. 12B is an enlarged sectional view thereof.
【図１３】（ａ）は本発明における第１１の実施形態の
ダイオードの構造を示す平面図であり、（ｂ）はその拡
大断面図である。FIG. 13A is a plan view showing a structure of a diode according to an eleventh embodiment of the present invention, and FIG. 13B is an enlarged sectional view thereof.
【図１４】（ａ）は従来のダイオードの構造を示す平面
図であり、（ｂ）はその拡大断面図である。FIG. 14A is a plan view showing a structure of a conventional diode, and FIG. 14B is an enlarged sectional view thereof.
【図１５】従来のダイオードの概略の製造工程を示す工
程別の断面図である。FIG. 15 is a sectional view for each step showing a schematic manufacturing process of a conventional diode.
１ 低濃度Ｎ型シリコン基板 ２ Ｐ型高濃度拡散領域（ベース） ３ａ、３ｂ Ｎ型高濃度拡散領域（エミッタ） ４ａ、４ｂ ＰＮ接合領域 ５ 下層の層間絶縁膜（ＢＰＳＧ） ５０ ＬＯＣＯＳ酸化膜の開口部 ５００ ＬＯＣＯＳ酸化膜（高融点絶縁保護膜） ５００ａ、５００ｂ ＬＯＣＯＳ酸化膜のブリッジ部 ７ａ、７ｂ 下層電極（Ａｌ） ８ 上層の層間絶縁膜（ＴＥＯＳ） ９ａ、９ｂ 上層電極（Ａｌ） ９０ａ、９０ｂ パッド １０ 保護膜（ＳｉＮ） 1 Low concentration N type silicon substrate 2 P type high concentration diffusion region (base) 3a, 3b N-type high concentration diffusion region (emitter) 4a, 4b PN junction region 5 Lower interlayer insulating film (BPSG) 50 LOCOS oxide film opening 500 LOCOS oxide film (high melting point insulation protection film) 500a, 500b LOCOS oxide film bridge 7a, 7b Lower layer electrode (Al) 8 Upper interlayer insulating film (TEOS) 9a, 9b Upper layer electrode (Al) 90a, 90b pad 10 Protective film (SiN)
フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 27/06 ３１１ Ｈ０１Ｌ 27/06 １０１Ｐ 27/092 29/861 Ｆターム(参考） 5F038 AV06 BH04 BH13 CA02 EZ20 5F048 AA02 AC03 AC10 BB05 BB09 BE03 BF11 BF16 BG12 CC06 CC13 CC19 DA07 DA08 5F082 AA31 BA48 BC09 BC11 EA09 FA16 GA02 Front page continuation (51) Int.Cl. 7 Identification code FI theme code (reference) H01L 27/06 311 H01L 27/06 101P 27/092 29/861 F term (reference) 5F038 AV06 BH04 BH13 CA02 EZ20 5F048 AA02 AC03 AC10 BB05 BB09 BE03 BF11 BF16 BG12 CC06 CC13 CC19 DA07 DA08 5F082 AA31 BA48 BC09 BC11 EA09 FA16 GA02
Claims (19)
ジ部で分割される３個の開口部を備える高融点絶縁保護
膜と、 前記３個の開口部の中央の開口部を介して半導体中に配
置され、Ｐ型またはＮ型からなる第１高濃度拡散領域
と、 前記３個の開口部の両端の開口部を介して半導体中に配
置され、前記第１高濃度拡散領域とは逆型のＰ型または
Ｎ型からなる２個の第２高濃度拡散領域とを有し、 前記２本の等幅ブリッジ部の下に配置され、前記第１高
濃度拡散領域と前記第２高濃度拡散領域の間の半導体か
らなるＰＮ接合領域が、等幅に２本形成され、 前記２個の第２高濃度拡散領域同士が電極を介して互い
に接続されることを特徴とするダイオード。1. A high-melting-point insulating protective film provided on a semiconductor and having three openings divided by two equal-width bridge portions, and a central opening of the three openings. The first high-concentration diffusion region which is arranged in the semiconductor and is of P-type or N-type and the first high-concentration diffusion region which is arranged in the semiconductor through the openings at both ends of the three openings And two second high-concentration diffusion regions of inverted P-type or N-type, which are arranged below the two equal-width bridge portions, and have the first high-concentration diffusion region and the second high-concentration diffusion region. A diode, wherein two PN junction regions made of a semiconductor between the concentration diffusion regions are formed with an equal width, and the two second high concentration diffusion regions are connected to each other via electrodes.
ジ部で分割される３個の開口部を１組の開口群として、
前記開口群をｍ組備える高融点絶縁保護膜と、 前記ｍ組の開口群の各々の中央の開口部を介して半導体
中に配置され、Ｐ型またはＮ型のどちらか１つの型から
なるｍ個の第１高濃度拡散領域と、 前記ｍ組の開口群の各々の両端の開口部を介して半導体
中に配置され、前記第１高濃度拡散領域とは逆型のＰ型
またはＮ型からなる２ｍ個の第２高濃度拡散領域とを有
し、 前記ｍ組の各々の開口群の２本の等幅ブリッジ部の下に
配置され、前記第１高濃度拡散領域と前記第２高濃度拡
散領域の間の半導体からなるＰＮ接合領域が、等幅に２
ｍ本形成され、 前記ｍ個の第１高濃度拡散領域同士が電極を介して互い
に接続され、 前記２ｍ個の第２高濃度拡散領域同士が電極を介して互
いに接続されることを特徴とするダイオード。2. A group of three openings arranged on a semiconductor and divided by two equal-width bridge parts,
A high-melting-point insulating protective film having m sets of the opening groups, and an m-type high-melting-point insulating protection film disposed in the semiconductor through the central opening of each of the m sets of the opening groups. A plurality of first high-concentration diffusion regions and a first high-concentration diffusion region, which is arranged in the semiconductor through the openings at both ends of each of the m sets of openings, 2m second high-concentration diffusion regions, which are arranged below the two equal-width bridge portions of each of the m sets of aperture groups, the first high-concentration diffusion regions and the second high-concentration diffusion regions. The PN junction region made of a semiconductor between the diffusion regions has a uniform width of 2
m pieces are formed, the m first high-concentration diffusion regions are connected to each other via electrodes, and the 2m second high-concentration diffusion regions are connected to each other via electrodes. diode.
ジ部で分割される（ｎ＋１）個の開口部を備える高融点
絶縁保護膜と、 前記（ｎ＋１）個の開口部のうち、１つおきに位置する
開口部からなる第１の開口群の各々の開口部を介して半
導体中に配置され、Ｐ型またはＮ型のどちらか１つの型
からなる複数個の第１高濃度拡散領域の組と、 前記第１の開口群の各々の開口部に隣接する、１つおき
に位置する開口部からなる第２の開口群の各々の開口部
を介して半導体中に配置され、前記第１高濃度拡散領域
とは逆型のＰ型またはＮ型からなる複数個の第２高濃度
拡散領域の組とを有し、 前記ｎ本の各々の等幅ブリッジ部の下に配置され、前記
第１高濃度拡散領域と前記第２高濃度拡散領域の間の半
導体からなるＰＮ接合領域が、等幅にｎ本形成され、 前記複数個の第１高濃度拡散領域同士が電極を介して互
いに接続され、 前記複数個の第２高濃度拡散領域同士が電極を介して互
いに接続されることを特徴とするダイオード。3. A high-melting-point insulating protective film provided on a semiconductor and having (n + 1) openings divided by n equal-width bridge portions, and one of the (n + 1) openings. A plurality of first high-concentration diffusion regions of one type of P-type or N-type which are arranged in the semiconductor through the respective openings of the first group of openings located at alternate intervals. And a second group of openings adjacent to each of the first group of openings adjacent to each other, the second group of openings being arranged in the semiconductor, 1 high-concentration diffusion region and a set of a plurality of second high-concentration diffusion regions of the opposite P-type or N-type, and arranged under each of the n equal-width bridge portions, The n high-concentration PN junction regions made of a semiconductor between the first high-concentration diffusion region and the second high-concentration diffusion region have the same width. A diode, wherein the plurality of first high-concentration diffusion regions are connected to each other via electrodes, and the plurality of second high-concentration diffusion regions are connected to each other via electrodes.
状が、前記等幅ブリッジ部を長辺とする矩形であること
を特徴とする請求項１乃至３のいずれか１つに記載のダ
イオード。4. The plan view of the opening of the high melting point insulating protective film is a rectangle having the constant width bridge portion as a long side. diode.
の開口部と前記第２高濃度拡散領域を形成するための開
口部とは、前記等幅ブリッジに沿った方向の長さが異な
ることを特徴とする請求項４に記載のダイオード。5. An opening for forming the first high-concentration diffusion region and an opening for forming the second high-concentration diffusion region have different lengths in the direction along the monospaced bridge. The diode according to claim 4, wherein:
の角部が丸められ、略矩形状に形成されることを特徴と
する請求項４または５に記載のダイオード。6. The diode according to claim 4, wherein a corner portion of a rectangular opening of the high melting point insulating protective film is rounded to be formed into a substantially rectangular shape.
される第１高濃度拡散領域、第２高濃度拡散領域の少な
くとも一方の高濃度拡散領域において、長手方向におけ
る矩形の両端部の周囲に、前記一方の高濃度拡散領域と
同型の不純物によって当該一方の高濃度拡散領域よりも
低濃度の低濃度拡散領域を形成したことを特徴とする請
求項４乃至６のいずれか１つに記載のダイオード。7. A high-concentration diffusion region of at least one of a first high-concentration diffusion region and a second high-concentration diffusion region formed in a rectangular shape through the rectangular opening, and at both end portions of the rectangle in the longitudinal direction. 7. A low-concentration diffusion region having a lower concentration than that of the one high-concentration diffusion region is formed in the periphery by impurities of the same type as that of the one high-concentration diffusion region. The diode described.
１高濃度拡散領域および前記第２高濃度拡散領域に接触
するそれぞれの電極のコンタクト面の形状は、 前記開口部の長辺をなす前記等幅ブリッジ部との間隔よ
りも、前記開口部の短辺との間隔のほうが大きいことを
特徴とする請求項４乃至７のいずれか１つに記載のダイ
オード。8. The shape of the contact surface of each electrode formed inside the rectangular opening and contacting the first high-concentration diffusion region and the second high-concentration diffusion region forms a long side of the opening. The diode according to any one of claims 4 to 7, wherein a distance between a short side of the opening is larger than a distance between the constant width bridge portion and the diode.
円状に形成されたことを特徴とする請求項１乃至３のい
ずれか１つに記載のダイオード。9. The diode according to claim 1, wherein the openings of the high melting point insulating protective film are formed in a concentric shape.
濃度拡散領域を形成するための前記高融点絶縁保護膜の
開口部上に第１高濃度拡散領域と第２高濃度拡散領域の
各々に対応して形成した第1下層電極および第２下層電
極が設けられ、 前記第1下層電極および第２下層電極上に層間絶縁膜が
形成され、 当該層間絶縁膜において、第1下層電極に対応して第1層
間絶縁膜開口部が形成され、第２下層電極に対応して第
２層間絶縁膜開口部が形成され、 前記層間絶縁膜上に第1上層電極および第２上層電極が
形成され、 第1上層電極は前記第1層間絶縁膜開口部を介して第１高
濃度拡散領域に対応する第1下層電極に接続され、第２
上層電極は前記第２層間絶縁膜開口部を介して第２高濃
度拡散領域に対応する第２下層電極に接続されたことを
特徴とする請求項１乃至９のいずれか１つに記載のダイ
オード。10. The first high-concentration diffusion region and the second high-concentration diffusion region are formed on the opening of the high-melting-point insulating protective film for forming the first high-concentration diffusion region and the second high-concentration diffusion region. A first lower layer electrode and a second lower layer electrode formed corresponding to each are provided, an interlayer insulating film is formed on the first lower layer electrode and the second lower layer electrode, and in the interlayer insulating film, a first lower layer electrode is formed. A first interlayer insulating film opening is formed correspondingly, a second interlayer insulating film opening is formed corresponding to the second lower layer electrode, and a first upper layer electrode and a second upper layer electrode are formed on the interlayer insulating film. The first upper layer electrode is connected to the first lower layer electrode corresponding to the first high concentration diffusion region through the first interlayer insulating film opening,
10. The diode according to claim 1, wherein the upper layer electrode is connected to the second lower layer electrode corresponding to the second high concentration diffusion region through the second interlayer insulating film opening. .
ける平面内の最短幅は、それぞれ、前記第1下層電極、
第２下層電極における平面内の最短幅より大きいことを
特徴とする請求項１０に記載のダイオード。11. The shortest widths in the plane of the first upper layer electrode and the second upper layer electrode are respectively the first lower layer electrode,
The diode according to claim 10, which is larger than the shortest width in the plane of the second lower layer electrode.
電極上に保護膜が形成され、 前記第１上層電極に対応して前記保護膜に開口を形成
し、この開口部により露出される前記第１上層電極によ
り第1パッドを形成し、 前記第２上層電極に対応して前記保護膜に開口を形成
し、この開口部により露出される前記第２上層電極によ
り第２パッドを形成し、 前記第1パッドと前記第２パッドが前記高融点絶縁保護
膜の開口部を間に挟んでその両側に配置され、前記第1
上層電極と前記第２上層電極の幅を、それぞれ、第1パ
ッドと第２パッドに近くなるほど大きくしたことを特徴
とする請求項１０または１１に記載のダイオード。12. A protective film is formed on the first upper layer electrode and the second upper layer electrode, an opening is formed in the protective film corresponding to the first upper layer electrode, and the opening is exposed by the opening. A first pad is formed by the first upper layer electrode, an opening is formed in the protective film corresponding to the second upper layer electrode, and a second pad is formed by the second upper layer electrode exposed by the opening, The first pad and the second pad are arranged on both sides of the opening of the high-melting point insulating protective film with the opening interposed therebetween.
12. The diode according to claim 10 or 11, wherein the upper electrode and the second upper electrode have a width that increases toward the first pad and the second pad, respectively.
拡散領域、前記第２高濃度拡散領域、前記ＰＮ接合領域
を、Ｐ型の第３高濃度拡散領域で取り囲み、前記第３高
濃度拡散領域を電極を介して接地したことを特徴とする
請求項１乃至１２のいずれか１つに記載のダイオード。13. The third high-concentration diffusion region is formed by surrounding the first high-concentration diffusion region, the second high-concentration diffusion region, and the PN junction region arranged in a semiconductor with a P-type third high-concentration diffusion region. The diode according to claim 1, wherein the diffusion region is grounded via an electrode.
拡散領域、前記第２高濃度拡散領域、前記ＰＮ接合領域
を、絶縁領域で取り囲んだことを特徴とする請求項１乃
至１２のいずれか１つに記載のダイオード。14. The method according to claim 1, wherein the first high concentration diffusion region, the second high concentration diffusion region and the PN junction region arranged in a semiconductor are surrounded by an insulating region. The diode according to item 1.
酸化膜、酸化シリコン膜、窒化シリコン膜のいずれか１
つの膜、もしくはそれらの積層膜よりなることを特徴と
する請求項１乃至１４のいずれか１つに記載のダイオー
ド。15. The high melting point insulating protective film is LOCOS.
Any one of oxide film, silicon oxide film, and silicon nitride film
15. The diode according to claim 1, comprising one film or a laminated film thereof.
ッジ部で分割される３個の開口部を備える高融点絶縁保
護膜を設ける工程と、 前記３個の開口部の中央の開口部を介して半導体中に不
純物をイオン注入して、Ｐ型またはＮ型からなる第１高
濃度拡散領域を形成する工程と、 前記３個の開口部の両端の開口部を介して半導体中に不
純物をイオン注入して、第１高濃度拡散領域とは逆型
の、Ｐ型またはＮ型からなる第２高濃度拡散領域を２個
形成する工程と、 前記２個の第２高濃度拡散領域同士を電極を介して互い
に接続する工程とを有することを特徴とするダイオード
の製造方法。16. A step of providing a high-melting-point insulating protective film having three openings arranged on a semiconductor and divided by two equal-width bridge parts, and an opening at the center of the three openings. A step of ion-implanting an impurity into the semiconductor through the step of forming a first high-concentration diffusion region of P-type or N-type, and impurities in the semiconductor through the openings at both ends of the three openings. Ion implantation is performed to form two second high-concentration diffusion regions of P-type or N-type that are opposite to the first high-concentration diffusion region, and the two second high-concentration diffusion regions are connected to each other. And a step of connecting the electrodes to each other via an electrode.
ッジ部で分割される３個の開口部を１組の開口群とし
て、前記開口群をｍ組備える高融点絶縁保護膜を設ける
工程と、 前記ｍ組の開口群の各々の中央の開口部を介して半導体
中に不純物をイオン注入して、Ｐ型またはＮ型からなる
第１高濃度拡散領域をｍ個形成する工程と、 前記ｍ組の開口群の各々の両端の開口部を介して半導体
中に不純物をイオン注入して、第１高濃度拡散領域とは
逆型の、Ｐ型またはＮ型からなる第２高濃度拡散領域を
２ｍ個形成する工程と、 前記ｍ個の第１高濃度拡散領域同士を電極を介して互い
に接続する工程と、 前記２ｍ個の第２高濃度拡散領域同士を電極を介して互
いに接続する工程とを有することを特徴とするダイオー
ドの製造方法。17. A step of providing a high-melting-point insulating protective film comprising m sets of three openings arranged on a semiconductor and divided by two equal-width bridge parts as one set of openings. And ion-implanting impurities into the semiconductor through the central opening of each of the m sets of openings to form m first high-concentration diffusion regions of P-type or N-type. A second high-concentration diffusion region of P-type or N-type, which is the opposite type to the first high-concentration diffusion region, is formed by ion-implanting impurities into the semiconductor through the openings at both ends of each of the m sets of openings. 2m, a step of connecting the m first high-concentration diffusion regions to each other via electrodes, and a step of connecting the 2m second high-concentration diffusion regions to each other via electrodes. A method for manufacturing a diode, comprising:
ッジ部で分割される（ｎ＋１）個の開口部を備える高融
点絶縁保護膜を設ける工程と、 前記（ｎ＋１）個の開口部のうち、１つおきに位置する
開口部からなる第１の開口群の各々の開口部を介して半
導体中に不純物をイオン注入して、Ｐ型またはＮ型から
なる第１高濃度拡散領域を複数個形成する工程と、 前記第１の開口群の各々の開口部に隣接する、１つおき
に位置する開口部からなる第２の開口群の各々の開口部
を介して半導体中に不純物をイオン注入して、第１高濃
度拡散領域とは逆型の、Ｐ型またはＮ型からなる第２高
濃度拡散領域を複数個形成する工程と、 前記複数個の第１高濃度拡散領域同士を電極を介して互
いに接続する工程と、 前記複数個の第２高濃度拡散領域同士を電極を介して互
いに接続する工程とを有することを特徴とするダイオー
ドの製造方法。18. A step of providing a high-melting-point insulating protective film having (n + 1) openings arranged on a semiconductor and divided by n equal-width bridge parts, and (n + 1) openings. Of these, a plurality of first high-concentration diffusion regions of P-type or N-type are formed by ion-implanting impurities into the semiconductor through the openings of the first opening group including the openings located at every other position. And a step of individually forming impurities, and ion-implanting impurities into the semiconductor through each opening of the second opening group, which is adjacent to each opening of the first opening group and is formed of every other opening. Implanting to form a plurality of P-type or N-type second high-concentration diffusion regions opposite to the first high-concentration diffusion regions; and forming an electrode between the plurality of first high-concentration diffusion regions. Connecting to each other through a plurality of second high-concentration diffusion regions Method for producing a diode; and a step of through electrodes connected to each other.
酸化膜、酸化シリコン膜、窒化シリコン膜のいずれか１
つの膜、もしくはそれらの積層膜よりなることを特徴と
する請求項１６乃至１８のいずれか１つに記載のダイオ
ードの製造方法。19. The high melting point insulating protective film is LOCOS.
Any one of oxide film, silicon oxide film, and silicon nitride film
19. The method for manufacturing a diode according to claim 16, comprising one film or a laminated film thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002020135A JP4144225B2 (en) | 2002-01-29 | 2002-01-29 | Diode and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002020135A JP4144225B2 (en) | 2002-01-29 | 2002-01-29 | Diode and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003224133A true JP2003224133A (en) | 2003-08-08 |
| JP4144225B2 JP4144225B2 (en) | 2008-09-03 |
Family
ID=27743715
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002020135A Expired - Fee Related JP4144225B2 (en) | 2002-01-29 | 2002-01-29 | Diode and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4144225B2 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005203707A (en) * | 2004-01-19 | 2005-07-28 | Denso Corp | Semiconductor device |
| JP2006319073A (en) * | 2005-05-11 | 2006-11-24 | Denso Corp | Protection element |
| JP2009076761A (en) * | 2007-09-21 | 2009-04-09 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method therefor |
| JP2010034518A (en) * | 2008-06-25 | 2010-02-12 | Semiconductor Energy Lab Co Ltd | Semiconductor device and electronic apparatus |
| JP2010041042A (en) * | 2008-07-10 | 2010-02-18 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| JP2010219504A (en) * | 2009-02-23 | 2010-09-30 | Seiko Instruments Inc | Semiconductor device |
| CN102891186A (en) * | 2011-07-20 | 2013-01-23 | 拉碧斯半导体株式会社 | Protection diode and semiconductor device having the same |
| US9293578B2 (en) | 2012-07-03 | 2016-03-22 | Hitachi, Ltd. | Semiconductor device |
| JP2019520710A (en) * | 2016-06-30 | 2019-07-18 | 日本テキサス・インスツルメンツ合同会社 | Contact Array Optimization for ESD Devices |
-
2002
- 2002-01-29 JP JP2002020135A patent/JP4144225B2/en not_active Expired - Fee Related
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005203707A (en) * | 2004-01-19 | 2005-07-28 | Denso Corp | Semiconductor device |
| JP2006319073A (en) * | 2005-05-11 | 2006-11-24 | Denso Corp | Protection element |
| JP2009076761A (en) * | 2007-09-21 | 2009-04-09 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method therefor |
| JP2010034518A (en) * | 2008-06-25 | 2010-02-12 | Semiconductor Energy Lab Co Ltd | Semiconductor device and electronic apparatus |
| JP2010041042A (en) * | 2008-07-10 | 2010-02-18 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| US8860081B2 (en) | 2008-07-10 | 2014-10-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| JP2010219504A (en) * | 2009-02-23 | 2010-09-30 | Seiko Instruments Inc | Semiconductor device |
| CN102891186A (en) * | 2011-07-20 | 2013-01-23 | 拉碧斯半导体株式会社 | Protection diode and semiconductor device having the same |
| JP2013026384A (en) * | 2011-07-20 | 2013-02-04 | Lapis Semiconductor Co Ltd | Protective diode and semiconductor device including the same |
| US9293578B2 (en) | 2012-07-03 | 2016-03-22 | Hitachi, Ltd. | Semiconductor device |
| JP2019520710A (en) * | 2016-06-30 | 2019-07-18 | 日本テキサス・インスツルメンツ合同会社 | Contact Array Optimization for ESD Devices |
| JP7021414B2 (en) | 2016-06-30 | 2022-02-17 | テキサス インスツルメンツ インコーポレイテッド | Contact array optimization for ESD devices |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4144225B2 (en) | 2008-09-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2913158B2 (en) | MOS transistor structure having electrostatic breakdown prevention circuit | |
| CN106409894B (en) | Semiconductor device and method for manufacturing the same | |
| US6855611B2 (en) | Fabrication method of an electrostatic discharge protection circuit with a low resistant current path | |
| JPH058583B2 (en) | ||
| JP2006310508A (en) | Semiconductor device and its manufacturing method | |
| KR101617544B1 (en) | Systems and methods for a semiconductor structure having multiple semiconductor-device layers | |
| US6943383B2 (en) | Diode and producing method thereof | |
| JP2003224133A (en) | Diode and its manufacturing method | |
| JP2007220814A (en) | Semiconductor device | |
| KR100945326B1 (en) | Soi type semiconductor device and method for fabricating the same | |
| KR100630649B1 (en) | Esd protection circuit | |
| JP2005183891A (en) | Structure of bidirectional block type planar device and method of manufacturing the same | |
| JP2005294634A (en) | Semiconductor device and manufacturing method thereof | |
| JP2004363136A (en) | Semiconductor circuit device | |
| JP2005203738A (en) | Diode | |
| JP3853294B2 (en) | SOI type semiconductor device and manufacturing method thereof | |
| JP4479041B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP6533266B2 (en) | Semiconductor device | |
| KR100418567B1 (en) | 2-input NOR Gate comprising NMOS tansistor and PMOS transistor formed on different semiconductor layers | |
| JP3211871B2 (en) | I / O protection circuit | |
| JP3237269B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3744460B2 (en) | Semiconductor device | |
| JP2008252038A (en) | Semiconductor device | |
| JP2004516650A (en) | Semiconductor device layout | |
| JP2001223277A (en) | I/o protective circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20040409 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20060215 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060221 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060411 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20070821 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20071005 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20080527 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20080609 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 4144225 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110627 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110627 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120627 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120627 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130627 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140627 Year of fee payment: 6 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |