JP6533266B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  Patent Document 1 discloses a semiconductor device including a p-type well region for separating an element formation region and a DMOS transistor formed in the element formation region. The semiconductor device has a p-type silicon substrate, n-type source and drain regions selectively formed on the surface of the silicon substrate and separated from each other by a field oxide film, and a gate oxide film on the silicon substrate. And a gate electrode formed on the substrate. A field oxide film is formed on the p-type well region.

JP 2012-156205 A

In a semiconductor device having an element isolation structure as in Patent Document 1, the DMOS transistor may be mixed with other elements. In such a semiconductor device, not only the wiring electrically connected to the DMOS transistor but a plurality of wirings electrically connected to other elements are formed. Then, various voltages adapted to the respective elements are applied to the plurality of wirings.
Here, when the wire passes near the field insulating film or intersects with the field insulating film, an area in the semiconductor substrate immediately below the field insulating film due to an electric field from the wire (ie, an element formation region Field inversion occurs in the p-well region). Therefore, the field-inverted region becomes a leak path, a leak current occurs, and an element isolation failure occurs. The generation of such a leak current due to the electric field from the wiring becomes more remarkable as the voltage applied to the wiring becomes higher.

In order to avoid this problem, it is possible to create a design rule in which the wiring is formed at a certain distance from the field insulating film according to the voltage applied to the wiring, and the device design can be performed accordingly. However, this method not only makes it possible to effectively utilize the semiconductor chip area, but also hinders high shrinkage of the semiconductor chip.
Therefore, an embodiment of the present invention has an object to provide a semiconductor device capable of realizing stable element isolation while suppressing the occurrence of field inversion.

  One embodiment of the present invention covers a semiconductor layer including an element region having a semiconductor element, an element isolation well formed in a surface layer portion of the semiconductor layer so as to partition the element region, and the element isolation well. A field insulating film formed on the semiconductor layer, an interlayer insulating film formed on the semiconductor layer, and a wire formed on the interlayer insulating film so as to cross the element region in plan view And a conductor film formed on the field insulating film so as to cross the region opposed to the wiring in the field insulating film and having a width equal to or less than the width of the element isolation well. .

  According to this configuration, the conductor film can reduce the influence of the electric field from the wiring. Specifically, since the conductor film fixed to a constant potential is disposed at a position closer to the wiring than the element isolation well, the electric field from the wiring can be effectively terminated by the conductor film. Thus, it is possible to suppress the occurrence of field inversion due to the ions in the element isolation well being attracted to the region directly below the field insulating film by the electric field from the wiring. As a result, it is possible to suppress the occurrence of a leak current by forming a leak path crossing the element isolation well, and it is possible to provide a semiconductor device capable of realizing stable element isolation. One embodiment of the present invention includes a low voltage device region having a low voltage device operating at a low reference voltage, and a high voltage device region having a high voltage device operating at a high reference voltage higher than the low reference voltage. A semiconductor layer, an element isolation well formed in a surface layer portion of the semiconductor layer so as to electrically isolate the low voltage element region and the high voltage element region, and a semiconductor layer of the semiconductor layer so as to cover the element isolation well A field insulating film formed thereon, an interlayer insulating film formed on the semiconductor layer, a wire formed on the interlayer insulating film, and electrically connected to the high voltage element region; A semiconductor device is provided, which is formed between an interlayer insulating film and the field insulating film, and includes a conductor film facing the element isolation well with the field insulating film interposed therebetween.

  According to this configuration, the conductor film can reduce the influence of the electric field from the wiring. Specifically, since the conductor film fixed to a constant potential is disposed at a position closer to the wiring than the element isolation well, the electric field from the wiring can be effectively terminated by the conductor film. Thus, it is possible to suppress the occurrence of field inversion due to the ions in the element isolation well being attracted to the region directly below the field insulating film by the electric field from the wiring. As a result, it is possible to suppress the occurrence of a leak current by forming a leak path crossing the element isolation well, and it is possible to provide a semiconductor device capable of realizing stable element isolation.

FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view as seen from section line II-II in FIG. FIG. 3A is an enlarged plan view showing an example of the layout of the conductive film of FIG. FIG. 3B is an enlarged plan view showing an example of the layout of the conductive film of FIG. FIG. 3C is an enlarged plan view showing an example of the layout of the conductive film of FIG. FIG. 4A is a cross-sectional view for illustrating an example of a manufacturing process of the semiconductor device of FIG. 1. FIG. 4B is a view showing the next manufacturing step of FIG. 4A. FIG. 4C is a view showing the next manufacturing step of FIG. 4B. FIG. 4D is a view showing the next manufacturing step of FIG. 4C. FIG. 4E is a view showing the next manufacturing step of FIG. 4D. FIG. 4F is a view showing the next manufacturing step of FIG. 4E. FIG. 4G is a view showing the next manufacturing step of FIG. 4F. FIG. 4H is a view showing the next manufacturing step of FIG. 4G. FIG. 5 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention. FIG. 6 is a schematic plan view of a semiconductor device according to a third embodiment of the present invention. FIG. 7 is a schematic plan view of a semiconductor device according to a fourth embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.
FIG. 1 is a schematic plan view of a semiconductor device 1 according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line II-II of FIG.
The semiconductor device 1 includes an epitaxial substrate 45 as an example of a semiconductor layer, and an element isolation well 7 for partitioning a low voltage element region 2 as an example of an element formation region which is electrically floated in a surface layer portion of the epitaxial substrate 45. including.

More specifically, the epitaxial substrate 45 includes a p-type silicon substrate 4 and an n ⁻ -type epitaxial layer 5 formed on the silicon substrate 4, and a strip-like p-type element separation exhibiting a closed curve in plan view Well 7 is formed to reach silicon substrate 4 from the surface of n ⁻ -type epitaxial layer 5. The layer thickness of the n ⁻ -type epitaxial layer 5 is, for example, 5.0 μm to 10 μm.

In this embodiment, the element isolation well 7 is formed in a square ring shape in plan view as shown in FIG. 1, but may be another closed curve structure such as an annular ring, a triangular ring, or the like. The element isolation well 7 has a two-layer structure of ap ⁺ well region 8 disposed on the upper side and ap ⁻ type low isolation (L / I) region 9 disposed on the lower side. The boundary between the regions 8 and 9 is set in the middle of the n ⁻ -type epitaxial layer 5 in the thickness direction. For example, the boundaries of the regions 8 and 9 are set at a depth of 1.0 μm to 2.0 μm from the surface of the epitaxial layer 5.

Thus, the low voltage device region 2 formed of a part of the n ⁻ -type epitaxial layer 5 surrounded by the device isolation well 7 on the silicon substrate 4 is partitioned in the epitaxial substrate 45.
In the low voltage element region 2, an n ⁺ -type embedded layer (B / L) 6 is selectively formed. The buried layer 6 is formed on the epitaxial substrate 45 so as to cross the boundary between the silicon substrate 4 and the n ⁻ -type epitaxial layer 5. The film thickness of the buried layer 6 is, for example, 2.0 μm to 3.0 μm.

  Further, in the epitaxial substrate 45, a high voltage element region 3 as an example of an element formation region which is electrically floated similarly to the low voltage element region 2 is partitioned in the outer peripheral region of the low voltage element region 2. The high voltage element region 3 may be formed adjacent to the low voltage element region 2 with the element isolation well 7 separated, as shown in FIG. 1, in the region away from the low voltage element region 2, It may be formed by a device isolation structure (for example, a well similar to the device isolation well 7).

Low voltage element region 2 is a region that operates based on a low reference voltage, and for example, a voltage of about 5 V to 100 V is applied. Further, a high voltage of, for example, about 400 V to 600 V is applied to high voltage element region 3.
A band-shaped field insulating film 10 having a closed curve is formed on the surface of the element isolation well 7. Similar to the element isolation well 7, the field insulating film 10 is formed in a square ring shape in plan view so as to surround the periphery of the low voltage element region 2. The field insulating film 10 is wider than the element isolation well 7 and is formed to completely cover the element isolation well 7. Field insulating film 10 is, for example, a LOCOS film formed by selectively oxidizing the surface of n ⁻ -type epitaxial layer 5.

  A conductor film 11 is formed on the field insulating film 10 so as to face the element isolation well 7 with the field insulating film 10 interposed therebetween. The conductor film 11 is formed in a strip shape that draws a closed curve, similarly to the element isolation well 7. That is, the conductor film 11 is formed in a square ring shape in plan view so as to surround the periphery of the low voltage element region 2. The conductor film 11 contains, for example, a conductive material such as polysilicon or aluminum, and the film thickness thereof is, for example, 0.4 μm to 1.0 μm. The conductor film 11 is fixed at a constant potential via, for example, a wiring formed on an interlayer insulating film such as a first interlayer insulating film 21 and a second interlayer insulating film 25 described later. In this embodiment, the conductor film 11 is fixed to the ground potential. In this case, the conductor film 11 can be fixed to the ground potential by connecting to the source wiring 29 described later.

In the low voltage element region 2, a DMOS (Double-Diffused MOSFET) 35 is formed.
DMOS 35 includes an n ⁻ type well region 13 and ap ⁻ type well region 15 formed on the surface of n ⁻ type epitaxial layer 5 at a distance from each other. The n ⁻ -type well region 13 is annularly formed along the field insulating film 10 so as to surround the p ⁻ -type well region 15.

An n ⁺ -type drain region 14 having an impurity concentration higher than that of the n ⁻ -type well region 13 is formed on the surface of the n ⁻ -type well region 13. Further, p ^- the surface of the type well region 15, p ^- n ⁺ -type source region 17 so as to surround the p ⁺ -type impurity regions 16 having an impurity concentration higher than type well region 15 is formed.
The outer peripheral edge of the n ⁺ -type source region 17 is arranged at a certain distance from the outer peripheral edge of the p ⁻ -type well region 15 at the inner side. The n ⁺ -type source region 17 is formed, for example, with the same concentration and the same depth as the n ⁺ -type drain region 14. The p ⁺ -type impurity region 16 is formed at the same depth as the n ⁺ -type source region 17.

An annular field insulating film 12 is formed on the surface of the n ⁻ -type epitaxial layer 5 in a portion between the n ⁻ -type well region 13 and the p ⁻ -type well region 15. The field insulating film 12 is a LOCOS film formed in a square ring shape in plan view in the same step as the field insulating film 10 described above.
The outer peripheral edge of the field insulating film 12 is disposed on the peripheral edge of the n ⁺ -type drain region 14, and the inner peripheral edge of the field insulating film 12 is spaced a certain distance from the outer peripheral edge of the p ⁻ -type well region 15. Is located in The n ⁺ -type drain region 14 is formed in a region sandwiched by the outer peripheral edge of the field insulating film 12 and the field insulating film 10.

Further, n ^- the surface of the type epitaxial layer 5, n ^- -type epitaxial layer 5 and the p ^- type well region 15 a gate insulating film 18 so as to straddle between the is formed. Then, the gate electrode 19 is formed via the gate insulating film 18. The gate electrode 19 is formed to selectively cover a part of the gate insulating film 18 and a part of the field insulating film 12.
The gate electrode 19 is formed of, for example, the same material and the same film thickness as the above-described conductor film 11. Gate insulating film 18 is, for example, a silicon oxide film formed by oxidizing the surface of n ⁻ -type epitaxial layer 5.

A region where the gate electrode 19 faces the p ⁻ -type well region 15 via the gate insulating film 18 is a channel region 20 of the DMOS 35. The formation of the channel of the channel region 20 is controlled by the gate electrode 19.
Then, first to fourth interlayer insulating films 21, 25, 27, 36 are formed so as to cover the entire low voltage element region 2. The first to fourth interlayer insulating films 21, 25, 27, 36 are formed of an insulating film such as an oxide film or a nitride film, for example. In the present embodiment, the first to fourth interlayer insulating films 21, 25, 27, 36 are formed, but the fifth, sixth or more interlayer insulating may be further provided on the upper layer of the fourth interlayer insulating film 36. It may be a configuration in which a film is formed.

Low voltage contacts 23 and 24 are formed in the first interlayer insulating film 21. The low voltage contacts 23 and 24 include a drain contact 23 formed through the first interlayer insulating film 21 and a source contact 24. Hereinafter, the drain contact 23 and the source contact 24 may be collectively referred to as low voltage contacts 23 and 24. The drain contact 23 is electrically connected to the n ⁺ -type drain region 14, and the source contact 24 is electrically connected to the p ⁺ -type impurity region 16 and the n ⁺ -type source region 17. The low voltage contact may include a gate contact (not shown) electrically connected to the gate electrode 19.

A second interlayer insulating film 25 and a third interlayer insulating film 27 are formed in this order on the first interlayer insulating film 21 so as to cover the low voltage contacts 23 and 24. Then, on the third interlayer insulating film 27, low voltage wires 28 and 29 as an example of wires electrically connected to the low voltage contacts 23 and 24 are selectively formed.
Low voltage interconnections 28 and 29 include drain interconnection 28 and source interconnection 29 as shown in FIG. Hereinafter, the drain wire 28 and the source wire 29 may be collectively referred to as low voltage wires 28 and 29. The drain wiring 28 is electrically connected to the n ⁺ -type drain region 14 through the drain contact 23, and the source wiring 29 is electrically connected to the n ⁺ -type source region 17 through the source contact 24. There is. The low voltage wiring may include a gate wiring (not shown) electrically connected to the gate electrode 19 through the gate contact.

In this embodiment, the drain wiring 28 and the source wiring 29 are drawn from the outer peripheral region across the element isolation well 7 in the width direction onto the drain contact 23 and the source contact 24, respectively. It is connected.
Source interconnection 29 is preferably fixed to a fixed potential, for example, the ground potential. Source interconnection 29 may be connected to conductor film 11, for example. Further, a voltage of, for example, about 5 V to 100 V is applied to drain interconnection 28, and a voltage of, for example, about 0 V to 30 V is applied to gate interconnection (not shown). Thus, the low voltage wiring is a low voltage wiring to which a relatively low voltage is applied. Then, a fourth interlayer insulating film 36 is formed on the third interlayer insulating film 27 so as to cover the low voltage wires 28 and 29 formed on the third interlayer insulating film 27.

  On the fourth interlayer insulating film 36, a high voltage wiring 30 as an example of a wiring is formed. The high voltage wiring 30 is a high voltage wiring to which a relatively higher voltage (for example, 400 V to 600 V) is applied than the low voltage wirings 28 and 29. In this embodiment, high voltage interconnection 30 is formed in a straight line crossing element isolation well 7 in the width direction so as to divide low voltage element region 2 into two parts. Drain contact of the high voltage element region 3).

Next, the layout of the conductor film 11 will be more specifically described with reference to FIGS. 3A to 3C. 3A to 3C are enlarged plan views showing an example of the layout of the conductive film 11 of FIG.
Referring to the layout of FIG. 3A, conductor film 11 is interposed between field insulating film 10 and intersection 31 where element isolation well 7 and high voltage interconnection 30 intersect. At this time, the width W ₁ of the field insulating film 10 is, for example, 5.0 μm to 10 μm. The width _{W 2} of the conductive film 11 is formed narrower than the width _{W 1} of the field insulating film 10, for example, a 2.0Myuemu～3.0Myuemu.

With respect to the direction in which the element isolation well 7 intersects the high voltage wiring 30 at the intersection 31 (the direction in which the element isolation well 7 extends), the length of the conductor film 11 is formed longer than the length L ₁ of the intersection 31 There is.
The length (that is, the width W ₂ of the conductor film 11) of the conductor film 11 is the intersection 31 in the direction in which the high voltage interconnection 30 intersects the element isolation well 7 at the intersection 31 (the extension direction of the high voltage interconnection 30). Less than the length L ₂ (ie, W ₂ <L ₂ ). In other words, in the conductor film 11, the area S ₁ (W ₂ × L _{1 in} this embodiment) of the intersection 34 where the conductor film 11 and the high voltage interconnection 30 intersect is the element isolation well 7 and the high voltage interconnection It is formed so as to be smaller than the area S ₂ (in this embodiment, L ₁ × L ₂ ) of the intersection 31 where 30 intersects (that is, S ₁ <S ₂ ).

Referring now to the layout of FIG. 3B, the width W ₂ of the conductive film 11 is different from the case of FIG. 3A described above, with respect to the extending direction of the high voltage line 30, inside the area of the field insulating film 10, cross It is formed in length L ₂ or more (that is, W ₂ LL ₂ ) of the portion 31. At this time, the width W ₂ of the conductor film 11 may be formed to be substantially equal to the width W ₁ of the field insulating film 10.

Further, in the conductor film 11, the area S ₁ (W ₂ × L _{1 in} this embodiment) of the intersection portion 34 where the conductor film 11 and the high voltage wiring 30 intersect is the element isolation well 7 and the high voltage wiring 30. There (in this embodiment, _{L 1} × _{L 2)} area _{S 2} of the cross section 31 which crosses over (i.e., _{S 1} ≧ _{S 2)} which is preferably formed so as to. With such a configuration, the conductor film 11 can completely and completely cover the region where the element isolation well 7 is formed via the field insulating film 10.

Next, referring to the layout in FIG. 3C, conductor film 11 is not formed in a band shape that draws a closed curve, and is formed only in the region where high voltage interconnection 30 and element isolation well 7 intersect and the periphery thereof. It differs from the previously described FIGS. 3A and 3B in that
In this case, the conductor film 11 is formed such that the length L ₃ of the conductor film 11 is equal to or more than the length L ₁ of the intersection 31 (L ₃ LL ₁ ) in the direction in which the element isolation well 7 extends. Is preferred. Further, FIG. 3C shows a configuration in which the width W ₂ of the conductor film 11 is formed to be equal to or less than the length L ₂ of the intersection portion 31 (that is, W ₂ ≦ L ₂ ) in the extending direction of the high voltage wiring 30. However, as in the case of FIG. 3B, it is preferable that the intersection 31 be formed to have a length L ₂ or more (that is, W ₂ L L ₂ ).

That is, the area S _{3 of the} region where the conductive film 11 is formed (in this embodiment, W ₂ × L ₃ ) is the area S of the intersection 34 between the conductive film 11 and the high voltage wiring 30 as shown in FIG. 3C. It is preferable to be formed larger than ₁ (in this embodiment, W ₂ × L ₁ ). With such a configuration, not only the element isolation well 7 immediately below the high voltage wiring 30 but also the element isolation well 7 located in a region separated from the high voltage wiring 30 can be reliably covered. The area S ₃ (in this embodiment, W ₂ × L ₃ ) of the region where the conductive film 11 is formed is the same as the area S ₁ (in this embodiment, W ₁ × L _{1 in} this embodiment) It may be S ₁ = S ₃ ) or may be the same area as the area S ₂ (in this embodiment, L ₁ × L _{2 in} this embodiment) of the intersection 31 (that is, S ₂ = S ₃ ).

3A to 3C show an example of the layout of the high voltage wiring 30 and the conductor film 11, but the layout of these is not limited to the high voltage wiring 30. For example, the low voltage wiring 28, It is applicable to 29.
As described above, in the semiconductor device 1, the high voltage wiring 30 and the low voltage wirings 28 and 29 intersect the element isolation well 7. Therefore, the distance between the element isolation well 7 and each of the interconnections 28, 29, 30 is shorter than when the interconnections 28, 29, 30 and the element isolation well 7 do not cross each other. Furthermore, since the high voltage wiring 30 is applied with a voltage higher than that of the low voltage wirings 28 and 29, an electric field relatively higher than that of the low voltage wirings 28 and 29 is generated. Therefore, under such a structure, field inversion is relatively likely to occur in the region immediately below field insulating film 10, that is, in element isolation well 7.

  However, according to the semiconductor device 1, the conductor film 11 can reduce the influence of the electric field from the low voltage wires 28 and 29 and the high voltage wire 30. Specifically, since conductor film 11 fixed at the ground potential is disposed at a position closer to low voltage interconnections 28 and 29 and high voltage interconnection 30 than element isolation well 7, high voltage interconnection 30 and low voltage interconnection The electric field from both 28 and 29 can be effectively terminated by the conductor film 11.

  Thereby, it is suppressed that the field in the element isolation well 7 is attracted to the region directly under the field insulating film 10 by the electric field from both the low voltage interconnections 28 and 29 and the high voltage interconnection 30 to cause field inversion. Can. As a result, a leak path crossing the element isolation well 7 can be formed, and the occurrence of a leak current can be suppressed. Thus, a semiconductor device capable of realizing more stable element isolation can be provided.

  Further, in the case where conductor film 11 is formed in a band shape that draws a closed curve (the configuration of FIGS. 3A and 3B), conductor film 11 is always disposed immediately above element isolation well 7 in the region over field insulating film 10. It is done. Therefore, even if element isolation well 7 crosses low voltage interconnections 28 and 29 and high voltage interconnection 30, the electric field due to low voltage interconnections 28 and 29 and high voltage interconnection 30 can be favorably terminated by conductor film 11. .

As a result, regardless of the wiring rules of the low voltage wirings 28 and 29 and the high voltage wiring 30, the occurrence of field inversion in the element isolation well 7 can be suppressed, so the degree of freedom of the design rules can be further enhanced. As a result, the semiconductor chip area can be effectively utilized, and the semiconductor chip can be highly shrunk.
Next, manufacturing steps of the semiconductor device 1 will be described with reference to FIGS. 4A to 4H.

4A to 4H are cross-sectional views for describing an example of a manufacturing process of semiconductor device 1. 4A to 4H correspond to FIG. 2 respectively.
In order to manufacture the semiconductor device 1, as shown to FIG. 4A, the silicon substrate 4 of ap < ^- > type | mold is prepared. Next, n-type impurities and p-type impurities are selectively implanted into the surface of silicon substrate 4. Then, for example, the silicon of the silicon substrate 4 is epitaxially grown at a temperature of 1100 ° C. or higher while adding an n-type impurity. Thereby, as shown to FIG. 4B, the epitaxial substrate 45 containing the silicon substrate 4 and the n < ^- > type | mold epitaxial layer 5 is formed.

During epitaxial growth of the silicon substrate 4, n-type impurities and p-type impurities implanted in the silicon substrate 4 are diffused in the growth direction of the n ⁻ -type epitaxial layer 5. Thus, the buried layer 6 and the p ⁻ -type low isolation region 9 are formed across the boundary between the silicon substrate 4 and the n ⁻ -type epitaxial layer 5. Examples of p-type impurities include B (boron) and Al (aluminum), and examples of n-type impurities include P (phosphorus) and As (arsenic). it can.

Next, as shown in FIG. 4C, an ion implantation mask (not shown) having an opening selectively in the region where the p ⁺ well region 8 is to be formed is formed on the n ⁻ epitaxial layer 5. Then, p-type impurities are implanted into the n ⁻ -type epitaxial layer 5 through the ion implantation mask. Thus, an element isolation well 7 having a two-layer structure of the p ⁺ well region 8 and the p ⁻ low isolation region 9 is formed. After the element isolation well 7 is formed, the ion implantation mask is removed.

Next, a hard mask 32 having an opening selectively in the region where field insulating films 10 and 12 are to be formed is formed on n ⁻ -type epitaxial layer 5. Then, the surface of the n ⁻ -type epitaxial layer 5 is thermally oxidized through the hard mask 32 to form field insulating films 10 and 12 made of LOCOS films. The hard mask 32 is then removed.
Next, as shown in FIG. 4D, the surface of the n ⁻ -type epitaxial layer 5 is thermally oxidized to form the gate insulating film 18. At this time, the gate insulating film 18 is formed to be continuous with the field insulating films 10 and 12. Next, polysilicon for the conductor film 11 and the gate electrode 19 is deposited on the n ⁻ -type epitaxial layer 5 to form a polysilicon layer 33.

  Next, as shown in FIG. 4E, a resist mask (not shown) having an opening selectively in the region where the conductor film 11 and the gate electrode 19 are to be formed is formed on the polysilicon layer 33. Then, unnecessary portions of the polysilicon layer 33 are removed by etching through the resist mask. Thereby, the conductor film 11 and the gate electrode 19 are simultaneously formed. At this time, the layout of each conductive film 11 shown in FIGS. 3A to 3C can be obtained only by changing the layout of the resist mask. Thereafter, the resist mask is removed.

Next, a hard mask (not shown) having an opening selectively is formed on the n ⁻ -type epitaxial layer 5 in order to remove an unnecessary portion of the gate insulating film 18. Then, an unnecessary portion of the gate insulating film 18 is etched through the hard mask. Thereby, a predetermined gate insulating film 18 is formed. After the gate insulating film 18 is formed, the hard mask is removed.

Next, as shown in FIG. 4F, an n ⁻ -type well region 13 and a p ⁻ -type well region 15 are formed. In order to form the n ⁻ -type well region 13, first, an ion implantation mask (not shown) having an opening selectively in the region where the n ⁻ -type well region 13 is to be formed is formed. Then, an n-type impurity is implanted into the n ⁻ -type epitaxial layer 5 through the ion implantation mask. Thereby, the n ⁻ -type well region 13 is formed. After the n ⁻ -type well region 13 is formed, the ion implantation mask is removed. Further, in the same procedure, an ion implantation mask (not shown) having an opening selectively in the region where the p ⁻ -type well region 15 is to be formed is formed. Then, p-type impurities are implanted into the n ⁻ -type epitaxial layer 5 through the ion implantation mask. Thereby, the p ⁻ -type well region 15 is formed. After the p ⁻ -type well region 15 is formed, the ion implantation mask is removed.

Next, the p ⁺ -type impurity region 16 is formed in the inward region of the p ⁻ -type well region 15. In order to form the p ⁺ -type impurity region 16, first, an ion implantation mask (not shown) having an opening selectively in the region where the p ⁺ -type impurity region 16 is to be formed is formed. Then, p-type impurities are implanted into the p ⁻ -type well region 15 through the ion implantation mask. Thus, the p ⁺ -type impurity region 16 is formed in the inward region of the p ⁻ -type well region 15. After the p ⁺ -type impurity region 16 is formed, the ion implantation mask is removed.

Next, an n ⁺ -type drain region 14 and an n ⁺ -type source region 17 are selectively formed in the inner regions of the n ⁻ -type well region 13 and the p ⁻ -type well region 15, respectively. In order to form the n ⁺ -type drain region 14 and the n ⁺ -type source region 17, first, an ion implantation mask having an opening selectively in the region where the n ⁺ -type drain region 14 and the n ⁺ -type source region 17 are to be formed Not shown) is formed. Then, n-type impurities are implanted into the n ⁻ -type well region 13 and the p ⁻ -type well region 15 through the ion implantation mask. Thereby, the n ⁺ -type drain region 14 and the n ⁺ -type source region 17 are formed. After the n ⁺ -type drain region 14 and the n ⁺ -type source region 17 are formed, the ion implantation mask is removed.

Next, as shown in FIG. 4G, an insulating material is deposited so as to cover the conductor film 11 and the gate electrode 19, and the first interlayer insulating film 21 is formed. Next, a low voltage contact including a drain contact 23 and a source contact 24 is formed so as to penetrate the first interlayer insulating film 21, and is electrically connected to the n ⁺ type drain region 14 and the n ⁺ type source region 17 respectively. Connected. Next, a second interlayer insulating film 25 and a third interlayer insulating film 27 are formed in this order on the first interlayer insulating film 21 so as to cover the drain contact 23 and the source contact 24.

  Next, as shown in FIG. 4H, the low voltage wiring (see FIG. 1) including the drain wiring 28 and the source wiring 29 electrically connected to the drain contact 23 and the source contact 24 is the third interlayer insulating film 27. Formed selectively on top. In order to form the low voltage interconnections 28, 29, a resist mask having a predetermined opening is formed in the region where the low voltage interconnections 28, 29 are to be formed. Then, low voltage wirings 28 and 29 can be formed by depositing an electrode material through the resist mask.

Next, a fourth interlayer insulating film 36 is formed on the third interlayer insulating film 27 so as to cover the low voltage wires 28 and 29. Next, high voltage interconnection 30 electrically connected to high voltage element region 3 is formed on fourth interlayer insulating film 36. The semiconductor device 1 according to the first embodiment is manufactured through the above steps.
As described above, according to the method of manufacturing the semiconductor device 1, the conductor film 11 can be formed in the same step as the step of forming the gate electrode 19 of the DMOS 35. That is, the gate electrode 19 and the conductor film 11 of the DMOS 35 can be formed only by changing the layout of the resist mask in the manufacturing process of the semiconductor device 1 (see FIG. 4E). Therefore, since it is not necessary to add a new manufacturing process, the increase in the number of processes can be prevented.

Further, in the manufacturing process of FIG. 4E, the length of the conductor film 11 is formed to be equal to or longer than the length L ₁ of the intersection 31 in the extending direction of the element isolation well 7 (see FIGS. 3A to 3C). Even if misalignment (alignment misalignment) of low voltage interconnections 28 and 29 and high voltage interconnection 30 occurs along the direction in which isolation well 7 extends, conductor film 11 and low voltage interconnections 28 and 29 and high voltage interconnection 30 can be assured Can be crossed. As a result, it is possible to manufacture the semiconductor device 1 capable of effectively suppressing the occurrence of the field inversion in the element isolation well 7 immediately below the field insulating film 10 at the intersection portion 31.

Next, a semiconductor device 41 according to a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a schematic cross-sectional view of a semiconductor device 41 according to a second embodiment of the present invention.
The semiconductor device 41 according to the second embodiment is different from the semiconductor device 1 according to the first embodiment described above in that a conductor film 42 is formed on the first interlayer insulating film 21. That is, the conductor film for suppressing field inversion does not have to be formed in contact with the surface of field insulating film 10, and may be formed on the interlayer insulating film on field insulating film 10. The other configuration is the same as that of the semiconductor device 1 according to the first embodiment described above. In FIG. 5, the parts corresponding to the parts shown in FIG. 2 are given the same reference numerals, and the description thereof will be omitted.

  In this embodiment, the conductor film 42 is formed on the first interlayer insulating film 21 in the same layer as the drain contact 23 and the source contact 24. At this time, the conductor film 42 is opposed to the element isolation well 7 via the first interlayer insulating film 21 and the field insulating film 10. As the layout of the conductive film 42, the same layout as each layout described in FIGS. 3A to 3C of the first embodiment described above can be applied.

  The conductor film 42 is formed of, for example, the same material and the same film thickness as the drain contact 23 and the source contact 24. As a material of the conductor film 42, aluminum, copper, tungsten etc. can be mentioned, for example, Moreover, the film thickness is 0.4 micrometer-2.0 micrometers, for example. The conductor film 42 is fixed at, for example, the same potential (for example, the ground potential) as that of the source wiring 29. In this case, the conductor film 42 may be formed to be continuous with the source wiring 29.

As described above, also by the semiconductor device 41 according to the second embodiment, the same effect as that of the semiconductor device 1 according to the first embodiment can be obtained.
In the semiconductor device 41, the conductor film 42 can be formed in the same step as the step of forming the low voltage contacts 23 and 24. That is, the low voltage contacts 23 and 24 and the conductor film 42 can be formed simply by changing the layout of the resist mask in the manufacturing process of the semiconductor device 41 (see the process of FIG. 4H). Therefore, since it is not necessary to add a new manufacturing process, the increase in the number of processes can be prevented.

Next, a semiconductor device 51 according to a third embodiment of the present invention will be described with reference to FIG.
FIG. 6 is a schematic plan view of a semiconductor device 51 according to a third embodiment of the present invention. The semiconductor device 51 according to the third embodiment differs from the semiconductor device 1 according to the first embodiment described above in that a high voltage wire 52 is formed instead of the high voltage wire 30. The other configuration is the same as that of the above-described semiconductor device 1. In FIG. 6, parts corresponding to the parts shown in FIG. 1 described above are given the same reference numerals, and descriptions thereof will be omitted.

The high voltage wiring 52 is formed along the element isolation well 7 at a position spaced a certain distance from the low voltage element region 2.
As described above, even with the configuration in which the element isolation well 7 and the high voltage wiring 52 do not intersect, the influence of the electric field from the high voltage wiring 52 can be reduced by the conductor film 11. In this embodiment, as in the first embodiment described above, the conductor film 11 is formed in a quadrangular ring shape in plan view, but the conductor film 11 is at least along the region where the high voltage wiring 52 is formed. It should just be formed.

  More specifically, as shown in FIG. 6, when high voltage interconnection 52 is formed at a predetermined distance from low voltage element region 2, element isolation well 7 adjacent to high voltage interconnection 52 has an electric field. Susceptible to Therefore, conductor film 11 may be formed to cover at least element isolation well 7 adjacent to high voltage interconnection 52. Thereby, the occurrence of the field inversion in the element isolation well 7 can be effectively suppressed.

Next, a semiconductor device 61 according to a fourth embodiment of the present invention will be described with reference to FIG.
FIG. 7 is a schematic plan view of a semiconductor device 61 according to a fourth embodiment of the present invention. The semiconductor device 61 according to the fourth embodiment differs from the semiconductor device 1 according to the first embodiment in that a high voltage wire 62 is formed instead of the high voltage wire 30. The other configuration is the same as that of the above-described semiconductor device 1. In FIG. 7, parts corresponding to the parts shown in FIG. 1 described above are given the same reference numerals, and descriptions thereof will be omitted.

The high voltage wiring 62 is formed to completely cover a part of the field insulating film 10 along the region where the field insulating film 10 is formed. That is, the high voltage wiring 62 is formed to cover the field insulating film 10 in accordance with the region in which the field insulating film 10 is formed (the region in which the element isolation well 7 is formed).
Also with such a configuration, the conductor film 11 can reduce the influence of the electric field from the high voltage wiring 62. In this embodiment, as in the first embodiment described above, the conductor film 11 is formed in a square ring in plan view, but in the conductor film 11, at least the high voltage wiring 62 and the element isolation well 7 are opposed to each other. It may be formed in the region to be Therefore, the conductor film 11 may be formed on the field insulating film 10 immediately below the region where the high voltage interconnection 62 is formed so as to face the high voltage interconnection 62.

Thereby, even if high voltage interconnection 62 is formed along the region where field insulating film 10 is formed so as to completely cover a part of field insulating film 10, the field in element isolation well 7 is obtained. The occurrence of inversion can be reliably suppressed.
Although the embodiments of the present invention have been described above, the present invention can be implemented in other forms.
For example, in the first embodiment described above, the conductor film 11 is formed on the central portion of the field insulating film 10. However, the conductor film 11 can suppress field inversion in the element isolation well 7. As long as it is formed to cover a part or all of the region where the element isolation well 7 is formed, it may be formed at a position shifted in the extending direction of the high voltage wiring 30.

  Further, in the first to fourth embodiments described above, the configuration in which the DMOS 35 is formed in the low voltage device region 2 as an example of the semiconductor device has been described, but the present invention is not limited to this. Therefore, in addition to the DMOS 35, there is formed a CMOS (Complementary MOS), a BJT (Bipolar Junction Transistor), an IGBT (Insulated Gate Bipolar Transistor), a JFET (Junction Field Effect Transistor), a nonvolatile memory having a control gate and a floating gate, etc. It may be

  Further, various circuit elements such as a capacitor and a resistor may be formed in the low voltage element region 2. Furthermore, by combination of these semiconductor elements and circuit elements, large scale integration (LSI), small scale integration (SSI), medium scale integration (MSI), very large scale integration (VLSI), ultra-very large scale (ULSI) Integrated circuit, etc. may be configured.

In the first to fourth embodiments described above, the p-type silicon substrate 4 is formed, but the n-type silicon substrate 4 whose conductivity type is reversed may be formed. In this case, the conductivity types of other impurity regions and the like are also reversed.
In addition, various design changes can be made within the scope of matters described in the claims.

Examples of features extracted from this specification and drawings are shown below.
[Item 1] A low voltage element region in which a low voltage element operating based on a low reference voltage is formed, and a high voltage forming a high voltage element operating based on a high reference voltage higher than the low reference voltage A semiconductor substrate having a semiconductor layer of a first conductivity type including an element region in a surface layer portion thereof and the low voltage element region are partitioned, and the low voltage element region is electrically separated from the high voltage element region An element isolation well of the second conductivity type formed in the surface layer of the semiconductor substrate, a field insulating film covering the surface of the element isolation well, an interlayer insulating film formed on the semiconductor substrate, and a plan view A high voltage interconnection formed on the interlayer insulating film so as to cross the low voltage element region, and electrically connected to the high voltage element in the high voltage element region; High Wherein formed on the field insulating film so as to cross the-pressure line and the opposing area, and includes a conductive film, wherein fixed to the low reference voltage, the semiconductor device.

  According to this configuration, the influence of the electric field from the high voltage wiring can be reduced by the conductor film fixed to the low reference voltage. Specifically, since the conductor film fixed to the low reference voltage is disposed at a position closer to the high voltage wiring than the element isolation well, the electric field from the high voltage wiring is effectively terminated by the conductor film. Can. As a result, it is possible to suppress the occurrence of field inversion due to the ions in the element isolation well being attracted to the region immediately below the field insulating film by the electric field from the high voltage wiring. As a result, it is possible to suppress the occurrence of a leak current by forming a leak path crossing the element isolation well, and it is possible to provide a semiconductor device capable of realizing more stable element isolation.

Therefore, the high voltage wiring can be brought close to or intersected with the field insulating film, so that the design rule of the high voltage wiring can be relaxed and the degree of freedom in design can be enhanced. As a result, the semiconductor chip area can be effectively utilized, and the semiconductor chip can be highly shrunk.
In the case of the high voltage wiring connected to the high voltage element region, the magnitude of the electric field by the high voltage wiring is relatively larger than that of the wiring connected to the low voltage element region. Is likely to occur. Therefore, according to this configuration, the high voltage wiring passing near the field insulating film on the element isolation well or crossing the field insulating film is connected to the high voltage element region, and the field inversion is relatively performed. The electric field due to the high voltage wiring can be effectively terminated by the conductor film even under the conditions that are likely to occur.

  When the high voltage line intersects the element isolation well, the distance between the high voltage line and the element isolation well is shorter than when the element isolation well does not intersect, so the element isolation well is affected by the electric field due to the high voltage line. And are prone to field inversion. Therefore, according to this configuration, the electric field by the high voltage wiring is effectively terminated by the conductor film even under the condition that the high voltage wiring crosses the element isolation well and the field inversion is relatively likely to occur. Can. Furthermore, the semiconductor chip area can be more effectively utilized by crossing the high voltage wiring with the element isolation well.

  [Item 2] The semiconductor device further includes a low voltage interconnection formed in the interlayer insulating film so as to cross the field insulating film in plan view and electrically connected to the low voltage element in the low voltage element region. The semiconductor device according to claim 1, wherein the conductor film is formed on the field insulating film so as to cross a region facing the low voltage wiring in the field insulating film.

  [Item 3] The element isolation well includes a crossing portion that intersects the high voltage wiring in plan view, and the length of the conductor film with respect to the direction in which the element isolation well intersects the high voltage wiring at the crossing portion A semiconductor device given in paragraph 1 or 2 whose length is more than the length of the crossing part. According to this configuration, the conductor film and the high voltage wiring reliably cross each other even when the high voltage wiring is displaced (alignment deviation) along the extending direction of the element isolation well when the high voltage wiring is formed. Can. Therefore, the occurrence of field inversion in the element isolation well immediately below the field insulating film at the intersection can be effectively suppressed.

[Item 4] The element isolation well includes an intersection portion that intersects the high voltage interconnection in plan view, and the length of the conductor film with respect to the direction in which the high voltage interconnection intersects the element isolation well at the intersection The semiconductor device according to any one of Items 1 to 3, wherein Y is shorter than the length of the intersection.
[Item 5] The element isolation well includes an intersection portion intersecting the high voltage interconnection in plan view, and the length of the conductor film in the direction in which the high voltage interconnection intersects the element isolation well at the intersection Item 4. The semiconductor device according to any one of Items 1 to 3, wherein is greater than or equal to the length of the intersection. According to this configuration, the element isolation well can be completely covered by the conductor film via the field insulating film in the extending direction of the high voltage wiring. Thereby, the occurrence of field inversion in the element isolation well immediately below the field insulating film can be effectively suppressed.

  [Item 6] The element isolation well is formed in a band shape along the periphery of the low voltage element region, and the field insulating film is formed in a band shape along the periphery of the low voltage element region. The semiconductor device according to any one of Items 1 to 5, wherein a film is formed in a band shape along the periphery of the low voltage element region. According to this configuration, the conductor film is necessarily disposed immediately above the element isolation well in the region on the field insulating film. Therefore, the electric field due to the high voltage wiring can be favorably terminated by the conductor film regardless of the positional relationship of the high voltage wiring with respect to the element isolation well in the cross relation, the proximity relation and the like. As a result, the occurrence of field inversion in the element isolation well can be suppressed regardless of the wiring rule of the high voltage wiring, so the degree of freedom of the design rule can be further enhanced.

[Item 7] The element isolation well is formed in an annular shape surrounding the low voltage element region, the field insulating film is formed in an annular shape surrounding the low voltage element region, and the conductor film is 7. The semiconductor device according to any one of Items 1 to 6, which is formed in an annular shape surrounding the low voltage element region.
[Item 8] A MOS transistor is formed as the low voltage element in the low voltage element region, and the conductor film has the same potential as the source of the MOS transistor. The semiconductor device according to claim 1.

  [Item 9] The semiconductor device according to Item 8, wherein the conductive film is formed of the same material as the gate in the same layer as the gate of the MOS transistor. According to this configuration, the conductor film can be formed in the same step as the step of forming the gate of the MOS transistor. That is, the gate of the MOS transistor and the conductor film can be simultaneously formed only by changing the layout of the resist mask in the manufacturing process of the semiconductor device. Therefore, since it is not necessary to add a new manufacturing process, the increase in the number of processes can be prevented.

[Item 10] The semiconductor device according to item 9, wherein the gate and the conductor film are made of polysilicon.
[Item 11] The semiconductor device according to any one of Items 1 to 10, wherein the interlayer insulating film includes a wiring layer, and the conductor film is formed of a wiring film disposed in the wiring layer.

REFERENCE SIGNS LIST 1 semiconductor device 2 low voltage element region 3 high voltage element region 4 silicon substrate 5 n ⁻ type epitaxial layer 7 element isolation well 10 field insulating film 11 conductor film 12 field insulating film 21 first interlayer insulating film 25 second interlayer insulating film 27 Third interlayer insulating film 30 High voltage wiring 31 Crossing 35 DMOS
36 fourth interlayer insulating film 41 semiconductor device 42 conductor film 45 epitaxial substrate 51 semiconductor device 52 high voltage wiring 61 semiconductor device 62 high voltage wiring

Claims (15)

A semiconductor layer including an element region having a semiconductor element;
An element isolation well formed in a surface layer portion of the semiconductor layer so as to partition the element region;
A field insulating film formed on the semiconductor layer so as to cover the element isolation well;
An interlayer insulating film formed on the semiconductor layer;
A wire formed on the interlayer insulating film so as to cross the element region in plan view;
It said field said to cross the wiring area opposite to the insulating film formed over the field insulating film, seen including a conductor film having a width equal to or smaller than that of the isolation well,
The device region includes a low voltage device region in which a low voltage device operating based on a low reference voltage is formed, and a high voltage device operating based on a high reference voltage higher than the low reference voltage. Including a voltage element region,
The device isolation well divides the low voltage element region and the high voltage element region so as to electrically isolate the low voltage element region and the high voltage element region from each other . The semiconductor device according to claim 1 , wherein the conductive film is fixed to the low reference voltage. The wire includes a low voltage wire electrically connected to the low voltage element,
The conductor film, the in the field insulating film crosses the low voltage wiring area opposite to the semiconductor device according to claim 1 or 2. The wire includes a high voltage wire electrically connected to the high voltage element,
Said conductor film, said field and across the high voltage wiring area opposite to the insulating film, a semiconductor device according to any one of claims 1 to 3. In the low voltage element region, a MOS transistor as the low voltage element is formed;
The semiconductor device according to any one of claims 1 to 4 , wherein the conductive film is at the same potential as the source of the MOS transistor. The semiconductor device according to claim 5 , wherein the conductive film is formed of the same material as the gate of the MOS transistor. The semiconductor device according to claim 6 , wherein the gate is made of polysilicon. The wiring includes a crossing portion crossing the element isolation well in a plan view,
The semiconductor device according to any one of claims 1 to 7 , wherein a length of the conductor film is equal to or less than a length of the intersection in a direction in which the wiring intersects the element isolation well at the intersection. The wiring includes a crossing portion crossing the element isolation well in a plan view,
The semiconductor device according to any one of claims 1 to 7 , wherein a length of the conductor film is equal to or greater than a length of the intersection in a direction in which the element isolation well intersects the wiring at the intersection. The element isolation well is formed in a band shape along the periphery of the element region,
The field insulating film is formed in a band shape along the periphery of the element region,
The semiconductor device according to any one of claims 1 to 9 , wherein the conductive film is formed in a band shape along the periphery of the element region. The element isolation well is formed in a ring shape surrounding the element region;
The field insulating film is formed in a ring shape surrounding the element region,
The semiconductor device according to any one of claims 1 to 10 , wherein the conductive film is formed in an annular shape surrounding the element region. The interlayer insulating film includes a wiring layer;
The semiconductor device according to any one of claims 1 to 11, wherein the conductor film is formed of a wiring film disposed in the wiring layer. A semiconductor layer including a low voltage element region having a low voltage element operating at a low reference voltage, and a high voltage element region having a high voltage element operating at a high reference voltage higher than the low reference voltage;
An isolation well formed in a surface layer portion of the semiconductor layer so as to electrically isolate the low voltage device region and the high voltage device region;
A field insulating film formed on the semiconductor layer so as to cover the element isolation well;
An interlayer insulating film formed on the semiconductor layer;
A wire formed on the interlayer insulating film and electrically connected to the high voltage element region;
And a conductor film formed between the interlayer insulating film and the field insulating film and facing the element isolation well with the field insulating film interposed therebetween,
The low voltage device includes a MOS transistor having a gate electrode,
The semiconductor device, wherein the conductive film is formed of the same kind of material as the gate electrode of the MOS transistor. The semiconductor device further includes a second field insulating film formed on the semiconductor layer in the low voltage element region,
The conductor film is formed on the field insulating film in a region outside the low voltage element region,
Wherein the gate electrode, the are formed on the second field insulating film in the low voltage device region, the semiconductor device according to claim 1 3. The conductive film is in contact with the field insulating film, a semiconductor device according to claim 1 3 or 1 4.

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