JP2010219504A - Semiconductor device - Google Patents

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JP2010219504A
JP2010219504A JP2010016340A JP2010016340A JP2010219504A JP 2010219504 A JP2010219504 A JP 2010219504A JP 2010016340 A JP2010016340 A JP 2010016340A JP 2010016340 A JP2010016340 A JP 2010016340A JP 2010219504 A JP2010219504 A JP 2010219504A
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metal wiring
source region
semiconductor device
supply line
type mos
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JP5603089B2 (en
JP2010219504A5 (en
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Sukehiro Yamamoto
祐広 山本
Akira Koyama
威 小山
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Seiko Instruments Inc
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Seiko Instruments Inc
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Priority to TW99104435A priority patent/TWI472014B/en
Priority to US12/709,762 priority patent/US8373231B2/en
Priority to KR1020100015648A priority patent/KR101629968B1/en
Priority to EP10154307A priority patent/EP2221875B1/en
Priority to CN201010131740.0A priority patent/CN101814501B/en
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
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    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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    • H01—ELECTRIC ELEMENTS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
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    • H01L2924/1304—Transistor
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device including N-type MOS transistors for ESD protection in which the overall transistors can be uniformly operated during protection against ESD even if a wire connected to the transistor is introduced perpendicularly to the channel width direction of the transistor. <P>SOLUTION: In the N-type MOS transistor for ESD protection, drain regions and source regions are alternatively arranged with gate electrodes interposed between the drain regions and the source regions. A plurality of the transistors are integrated. At least one of a first metal wire connected to the drain region and a first metal wire connected to the source region is connected to a second metal wire, and the number of via holes with which have certain sizes and are arranged for electrically connecting the first metal wires and the second metal has a ratio of 1 to 3 according to the distance of the wire extended from the outside to the N-type MOS transistor for ESD protection. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、マルチフィンガータイプ（櫛形）のＭＯＳ型トランジスタを有する半導体装置に関する。特に、Ｎ型のＭＯＳトランジスタをＥＳＤ保護素子として使用した半導体装置に関する。   The present invention relates to a semiconductor device having a multi-finger type (comb-shaped) MOS transistor. In particular, the present invention relates to a semiconductor device using an N-type MOS transistor as an ESD protection element.

ＭＯＳ型トランジスタを有する半導体装置では、外部接続用のＰＡＤからの静電気による内部回路の破壊を防止するためのＥＳＤ保護素子として、Ｎ型ＭＯＳトランジスタのゲート電位をグランド（Ｖｓｓ）に固定してオフ状態として設置する、いわゆるオフトランジスタが知られている。   In a semiconductor device having a MOS transistor, the gate potential of the N-type MOS transistor is fixed to the ground (Vss) as an ESD protection element for preventing destruction of the internal circuit due to static electricity from the external connection PAD. A so-called off-transistor installed as is known.

オフトランジスタは、他ロジック回路などの内部回路を構成するＭＯＳ型トランジスタと異なり、瞬時に多量の静電気による電流を流しきる必要があるため、数百ミクロン程度の大きな幅（Ｗ幅）を有するトランジスタで形成されることが多い。   An off-transistor is a transistor having a large width (W width) of about several hundred microns because it is necessary to instantaneously flow a large amount of static electricity, unlike a MOS transistor that constitutes an internal circuit such as another logic circuit. Often formed.

このため、オフトランジスタは占有面積が少なくなるようにために、複数のドレイン領域、ソース領域、ゲート電極を櫛形に組み合わせたマルチフィンガータイプの形態を取ることが多い。   For this reason, the off-transistor often takes a multi-finger type in which a plurality of drain regions, source regions, and gate electrodes are combined in a comb shape so that the occupied area is reduced.

しかしながら、複数のトランジスタを組み合わせた構造をとることにより、ＥＳＤ保護用のＮ型ＭＯＳトランジスタ全体で均一な動作をさせることは難しくなる。例えば外部接続端子からの距離が近い部分、または配線抵抗と配線間の抵抗の合計の小さい部分に電流集中が起こり、本来のＥＳＤ保護機能を十分に発揮できずに一極が破壊してしまうことがある。   However, by adopting a structure in which a plurality of transistors are combined, it becomes difficult to perform uniform operation over the entire N-type MOS transistor for ESD protection. For example, current concentration occurs in a portion that is close to the external connection terminal, or in a portion where the total of the resistance between the wiring resistance and the wiring is small, and the original ESD protection function cannot be fully exhibited, and one pole is destroyed. There is.

この改善策として、外部接続端子からの距離に応じて、特にドレイン領域上のコンタクトホールとゲート電極との距離を、外部接続端子からの距離が遠いほど小さくして、トランジスタの動作を速める工夫をした方法も提案されている（例えば、特許文献１の第２図参照）。また基板コンタクトからの距離に応じて、特にドレイン領域上のサリサイド化を防ぐサリサイドブロックの距離を、基板コンタクトからの距離が遠いほど長くして、トランジスタの動作を均一にする工夫をした提案もされている（例えば、特許文献２参照）。   As a measure to improve this, the distance between the contact hole on the drain region and the gate electrode is made smaller as the distance from the external connection terminal becomes longer according to the distance from the external connection terminal. This method has also been proposed (see, for example, FIG. 2 of Patent Document 1). There is also a proposal that makes the transistor operation uniform by increasing the distance of the salicide block, which prevents salicide formation on the drain region, as the distance from the substrate contact increases, depending on the distance from the substrate contact. (For example, refer to Patent Document 2).

特開平７−４５８２９号公報JP 7-45829 A 特開２００７−１１６０４９号公報JP 2007-116049 A

しかしながら、例えばオフトランジスタのＥＳＤに対する保護動作を均一にしようとＷ幅を小さくすると、十分な保護機能を果たせなくなってしまう。また上記特許文献１は、ドレイン領域における、コンタクトからゲート電極までの距離を調整することにより、局所的にトランジスタ動作速度を調整するものであるが、ドレイン領域の幅の縮小化に伴って所望のコンタクト位置を確保できないこと、近年の高融点金属を含む配線による配線の低抵抗化で、サージの伝播スピードがさらに速くなり、コンタクトとゲート電極までの距離だけでは調整しきれない場合が生じること、あるいは、トランジスタに導入される配線がトランジスタの幅方向と垂直の方向から導入される場合に適応が困難であることなどの課題を有していた。また、上記特許文献２は、ドレイン領域における、サリサイドブロックの長さを調節することにより、局所的にトランジスタの動作速度を調整するものであるが、製造プロセスバラツキにより所望の長さを確保できないこと、近年の高融点金属を含む配線による配線の低抵抗化で、サージの伝播スピードがさらに速くなり、逆に一部のサリサイド領域にサージが集中してしまうこと、あるいは、サリサイドブロックの長さ調整により、Ｎ型ＭＯＳオフトランジスタの占有面積が増加してしまうなどの課題を有していた。   However, for example, if the W width is reduced in order to make the protection operation against ESD of the off transistor uniform, a sufficient protection function cannot be performed. Further, the above-mentioned Patent Document 1 adjusts the transistor operation speed locally by adjusting the distance from the contact to the gate electrode in the drain region. The inability to secure the contact position, and the recent low resistance of the wiring with high melting point metal wiring, the surge propagation speed will be even faster, and the distance between the contact and the gate electrode may not be adjusted. Alternatively, there is a problem that adaptation is difficult when the wiring introduced into the transistor is introduced from a direction perpendicular to the width direction of the transistor. Moreover, although the said patent document 2 adjusts the operation speed of a transistor locally by adjusting the length of the salicide block in a drain region, it cannot secure a desired length by manufacturing process variation. In recent years, the resistance of wiring with low-melting-point metal wiring has further reduced the propagation speed of surges, and conversely, surges are concentrated in some salicide regions, or the length of salicide blocks can be adjusted. As a result, there is a problem that the area occupied by the N-type MOS off transistor increases.

上記課題を解決するために、本発明は半導体装置を以下のように構成する。   In order to solve the above problems, the present invention configures a semiconductor device as follows.

複数のドレイン領域と複数のソース領域が交互に配置され、前記ドレイン領域と前記ソース領域の間にゲート電極が配置された、複数のトランジスタが一体化した構造を有するＥＳＤ保護用のＮ型ＭＯＳトランジスタにおいて、ドレイン領域は外部接続端子と電気的に接続され、ソース領域はグランド電位供給ラインと電気的に接続されており、ドレイン領域に接続される第１のメタル配線とソース領域に接続される第１のメタル配線の片方あるいは両方が、第１のメタル配線以外の複数層のメタル配線と接続されており、第１のメタル配線と第１のメタル配線以外の複数層のメタル配線とを電気的に接続するためのビアホールの数を、ＥＳＤ保護用のＮ型ＭＯＳトランジスタへ外部から配線される配線の距離に応じて、配置数を変えて形成した。   N-type MOS transistor for ESD protection having a structure in which a plurality of transistors are integrated, in which a plurality of drain regions and a plurality of source regions are alternately arranged, and a gate electrode is arranged between the drain region and the source region The drain region is electrically connected to the external connection terminal, the source region is electrically connected to the ground potential supply line, and the first metal wiring connected to the drain region is connected to the source region. One or both of the metal wirings of 1 are connected to a plurality of layers of metal wiring other than the first metal wiring, and the first metal wiring and the plurality of layers of metal wiring other than the first metal wiring are electrically connected. The number of via holes for connecting to the N-type MOS transistor is changed by changing the number of arrangement according to the distance of the wiring routed from the outside to the N-type MOS transistor for ESD protection It was.

また、第１のメタル配線以外の複数層のメタル配線はＥＳＤ保護用のＮ型ＭＯＳトランジスタのチャネル幅方向と垂直な方向から配線されており、第１のメタル配線はＥＳＤ保護用のＮ型ＭＯＳトランジスタのチャネル幅方向と水平な方向に配置されており、第１のメタル配線以外の複数層のメタル配線と第１のメタル配線とは、ドレイン領域の上あるいは、ソース領域の上の領域にてビアホールにより接続されるようにした。   In addition, a plurality of layers of metal wiring other than the first metal wiring are wired from a direction perpendicular to the channel width direction of the ESD protection N-type MOS transistor, and the first metal wiring is an N-type MOS for ESD protection. The transistors are arranged in a direction horizontal to the channel width direction of the transistor, and the plurality of layers of metal wiring other than the first metal wiring and the first metal wiring are in a region above the drain region or the source region. Connected via holes.

また、ビアホールはドレイン領域あるいは、ソース領域の上の領域において、ＥＳＤ保護用のＮ型ＭＯＳトランジスタのチャネル幅方向と水平な方向に広く分布するように配置するようにした。   Also, the via holes are arranged so as to be widely distributed in the direction horizontal to the channel width direction of the N-type MOS transistor for ESD protection in the drain region or the region above the source region.

あるいは、ビアホールはドレイン領域あるいは、ソース領域の一部の領域の上に固まるように配置されるようにした。   Alternatively, the via hole is arranged to be solidified on the drain region or a part of the source region.

また、第１のメタル配線と第１のメタル配線以外の複数層のメタル配線とを電気的に接続するためのビアホールの数を、ＥＳＤ保護用のＮ型ＭＯＳトランジスタへ外部から配線される配線の距離に応じて、配置数の比を１〜３まで変化させて形成した。   In addition, the number of via holes for electrically connecting the first metal wiring and a plurality of layers of metal wiring other than the first metal wiring is set to the number of wirings to be wired from the outside to the N-type MOS transistor for ESD protection. It was formed by changing the ratio of the number of arrangements from 1 to 3 according to the distance.

以上説明したように、本発明によれば、これらの手段によって、高融点金属を含む高速配線多層配線を使用してトランジスタに導入される配線がトランジスタのチャネル幅方向と垂直の方向から導入される場合においても、ＥＳＤ保護用のＮ型ＭＯＳトランジスタのマルチフィンガー全体で均一に動作することが可能となる。   As described above, according to the present invention, by these means, the wiring introduced into the transistor using the high-speed wiring multilayer wiring containing the refractory metal is introduced from the direction perpendicular to the channel width direction of the transistor. Even in this case, the entire multi-finger of the N-type MOS transistor for ESD protection can be operated uniformly.

これにより、十分なＥＳＤ保護機能を持たせたＥＳＤ保護用のＮ型ＭＯＳトランジスタを有する半導体装置を得ることができる。   As a result, a semiconductor device having an N-type MOS transistor for ESD protection having a sufficient ESD protection function can be obtained.

本発明による半導体装置の、ＥＳＤ保護用のＮ型ＭＯＳトランジスタの第１の実施例を示す模式的平面図である。1 is a schematic plan view showing a first embodiment of an N-type MOS transistor for ESD protection in a semiconductor device according to the present invention. 本発明による半導体装置の、ＥＳＤ保護用のＮ型ＭＯＳトランジスタの第２の実施例を示す模式的平面図である。FIG. 6 is a schematic plan view showing a second embodiment of an N-type MOS transistor for ESD protection of a semiconductor device according to the present invention. 本発明による半導体装置の、ＥＳＤ保護用のＮ型ＭＯＳトランジスタの第３の実施例を示す模式的平面図である。FIG. 6 is a schematic plan view showing a third embodiment of an N-type MOS transistor for ESD protection of a semiconductor device according to the present invention. 本発明による半導体装置の、ＥＳＤ保護用のＮ型ＭＯＳトランジスタの第４の実施例を示す模式的平面図である。FIG. 6 is a schematic plan view showing a fourth embodiment of an N-type MOS transistor for ESD protection of a semiconductor device according to the present invention. 本発明による半導体装置の、最適なビアホール配置個数に関する実験データを示す図である。（ａ）実験に用いたＥＳＤ保護用のＮ型ＭＯＳトランジスタの模式的平面図である。（ｂ）はＥＳＤ試験（ＨＭＢモード）にて破壊までパルスを印加した後の破壊箇所の発生比率を示す図である。It is a figure which shows the experimental data regarding the optimal number of via-hole arrangement | positioning of the semiconductor device by this invention. (A) It is a typical top view of the N type MOS transistor for ESD protection used for experiment. (B) is a figure which shows the generation | occurrence | production ratio of the destruction location after applying a pulse to destruction by an ESD test (HMB mode). 本発明による半導体装置の、ＥＳＤ保護用のＮ型ＭＯＳトランジスタの第５の実施例を示す模式的平面図である。FIG. 9 is a schematic plan view showing a fifth embodiment of an N-type MOS transistor for ESD protection in a semiconductor device according to the present invention. 本発明による半導体装置の、ＥＳＤ保護用のＮ型ＭＯＳトランジスタの第６の実施例を示す模式的平面図である。It is a typical top view which shows the 6th Example of the N-type MOS transistor for ESD protection of the semiconductor device by this invention.

本発明を実施するための形態について図面を参照して説明する。   DESCRIPTION OF EMBODIMENTS Embodiments for carrying out the present invention will be described with reference to the drawings.

図１は、本発明による半導体装置の、ＥＳＤ保護用のＮ型ＭＯＳトランジスタの第１の実施例を示す模式的平面図である。   FIG. 1 is a schematic plan view showing a first embodiment of an N-type MOS transistor for ESD protection of a semiconductor device according to the present invention.

Ｎ型の高濃度不純物領域からなる第１のソース領域１０１と第１のドレイン領域３０１が形成されており、第１のソース領域１０１と第１のドレイン領域３０１の間には、図示しないがシリコン酸化膜などからなるゲート絶縁膜が設けられ、その上面にポリシリコンなどからなるゲート電極２０１が形成されている。順次折り返したパターンを繰り返し配置して、第１のドレイン領域３０１からゲート電極２０１を介して第２のソース領域１０２、またゲート電極２０１を介して第２のドレイン領域３０２、さらにゲート電極２０１を介して第３のソース領域１０３、またゲート電極２０１を介して第３のドレイン領域３０３、さらにゲート電極２０１を介して第４のソース領域１０４が形成されている。第１の実施例においては、ソース領域を４つ、ドレイン領域を３つ、ゲート電極を６つ配置した櫛型形の例を示した。ＭＯＳトランジスタとしては６つのものが組み合わさった形である。   A first source region 101 and a first drain region 301 made of an N-type high-concentration impurity region are formed. Between the first source region 101 and the first drain region 301, although not shown, silicon A gate insulating film made of an oxide film or the like is provided, and a gate electrode 201 made of polysilicon or the like is formed on the upper surface thereof. A pattern that is sequentially folded is repeatedly arranged, and the first drain region 301 is passed through the gate electrode 201 to the second source region 102, the gate electrode 201 is passed through the second drain region 302, and the gate electrode 201 is passed through. The third source region 103, the third drain region 303 through the gate electrode 201, and the fourth source region 104 through the gate electrode 201 are formed. In the first embodiment, an example of a comb shape in which four source regions, three drain regions, and six gate electrodes are arranged is shown. Six MOS transistors are combined.

ここで、第１のソース領域１０１、第２のソース領域１０２、第３のソース領域１０３、および第４のソース領域１０４には、図ではトランジスタを挟んで上下に２本配置されたグランド電位供給ライン７０１に接続された、翼の形をした第２のメタル配線７１１によりグランド電位が供給される。グランド電位供給ライン７０１は高融点金属を含むメタル材料などを原料とする太く低抵抗な配線により形成される。第２のメタル配線７１１も高融点金属を含む材料などで形成される。第２のメタル配線７１１は、ＥＳＤ保護用のＮ型ＭＯＳトランジスタのチャネル幅方向と垂直な向きでグランド電位供給ライン７０１から配線されており、ビアホール６０１を介して、高融点金属を含む材料などからなる第１のメタル配線９０１と接続され、さらに簡単のため図示は省略するが、第１のソース領域１０１、第２のソース領域１０２、第３のソース領域１０３、および第４のソース領域１０４へコンタクトホールを介して接続される。   Here, in the first source region 101, the second source region 102, the third source region 103, and the fourth source region 104, two ground potential supplies are arranged above and below the transistor in the figure. A ground potential is supplied by a second metal wiring 711 having a wing shape connected to the line 701. The ground potential supply line 701 is formed by a thick and low resistance wiring made of a metal material containing a refractory metal or the like as a raw material. The second metal wiring 711 is also formed of a material containing a refractory metal or the like. Second metal wiring 711 is wired from ground potential supply line 701 in a direction perpendicular to the channel width direction of the N-type MOS transistor for ESD protection, and is made of a material containing a refractory metal via via hole 601. To the first source region 101, the second source region 102, the third source region 103, and the fourth source region 104. Connected via contact hole.

ここで、ビアホール６０１の数は、グランド電位供給ライン７０１から最も離れた位置に配置された第２のソース領域１０２、あるいは第３のソース領域１０３上で、最も多く設置され、グランド電位供給ライン７０１に最も近い位置に配置された第１のソース領域１０１、あるいは第４のソース領域１０４上で最も少なくなるように設置される。   Here, the number of via holes 601 is the largest on the second source region 102 or the third source region 103 disposed farthest from the ground potential supply line 701, and the ground potential supply line 701. The first source region 101 or the fourth source region 104 arranged at a position closest to the first source region 104 is disposed so as to be the smallest.

ビアホール数を適正な値に設定することにより、第１のソース領域１０１、第２のソース領域１０２、第３のソース領域１０３、および第４のソース領域１０４において、グランド電位供給ライン７０１に接続された第２のメタル配線７１１の配線抵抗と、ビアホール６０１による接続抵抗とを組み合わせた抵抗値の合計を略等しくすることができ、グランド電位供給ライン７０１に近い部分に偏ることなく、ＥＳＤ保護用のＮ型ＭＯＳトランジスタ全体で均一に動作させることができる。   By setting the number of via holes to an appropriate value, the first source region 101, the second source region 102, the third source region 103, and the fourth source region 104 are connected to the ground potential supply line 701. In addition, the sum of the resistance values obtained by combining the wiring resistance of the second metal wiring 711 and the connection resistance by the via hole 601 can be made substantially equal, and the ESD protection without being biased toward the portion near the ground potential supply line 701. The entire N-type MOS transistor can be operated uniformly.

また、第２のメタル配線７１１は、グランド電位供給ライン７０１から遠ざかるほど、太くなる例を示したが、このような形態をとることで、第２のメタル配線７１１の配線抵抗の影響を緩和することができる。   In addition, the example in which the second metal wiring 711 becomes thicker as the distance from the ground potential supply line 701 is increased is shown. However, by taking such a form, the influence of the wiring resistance of the second metal wiring 711 is reduced. be able to.

一方、外部接続端子８０１には、高融点金属を含む材料などからなる第１のメタル配線８１１が接続され、第１のドレイン領域３０１、第２のドレイン領域３０２、および第３のドレイン領域３０３に接続される。そして図示は省略するが、コンタクトホールを介して第１のドレイン領域３０１、第２のドレイン領域３０２、および第３のドレイン領域３０３と第１のメタル配線８１１が接続されている。   On the other hand, a first metal wiring 811 made of a material containing a refractory metal or the like is connected to the external connection terminal 801, and the first drain region 301, the second drain region 302, and the third drain region 303 are connected to the external connection terminal 801. Connected. Although not shown, the first drain region 301, the second drain region 302, and the third drain region 303 are connected to the first metal wiring 811 through contact holes.

図１に示した第１の実施例に置いては、ＥＳＤ保護用のＮ型ＭＯＳトランジスタのソース領域の電位を供給、固定するための配線を第２のメタル配線として、ドレイン領域に接続する配線を第１のメタル配線とした例を示したが、反対にソース領域の電位を供給、固定するための配線を第１のメタル配線として、ドレイン領域に接続する配線を第２のメタル配線としたり、その他の組み合わせにしたりすることは自由に行われてよい。その際に、第２のメタル配線を用いた側に配置されるビアホールの個数を、図１に示した第１の実施例の説明の主旨に沿って、ＥＳＤ保護用のＮ型ＭＯＳトランジスタにおける複数のドレインあるいは、ソース領域において導入される配線抵抗と配線間の抵抗の合計が、略等しくなるように分配配置することが肝要である。   In the first embodiment shown in FIG. 1, the wiring for supplying and fixing the potential of the source region of the N-type MOS transistor for ESD protection is used as the second metal wiring and is connected to the drain region. The first metal wiring is shown as an example. Conversely, the wiring for supplying and fixing the potential of the source region is used as the first metal wiring, and the wiring connected to the drain region is used as the second metal wiring. Other combinations may be freely performed. At that time, the number of via holes arranged on the side using the second metal wiring is set in accordance with the gist of the explanation of the first embodiment shown in FIG. 1 in the N-type MOS transistor for ESD protection. It is important to distribute and arrange the wiring resistance introduced in the drain or source region and the total resistance between the wirings to be substantially equal.

また、図１に示した第１の実施例に置いては、２層のメタル配線を用いた例を示したが、３層以上の複数層の配線を用いても構わない。その際には２層の例で説明した事項と同様の点に留意することが必要である。   Further, in the first embodiment shown in FIG. 1, an example using two layers of metal wiring is shown, but a plurality of layers of three or more layers may be used. In that case, it is necessary to pay attention to the same points as described in the two-layer example.

図２は、本発明による半導体装置の、ＥＳＤ保護用のＮ型ＭＯＳトランジスタの第２の実施例を示す模式的平面図である。図１と対応する部分には同じ番号が付してある。図１に示した第１の実施例と異なる点は、ビアホール６０１の配置である。図１に示した第１の実施例では、第１のソース領域１０１、第２のソース領域１０２、第３のソース領域１０３、および第４のソース領域１０４の上に配置されたビアホール６０１は、ＥＳＤ保護用のＮ型ＭＯＳトランジスタのチャネル幅方向と水平な方向に広く分布する形で配置した。一方、図２に示した第２の実施例においては、ビアホール６０１は、第１のソース領域１０１、第２のソース領域１０２、第３のソース領域１０３、および第４のソース領域１０４の一部の領域の上に集合して配置されるようにした。   FIG. 2 is a schematic plan view showing a second embodiment of the N-type MOS transistor for ESD protection of the semiconductor device according to the present invention. Parts corresponding to those in FIG. 1 are given the same numbers. The difference from the first embodiment shown in FIG. 1 is the arrangement of via holes 601. In the first embodiment shown in FIG. 1, the via hole 601 disposed on the first source region 101, the second source region 102, the third source region 103, and the fourth source region 104 is The N-type MOS transistors for ESD protection are arranged so as to be widely distributed in the horizontal direction and the channel width direction. On the other hand, in the second embodiment shown in FIG. 2, the via hole 601 is part of the first source region 101, the second source region 102, the third source region 103, and the fourth source region 104. It was arranged to be gathered over the area.

これは、第１のドレイン領域３０１、第２のドレイン領域３０２、および第３のドレイン領域３０３と第１のメタル配線８１１の接続に注意した結果である。即ち、外部接続端子８０１から配線されたメタル配線８１１は、第１のドレイン領域３０１、第２のドレイン領域３０２、および第３のドレイン領域３０３の一端から第１のドレイン領域３０１、第２のドレイン領域３０２、および第３のドレイン領域３０３に導入されるため、チャネル幅方向において外部接続端子８０１に近い側と遠い側とでメタル配線８１１の配線抵抗値が異なることになり、第１のドレイン領域３０１、第２のドレイン領域３０２、および第３のドレイン領域３０３のそれぞれの外部接続端子８０１に近い側の方が、比較的動作し易い状態になる。   This is a result of paying attention to the connection of the first drain region 301, the second drain region 302, the third drain region 303, and the first metal wiring 811. That is, the metal wiring 811 wired from the external connection terminal 801 is connected to the first drain region 301, the second drain from one end of the first drain region 301, the second drain region 302, and the third drain region 303. Since it is introduced into the region 302 and the third drain region 303, the wiring resistance value of the metal wiring 811 differs between the side closer to the external connection terminal 801 and the side far from the external connection terminal 801 in the channel width direction. The side closer to the external connection terminal 801 of each of the 301, the second drain region 302, and the third drain region 303 becomes relatively easy to operate.

この状況に鑑みて、第１のドレイン領域３０１、第２のドレイン領域３０２、および第３のドレイン領域３０３と対になる第１のソース領域１０１、第２のソース領域１０２、第３のソース領域１０３、および第４のソース領域１０４において外部接続端子８０１から遠い領域に集中するようにビアホール６０１を設置することで、ＥＳＤ保護用のＮ型ＭＯＳトランジスタの動作に際してチャネル幅方向における外部接続端子８０１との距離依存性が生じることを緩和することを目的としている。   In view of this situation, the first source region 101, the second source region 102, and the third source region that are paired with the first drain region 301, the second drain region 302, and the third drain region 303. 103 and the fourth source region 104 are provided with via holes 601 so as to be concentrated in a region far from the external connection terminal 801, so that the external connection terminal 801 in the channel width direction and the operation of the N-type MOS transistor for ESD protection The purpose is to alleviate the occurrence of distance dependency.

図２に示した第２の実施例に置いては、ＥＳＤ保護用のＮ型ＭＯＳトランジスタのソース領域の電位を供給、固定するための配線を第２のメタル配線として、ドレイン領域に接続する配線を第１のメタル配線とした例を示したが、図１の例と同様に、ソース領域の電位を供給、固定するための配線を第１のメタル配線として、ドレイン領域に接続する配線を第２のメタル配線としたり、その他の組み合わせにしたりすることは自由に行われてよい。   In the second embodiment shown in FIG. 2, a wiring for supplying and fixing the potential of the source region of the N-type MOS transistor for ESD protection is a second metal wiring and is connected to the drain region. The first metal wiring is shown as an example. However, as in the example of FIG. 1, the wiring for supplying and fixing the potential of the source region is the first metal wiring, and the wiring connected to the drain region is the first metal wiring. The metal wiring of 2 or other combinations may be freely performed.

その際に、第２のメタル配線を用いた側に配置されるビアホールの個数を、図１に示した第１の実施例の説明の主旨に沿って、ＥＳＤ保護用のＮ型ＭＯＳトランジスタにおける複数のドレインあるいは、ソース領域において導入される配線抵抗と配線間の抵抗の合計が、略等しくなるように分配配置することが肝要であるという点、および３層以上の複数層のメタル配線にも適用可能である点も図１の例と同様である。その他の説明については、図１と同一の符号を付記することで説明に代える。   At that time, the number of via holes arranged on the side using the second metal wiring is set in accordance with the gist of the explanation of the first embodiment shown in FIG. 1 in the N-type MOS transistor for ESD protection. It is important to distribute and arrange so that the total of the wiring resistance introduced in the drain or source region and the resistance between the wirings is substantially equal, and also applies to multi-layer metal wiring of three or more layers This is also possible as in the example of FIG. Other descriptions will be replaced by the same reference numerals as those in FIG.

図３は、本発明による半導体装置の、ＥＳＤ保護用のＮ型ＭＯＳトランジスタの第３の実施例を示す模式的平面図である。図面上は図１に示した第１の実施例とよく似ているので、第１の実施例と同じ点の説明は省略し、異なる点において説明を行なう。第１の実施例と異なる点は、ビアホール６０１の配置であり、以下この点ついて説明する。   FIG. 3 is a schematic plan view showing a third embodiment of the N-type MOS transistor for ESD protection of the semiconductor device according to the present invention. Since the drawing is very similar to the first embodiment shown in FIG. 1, the description of the same points as in the first embodiment will be omitted, and the description will be given in different points. The difference from the first embodiment is the arrangement of the via holes 601, which will be described below.

第１の実施例では、第２のメタル配線を用いた側に配置されるビアホールの配置個数を、図１に示した第１の実施例の説明の主旨に沿って、ＥＳＤ保護用のＮ型ＭＯＳトランジスタにおける複数のドレインあるいは、ソース領域において導入される配線抵抗と配線間の抵抗の合計が、略等しくなるように分配配置することとした。ここで、一定の大きさを有するビアホールの配置個数の上限について実験したデータを図５に示す。   In the first embodiment, the number of via holes arranged on the side using the second metal wiring is determined in accordance with the gist of the explanation of the first embodiment shown in FIG. A plurality of drains in the MOS transistor or the wiring resistance introduced in the source region and the total resistance between the wirings are distributed so as to be substantially equal. Here, FIG. 5 shows data obtained by experimenting on the upper limit of the number of via holes having a certain size.

図５は、ＥＳＤ耐性を向上させるための最適なビアホール配置個数に関する実験データを示しており、図５（ａ）は、評価サンプル構造の平面模式図を示している。全てのビアホールは同一の大きさを有している。簡略のためにゲート電極とドレイン領域は省略してある。図５（ｂ）は、ＥＳＤ試験（ＨＭＢモード）にて破壊までパルスを印加した後にフォトエミッションにて破壊箇所を特定した際の破壊箇所の発生比率を示している。このグラフの横軸の１，１，２，３，４はＡ点を基準にしたときのビアホールの個数比を示し、それぞれ図５（ａ）のＡ点、Ｂ点、Ｃ点、Ｄ点、Ｅ点に対応するものである。この実験から、Ａ点とＥ点のようにグランド電位供給ラインからの距離等の条件が同一でもビアホールの個数比が４倍と多くなっているＥ点の場合にはＥＳＤによる破壊が起きやすいことが分かる。   FIG. 5 shows experimental data relating to the optimum number of via holes for improving ESD resistance, and FIG. 5A shows a schematic plan view of an evaluation sample structure. All via holes have the same size. For simplicity, the gate electrode and the drain region are omitted. FIG. 5 (b) shows the occurrence ratio of the destruction location when the destruction location is specified by photoemission after applying the pulse until the destruction in the ESD test (HMB mode). 1, 1, 2, 3, and 4 on the horizontal axis of this graph indicate the number ratios of via holes with respect to point A, and points A, B, C, D, This corresponds to point E. From this experiment, ESD damage is likely to occur in the case of point E where the number ratio of via holes is four times as large as the points A and E, even if the conditions such as the distance from the ground potential supply line are the same. I understand.

この実験結果は、図３においては、グランド電位供給ライン７０１から最も離れた位置に配置された第２のソース領域１０２、あるいは第３のソース領域１０３上のビアホール配置個数は、グランド電位供給ライン７０１から最も近い位置に配置された第１のソース領域１０１、あるいは第４のソース領域１０４上のビアホール数の３倍以下とすることが肝要であるということを示している。これより、Ｗ長延長のためフィンガー数が増えた場合においても、グランド電位供給ライン７０１から最も離れた位置に配置されたソース領域のビアホールの配置個数は、グランド電位供給ライン７０１から最も近い位置に配置されたソース領域のビアホール個数との比の３倍までとすることで、ＥＳＤ保護用のＮ型ＭＯＳトランジスタ全体で均一に動作させることができる。   As a result of this experiment, the number of via holes on the second source region 102 or the third source region 103 arranged farthest from the ground potential supply line 701 in FIG. This indicates that it is important that the number of via holes on the first source region 101 or the fourth source region 104 disposed at the closest position to the first source region 101 is three times or less. As a result, even when the number of fingers is increased due to the extension of the W length, the number of via holes in the source region arranged farthest from the ground potential supply line 701 is closest to the ground potential supply line 701. By making the ratio up to three times the ratio of the number of via holes in the arranged source region, the entire N-type MOS transistor for ESD protection can be operated uniformly.

図４は、本発明による半導体装置の、ＥＳＤ保護用のＮ型ＭＯＳトランジスタの第４の実施例を示す模式的平面図である。第２の実施例と第３の実施例を組み合わせたものである。従って説明は省略するが、Ｗ長延長のためフィンガー数が増えた場合においても、グランド電位供給ライン７０１から最も離れた位置に配置されたソース領域のビアホールの配置個数は、グランド電位供給ライン７０１から最も近い位置に配置されたソース領域のビアホール個数との比の３倍までとすることで、ＥＳＤ保護用のＮ型ＭＯＳトランジスタ全体で均一に動作させることができる。   FIG. 4 is a schematic plan view showing a fourth embodiment of the N-type MOS transistor for ESD protection of the semiconductor device according to the present invention. The second embodiment and the third embodiment are combined. Therefore, although explanation is omitted, even when the number of fingers is increased due to the extension of the W length, the number of via holes in the source region arranged farthest from the ground potential supply line 701 is the same as that of the ground potential supply line 701. By making the ratio up to three times the ratio of the number of via holes in the source region arranged at the closest position, the entire N-type MOS transistor for ESD protection can be operated uniformly.

図６は、本発明による半導体装置の、ＥＳＤ保護用のＮ型ＭＯＳトランジスタの第５の実施例を示す模式的平面図である。図１と対応する部分には同じ番号が付してある。図１に示す第１の実施例と異なる点は、一定の幅を有し長さの異なる線状ビアホール１１０１の配置である。   FIG. 6 is a schematic plan view showing a fifth embodiment of the N-type MOS transistor for ESD protection of the semiconductor device according to the present invention. Parts corresponding to those in FIG. 1 are given the same numbers. The difference from the first embodiment shown in FIG. 1 is the arrangement of linear via holes 1101 having a constant width and different lengths.

従って、ビアホール６０１の替わりに、線状のビアホールを設置することで第１のメタル配線との接続面積の増加により、低抵抗化を実現し、実施例１の特徴を有しながら、ＥＳＤサージの伝播スピードをさらに伝達・動作しやすくすることができる。   Therefore, by installing a linear via hole instead of the via hole 601, a reduction in resistance is realized by increasing the connection area with the first metal wiring, and the ESD surge is reduced while having the characteristics of the first embodiment. Propagation speed can be further transmitted and operated more easily.

図７は、本発明による半導体装置の、ＥＳＤ保護用のＮ型ＭＯＳトランジスタの第６の実施例を示す模式的平面図である。図２と対応する部分には同じ番号が付してある。図２に示す第２の実施例と異なる点は、一定の幅を有し長さの異なる線状ビアホール１１０１の配置である。   FIG. 7 is a schematic plan view showing a sixth embodiment of the N-type MOS transistor for ESD protection of the semiconductor device according to the present invention. Portions corresponding to those in FIG. 2 are given the same numbers. The difference from the second embodiment shown in FIG. 2 is the arrangement of linear via holes 1101 having a constant width and different lengths.

従って、ビアホール６０１の替わりに、線状のビアホールを設置することで第１のメタル配線との接続面積の増加により、低抵抗化を実現し、実施例２の特徴を有しながら、ＥＳＤサージの伝播スピードをさらに伝達・動作しやすくすることができる。   Therefore, by installing a linear via hole in place of the via hole 601, the resistance is reduced by increasing the connection area with the first metal wiring, and the ESD surge is reduced while having the characteristics of the second embodiment. Propagation speed can be further transmitted and operated more easily.

１０１ 第１のソース領域
１０２ 第２のソース領域
１０３ 第３のソース領域
１０４ 第４のソース領域
２０１ ゲート電極
３０１ 第１のドレイン領域
３０２ 第２のドレイン領域
３０３ 第３のドレイン領域
６０１ ビアホール
７０１ グランド電位供給ライン
７１１ 第２のメタル配線
８０１ 外部接続端子
８１１ 第１のメタル配線
９０１ 第１のメタル配線
１１０１ 線状ビアホール 101 First source region 102 Second source region 103 Third source region 104 Fourth source region 201 Gate electrode 301 First drain region 302 Second drain region 303 Third drain region 601 Via hole 701 Ground potential Supply line 711 Second metal wiring 801 External connection terminal 811 First metal wiring 901 First metal wiring 1101 Linear via hole

Claims (12)

ドレイン領域とソース領域がひとつずつゲート電極を挟んで交互に配置された、複数のトランジスタが一体化したマルチフィンガータイプのＥＳＤ保護用のＮ型ＭＯＳトランジスタを有する半導体装置であって、
前記ドレイン領域は外部接続端子と電気的に接続され、
前記ソース領域は、前記ソース領域上に配置され接続された第１のメタル配線と、一定の大きさを有するビアホールによって前記第１のメタル配線と接続された第２のメタル配線とを介してグランド電位供給ラインと電気的に接続されており、
前記ビアホールの数が、前記グランド電位供給ラインからの距離に応じて、遠くなるほど数多く配置されている半導体装置。 A semiconductor device having a multi-finger type ESD protection N-type MOS transistor in which a plurality of transistors are integrated, each having a drain region and a source region alternately arranged with a gate electrode interposed therebetween,
The drain region is electrically connected to an external connection terminal;
The source region is grounded via a first metal wiring arranged and connected on the source region and a second metal wiring connected to the first metal wiring by a via hole having a certain size. Electrically connected to the potential supply line,
A semiconductor device in which the number of via holes is increased as the distance from the ground potential supply line increases. 前記第２のメタル配線は前記ＥＳＤ保護用のＮ型ＭＯＳトランジスタのチャネル幅方向と垂直な方向から配線されており、前記第１のメタル配線は前記ＥＳＤ保護用のＮ型ＭＯＳトランジスタのチャネル幅方向と水平な方向に配置されており、前記第２のメタル配線と前記第１のメタル配線とは、前記ソース領域の上の領域にて前記ビアホールにより接続されている請求項１記載の半導体装置。   The second metal wiring is wired from a direction perpendicular to the channel width direction of the ESD protection N-type MOS transistor, and the first metal wiring is the channel width direction of the ESD protection N-type MOS transistor. 2. The semiconductor device according to claim 1, wherein the second metal wiring and the first metal wiring are connected by the via hole in a region above the source region. グランド電位供給ラインから最も離れた位置に配置されたソース領域上のビアホールの配置個数と、グランド電位供給ラインから最も近い位置に配置されたソース領域上のビアホール配置個数との比が３を超えない請求項１記載の半導体装置。   The ratio between the number of via holes arranged on the source region located farthest from the ground potential supply line and the number of via holes arranged on the source region located closest to the ground potential supply line does not exceed 3. The semiconductor device according to claim 1. 前記第１のメタル配線および前記第２のメタル配線は高融点金属を含む請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the first metal wiring and the second metal wiring contain a refractory metal. 前記ビアホールは、前記ソース領域上に配置され接続された第１のメタル配線において、前記ＥＳＤ保護用のＮ型ＭＯＳトランジスタのチャネル幅方向と水平な方向に広く分布するように配置されている請求項２記載の半導体装置。   The via hole is arranged so as to be widely distributed in a direction horizontal to a channel width direction of the N-type MOS transistor for ESD protection in a first metal wiring arranged and connected on the source region. 2. The semiconductor device according to 2. 前記ビアホールは前記ソース領域上に配置され接続された第１のメタル配線の一部の領域の上に固まって配置されている請求項２記載の半導体装置。   3. The semiconductor device according to claim 2, wherein the via hole is fixedly disposed on a partial region of the first metal wiring disposed and connected on the source region. グランド電位供給ラインから最も離れた位置に配置されたソース領域上のビアホールの配置個数と、グランド電位供給ラインから最も近い位置に配置されたソース領域上のビアホール配置個数との比が３を超えない請求項５記載の半導体装置。   The ratio between the number of via holes arranged on the source region located farthest from the ground potential supply line and the number of via holes arranged on the source region located closest to the ground potential supply line does not exceed 3. The semiconductor device according to claim 5. 各ドレイン領域と各ソース領域がひとつずつゲート電極を挟んで交互に配置された、複数のトランジスタが一体化したマルチフィンガータイプのＥＳＤ保護用のＮ型ＭＯＳトランジスタを有する半導体装置であって、
前記各ドレイン領域は外部接続端子と電気的に接続され、
前記各ソース領域は、前記各ソース領域上に配置され接続された第１のメタル配線と、前記第１のメタル配線上に配置されたビアホールによって前記第１のメタル配線と接続された第２のメタル配線とを介してグランド電位供給ラインと電気的に接続されており、
前記各ソース領域においては、前記グランド電位供給ラインに接続された前記第２のメタル配線の配線抵抗と、前記ビアホールよる接続抵抗とを加算したそれぞれの抵抗値が互いに概ね等しい半導体装置。 A semiconductor device having a multi-finger type ESD protection N-type MOS transistor in which a plurality of transistors are integrated, each drain region and each source region being alternately arranged with a gate electrode interposed therebetween,
Each of the drain regions is electrically connected to an external connection terminal,
Each of the source regions includes a first metal wiring disposed on and connected to each of the source regions, and a second metal interconnected to the first metal wiring by a via hole disposed on the first metal wiring. It is electrically connected to the ground potential supply line via metal wiring,
In each of the source regions, a semiconductor device in which resistance values obtained by adding the wiring resistance of the second metal wiring connected to the ground potential supply line and the connection resistance of the via hole are substantially equal to each other. 前記ビアホールは一定の大きさを有し、前記第１のメタル配線上に配置された前記ビアホールの数を変えることで前記それぞれの抵抗値を互いに概ね等しくする請求項８記載の半導体装置。   9. The semiconductor device according to claim 8, wherein the via hole has a certain size, and the resistance values thereof are made substantially equal to each other by changing the number of the via holes arranged on the first metal wiring. 前記ビアホールは一定の幅を有する線状ビアホールであり、前記第１のメタル配線上に配置された前記線状ビアホールの長さを変えることで前記それぞれの抵抗値を互いに概ね等しくする請求項８記載の半導体装置。   9. The via hole is a linear via hole having a certain width, and the respective resistance values are made substantially equal to each other by changing the length of the linear via hole disposed on the first metal wiring. Semiconductor device. 前記第２のメタル配線は、前記グランド電位供給ラインからの距離が遠いほど、前記ＥＳＤ保護用のＮ型ＭＯＳトランジスタの幅と平行する方向の配線幅が大きい請求項８記載の半導体装置。   9. The semiconductor device according to claim 8, wherein the second metal wiring has a larger wiring width in a direction parallel to the width of the N-type MOS transistor for ESD protection as the distance from the ground potential supply line increases. ドレイン領域とソース領域がひとつずつゲート電極を挟んで交互に配置された、複数のトランジスタが一体化したマルチフィンガータイプのＥＳＤ保護用のＮ型ＭＯＳトランジスタを有する半導体装置であって、
前記ドレイン領域は外部接続端子と電気的に接続され、
前記ソース領域は、前記ソース領域上に配置され接続された第１のメタル配線と、一定の幅を有する線状ビアホールによって前記第１のメタル配線と接続された第２のメタル配線とを介してグランド電位供給ラインと電気的に接続されており、
前記線状ビアホールの長さが、前記グランド電位供給ラインからの距離に応じて、遠くなるほど長くなるよう配置されている半導体装置。

A semiconductor device having a multi-finger type ESD protection N-type MOS transistor in which a plurality of transistors are integrated, each having a drain region and a source region alternately arranged with a gate electrode interposed therebetween,
The drain region is electrically connected to an external connection terminal;
The source region is arranged via a first metal wiring arranged and connected on the source region, and a second metal wiring connected to the first metal wiring by a linear via hole having a certain width. It is electrically connected to the ground potential supply line,
A semiconductor device in which the length of the linear via hole is increased as the distance from the ground potential supply line increases.

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US8373231B2 (en) 2013-02-12
EP2221875A3 (en) 2011-10-19
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TWI472014B (en) 2015-02-01
KR101629968B1 (en) 2016-06-13
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JP5603089B2 (en) 2014-10-08
TW201103124A (en) 2011-01-16

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