CN102446961B - Semiconductor device containing power device and preparation method thereof - Google Patents
Semiconductor device containing power device and preparation method thereof Download PDFInfo
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- CN102446961B CN102446961B CN201110409281.2A CN201110409281A CN102446961B CN 102446961 B CN102446961 B CN 102446961B CN 201110409281 A CN201110409281 A CN 201110409281A CN 102446961 B CN102446961 B CN 102446961B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000002360 preparation method Methods 0.000 title claims abstract description 21
- 238000009792 diffusion process Methods 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 230000003071 parasitic effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 230000035515 penetration Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
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Abstract
The invention, which belongs to the semiconductor manufacturing filed, discloses a semiconductor device containing a power device and a preparation method thereof. The semiconductor device comprises an MOS tube. The MOS tube includes gates, sources and drains, wherein the sources and the drains are distributed at two sides of the gates; and contact holes are formed on the sources and the drains, wherein the sizes of the contact holes are greater than sizes of contact holes in a standard technology. According to the semiconductor device containing a power device in the invention, the power device is provided with contact holes, wherein the sizes of the contact holes are greater than sizes of contact holes in a standard technology; therefore, parasitic resistances of the contact holes in the power device are obviously reduced, thereby improving current density of the power device.
Description
[technical field]
The present invention relates to field of semiconductor manufacture, particularly a kind of semiconductor device that comprises power device and preparation method thereof.
[background technology]
Power device is one of device comparatively common in integrated circuit.Power device can comprise powerful NMOS pipe (NMOSFET, N-type MOS (metal-oxide-semiconductor) memory) and PMOS pipe (PMOSFET, P type MOS (metal-oxide-semiconductor) memory).
Please refer to Fig. 1, it shows the domain schematic diagram of a kind of NMOS pipe 100 of the prior art.This NMOS pipe 100 can be by planar technique and self-registered technology preparation.This NMOS pipe 100 comprises three electrodes, is respectively source electrode (source), drain electrode (drain) and grid (gate).In diagram domain, grid 101 is between source electrode 102 and drain electrode 103, for source electrode 102 and drain electrode 103 are separated.The layout area of described grid 101 comprises the rectangle grid of some parallel vertical bar types arranged side by side, is generally polysilicon layer.Described source electrode 102 and drain electrode 103 are generally the N of the both sides that are distributed in described grid 101
+diffusion region, be positioned at the lower floor of described grid 101 place layers, and the corresponding metal level that is connected in integrated circuit surface by contact hole 105 is with mutual conducting.Described NMOS pipe 100 also comprises by P
+the P type lining body 104 that diffusion region forms.
In existing conventional planar technique, contact hole is conventionally used in and in integrated circuit, is connected with diffusion region for metal or metal is connected with polysilicon, such as the contact hole 105 in Fig. 1 is used in the N of metal and source, drain electrode
+diffusion region connects, and is also used in metal and is connected with the polysilicon layer of grid.Contact hole is designed to square conventionally, is also that the each contact hole on chip piece adopts the square of fixing the length of side.Compare when NMOS pipe adopts the integrated circuit technology of 0.5 micron of minimum lithographic precision to prepare as shown in Figure 1,105 of described contact holes are that the fixing length of side is the square of 0.5 micron, and the length of side of this contact hole 105 all adopts the minimal-contact hole width stipulating in manufacture craft conventionally.
But find in actual use, conducting resistance that often need to be lower in the design of power device and the current density of Geng Gao, the dead resistance that prior art adopts standard-sized contact hole to produce is larger, causes the current density of power device lower, cannot meet the demand under some application scenarios.
For this reason, be necessary to provide a kind of new technical scheme to solve the problems referred to above.
[summary of the invention]
The object of this part is to summarize some aspects of embodiments of the invention and briefly introduces some preferred embodiments.In this part and the application's specification digest and denomination of invention, may do a little simplification or omit to avoid the making object of this part, specification digest and denomination of invention fuzzy, and this simplification or omit and can not be used for limiting the scope of the invention.
One object of the present invention is to provide a kind of semiconductor device that comprises power device, and it has less contact hole dead resistance and larger current density.
Another object of the present invention is to provide a kind of preparation method of the semiconductor device that comprises power device, for the preparation of the described semiconductor device that comprises power device.
In order to reach object of the present invention, according to an aspect of the present invention, the embodiment of the present invention provides a kind of semiconductor device that comprises power device, and described semiconductor device comprises;
Metal-oxide-semiconductor, described metal-oxide-semiconductor comprises grid and is distributed in source electrode and the drain electrode of described grid both sides, in described source electrode and drain electrode, is formed with contact hole, the size of described contact hole is greater than the contact hole size in standard technology.
Further, in described source electrode and drain electrode, an earth-free included contact hole below, also comprises that the degree of depth of described well area is greater than the degree of depth of the diffusion region of described source electrode and drain electrode corresponding to the well area of the diffusion region type of described source electrode and drain electrode.
Further, the contact hole of described source electrode and drain electrode is rectangle contact hole, and the limit of described rectangle contact hole is parallel with the long limit of described grid.
Further, described metal-oxide-semiconductor also comprises lining body, on described lining body, is formed with contact hole, and the size of the contact hole of described lining body is greater than the contact hole size in standard technology.
Further, the wide minimal-contact hole width equaling in standard technology of described rectangle contact hole, the minimal-contact hole width of growing up in standard technology of described rectangle contact hole.
Further, described grid comprises some parallel rectangle grids arranged side by side, and the spacing between described some parallel rectangle grids arranged side by side equates.
Further, described grid comprises some parallel rectangle grids arranged side by side, under drain electrode between described some parallel rectangle grids arranged side by side, spacing equals the first spacing, under source electrode between described some parallel rectangle grids arranged side by side, spacing equals the second spacing, and described the first spacing is greater than the second spacing.
According to a further aspect in the invention, the embodiment of the present invention also provides a kind of preparation method of the semiconductor device that comprises power device, and described method comprises: semi-conductive substrate is provided; In described Semiconductor substrate, form grid and be distributed in source electrode and the drain electrode of described grid both sides; In described source electrode and drain electrode, form the contact hole that size is greater than the contact hole size in standard technology.
Further, described method also comprises:
In the time forming described source electrode and drain electrode, also in described source electrode and drain electrode below an earth-free included contact hole, form the well area corresponding to the diffusion region type of described source electrode and drain electrode, the degree of depth of described well area is greater than the degree of depth of the diffusion region of described source electrode and drain electrode.
Further, in described source electrode and drain electrode, form rectangle contact hole, the wide minimal-contact hole width being equal to or greater than in standard technology of described rectangle contact hole, the minimal-contact hole width of growing up in standard technology of described rectangle contact hole.
Compared with prior art, the semiconductor device of power device and preparation method thereof that comprises in the present invention has the following advantages:
By the contact hole that provides size to be greater than the contact hole of standard technology to the power device in the semiconductor device that comprises power device, the dead resistance of the contact hole in this power device is obviously reduced, thereby improved the current density of power device.
[accompanying drawing explanation]
In conjunction with reference to accompanying drawing and ensuing detailed description, the present invention will be easier to understand, wherein structure member corresponding to same Reference numeral, wherein:
Fig. 1 is the domain schematic diagram of a kind of NMOS pipe of the prior art;
Fig. 2 is the semiconductor device that comprises power device in the present invention domain schematic diagram in one embodiment.
Fig. 3 is the semiconductor device that comprises power device in the present invention generalized section in one embodiment;
Fig. 4 A is the semiconductor device that comprises power device in the present invention domain schematic diagram in another embodiment;
Fig. 4 B is the semiconductor device that comprises power device in the present invention generalized section in Fig. 4 A illustrated embodiment;
Fig. 5 is the method flow diagram in one embodiment of preparation method of the semiconductor device that comprises power device in the present invention.
[embodiment]
Detailed description of the present invention is mainly carried out the running of direct or indirect simulation technical solution of the present invention by program, step, logical block, process or other symbolistic descriptions.For the thorough the present invention that understands, a lot of specific detail in ensuing description, are stated.And in the time there is no these specific detail, the present invention may still can realize.Under those of skill in the art uses these descriptions herein and states the work essence of effectively introducing them to the others skilled in the art in affiliated field.In other words, be the object of the present invention of avoiding confusion, because the method for knowing, program, composition and circuit are readily appreciated that, therefore they are not described in detail.
Alleged " embodiment " or " embodiment " refers to special characteristic, structure or the characteristic that can be contained at least one implementation of the present invention herein.Different local in this manual " in one embodiment " that occur not all refer to same embodiment, neither be independent or the embodiment mutually exclusive with other embodiment optionally.In addition, represent sequence of modules in method, flow chart or the functional block diagram of one or more embodiment and revocablely refer to any particular order, not also being construed as limiting the invention.
The emphasis that comprises semiconductor device of power device and preparation method thereof and bright spot in the present invention are: provide size to be greater than the contact hole of the contact hole size in standard technology to the power device in semiconductor device, the dead resistance that contact hole in this power device is produced diminishes, thereby improves the current density in this power device.
For convenience of description, power device herein is all described as a specific example with NMOS pipe, the embodiment for PMOS pipe as power device, be the easy full of beard of those skilled in the art and part, repeat no longer one by one.
Please refer to Fig. 2, it shows the semiconductor device that comprises power device in the present invention domain schematic diagram in an embodiment 200.The described semiconductor device that comprises power device 200 comprises NMOS pipe.Described NMOS pipe comprises three electrodes, is respectively source electrode (source), drain electrode (drain) and grid (gate).In diagram domain, grid 201 is between source electrode 202 and drain electrode 203, for source electrode 202 and drain electrode 203 are separated.The layout area of described grid 201 comprises the rectangle grid of some parallel vertical bar types arranged side by side, and this rectangle grid is generally polysilicon layer.Described source electrode 202 and drain electrode 203 are generally the N of the both sides that are distributed in described grid 201
+diffusion layer, be positioned at the lower floor of described grid 201 place layers, and the corresponding metal level that is connected in integrated circuit surface by the contact hole 205 of portion formed thereon is with mutual conducting.Described NMOS pipe also comprises by P
+the P type lining body 204 that diffusion region forms.
Wherein, contact hole 205 is rectangle contact hole, and its size is greater than the contact hole size in standard technology.The long limit of this rectangle contact hole and the limit of described grid 201 are parallel to each other.The semiconductor device 200 that comprises power device described in supposing adopts the integrated circuit technology preparation of 0.5 micron of minimum lithographic precision, the minimal-contact hole dimension of its regulation is 0.5 micron, described rectangle contact hole 205 wide can be 0.5 micron or be greater than 0.5, and its length can be greater than 0.5 micron, such as its length can be 5 microns; Again such as, the wide of described rectangle contact hole 205 can be 0.6 micron or 1 micron, and length can be 4 microns etc.Certainly,, for the contact hole 206 being formed on P type lining body 204, also can adopt rectangle contact hole.And for other non-power device on this semiconductor device, can still adopt the contact hole size providing in standard technology, such as adopting the square contact hole of 0.5 micron * 0.5 micron.
In sum, the present embodiment provides size to be greater than the contact hole of the contact hole size in standard technology to the power device in described semiconductor device, the dead resistance that contact hole in this power device is produced diminishes, thereby improves the current density in this power device.Specifically, rectangle contact hole in the present embodiment is not square contact hole of the prior art, but be equivalent to the strip contact hole that multiple square contact hole parallel connections form afterwards, obviously on identical chip area, greatly increase the area of contact hole, thereby reduced the dead resistance that contact hole produces.In addition, this rectangle contact hole also provides the longitudinal current path along long side direction.In actual preparation technology, general power device adopts double layer of metal wiring, longitudinal electric current is provided by first layer metal conventionally, the longitudinal current path that rectangle contact hole in the present embodiment provides is identical with first layer metal direction of routing, be equivalent to provide another current path in parallel, thereby increased the current density of power device.Because the thickness of the depth ratio first layer metal of contact hole in most of technique is large, so the current density increasing is appreciable.
But find according to experiment, simply adopt large scale contact hole may cause the diffusion region of some metal piercing source electrode or drain electrode, thereby cause short circuit.Please refer to shown in Fig. 3, large scale contact hole 302 may penetrate the N of source electrode or drain electrode
+diffusion region 304 and touching on P type substrate 306.Can cause so dissimilar N
+diffusion region and the short circuit of P type substrate.For this reason, the embodiment of the present invention also provides more preferably embodiment.
Incorporated by reference to reference to figure 4A and Fig. 4 B, it shows respectively domain schematic diagram in an embodiment 400 of the semiconductor device that comprises power device in the present invention and the generalized section along BB direction.The described semiconductor device that comprises power device 400 comprises NMOS pipe.Described NMOS pipe comprises three electrodes, is respectively source electrode (source), drain electrode (drain) and grid (gate).In diagram domain, grid 401 is between source electrode 402 and drain electrode 403, for source electrode 402 and drain electrode 403 are separated.The layout area of described grid 401 comprises the rectangle grid of some parallel vertical bar types arranged side by side, is generally polysilicon layer.Described source electrode 402 and drain electrode 403 are generally the N of the both sides that are distributed in described grid 401
+diffusion region, is positioned at the lower floor of described grid 401 place layers, and respectively by being formed at the contact hole 405 on described source electrode 402 tops and being formed at corresponding metal level that the contact hole 406 on described drain electrode 403 tops is connected in integrated circuit surface with mutual conducting.Described NMOS pipe also comprises by P
+the P type lining body 404 that diffusion region forms.
Wherein, the contact hole 406 in contact hole 405 and described drain electrode 403 in described source electrode 402 is rectangle contact hole, and its size is greater than the contact hole size in standard technology.The long limit of this rectangle contact hole and the limit of described grid 201 are parallel to each other.Suppose that the semiconductor device 200 that comprises power device adopts the integrated circuit technology preparation of 0.5 micron of minimum lithographic precision, the minimal-contact hole dimension of its regulation is 0.5 micron, the wide minimal-contact hole dimension that is equal to or greater than of described rectangle contact hole 205, and its length can be greater than 0.5 micron, such as its length can be 5 microns; Again such as, the wide of described rectangle contact hole 205 can be 0.6 micron or 1 micron, and length can be 4 microns etc.Certainly,, for the contact hole 407 being formed on P type lining body 404, also can adopt rectangle contact hole.And for other non-power device on this semiconductor device, can still adopt the contact hole size providing in standard technology, such as the square contact hole of 0.5 micron * 0.5 micron.
Different from previous embodiment, contact hole 406 belows in the drain electrode 403 of the NMOS pipe that the present embodiment provides are also formed with N trap 408.The degree of depth of this N trap 408 is greater than the degree of depth of the N+ diffusion region of drain electrode 403.Due to most of power NMOS pipes, its source electrode and lining body are all ground connection.Therefore in these source electrodes and lining body directly grounded application, can be directly source electrode and the contact hole that serves as a contrast tagma be designed to as the rectangle contact hole as described in Fig. 4.Even if there is penetration phenomenon as shown in Figure 3, due under normal circumstances, P type substrate is also ground connection, thus just cause two all the partial short circuit of ground connection to together, can not cause other problem.But, for drain electrode 403, conventionally need to connect other current potentials, not generally earthing potential.In order still to adopt rectangle contact hole and to prevent the generation of penetration phenomenon, can below rectangle contact hole 406, form a N trap 408.Because N trap 408 is deep, be difficult for occurring penetration phenomenon as shown in Figure 2 so general.
In sum, the present embodiment provides size to be greater than the contact hole of the contact hole size in standard technology to the power device in described semiconductor device, the dead resistance that contact hole in this power device is produced diminishes, thereby improves the current density in this power device.And, below the included contact hole of earth-free drain electrode, also comprise the N corresponding to described drain electrode
+the N well area of diffusion region, the degree of depth of described N well area is greater than the N of described drain electrode
+the degree of depth of diffusion region.Easily full of beard and, no matter be NMOS pipe or PMOS pipe, only need be in the source electrode of metal-oxide-semiconductor and drain electrode below an earth-free included contact hole, form the well area corresponding to the diffusion region type of described source electrode and drain electrode, the degree of depth of described well area is greater than the degree of depth of the diffusion region of described source electrode and drain electrode, just can reach the object that this prevents that penetration phenomenon from occurring.
It should be noted that, grid shown in previous embodiment comprises some parallel rectangle grids arranged side by side, between between described some parallel rectangle grids arranged side by side or include source electrode and drain electrode, in embodiment, the spacing between described some parallel rectangle grids arranged side by side equates conventionally.But under some embodiment; in order to reach good electrostatic protection requirement; need larger drain electrode spacing; that is to say; need to drain 403 region is larger than the region of source electrode 402, and the contact hole 406 that makes to drain in 403 is larger to the distance (spacing drains) of any conducting channel (being grid below).Now, under drain electrode 403 between some parallel rectangle grids 401 arranged side by side, spacing equals the first space D 1, under source electrode 402 between some parallel rectangle grids 401 arranged side by side, spacing equals the second space D 2, and described the first space D 1 is greater than the second space D 2.
The embodiment of the present invention also provides a kind of preparation method of the semiconductor device that comprises power device simultaneously.Please refer to Fig. 5, the method flow diagram of its preparation method who shows the semiconductor device that comprises power device in the present invention in an embodiment 500.The preparation method 500 of the described semiconductor device that comprises power device comprises;
This semiconductor device that comprises power device can adopt planar technique and self-registered technology preparation.First semi-conductive substrate can be provided, then in described Semiconductor substrate, form grid and be distributed in source electrode and the drain electrode of described grid both sides through steps such as photoetching, burn into Implantations.Be example take NMOS pipe as power device, described grid can be the rectangle grid of some parallel distributions arranged side by side.Between between adjacent rectangle grid or be formed with source region and drain region.Certainly,, in different embodiment, described grid can be also other shape
In order to prevent the generation of penetration phenomenon, in the time forming described source electrode and drain electrode, can also be in the source electrode of metal-oxide-semiconductor and drain electrode below an earth-free included contact hole position, form the well area corresponding to the diffusion region type of described source electrode and drain electrode, the degree of depth of described well area is greater than the degree of depth of the diffusion region of described source electrode and drain electrode.Such as, below the included contact hole of the earth-free drain electrode of NMOS pipe, also form the N corresponding to described drain electrode
+the N well area of diffusion region, the degree of depth of described N well area is greater than the N of described drain electrode
+the degree of depth of diffusion region.
Then, can in source region and drain region, form the contact hole that size is greater than the contact hole size in standard technology.Such as can form rectangle contact hole in source region and drain region, the wide minimal-contact hole width that can be more than or equal in standard technology of this rectangle contact hole, the length of this rectangle contact hole can be greater than the minimal-contact hole width in standard technology.The long limit of this rectangle contact hole can parallel with the limit of grid.The formation of this rectangle contact hole can adopt one or more in the modes such as growth, photoetching, filling, deposition and the sputter in standard technology.Contact hole for the lining body in power device also can adopt rectangle contact hole; Other device for non-power device in this semiconductor device can still adopt the square contact hole in standard technology, and the length of side of this square contact hole is generally equal to the minimal-contact hole width in standard technology.
In sum, the preparation method that the present embodiment provides provides size to be greater than the contact hole of the contact hole size in standard technology to the power device in described semiconductor device, the dead resistance that contact hole in this power device is produced diminishes, thereby improves the current density in this power device.And, also in the source electrode of metal-oxide-semiconductor and drain electrode below an earth-free included contact hole, form the well area corresponding to the diffusion region type of described source electrode and drain electrode, the degree of depth of described well area is greater than the degree of depth of the diffusion region of described source electrode and drain electrode, to reach the object that prevents that penetration phenomenon from occurring.
Above-mentioned explanation has fully disclosed the specific embodiment of the present invention.It is pointed out that and be familiar with the scope that any change that person skilled in art does the specific embodiment of the present invention does not all depart from claims of the present invention.Correspondingly, the scope of claim of the present invention is also not limited only to described embodiment.
Claims (6)
1. a semiconductor device that comprises power device, is characterized in that, it comprises:
Metal-oxide-semiconductor, described metal-oxide-semiconductor comprises grid and is distributed in source electrode and the drain electrode of described grid both sides, in described source electrode and drain electrode, is formed with contact hole, the size of described contact hole is greater than the contact hole size in standard technology,
In described source electrode and drain electrode, an earth-free included contact hole below, also comprises that the degree of depth of described well area is greater than the degree of depth of the diffusion region of described source electrode and drain electrode corresponding to the well area of the diffusion region type of described source electrode and drain electrode,
Described grid comprises some parallel rectangle grids arranged side by side, under drain electrode between described some parallel rectangle grids arranged side by side, spacing equals the first spacing, under source electrode between described some parallel rectangle grids arranged side by side, spacing equals the second spacing, and described the first spacing is greater than the second spacing.
2. semiconductor device according to claim 1, is characterized in that, the contact hole of described source electrode and drain electrode is rectangle contact hole, and the long limit of described rectangle contact hole is parallel with the long limit of described grid.
3. semiconductor device according to claim 2, is characterized in that, described metal-oxide-semiconductor also comprises lining body, on described lining body, is formed with contact hole, and the size of the contact hole of described lining body is greater than the contact hole size in standard technology.
4. semiconductor device according to claim 2, is characterized in that, the wide minimal-contact hole width being equal to or greater than in standard technology of described rectangle contact hole, the minimal-contact hole width of growing up in standard technology of described rectangle contact hole.
5. a preparation method who comprises the semiconductor device of power device, is characterized in that, it comprises:
Semi-conductive substrate is provided;
In described Semiconductor substrate, form grid and be distributed in source electrode and the drain electrode of described grid both sides;
In described source electrode and drain electrode, form the contact hole that size is greater than the contact hole size in standard technology,
Described method also comprises:
In the time forming described source electrode and drain electrode, also in described source electrode and drain electrode below an earth-free included contact hole, form the well area corresponding to the diffusion region type of described source electrode and drain electrode, the degree of depth of described well area is greater than the degree of depth of the diffusion region of described source electrode and drain electrode
Described grid comprises some parallel rectangle grids arranged side by side, under drain electrode between described some parallel rectangle grids arranged side by side, spacing equals the first spacing, under source electrode between described some parallel rectangle grids arranged side by side, spacing equals the second spacing, and described the first spacing is greater than the second spacing.
6. the preparation method of the semiconductor device that comprises power device according to claim 5, is characterized in that, described described source electrode and drain electrode on form the contact hole that size is greater than the contact hole size in standard technology, specifically comprise;
In described source electrode and drain electrode, form rectangle contact hole, the wide minimal-contact hole width being equal to or greater than in standard technology of described rectangle contact hole, the minimal-contact hole width of growing up in standard technology of described rectangle contact hole.
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| CN1159250A (en) * | 1995-07-11 | 1997-09-10 | 爱特梅尔股份有限公司 | Integrated circuit contacts with secured stringers |
| CN1189694A (en) * | 1996-12-20 | 1998-08-05 | 日本电气株式会社 | Semiconductor device having N mos and P mos transmistors on common substrate |
| CN101814501A (en) * | 2009-02-23 | 2010-08-25 | 精工电子有限公司 | Semiconductor device |
| CN202423295U (en) * | 2011-12-09 | 2012-09-05 | 无锡中星微电子有限公司 | Integrated circuit chip |
-
2011
- 2011-12-09 CN CN201110409281.2A patent/CN102446961B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1159250A (en) * | 1995-07-11 | 1997-09-10 | 爱特梅尔股份有限公司 | Integrated circuit contacts with secured stringers |
| CN1189694A (en) * | 1996-12-20 | 1998-08-05 | 日本电气株式会社 | Semiconductor device having N mos and P mos transmistors on common substrate |
| CN101814501A (en) * | 2009-02-23 | 2010-08-25 | 精工电子有限公司 | Semiconductor device |
| CN202423295U (en) * | 2011-12-09 | 2012-09-05 | 无锡中星微电子有限公司 | Integrated circuit chip |
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Effective date of registration: 20240812 Address after: Room 606, Building C, Entrepreneurship Building, No.1 Zhizhi Island Road, High tech Zone, Qingdao City, Shandong Province, China 266112 Patentee after: Vimicro Qingdao Corp. Country or region after: China Address before: 214028 10-storey Building 530 Qingjia Road, Taihu International Science Park, Wuxi New District, Jiangsu Province Patentee before: Zgmicro Corporation Country or region before: China |
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