CN102446961A - Semiconductor device containing power device and preparation method thereof - Google Patents
Semiconductor device containing power device and preparation method thereof Download PDFInfo
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- CN102446961A CN102446961A CN2011104092812A CN201110409281A CN102446961A CN 102446961 A CN102446961 A CN 102446961A CN 2011104092812 A CN2011104092812 A CN 2011104092812A CN 201110409281 A CN201110409281 A CN 201110409281A CN 102446961 A CN102446961 A CN 102446961A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 238000005516 engineering process Methods 0.000 claims abstract description 41
- 238000009792 diffusion process Methods 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000009826 distribution Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000003071 parasitic effect Effects 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 6
- 230000035515 penetration Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
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Abstract
The invention, which belongs to the semiconductor manufacturing filed, discloses a semiconductor device containing a power device and a preparation method thereof. The semiconductor device comprises an MOS tube. The MOS tube includes gates, sources and drains, wherein the sources and the drains are distributed at two sides of the gates; and contact holes are formed on the sources and the drains, wherein the sizes of the contact holes are greater than sizes of contact holes in a standard technology. According to the semiconductor device containing a power device in the invention, the power device is provided with contact holes, wherein the sizes of the contact holes are greater than sizes of contact holes in a standard technology; therefore, parasitic resistances of the contact holes in the power device are obviously reduced, thereby improving current density of the power device.
Description
[technical field]
The present invention relates to field of semiconductor manufacture, particularly a kind of semiconductor device that comprises power device and preparation method thereof.
[background technology]
Power device is one of device comparatively common in the integrated circuit.Power device can comprise powerful NMOS pipe (NMOSFET, N type MOS memory) and PMOS pipe (PMOSFET, P type MOS memory).
Please refer to Fig. 1, it shows the domain sketch map of a kind of NMOS pipe 100 of the prior art.This NMOS pipe 100 can be through planar technique and self-registered technology preparation.This NMOS pipe 100 comprises three electrodes, is respectively source electrode (source), drain electrode (drain) and grid (gate).In the diagram domain, grid 101 is at source electrode 102 and drain between 103, is used for source electrode 102 and drain electrode were opened in 103 minutes.The layout area of said grid 101 comprises the rectangle grid of some parallel vertical bar types arranged side by side, is generally polysilicon layer.Said source electrode 102 and drain electrode 103 are generally the N of the both sides that are distributed in said grid 101
+The diffusion region is positioned at the lower floor of said grid 101 place layers, and the corresponding metal level that is connected in integrated circuit surface through contact hole 105 is with mutual conducting.Said NMOS pipe 100 also comprises by P
+The P type lining body 104 that the diffusion region forms.
In the existing conventional planar technique, contact hole is used in usually and is used in the integrated circuit that metal is connected with the diffusion region or metal is connected with polysilicon, is used in the N of metal and source, drain electrode such as the contact hole among Fig. 1 105
+The diffusion region connects, and also is used in metal and is connected with the polysilicon layer of grid.Contact hole is designed to square usually, also is that each contact hole on the chip piece all adopts the fixedly square of the length of side.When adopting the integrated circuit technology of 0.5 micron of minimum lithographic precision to prepare such as NMOS pipe shown in Figure 1; 105 of said contact holes are that the fixing length of side is 0.5 micron a square, and the length of side of this contact hole 105 all adopts the minimum contact hole width of stipulating in the manufacture craft usually.
But find in actual the use; Often need lower conducting resistance and the current density of Geng Gao in the design of power device; The dead resistance that prior art adopts standard-sized contact hole to produce is bigger, causes the current density of power device lower, can't satisfy the demand under some application scenarios.
For this reason, be necessary to provide a kind of new technical scheme to solve the problems referred to above.
[summary of the invention]
The purpose of this part is to summarize some aspects of embodiments of the invention and briefly introduces some preferred embodiments.In this part and the application's specification digest and denomination of invention, may do a little simplification or omit avoiding the making purpose of this part, specification digest and denomination of invention fuzzy, and this simplification or omit and can not be used to limit scope of the present invention.
One object of the present invention is to provide a kind of semiconductor device that comprises power device, and it has less contact hole dead resistance and bigger current density.
Another object of the present invention is to provide a kind of preparation method who comprises the semiconductor device of power device, be used to prepare the said semiconductor device that comprises power device.
In order to reach the object of the invention, according to an aspect of the present invention, the embodiment of the invention provides a kind of semiconductor device that comprises power device, and said semiconductor device comprises;
Metal-oxide-semiconductor, said metal-oxide-semiconductor comprise the source electrode and the drain electrode of grid and distribution and said grid both sides, are formed with contact hole, the contact hole size in the size overgauge technology of said contact hole in said source electrode and the drain electrode.
Further, an earth-free included contact hole below comprises that also the degree of depth of said well area is greater than the degree of depth of the diffusion region of said source electrode and drain electrode corresponding to the well area of the diffusion region type of said source electrode and drain electrode in said source electrode and the drain electrode.
Further, the contact hole of said source electrode and drain electrode is the rectangle contact hole, and the limit of said rectangle contact hole is parallel with the limit of said grid.
Further, said metal-oxide-semiconductor also comprises the lining body, is formed with contact hole on the said lining body, the contact hole size in the size overgauge technology of the contact hole of said lining body.
Further, the wide minimum contact hole width that equals in the standard technology of said rectangle contact hole, the minimum contact hole width in standard technology of growing up of said rectangle contact hole.
Further, said grid comprises some parallel rectangle grids arranged side by side, and the spacing between said some the parallel rectangle grids arranged side by side equates.
Further; Said grid comprises some parallel rectangle grids arranged side by side; Spacing equals first spacing under the drain electrode between said some the parallel rectangle grids arranged side by side; Spacing equals second spacing under the source electrode between said some the parallel rectangle grids arranged side by side, and said first spacing is greater than second spacing.
According to a further aspect in the invention, the embodiment of the invention also provides a kind of preparation method who comprises the semiconductor device of power device, and said method comprises: semi-conductive substrate is provided; On said Semiconductor substrate, form the source electrode and the drain electrode of grid and distribution and said grid both sides; Form the contact hole of the contact hole size in the size overgauge technology in said source electrode and drain electrode.
Further, said method also comprises:
When forming said source electrode with drain electrode; Also in said source electrode and drain electrode below the earth-free included contact hole; Formation is corresponding to the well area of the diffusion region type of said source electrode and drain electrode, and the degree of depth of said well area is greater than the degree of depth of the diffusion region of said source electrode and drain electrode.
Further, in said source electrode and drain electrode, form the rectangle contact hole, the wide minimum contact hole width that is equal to or greater than in the standard technology of said rectangle contact hole, the minimum contact hole width in standard technology of growing up of said rectangle contact hole.
Compared with prior art, semiconductor device that comprises power device among the present invention and preparation method thereof has the following advantages:
Through the power device in the semiconductor device that comprises power device being provided the contact hole of the contact hole of size overgauge technology, make the dead resistance of the contact hole in this power device obviously reduce, thereby improved the current density of power device.
[description of drawings]
In conjunction with reference to accompanying drawing and ensuing detailed description, the present invention will be more readily understood, the structure member that wherein same Reference numeral is corresponding same, wherein:
Fig. 1 is the domain sketch map of a kind of NMOS pipe of the prior art;
Fig. 2 is the semiconductor device that the comprises power device domain sketch map in one embodiment among the present invention.
Fig. 3 is the semiconductor device that the comprises power device generalized section in one embodiment among the present invention;
Fig. 4 A is the semiconductor device that the comprises power device domain sketch map in another embodiment among the present invention;
Fig. 4 B is the generalized section of the semiconductor device that comprises power device in Fig. 4 A illustrated embodiment among the present invention;
Fig. 5 is preparation method's method flow diagram in one embodiment of the semiconductor device that comprises power device among the present invention.
[embodiment]
Detailed description of the present invention is mainly come the running of direct or indirect simulation technical scheme of the present invention through program, step, logical block, process or other symbolistic descriptions.Be the thorough the present invention that understands, in ensuing description, stated a lot of specific detail.And when not having these specific detail, the present invention then possibly still can realize.Affiliated those of skill in the art use these descriptions here and state that the others skilled in the art in affiliated field effectively introduce their work essence.In other words, be the object of the invention of avoiding confusion, owing to method, program, composition and the circuit known are readily appreciated that, so they are not described in detail.
Alleged here " embodiment " or " embodiment " are meant special characteristic, structure or the characteristic that can be contained at least one implementation of the present invention.Different in this manual local " in one embodiment " that occur not are all to refer to same embodiment, neither be independent or optionally mutually exclusive with other embodiment embodiment.In addition, represent that the sequence of modules and revocable in method, flow chart or the functional block diagram of one or more embodiment refers to any particular order, also be not construed as limiting the invention.
The emphasis and the bright spot of semiconductor device that comprises power device among the present invention and preparation method thereof are: the contact hole that the power device in the semiconductor device is provided the contact hole size in the size overgauge technology; The dead resistance that makes contact hole in this power device produce diminishes, thereby improves the current density in this power device.
For the ease of description, the power device among this paper is all described with the NMOS pipe as a specific example, for the embodiment of PMOS pipe as power device, is that those skilled in the art are prone to the part that full of beard reaches, and gives unnecessary details no longer one by one.
Please refer to Fig. 2, it shows the domain sketch map of the semiconductor device that comprises power device in an embodiment 200 among the present invention.The said semiconductor device 200 that comprises power device comprises the NMOS pipe.Said NMOS pipe comprises three electrodes, is respectively source electrode (source), drain electrode (drain) and grid (gate).In the diagram domain, grid 201 is at source electrode 202 and drain between 203, is used for source electrode 202 and drain electrode were opened in 203 minutes.The layout area of said grid 201 comprises the rectangle grid of some parallel vertical bar types arranged side by side, and this rectangle grid is generally polysilicon layer.Said source electrode 202 and drain electrode 203 are generally the N of the both sides that are distributed in said grid 201
+Diffusion layer is positioned at the lower floor of said grid 201 place layers, and the corresponding metal level that the contact hole 205 through formed thereon is connected in integrated circuit surface is with mutual conducting.Said NMOS pipe also comprises by P
+The P type lining body 204 that the diffusion region forms.
Wherein, contact hole 205 is the rectangle contact hole, the contact hole size in its size overgauge technology.The long limit of this rectangle contact hole and the limit of said grid 201 are parallel to each other.Suppose that the said semiconductor device 200 that comprises power device adopts the integrated circuit technology preparation of 0.5 micron of minimum lithographic precision; The minimum contact hole of its regulation is of a size of 0.5 micron; The wide of then said rectangle contact hole 205 can be for 0.5 micron or greater than 0.5; And its length can be 5 microns such as its length greater than 0.5 micron; Can be 0.6 micron or 1 micron such as the wide of, said rectangle contact hole 205 again, and length can be 4 microns or the like.Certainly, the contact hole 206 for being formed on the P type lining body 204 also can adopt the rectangle contact hole.And, can still adopt the contact hole size that provides in the standard technology for other non-power device on this semiconductor device, such as the square contact hole that adopts 0.5 micron of 0.5 micron *.
In sum; Present embodiment provides the contact hole of the contact hole size in the size overgauge technology to the power device in the said semiconductor device; The dead resistance that makes contact hole in this power device produce diminishes, thereby improves the current density in this power device.Specifically; Rectangle contact hole in the present embodiment is not a square contact hole of the prior art; But be equivalent to the strip contact hole that forms after a plurality of square contact hole parallel connections; Obviously on identical chip area, greatly increase the area of contact hole, thereby reduced the dead resistance that contact hole produces.In addition, this rectangle contact hole also provides the longitudinal current path along long side direction.In the actual fabrication technology; General power device adopts the double layer of metal wiring; Electric current is provided by the ground floor metal usually longitudinally; The longitudinal current path that rectangle contact hole in the present embodiment provides is identical with ground floor metal routing direction, has been equivalent to provide another parallelly connected current path, thereby has increased the current density of power device.Because the thickness of the depth ratio ground floor metal of contact hole is big in most of technologies, so the current density that increases is appreciable.
But find according to experiment, simply adopt the large scale contact hole may cause the diffusion region of some metal piercing source electrode or drain electrode, thereby cause short circuit.Please refer to shown in Figure 3, large scale contact hole 302 possibly penetrate source electrode or the drain electrode N
+Diffusion region 304 and touching on the P type substrate 306.Can cause dissimilar N like this
+Diffusion region and the short circuit of P type substrate.For this reason, the embodiment of the invention also provides more preferably embodiment.
Please combine with reference to figure 4A and Fig. 4 B, its show respectively the semiconductor device that comprises power device among the present invention in an embodiment 400 the domain sketch map and along the generalized section of BB direction.The said semiconductor device 400 that comprises power device comprises the NMOS pipe.Said NMOS pipe comprises three electrodes, is respectively source electrode (source), drain electrode (drain) and grid (gate).In the diagram domain, grid 401 is at source electrode 402 and drain between 403, is used for source electrode 402 and drain electrode were opened in 403 minutes.The layout area of said grid 401 comprises the rectangle grid of some parallel vertical bar types arranged side by side, is generally polysilicon layer.Said source electrode 402 and drain electrode 403 are generally the N of the both sides that are distributed in said grid 401
+The diffusion region is positioned at the lower floor of said grid 401 place layers, and the corresponding metal level that is connected in integrated circuit surface through contact hole 405 that is formed at said source electrode 402 tops and the contact hole 406 that is formed at said drain electrode 403 tops respectively is with mutual conducting.Said NMOS pipe also comprises by P
+The P type lining body 404 that the diffusion region forms.
Wherein, the contact hole 405 in the said source electrode 402 is the rectangle contact hole with the contact hole 406 in the said drain electrode 403, the contact hole size in its size overgauge technology.The long limit of this rectangle contact hole and the limit of said grid 201 are parallel to each other.Suppose that the semiconductor device 200 that comprises power device adopts the integrated circuit technology of 0.5 micron of minimum lithographic precision to prepare; The minimum contact hole of its regulation is of a size of 0.5 micron; Then said rectangle contact hole 205 wide is equal to or greater than minimum contact hole size; And its length can be 5 microns such as its length greater than 0.5 micron; Can be 0.6 micron or 1 micron such as the wide of, said rectangle contact hole 205 again, and length can be 4 microns or the like.Certainly, the contact hole 407 for being formed on the P type lining body 404 also can adopt the rectangle contact hole.And, can still adopt the contact hole size that provides in the standard technology for other non-power device on this semiconductor device, such as the square contact hole of 0.5 micron of 0.5 micron *.
Different with previous embodiment, contact hole 406 belows in the drain electrode 403 of the NMOS pipe that present embodiment provides also are formed with N trap 408.The degree of depth of this N trap 408 is greater than the degree of depth of the N+ diffusion region of drain electrode 403.Because most of power NMOS pipes, its source electrode all is a ground connection with the lining body.Therefore in these source electrodes and the directly grounded application of lining body, can directly the contact hole of source electrode with the lining tagma be designed to like the described rectangle contact hole among Fig. 4.Even penetration phenomenon as shown in Figure 3 occurred, because generally, P type substrate also is a ground connection, thus just cause two all the partial short circuit of ground connection can not cause other problem to together.But, for drain electrode 403, need usually to connect other current potentials, generally not earthing potential.In order still to adopt the rectangle contact hole and to prevent the generation of penetration phenomenon, can below rectangle contact hole 406, form a N trap 408.Because N trap 408 is deep, so the general generation penetration phenomenon as shown in Figure 2 that is difficult for.
In sum; Present embodiment provides the contact hole of the contact hole size in the size overgauge technology to the power device in the said semiconductor device; The dead resistance that makes contact hole in this power device produce diminishes, thereby improves the current density in this power device.And, below the included contact hole of earth-free drain electrode, also comprise N corresponding to said drain electrode
+The N well area of diffusion region, the degree of depth of said N well area is greater than the N of said drain electrode
+The degree of depth of diffusion region.Easy full of beard reaches; No matter be NMOS pipe or PMOS pipe; Only need in the source electrode of metal-oxide-semiconductor and drain electrode below the earth-free included contact hole; Formation is corresponding to the well area of the diffusion region type of said source electrode and drain electrode, and the degree of depth of said well area just can reach the purpose that this prevents that penetration phenomenon from taking place greater than the degree of depth of the diffusion region of said source electrode and drain electrode.
Need to prove; Grid shown in the previous embodiment comprises some parallel rectangle grids arranged side by side; Between between said some the parallel rectangle grids arranged side by side or include source electrode and drain electrode, usually among the embodiment, the spacing between said some the parallel rectangle grids arranged side by side equates.But under some embodiment; In order to reach electrostatic protection requirement preferably; Need bigger drain electrode spacing; That is to say, need the zone of drain electrode 403 bigger, make the contact hole 406 in the drain electrode 403 bigger to the distance (spacing promptly drains) of any conducting channel (being the grid below) than the zone of source electrode 402.At this moment; Spacings equal first space D 1 under the drain electrode 403 between some parallel rectangle grids 401 arranged side by side; Spacings equal second space D 2 under the source electrode 402 between some parallel rectangle grids 401 arranged side by side, and said first space D 1 is greater than second space D 2.
The embodiment of the invention also provides a kind of preparation method who comprises the semiconductor device of power device simultaneously.Please refer to Fig. 5, it shows the method flow diagram of preparation method in an embodiment 500 of the semiconductor device that comprises power device among the present invention.The said preparation method 500 who comprises the semiconductor device of power device comprises;
This semiconductor device that comprises power device can adopt planar technique and self-registered technology preparation.At first semi-conductive substrate can be provided, on said Semiconductor substrate, pass through source electrode and the drain electrode that steps such as photoetching, the injection of burn into ion form grid and distribution and said grid both sides then.Is example with the NMOS pipe as power device, and said grid can be the rectangle grid of some parallel distributions arranged side by side.Between between the adjacent rectangle grid or be formed with source region and drain region.Certainly, in various embodiment, said grid also can be other shape
In order to prevent the generation of penetration phenomenon; When forming said source electrode with drain electrode; Can also be below an earth-free included contact hole position in the source electrode of metal-oxide-semiconductor and the drain electrode; Formation is corresponding to the well area of the diffusion region type of said source electrode and drain electrode, and the degree of depth of said well area is greater than the degree of depth of the diffusion region of said source electrode and drain electrode.Such as, below the included contact hole of the earth-free drain electrode of NMOS pipe, also form N corresponding to said drain electrode
+The N well area of diffusion region, the degree of depth of said N well area is greater than the N of said drain electrode
+The degree of depth of diffusion region.
Then, can in source region and drain region, form the contact hole of the contact hole size in the size overgauge technology.Such as can in source region and drain region, forming the rectangle contact hole, the wide of this rectangle contact hole can be more than or equal to the minimum contact hole width in the standard technology, the minimum contact hole width of the length of this rectangle contact hole in can overgauge technology.The long limit of this rectangle contact hole can parallel with the limit of grid.The formation of this rectangle contact hole can be adopted one or more in the modes such as growth, photoetching, filling, deposition and sputter in the standard technology.Contact hole for the lining body in the power device also can adopt the rectangle contact hole; Other device for non-power device in this semiconductor device can still adopt the square contact hole in the standard technology, and the length of side of this square contact hole is generally equal to the minimum contact hole width in the standard technology.
In sum; The preparation method that present embodiment provides provides the contact hole of the contact hole size in the size overgauge technology to the power device in the said semiconductor device; The dead resistance that makes contact hole in this power device produce diminishes, thereby improves the current density in this power device.And; Also in the source electrode of metal-oxide-semiconductor and drain electrode below the earth-free included contact hole; Formation is corresponding to the well area of the diffusion region type of said source electrode and drain electrode; The degree of depth of said well area is greater than the degree of depth of the diffusion region of said source electrode and drain electrode, to reach the purpose that prevents that penetration phenomenon from taking place.
Above-mentioned explanation has fully disclosed embodiment of the present invention.It is pointed out that any change that technical staff's specific embodiments of the invention of being familiar with this field is done does not all break away from the scope of claims of the present invention.Correspondingly, the scope of claim of the present invention also is not limited only to said embodiment.
Claims (10)
1. semiconductor device that comprises power device is characterized in that it comprises:
Metal-oxide-semiconductor, said metal-oxide-semiconductor comprise the source electrode and the drain electrode of grid and distribution and said grid both sides, are formed with contact hole, the contact hole size in the size overgauge technology of said contact hole in said source electrode and the drain electrode.
2. semiconductor device according to claim 1; It is characterized in that; An earth-free included contact hole below in said source electrode and the drain electrode; Comprise that also the degree of depth of said well area is greater than the degree of depth of the diffusion region of said source electrode and drain electrode corresponding to the well area of the diffusion region type of said source electrode and drain electrode.
3. semiconductor device according to claim 1 and 2 is characterized in that, the contact hole of said source electrode and drain electrode is the rectangle contact hole, and the long limit of said rectangle contact hole is parallel with the limit of said grid.
4. semiconductor device according to claim 3 is characterized in that said metal-oxide-semiconductor also comprises the lining body, is formed with contact hole on the said lining body, the contact hole size in the size overgauge technology of the contact hole of said lining body.
5. semiconductor device according to claim 3 is characterized in that, the wide minimum contact hole width that is equal to or greater than in the standard technology of said rectangle contact hole, the minimum contact hole width in standard technology of growing up of said rectangle contact hole.
6. semiconductor device according to claim 3 is characterized in that, said grid comprises some parallel rectangle grids arranged side by side, and the spacing between said some the parallel rectangle grids arranged side by side equates.
7. semiconductor device according to claim 3; It is characterized in that; Said grid comprises some parallel rectangle grids arranged side by side; Spacing equals first spacing under the drain electrode between said some the parallel rectangle grids arranged side by side, and spacing equals second spacing under the source electrode between said some the parallel rectangle grids arranged side by side, and said first spacing is greater than second spacing.
8. preparation method who comprises the semiconductor device of power device is characterized in that it comprises:
Semi-conductive substrate is provided;
On said Semiconductor substrate, form the source electrode and the drain electrode of grid and distribution and said grid both sides;
Form the contact hole of the contact hole size in the size overgauge technology in said source electrode and drain electrode.
9. the preparation method who comprises the semiconductor device of power device according to claim 8 is characterized in that, said method also comprises:
When forming said source electrode with drain electrode; Also in said source electrode and drain electrode below the earth-free included contact hole; Formation is corresponding to the well area of the diffusion region type of said source electrode and drain electrode, and the degree of depth of said well area is greater than the degree of depth of the diffusion region of said source electrode and drain electrode.
10. according to Claim 8 or the 9 described preparation methods that comprise the semiconductor device of power device, it is characterized in that the said contact hole that in said source electrode and drain electrode, forms the contact hole size in the size overgauge technology specifically comprises;
In said source electrode and drain electrode, form the rectangle contact hole, the wide minimum contact hole width that is equal to or greater than in the standard technology of said rectangle contact hole, the minimum contact hole width in standard technology of growing up of said rectangle contact hole.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108122267A (en) * | 2016-11-30 | 2018-06-05 | 中国科学院微电子研究所 | Filling method and device for redundant metal |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1159250A (en) * | 1995-07-11 | 1997-09-10 | 爱特梅尔股份有限公司 | Integrated circuit contacts with secured stringers |
| CN1189694A (en) * | 1996-12-20 | 1998-08-05 | 日本电气株式会社 | Semiconductor device having N mos and P mos transmistors on common substrate |
| CN101814501A (en) * | 2009-02-23 | 2010-08-25 | 精工电子有限公司 | Semiconductor device |
| CN202423295U (en) * | 2011-12-09 | 2012-09-05 | 无锡中星微电子有限公司 | Integrated circuit chip |
-
2011
- 2011-12-09 CN CN201110409281.2A patent/CN102446961B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1159250A (en) * | 1995-07-11 | 1997-09-10 | 爱特梅尔股份有限公司 | Integrated circuit contacts with secured stringers |
| CN1189694A (en) * | 1996-12-20 | 1998-08-05 | 日本电气株式会社 | Semiconductor device having N mos and P mos transmistors on common substrate |
| CN101814501A (en) * | 2009-02-23 | 2010-08-25 | 精工电子有限公司 | Semiconductor device |
| CN202423295U (en) * | 2011-12-09 | 2012-09-05 | 无锡中星微电子有限公司 | Integrated circuit chip |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108122267A (en) * | 2016-11-30 | 2018-06-05 | 中国科学院微电子研究所 | Filling method and device for redundant metal |
| CN108122267B (en) * | 2016-11-30 | 2021-05-11 | 中国科学院微电子研究所 | Filling method and device for redundant metal |
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| CN102446961B (en) | 2014-05-28 |
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