JP2003203852A - アライメントマーク構造およびその製造方法、アライメントマーク検出方法 - Google Patents

アライメントマーク構造およびその製造方法、アライメントマーク検出方法

Info

Publication number
JP2003203852A
JP2003203852A JP2002002280A JP2002002280A JP2003203852A JP 2003203852 A JP2003203852 A JP 2003203852A JP 2002002280 A JP2002002280 A JP 2002002280A JP 2002002280 A JP2002002280 A JP 2002002280A JP 2003203852 A JP2003203852 A JP 2003203852A
Authority
JP
Japan
Prior art keywords
alignment mark
pattern
underlayer
mark structure
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002002280A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003203852A5 (https=
Inventor
Tetsuya Yamada
哲也 山田
Atsushi Ueno
敦史 上野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2002002280A priority Critical patent/JP2003203852A/ja
Priority to US10/202,656 priority patent/US20030127751A1/en
Publication of JP2003203852A publication Critical patent/JP2003203852A/ja
Publication of JP2003203852A5 publication Critical patent/JP2003203852A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP2002002280A 2002-01-09 2002-01-09 アライメントマーク構造およびその製造方法、アライメントマーク検出方法 Pending JP2003203852A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2002002280A JP2003203852A (ja) 2002-01-09 2002-01-09 アライメントマーク構造およびその製造方法、アライメントマーク検出方法
US10/202,656 US20030127751A1 (en) 2002-01-09 2002-07-25 Alignment mark structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002002280A JP2003203852A (ja) 2002-01-09 2002-01-09 アライメントマーク構造およびその製造方法、アライメントマーク検出方法

Publications (2)

Publication Number Publication Date
JP2003203852A true JP2003203852A (ja) 2003-07-18
JP2003203852A5 JP2003203852A5 (https=) 2005-08-04

Family

ID=19190721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002002280A Pending JP2003203852A (ja) 2002-01-09 2002-01-09 アライメントマーク構造およびその製造方法、アライメントマーク検出方法

Country Status (2)

Country Link
US (1) US20030127751A1 (https=)
JP (1) JP2003203852A (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008503897A (ja) * 2004-06-23 2008-02-07 インテル コーポレイション 位置合わせ処理プロセスの改良された統合を提供する細長い構造物
WO2008066173A1 (fr) * 2006-12-01 2008-06-05 Tokyo Electron Limited Film de carbone amorphe, dispositif semi-conducteur, procédé de formation de film, appareil de formation de film et support de stockage
JP2009170899A (ja) * 2007-12-27 2009-07-30 Asml Netherlands Bv 基板上にアライメントマークを作成する方法および基板

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100519252B1 (ko) * 2003-11-24 2005-10-06 삼성전자주식회사 오버레이 마크, 오버레이 마크 형성방법 및 오버레이측정방법
US7449790B2 (en) * 2004-08-26 2008-11-11 Hitachi Global Storage Technologies, Inc. Methods and systems of enhancing stepper alignment signals and metrology alignment target signals
US8283792B1 (en) 2004-08-26 2012-10-09 Hitachi Global Storage Technologies, Netherlands B.V. Methods and systems for forming an alignment mark with optically mismatched alignment mark stack materials
US20130321719A1 (en) * 2011-02-22 2013-12-05 Sharp Kabushiki Kaisha Electronic device and method for manufacturing same
TWI603216B (zh) * 2012-11-21 2017-10-21 克萊譚克公司 處理相容分段目標及設計方法
JP2014216377A (ja) * 2013-04-23 2014-11-17 イビデン株式会社 電子部品とその製造方法及び多層プリント配線板の製造方法
KR20160015094A (ko) 2014-07-30 2016-02-12 삼성전자주식회사 오버레이 마크, 오버레이 마크를 형성하는 방법 및 오버레이 마크를 이용하여 반도체 소자를 제조하는 방법
US10461037B2 (en) * 2017-10-30 2019-10-29 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming semiconductor device structure with overlay grating
US11694968B2 (en) 2020-11-13 2023-07-04 Samsung Electronics Co., Ltd Three dimensional integrated semiconductor architecture having alignment marks provided in a carrier substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008503897A (ja) * 2004-06-23 2008-02-07 インテル コーポレイション 位置合わせ処理プロセスの改良された統合を提供する細長い構造物
WO2008066173A1 (fr) * 2006-12-01 2008-06-05 Tokyo Electron Limited Film de carbone amorphe, dispositif semi-conducteur, procédé de formation de film, appareil de formation de film et support de stockage
JP2008141009A (ja) * 2006-12-01 2008-06-19 Tokyo Electron Ltd アモルファスカーボン膜、半導体装置、成膜方法、成膜装置及び記憶媒体
JP2009170899A (ja) * 2007-12-27 2009-07-30 Asml Netherlands Bv 基板上にアライメントマークを作成する方法および基板

Also Published As

Publication number Publication date
US20030127751A1 (en) 2003-07-10

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