JP2003198369A - A/d converter and signal processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an A/D converter in which a temporal margin can be provided between A/D conversions without increasing the burden on a CPU or occupying a bus. <P>SOLUTION: The A/D converter 32 comprises an A/D converter 34 performing A/D conversion, a timer 35 performing count operation and outputting a count end signal when a specified count is reached, and an A/D conversion control circuit 33 receiving the count end signal from the timer 35 and delivering an A/D conversion start command to the A/D converter 34. The A/D converter 32 has a function for making a decision whether A/D conversions to be performed are left or not upon ending A/D conversion by the A/D converter 34 and restarting count operation of the timer 35 if A/D conversions to be performed are left. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D conversion device and a signal processing system, and more particularly, it is possible to provide a time margin between A / D conversion processing and A / D conversion processing. The present invention relates to an A / D conversion device and a signal processing system.

[0002]

2. Description of the Related Art Generally, A / D conversion includes repeat conversion in which analog signals of the same channel are repeatedly converted into digital signals, and scanning in which analog signals of different channels are converted into digital signals for each channel. There is one called conversion or single conversion in which an analog signal of one channel is converted into a digital signal only once.

FIG. 6 is a block diagram schematically showing a main part of a signal processing system adopting a conventional A / D conversion method (repeat conversion). The signal processing system is a CPU
1 and an A / D conversion device 2 including an A / D conversion control circuit 3 and an A / D converter 4. Also,
The A / D conversion control circuit 3 includes a storage unit 3a for temporarily storing the digital signal converted by the A / D converter 4.
Is equipped with.

CPU 1 sends A / D conversion control circuit 3 A / D
The number of conversions is designated and the A / D conversion control circuit 3 is instructed to start A / D conversion control. Also, A
Upon receiving the instruction from the CPU 1, the / D conversion control circuit 3 instructs the A / D converter 4 to start A / D conversion activation. When the A / D converter 4 receives the instruction from the A / D conversion control circuit 3, the input analog signal is converted into a digital signal and the conversion result is converted into an A / D signal.
It is output to the conversion control circuit 3.

Next, A / in the signal processing system
The operation procedure of the D conversion process will be described based on the timing chart shown in FIG. First of all, CPU1 is A / D
To conversion control circuit 3 to specify the A / D conversion times (n _a times) (a-), followed by an instruction to start A / D conversion control (a-).

When the A / D conversion control circuit 3 receives the instruction from the CPU 1, the A / D converter 4 is instructed to start the A / D conversion activation (a-), and the A / D converter 4 receives the instruction. When receiving the instruction, the input analog signal is converted into a digital signal, and the conversion result is output to the A / D conversion control circuit 3 (a-).

[0007] A / D conversion control circuit 3 obtains a conversion result output from the A / D converter 4, together hold the result obtained to the storage unit 3a, n from the A / D converter 4 _a
If it is determined whether or not the conversion results for the batch have been acquired, and if it is determined that the conversion results for the n _a cycles have been acquired, A is sent to the CPU 1.
/ D conversion end notification (interruption) is performed (a-). On the other hand, if it is determined that the conversion results for n _a times have not been acquired, the A / D converter 4 is again instructed to start A / D conversion activation (a−). When the CPU 1 receives the A / D conversion end notification from the A / D conversion control circuit 3, the A / D conversion
The conversion result stored in the storage unit 3a of the conversion control circuit 3 is read, and a predetermined process is performed using the read conversion result.

FIG. 8 is a block diagram schematically showing a main part of a signal processing system adopting a conventional A / D conversion method (scan conversion). The signal processing system is a CPU
11, an A / D conversion control circuit 13, an A / D converter 14,
And different analog signals s ₁ ~s _m channels are configured to include an A / D converter 12 having an analog input selection circuit 15 to be input was. Further, the A / D conversion control circuit 13 is equipped with a storage unit 13a for temporarily storing the digital signal converted by the A / D converter 14.

[0009] is input to the analog input selection circuit 15, the analog signals of different channels s ₁ ~s _m
Any of the signals is selected by the analog input selection circuit 15, and the selected analog signal is given to the A / D converter 14. For example, the analog signal s ₁ ~s _m different channel, A / D for each channel from the analog signal s ₁ to the analog signal s _m
As you given to the converter 14, so that the analog signal s ₁ ~s _m by the A / D converter 14 is gradually converted into continuous digital signal.

CPU 11 sends A / D conversion control circuit 13 A
The number of A / D conversions and the channel are designated, and the A / D conversion control circuit 13 is instructed to start A / D conversion control. Further, the A / D conversion control circuit 13 is a CPU
When receiving the instruction from 11, the A / D converter 14 is instructed to start the A / D conversion activation. When the A / D converter 14 receives the instruction from the A / D conversion control circuit 13, it converts the input analog signal into a digital signal, and the conversion result is converted into the A / D conversion control circuit 13.
Is output to.

Next, A / in the signal processing system
The operation procedure of the D conversion process will be described based on the timing chart shown in FIG. First of all, the CPU 11
The A / D conversion number (n _b times) and the channel i are designated to the D conversion control circuit 13 (b−), and then the start of A / D conversion control is instructed (b−).

When the A / D conversion control circuit 13 receives the instruction from the CPU 11, it instructs the analog input selection circuit 15 to output the analog signal s _i to the A / D converter 14, and (b- ), A to the A / D converter 14
When an instruction to start A / D conversion is given (b-), and the A / D converter 14 receives the instruction, the input analog signal is converted into a digital signal, and the conversion result is sent to the A / D conversion control circuit 13. Output (b-).

The A / D conversion control circuit 13 includes an A / D converter 1
When the conversion result output from 4 is acquired, the acquired conversion result is stored in the storage unit 13a and the A / D converter 14
From n _b conversion results are acquired,
If it is determined that the _b conversion results have been acquired, the CPU 11
To the A / D conversion end notification (interruption) (b)
-). On the other hand, if it is determined that the conversion result for n _b times has not been acquired, the analog input selection circuit 15
The analog signal s _i (i ← i + 1) is instructed to be output to the A / D converter 14 (b−), and the A / D converter 14 is instructed to start the A / D conversion activation (b−). .
However, when i becomes larger than m as a result of the above calculation, i is set to 1. The CPU 11 is an A / D conversion control circuit 13
When A / D conversion end notification is received from
The conversion result stored in the storage unit 13a of the D conversion control circuit 13 is read, and a predetermined process is performed using the read conversion result.

As described above, according to the signal processing system shown in FIG. 6, the analog signal of the same channel can be repeatedly converted into a digital signal (repeat conversion), and the signal processing system shown in FIG. According to
It is possible to convert analog signals of different channels into digital signals for each channel (scan conversion).

However, in any of the signal processing systems shown in FIGS. 6 and 8, as apparent from the timing charts shown in FIGS. 7 and 9, the A / D conversion processing and the A / D conversion processing are performed. Since there is almost no time margin between them (a-, b-), the A / D conversion processing is continuously performed in a short time, and the desired result of the A / D conversion processing cannot be obtained. There was a problem. This is because, for example, there is a case where it is desired to perform the A / D conversion processing a plurality of times within a certain long time and acquire the average value thereof.

[0016]

As a method for solving the above problems, there is a method of activating single conversion while monitoring a timer. FIG. 10 shows a signal processing system for realizing the single conversion.

The signal processing system shown in FIG. 10 is a CPU
21, A / D conversion control circuit 23 and A / D converter 24
And an A / D conversion device 22 including a CPU, a timer 25, a CPU 21, an A / D conversion control circuit 23,
The timer 25 is connected via a bus 26. Further, the A / D conversion control circuit 23 is equipped with a storage unit 23a for temporarily storing the digital signal converted by the A / D converter 24.

The CPU 21 instructs the A / D conversion control circuit 23 to start the A / D conversion control at a constant cycle T while monitoring the timer 25, and the A / D conversion control circuit 23 has the CPU 21. Upon receiving the instructions from
The A / D converter 24 is instructed to start A / D conversion activation. Upon receiving the instruction from the A / D conversion control circuit 23, the A / D converter 24 converts the input analog signal into a digital signal and outputs the conversion result to the A / D conversion control circuit 23. .

Next, A / in the signal processing system
The operation procedure of the D conversion process will be described based on the timing chart shown in FIG. First of all, CPU21
The A / D conversion control circuit 23 is instructed to start A / D conversion control (c-).

When the A / D conversion control circuit 23 receives the instruction from the CPU 21, the A / D converter 24 is instructed to start A / D conversion activation (c-), and the A / D converter 24 outputs the instruction. When receiving the instruction, the input analog signal is converted into a digital signal, and the conversion result is output to the A / D conversion control circuit 23 (c-).

The A / D conversion control circuit 23 uses the A / D converter 2
When the conversion result output from No. 4 is acquired, the acquired conversion result is stored in the storage unit 23a, and the CPU 21 is notified (interrupted) of A / D conversion end (c-
). The CPU 21 uses the A / D conversion control circuit 23
Upon receiving the notification of the D conversion end, the conversion result stored in the storage unit 23a of the A / D conversion control circuit 23 is read out and a predetermined process is performed using the read conversion result.

As described above, according to the signal processing system shown in FIG. 10, the CPU 21 instructs the A / D conversion control circuit 23 to start the A / D conversion control at a constant period T while monitoring the timer 25. Therefore, the analog signal of one channel can be converted into a digital signal at a constant period T. Therefore, a time margin can be provided between the A / D conversion processing and the A / D conversion processing.

However, the signal processing system is
It is necessary for the CPU 21 to give an instruction to start A / D conversion control every fixed period T while monitoring the timer 25, which causes a problem that the load on the CPU 21 becomes large and the bus 26 is used for A / D conversion processing. There is a problem of being occupied.

As a method for solving such a problem, as shown in FIG. 12, a DMA controller 27 is provided and the DMA controller 27 is provided with the A / D conversion control circuit 23.
There is a method of instructing to start A / D conversion control with respect to, but the problem of occupying the bus 26 remains unsolved.

The present invention has been made in view of the above problems, and does not increase the load on the CPU or occupy the bus, and the A / D conversion processing can be performed between the A / D conversion processing. It is an object of the present invention to provide an A / D conversion device and a signal processing system that can have a time margin.

[0026]

Means for Solving the Problems and Effects Thereof In order to achieve the above object, an A / D conversion device (1) according to the present invention comprises:
A / D conversion means for performing an A / D conversion process for converting an analog signal into a digital signal, and a timer means for performing a count operation and outputting a count end signal indicating the end of the count when the count up to a predetermined count value is completed And an A / D conversion control unit that receives the count end signal from the timer unit and gives an instruction to start A / D conversion to the A / D conversion unit. Then, when the A / D conversion processing by the A / D conversion means is completed, a judgment means for judging whether or not the A / D conversion processing has been performed a predetermined number of times, and the predetermined number of times by the judgment means, Receiving the judgment that the A / D conversion processing is not performed, the timer means is provided with a restart means for restarting the counting operation, and the timer means is provided with a command from the restart means. Receiving, and characterized in that to resume the counting operation.

According to the A / D converter (1), when the timer means counts up to the predetermined count value and the count end signal is output, the A / D conversion control means. Thus, an instruction to start A / D conversion is given to the A / D conversion unit, and the A / D conversion process is performed by the A / D conversion unit. That is, the A / D conversion process can be performed by starting the counting operation of the timer means.

Therefore, for example, an instruction to start the counting operation is given to the timer means from the outside (CPU or the like), and the counting operation of the timer means is started. After that, the operation is independent from the outside. 1st A
/ D conversion processing can be performed.

When the first A / D conversion process is completed, it is determined whether or not the A / D conversion process has been performed the predetermined number of times, and the A / D conversion process is performed the predetermined number of times. Not (that is, the predetermined number is set to 2 or more, and the number of times the A / D conversion process should be performed remains)
If it is determined that the timer means is restarted, the counting operation of the timer means is restarted.

Therefore, by the timer means,
When counting is performed up to the predetermined count value and the count end signal is output, the A / D conversion control unit gives an instruction to start A / D conversion to the A / D conversion unit. , A / D by the A / D conversion means
Conversion processing is performed. That is, when the predetermined number of times is set to be two or more, after the first A / D conversion process is completed, a predetermined time (at least a time required for counting up to the predetermined count value) is exceeded, and A / th
D conversion processing is performed.

Therefore, a time margin (at least the time required to count up to the predetermined count value) is provided between the first A / D conversion process and the second A / D conversion process, and A second A / D conversion process can be performed. In addition, the series of operations described above is performed by an external (for example,
Since the A / D conversion process is repeated until it is performed a predetermined number of times in an operation independent of U), the load on the CPU can be kept small and the bus connecting various hardware can be occupied. Without A / D conversion processing and A / D
The A / D conversion process can be performed a predetermined number of times with a time margin between the A / D conversion process and the D conversion process.

Further, the A / D conversion device (2) according to the present invention
In the A / D conversion device (1), a first count value storage means for storing a count value to be counted is provided, and a count value input from the outside is stored in the first count value storage means. It is configured to be written, and the timer means outputs the count end signal when the count up to the count value stored in the first count value storage means is completed.

According to the above A / D converter (2), when the timer means counts up to the count value stored in the first count value storage means,
The count end signal is output. Further, since the A / D conversion device (2) is a reference of the A / D conversion device (1), when the count end signal is output, the A / D conversion means
A / D conversion processing is performed.

That is, when the timer means counts up to the count value stored in the first count value storage means, the A / D conversion means performs A / D conversion processing. Becomes In other words, unless the count value stored in the first count value storage means is counted, the next A / D
The conversion process will not be performed.

Therefore, it is possible to provide a time required to count at least the count value stored in the first count value storage means between the A / D conversion processing and the A / D conversion processing.

Further, according to the A / D converter (2), the count value input from the outside (eg, CPU) is written in the first count value storage means. , The length between the A / D conversion processing and the A / D conversion processing can be freely set from the outside.

Further, the A / D converter according to the present invention (3)
The A / D converter (2) includes second count value storage means for storing a count value input from the outside, and the second count value storage means stores a second count value when the predetermined condition is satisfied.
The count value stored in the count value storage means of
It is characterized in that it is configured to be written in the first count value storage means.

According to the A / D conversion device (3), when the predetermined condition is satisfied, the count value stored in the second count value storage means becomes the first count value storage means. Since it is configured to be written into the second count value storage means, a count value different from the count value stored in the first count value storage means is stored in the second count value storage means. By satisfying the condition, the length between the A / D conversion processing and the A / D conversion processing can be changed.

Further, according to the A / D converter (3), the count value input from the outside (for example, CPU) is written in the second count value storage means. , The length between the A / D conversion processing and the A / D conversion processing can be freely changed from the outside.

Further, the A / D conversion device (4) according to the present invention
In the A / D converter (3), the predetermined condition includes an instruction to start the counting operation to the timer means.

According to the A / D converter (4), when the predetermined condition including the condition that the timer means is instructed to start the counting operation is satisfied,
The count value stored in the second count value storage means is configured to be written in the first count value storage means. Further, since the A / D conversion device (4) is a reference of the A / D conversion device (1), the number of times that the A / D conversion process should be performed remains after the A / D conversion process is completed. If so, the timer unit is instructed to restart the counting operation.

Therefore, if, for example, the predetermined condition is that the timer means is instructed to start the counting operation, the number of times of A / D conversion processing remains after the end of A / D conversion processing. If so, the timer means is instructed to restart the counting operation, and the second
The count value stored in the count value storage means of
It is written in the first count value storage means.

Therefore, as shown in FIG. 4 described later, for example, when it is desired to change the length between the second A / D conversion processing and the third A / D conversion processing, From the start of the timer start of to the start of the third timer start, input a new count value from the outside,
The count value may be written in the second count value storage means.

Further, the A / D converter according to the present invention (5)
In any one of the A / D converters (1) to (4), the A / D converter includes a number storage unit for storing the number of A / D conversion processes to be performed by the A / D conversion unit, and an external input. The number of times performed is configured to be written in the number of times storing means, and the predetermined number of times is the number of times stored in the number of times storing means.

According to the A / D conversion device (5), the predetermined number of times (that is, the number of times that the A / D conversion process should be performed).
Is the number of times stored in the number-of-times storage means, and the number of times input from the outside (for example, CPU) is written in the number-of-times storage means. The number of times to perform can be freely set from the outside.

Further, the A / D converter according to the present invention (6)
Is based on the conversion result by the A / D conversion means in any of the A / D conversion devices (1) to (5),
It is characterized in that it is provided with an arithmetic means for performing a predetermined arithmetic processing. Further, the A / D conversion device (7) according to the present invention
In the A / D conversion device (6), the computing means is configured to calculate the sum of a plurality of conversion results, the average value of the plurality of conversion results, the maximum value of the plurality of conversion results, and the plurality of conversion results. It is characterized in that either the minimum value or the difference between the maximum value and the minimum value of the plurality of conversion results is obtained.

According to the A / D conversion device (6) or (7), since the arithmetic means is provided, the arithmetic processing based on the conversion result by the A / D conversion means is external (for example, CPU). Since it is not necessary to do so, it is possible to reduce the load on the CPU. It should be noted that, for example, the sum of the plurality of conversion results, the average value of the plurality of conversion results, the maximum value of the plurality of conversion results, the minimum value of the plurality of conversion results, and For example, the difference between the maximum value and the minimum value of the plurality of conversion results can be given.

Further, the A / D conversion device (8) according to the present invention
In the above A / D converter (6) or (7), the arithmetic means can perform plural kinds of arithmetic processing, and based on designation from the outside, these plural kinds of arithmetic processing can be performed. It is characterized in that the type of arithmetic processing is selected from the inside and the arithmetic processing of the selected type is performed.

According to the A / D converter (8), the type of arithmetic processing can be freely selected from a plurality of types of arithmetic processing, and therefore the arithmetic result by the desired arithmetic processing can be obtained. You can

Further, the A / D conversion device (9) according to the present invention
In any one of the above A / D converters (6) to (8), a calculation result storage means for storing a calculation result by the calculation means is provided, and a plurality of conversion results are obtained by the calculation means. Of the desired value obtained by the calculation means and the processing order of the conversion processing from which the desired value is obtained among the plurality of conversion processing are the calculation result storage means. It is characterized in that it is configured to be written in.

By the way, among the values obtained by converting analog signals of different channels into digital signals for each channel, the maximum value (or minimum value) is obtained.
In some cases, not only the maximum value (or the minimum value) but also the information such as from which channel the value is obtained may be desired.

According to the A / D conversion device (9), the desired value (for example, the maximum value or the minimum value) of the plurality of conversion results is stored in the operation result storage means, so that the operation is performed. The CPU or the like can acquire the desired value by reading the data stored in the result storage means.

Further, regarding the processing order among a plurality of conversion processes for the conversion process for which the desired value is obtained,
Since it is stored in the calculation result storage unit, the CPU or the like can obtain the processing order by reading the data stored in the calculation result storage unit.

Therefore, for example, different channel ch
The maximum value of the values obtained by converting the analog signals of _{1 to} ch _m into digital signals for each channel, and the conversion processing of a plurality of m for the conversion processing for which the maximum value is obtained Since the processing order (i-th) is stored in the calculation result storage means, by reading the data stored in the calculation result storage means, the CP
It is possible for U to obtain the maximum value, and also for the order in which the maximum value was obtained (i-th), that is, the information that the maximum value was obtained from channel ch _i. it can.

Further, the A / D conversion device (1 according to the present invention
0) is the A / D conversion device (6) to (9) described above, the arithmetic means receives the judgment by the judgment means that the A / D conversion processing has been performed the predetermined number of times. It is characterized in that the predetermined arithmetic processing is performed.

According to the above A / D conversion device (10), the arithmetic means receives the judgment by the judgment means that the number of times of the A / D conversion processing does not remain, and the predetermined arithmetic processing is performed. Is supposed to do. Therefore, instead of performing the predetermined arithmetic processing every time the A / D conversion processing is completed once, it is possible to collectively perform the predetermined arithmetic processing at the end.

In addition, the A / D converter according to the present invention (1
1) In any one of the above A / D conversion devices (6) to (9), the arithmetic means is arranged to perform the A / D conversion processing by the A / D conversion means once or every plural times. The above-mentioned predetermined arithmetic processing is performed.

According to the above A / D conversion device (11), the arithmetic operation means performs the predetermined arithmetic processing every time the A / D conversion processing by the A / D conversion means is completed once or plural times. Is supposed to do.

For example, when the sum of the conversion results of 16 A / D conversion processes (8 bits / 1 time) is calculated, 16 (= 2 ⁴ ) conversions are performed as in the A / D converter (10). At least 128 (=
Although it is necessary to prepare a register for 8 × 16) bits, in the case of the A / D conversion device (11), for example, the addition process is performed every time the A / D conversion process is completed once. Since this is done, it is sufficient to prepare a register for 12 (= 8 + 4) bits, and therefore the register capacity can be reduced.

Further, the signal processing system (1) according to the present invention converts an analog signal into a digital signal A
When the counting operation is performed with the A / D conversion means for performing the A / D conversion processing and the counting up to a predetermined count value is completed,
A timer unit that outputs a count end signal indicating the end of counting, and an A / D conversion control that receives the count end signal from the timer unit and gives an instruction to start the A / D conversion to the A / D conversion unit. A signal processing system including means for determining whether or not the A / D conversion processing has been performed a predetermined number of times when the A / D conversion processing by the A / D conversion means ends. When the judgment means judges that the A / D conversion processing has not been performed the predetermined number of times, the timer means is provided with restart means for restarting the counting operation, and the timer means is provided. However, the counting operation is restarted in response to an instruction from the restarting means.

According to the signal processing system (1), when the timer means counts up to the predetermined count value and the count end signal is output,
The A / D conversion control unit gives an instruction to start the A / D conversion to the A / D conversion unit, and the A / D conversion unit performs the A / D conversion process. That is,
A / D conversion processing can be performed by starting the counting operation of the timer means.

Therefore, for example, an instruction to start the counting operation is given to the timer means from the outside (CPU or the like), and the counting operation of the timer means is started. After that, the operation is independent from the outside. 1st A
/ D conversion processing can be performed.

When the first A / D conversion process is completed, it is determined whether or not the A / D conversion process has been performed the predetermined number of times, and the A / D conversion process is performed the predetermined number of times. Not (that is, the predetermined number is set to 2 or more, and the number of times the A / D conversion process should be performed remains)
If it is determined that the timer means is restarted, the counting operation of the timer means is restarted.

Therefore, by the timer means,
When counting is performed up to the predetermined count value and the count end signal is output, the A / D conversion control unit gives an instruction to start A / D conversion to the A / D conversion unit. , A / D by the A / D conversion means
Conversion processing is performed. That is, when the predetermined number of times is set to be two or more, after the first A / D conversion process is completed, a predetermined time (at least a time required for counting up to the predetermined count value) is exceeded, and A / th
D conversion processing is performed.

Therefore, a time margin (at least the time required to count up to the predetermined count value) is provided between the first A / D conversion processing and the second A / D conversion processing, and 2 A second A / D conversion process can be performed. In addition, the series of operations described above is performed by an external (for example, CP
Since the A / D conversion process is repeated until it is performed a predetermined number of times in an operation independent of U), the load on the CPU can be kept small and the bus connecting various hardware can be occupied. Without A / D conversion processing and A / D
The A / D conversion process can be performed a predetermined number of times with a time margin between the A / D conversion process and the D conversion process.

[0066]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of an A / D converter and a signal processing system according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram schematically showing a main part of a signal processing system that employs the A / D conversion device according to the embodiment (1). In the figure, reference numeral 32 denotes an A / D conversion device, and the A / D conversion device 32 is the A / D conversion control circuit 3
3, an A / D converter 34, and a timer 35.

The A / D conversion control circuit 33 receives the count end signal from the timer 35 and gives an instruction to start the A / D conversion to the A / D converter 34.
The A / D conversion control circuit 33 includes a storage unit 3 for temporarily storing the digital signal converted by the A / D converter 34.
3a and a number memory 33b for storing the number of A / D conversion processes set by the CPU 31 are provided.

The timer 35 includes an oscillation circuit 35a, a counter 35b, a count value memory 35c for storing the count value set by the CPU 31, and a comparison circuit 3.
5d, the clock pulse from the oscillation circuit 35a is counted by the counter 35b, the count value of the counter 35b is compared with the count value stored in the count value memory 35c by the comparison circuit 35d, and these count values are compared. When they match, the count end signal is output to the A / D conversion control circuit 33.

Further, the count value of the counter 35b,
When the count value stored in the count value memory 35c matches, a reset signal is output from the comparison circuit 35d to the counter 35b, and the count value of the counter 35b is reset.

When the A / D converter 34 receives an A / D conversion start instruction from the A / D conversion control circuit 33, the A / D converter 34 converts the input analog signal into a digital signal and outputs the conversion result to A / D.
It is configured to output to the / D conversion control circuit 33.

The CPU 31 sets the number of A / D conversions in the A / D conversion control circuit 33 and the counter 3 in the timer 35.
5b is configured to set a count value to be counted, and to instruct the counter 35b to start counting clock pulses.

Next, A / in the signal processing system
The operation procedure of the D conversion process will be described based on the timing chart shown in FIG. First, the CPU 31 designates the count value ct to the timer 35 and the A / D conversion number (n ₁ ) to the A / D conversion control circuit 33 (1-
).

The timer 35 sends the count value c from the CPU 31.
When the designation of t is received, the designated count value ct is stored in the count value memory 35c, and when the A / D conversion number n ₁ is designated by the CPU 31, the count memory 33b is stored. The number of times n ₁ designated is stored.

Next, the CPU 31 instructs the timer 35 to start counting (1-), and when the timer 35 receives the instruction to start counting, it starts counting and the count value in the counter 35b and the count value. The count value ct stored in the memory 35c matches (that is,
When the counter 35b counts up to the count value ct), the count end signal is output to the A / D conversion control circuit 33 (1-).

When the A / D conversion control circuit 33 receives the count end signal from the timer 35, it instructs the A / D converter 34 to start the A / D conversion activation (1-), and the A / D converter 34 is started. Receives the instruction, the input analog signal is converted into a digital signal, and the conversion result is output to the A / D conversion control circuit 33 (1-).

The A / D conversion control circuit 33 uses the A / D converter 3
When the conversion result output from 4 is acquired, the acquired conversion result is stored in the storage unit 33a, and the A / D converter 34
To determine whether n ₁ conversion results have been acquired, and
If it is determined that _one conversion result has been acquired, the CPU 31
A / D conversion end notification (interruption) is sent to (1
-). On the other hand, if it is determined that the conversion result for n ₁ times has not been acquired, the timer 35 is instructed to start the counting operation (1-).

When the CPU 31 receives the A / D conversion end notification from the A / D conversion control circuit 33, the A / D conversion is performed thereafter.
The conversion result stored in the storage unit 33a of the conversion control circuit 33 is read, and a predetermined process is performed using the read conversion result.

According to the A / D converter of the above embodiment (1), the count value memory 35 is controlled by the timer 35.
The count value ct stored in c (that is, the CPU
When the counting up to the count value ct set by 31 is performed and the count end signal is output to the A / D conversion control circuit 33, the A / D conversion control circuit 33 causes the A / D conversion control circuit 33 to
An instruction to start A / D conversion is given to the D converter 34, and the A / D converter 34 performs A / D conversion processing. That is, the A / D conversion process can be performed by starting the counting operation of the timer 35.

Therefore, the CPU 31 merely gives an instruction to start the counting operation to the timer 35 to start the counting operation of the timer 35, and thereafter, in an operation independent of the CPU 31, the first A / D conversion is performed. Processing can be performed.

When the first A / D conversion process is completed, the number of times n ₁ stored in the number memory 33b in the A / D conversion control circuit 33 (that is, the number of times n ₁ set by the CPU 31), A When it is determined whether or not the A / D conversion process has been performed, and it is determined that the A / D conversion process has not been performed n ₁ times (that is, the number of times that the A / D conversion process should be performed remains), the timer 35, the counting operation is restarted, and the counting operation of the timer 35 is restarted.

Therefore, when the timer 35 again counts up to the count value ct and the count end signal is output, the A / D conversion control circuit 33 causes
An instruction to start the A / D conversion is given to the A / D converter 34, and the A / D converter 34 performs the A / D conversion process. That is, when the number of times n ₁ stored in the number of times memory 33b is 2 or more, after a predetermined time (at least the time required to count up to the count value ct) from the end of the first A / D conversion process, The second A / D conversion process is performed.

Therefore, there is a time margin (at least the time required to count up to the count value ct) between the first A / D conversion process and the second A / D conversion process, and the second time A / D conversion processing can be performed.
Further, since the series of operations described above is repeated independently of the CPU 31 until the A / D conversion process is performed n ₁ times, the load on the CPU 31 can be reduced and various hardware can be used. It is possible to perform the A / D conversion processing n ₁ times with a time margin between the A / D conversion processing and the A / D conversion processing without occupying the bus connecting the two.

FIG. 3 is a block diagram schematically showing a main part of a signal processing system that employs the A / D conversion device according to the embodiment (2). In the figure, reference numeral 42 denotes an A / D conversion device, and the A / D conversion device 42 is the A / D conversion control circuit 4
3, an A / D converter 44, and a timer 45.

The A / D conversion control circuit 43 receives the count end signal from the timer 45 and gives an A / D conversion start instruction to the A / D converter 44.
The A / D conversion control circuit 43 includes a storage unit 4 for temporarily storing the digital signal converted by the A / D converter 44.
3a and a number memory 43b for storing the number of A / D conversion processes set by the CPU 41 are provided.

The timer 45 includes an oscillation circuit 45a, a counter 45b, a count value memory 45c for storing the count value set by the CPU 41, and a count value stored in the count value memory 45c at a predetermined timing. Is provided with a count value memory 45d and a comparison circuit 45e, and the counter 35b counts clock pulses from the oscillation circuit 45a.
And the count value ct stored in the count value memory 45d are compared by the comparison circuit 45e. When these count values match, the count end signal is set to A /
It is configured to output to the D conversion control circuit 43.

Further, the count value of the counter 45b,
Count value c stored in the count value memory 45d
When t and t match, the comparison circuit 45e causes the counter 45b to
A reset signal is output to and the count value of the counter 45b is reset.

When the A / D converter 44 receives an A / D conversion start instruction from the A / D conversion control circuit 43, the A / D converter 44 converts the input analog signal into a digital signal, and converts the conversion result into the A / D conversion signal.
It is configured to output to the / D conversion control circuit 43.

The CPU 41 sets the number of A / D conversions in the A / D conversion control circuit 43, and the counter 4 in the timer 45.
5b is configured to set a count value to be counted, and to instruct the counter 45b to start counting clock pulses.

Next, A / in the signal processing system
The operation procedure of the D conversion process will be described based on the timing chart shown in FIG. First, the CPU 41 specifies the count value ct ₁ to the timer 45 and the A / D conversion number (n ₂ times) to the A / D conversion control circuit 43 (2-
).

The timer 45 sends the count value c from the CPU 41.
When receiving the designation of t _1, the designated count value ct ₁ is stored in the count value memory 45c, and when the A / D conversion control circuit 43 receives the designation of the A / D conversion number n ₂ from the CPU 41, Number of times n ₂ specified in the memory 43b
Memorize

Next, when the CPU 41 instructs the timer 45 to start counting (2-) and the timer 45 receives the instruction to start counting, first, the count value memory 45
The count value ct '(= ct ₁ ) stored in c is read, the read count value ct' (= ct ₁ ) is written to the count value memory 45d, then counting is started, and the count in the counter 45b is performed. Value and the count value ct (= c
When t ₁ ) matches (that is, the counter 45b counts up to the count value ct), a count end signal is output to the A / D conversion control circuit 43 (2
-).

When the A / D conversion control circuit 43 receives the count end signal from the timer 45, it instructs the A / D converter 44 to start the A / D conversion activation (2-), and the A / D converter 44. Receives the instruction, the input analog signal is converted into a digital signal, and the conversion result is output to the A / D conversion control circuit 43 (2-).

The A / D conversion control circuit 43 uses the A / D converter 4
When the conversion result output from 4 is acquired, the acquired conversion result is stored in the storage unit 43a and the A / D converter 44
From n, it is judged whether or not the conversion result for n ₂ times has been acquired, and n
If it is determined that the conversion results for _two times have been acquired, the CPU 41
A / D conversion end notification (interruption) to (2
-). When the CPU 41 receives the notification of A / D conversion end from the A / D conversion control circuit 43, the CPU 41 thereafter reads the conversion result stored in the storage unit 43 a of the A / D conversion control circuit 43, and the read conversion result. Is used to perform a predetermined process.

On the other hand, if it is determined that the conversion results for n ₂ times have not been obtained, the timer 45 is instructed to start the counting operation (2-), and when the timer 45 receives the instruction to start counting, first, , Reading the count value ct 'stored in the count value memory 45c, writing the read count value ct' into the count value memory 45d,
After that, when counting is started and the count value in the counter 45b and the count value ct stored in the count value memory 45d match (that is, the counter 45b counts up to the count value ct), A / D
A count end signal is output to the conversion control circuit 43 (2-).

According to the A / D converter of the above embodiment (2), the timer 45 allows the count value memory 45 to operate.
When the count value ct stored in d is counted and the count end signal is output to the A / D conversion control circuit 43, the A / D conversion control circuit 43 causes the A / D converter 44 to , A / D conversion start instruction is given, and A
The A / D conversion process is performed by the / D converter 44. That is, the A / D conversion process can be performed by starting the count operation of the timer 45.

Therefore, the CPU 41 only gives an instruction to start the counting operation to the timer 45 to start the counting operation of the timer 45, and thereafter, in an operation independent of the CPU 41, the first A / D conversion is performed. Processing can be performed.

When the first A / D conversion process is completed, the number of times n ₂ stored in the number memory 43b in the A / D conversion control circuit 43 (ie, the number of times n ₂ set by the CPU 41), A When it is determined whether or not the A / D conversion process is performed and it is determined that the A / D conversion process has not been performed n ₂ times (that is, the number of A / D conversion processes to be performed remains), the timer The counting operation of the timer 45 is restarted, and the counting operation of the timer 45 is restarted.

Therefore, when the timer 45 again counts up to the count value ct and the count end signal is output, the A / D conversion control circuit 43 causes
An instruction to start A / D conversion is given to the A / D converter 44, and the A / D converter 44 performs A / D conversion processing. That is, when the number of times n ₂ stored in the number-of-times memory 43b is 2 or more, after a predetermined time (at least the time required for counting up to the count value ct) from the end of the first A / D conversion process, The second A / D conversion process is performed.

Therefore, a time margin (at least the time required to count up to the count value ct) is provided between the first A / D conversion process and the second A / D conversion process, and the second time is set. A / D conversion processing can be performed.
In addition, the series of operations described above are performed independently of the CPU 41 and are repeatedly performed until the A / D conversion process is performed n ₂ times, so that the load on the CPU 41 can be suppressed to a small level and various hardware can be used. It is possible to perform the A / D conversion process n ₂ times with a time margin between the A / D conversion process and the A / D conversion process without occupying the bus connecting the _two .

When the count value is designated from the CPU 41 to the timer 45, the designated count value is written in the count value memory 45c.
When there is an instruction to start counting from the U41 or the A / D conversion control circuit 43, the count value stored in the count value memory 45c is written in the count value memory 45d.

Therefore, if the CPU 41 sets a new count value between the start of the i-th counting operation and the start of the (i + 1) -th counting operation, the (i + 1) -th counting It will count up to the newly set count value. For example, as shown in FIG. 4, after the second counting operation is started,
By the time the third counting operation is started, the CPU
When the count value ct ₂ is set by 41, the third count starts counting up to the count value ct ₂ . Thereby, the length between the A / D conversion process and the A / D conversion process can be freely changed from the outside.

In addition, in the A / D conversion device according to the above-mentioned embodiment (1) or (2), the CPU 31 (41) is the A / D converter.
When the A / D conversion end notification is received from the D conversion control circuit 33 (43), then the A / D conversion control circuit 33 (4
The conversion result stored in the storage unit 33a (43a) in 3) is read out, and predetermined processing is performed using the read-out conversion result.
In the D conversion device, a storage means 33a (4
Based on the conversion result stored in 3a), predetermined arithmetic processing is performed, and the CPU 31 (41) reads not the conversion result by the A / D converter 34 (44) but the calculation result by the arithmetic means. You may be able to. As a result, the load on the CPU 31 (41) can be further reduced. The arithmetic means need not be provided in the A / D conversion control circuit 33 (43).

As the predetermined arithmetic processing, for example, the sum of a plurality of conversion results, the average value of a plurality of conversion results, the maximum value of a plurality of conversion results, the minimum value of a plurality of conversion results, And the difference between the maximum value and the minimum value of the plurality of conversion results.

FIG. 5 shows an A / D according to another embodiment.
The A / D conversion control circuit in a converter is shown. 33 in the figure
A indicates an A / D conversion control circuit, and the A / D conversion control circuit 33A includes a storage unit 33a for temporarily storing the digital signal converted by the A / D converter 34, and a CP.
A number memory 33b for storing the A / D conversion processing number n ₁ set by U31, a calculation means 51 for obtaining an average value of conversion results for n ₁ times, and a calculation result obtained by the calculation means. The calculation result storage unit 52 is provided, and the storage unit 33a, the calculation unit 51, and the calculation result storage unit 52 are provided.
It is connected with the bus 53.

Further, when the calculation means 51 acquires the conversion results for n ₁ times, it calculates the average value of the conversion results for n ₁ times stored in the storage unit 33a and stores the calculated value in the calculation result storage unit 52. It is configured to be stored. Note that the calculation result may be stored in the storage unit 33a without providing the calculation result storage unit 52.

By the way, in the A / D converter shown in FIG. 5, since the conversion results for n ₁ times are obtained, the arithmetic processing is collectively performed at the end, so that the A / D conversion is performed once.
An 8-bit register is required to store the conversion result (for example, 8-bit data) by the conversion process.
When the number of D conversions is set to 16 (= 2 ⁴ ) times, it is necessary to prepare a register of at least 128 (= 8 × 16) bits.

However, the amount of registers to be prepared is reduced by performing the arithmetic processing periodically (for example, every time when one conversion result is obtained) instead of collectively performing the arithmetic processing at the end. be able to. For example,
If addition processing is performed each time one conversion result is acquired, a register that accumulates operation results, that is, 1
It is only necessary to prepare 2 (= 8 + 4) bits.

In addition, the A / D conversion device according to another embodiment is configured to be capable of performing a plurality of types of arithmetic processing, and the plurality of types of arithmetic processing are performed based on the designation from the CPU. It may be possible to select the arithmetic processing from among the above. As the timing to be specified, it is desirable to initialize the count value and the number of A / D conversions.

Further, in the A / D conversion device according to the above-mentioned embodiment (1) or (2), the CPU 31 (41) is used to control the A / D converter.
Although it is possible to set the number of D conversions,
In the A / D conversion device according to another embodiment, the number of A / D conversions may be fixed so that the load on the CPU 31 (41) does not increase.

Further, in the A / D converter according to the above-mentioned embodiment (1) or (2), only the repeat conversion for repeatedly converting the analog signal of the same channel into the digital signal is explained, but the different channel is used. The scan conversion in which the analog signal of is converted into a digital signal for each channel can be realized in the same manner as described above. For example, the maximum value (or the minimum value) of a plurality of conversion results is calculated, By obtaining information such as how many times the calculated maximum value (or minimum value) is the conversion result of the A / D conversion processing, the maximum value (or the minimum value) can be obtained from which channel. Information such as whether or not there is also can be obtained.

Further, here, the A / D conversion control circuit 33
(43), A / D converter 34 (44), and timer 35
(45) and an A / D conversion device 32 (4
Although only the signal processing system adopting 2) has been described, in the signal processing system according to another embodiment,
The A / D converter has at least an A / D converter, and
The / D conversion control circuit and the timer may be separate from the A / D conversion device.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing a main part of a signal processing system that employs an A / D conversion device according to an embodiment (1) of the present invention.

FIG. 2 is an A / D in the signal processing system shown in FIG.
7 is a timing chart showing an operation procedure of conversion processing.

FIG. 3 is a block diagram schematically showing a main part of a signal processing system that employs an A / D conversion device according to an embodiment (2).

4 is an A / D in the signal processing system shown in FIG.
7 is a timing chart showing an operation procedure of conversion processing.

FIG. 5 is a block diagram schematically showing a main part of an A / D conversion control circuit in an A / D conversion device according to another embodiment.

FIG. 6 is a block diagram schematically showing a main part of a signal processing system that employs a conventional A / D conversion method (repeat conversion).

7 is an A / D in the signal processing system shown in FIG.
7 is a timing chart showing an operation procedure of conversion processing.

FIG. 8 is a block diagram schematically showing a main part of a signal processing system adopting a conventional A / D conversion method (scan conversion).

9 is an A / D in the signal processing system shown in FIG.
7 is a timing chart showing an operation procedure of conversion processing.

FIG. 10 is a block diagram schematically showing a main part of a signal processing system adopting a conventional A / D conversion method (single conversion).

11 is a view of the signal processing system shown in FIG.
6 is a timing chart showing an operation procedure of a / D conversion process.

FIG. 12 Another conventional A / D conversion method (single conversion)
It is the block diagram which showed the principal part of the signal processing system which adopted the outline.

[Explanation of symbols]

31, 41 CPU 32, 42 A / D converter 33, 33A, 43 A / D conversion control circuit 34,44 A / D converter 35, 45 timer

Claims (12)

[Claims] 1. An A / D conversion means for performing an A / D conversion process for converting an analog signal into a digital signal, and a count end signal indicating the end of the count when the count operation is completed and the count up to a predetermined count value is completed. A / D conversion control means for outputting an A / D conversion control means for receiving the count end signal from the timer means and for giving an instruction to start the A / D conversion to the A / D conversion means. A D conversion device, wherein when the A / D conversion processing by the A / D conversion means is completed, a judgment means for judging whether or not the A / D conversion processing has been performed a predetermined number of times, and the judgment means, The timer means is provided with a restart means for restarting the counting operation in response to the judgment that the A / D conversion processing has not been performed for the predetermined number of times, and the timer means is configured to restart the count operation. In response to an instruction from the motion means, A / D converter, characterized in that is to resume counting. 2. A first count value storage means for storing a count value to be counted is provided, and a count value input from the outside is written in the first count value storage means. When the timer means finishes counting up to the count value stored in the first count value storage means,
The A / D conversion device according to claim 1, wherein the count end signal is output. 3. A second count value storage means for storing a count value input from the outside, and the count value stored in the second count value storage means when a predetermined condition is satisfied. 3. The A / D conversion device according to claim 2, wherein the A / D conversion device is configured to be written in the first count value storage means. 4. The A / D converter according to claim 3, wherein the predetermined condition includes an instruction to start the counting operation to the timer means. 5. A / D to be performed by the A / D conversion means
A number storage means for storing the number of times of D conversion processing is provided, and the number input from the outside is configured to be written in the number storage means, and the predetermined number is stored in the number storage means. It is the number of times, The A / D conversion device according to any one of claims 1 to 4. 6. The A according to any one of claims 1 to 5, further comprising arithmetic means for performing a predetermined arithmetic processing based on a conversion result by the A / D conversion means.
/ D converter. 7. The calculation means is a sum of a plurality of conversion results,
Obtaining either the average value of multiple conversion results, the maximum value of multiple conversion results, the minimum value of multiple conversion results, or the difference between the maximum and minimum values of multiple conversion results The A / D conversion device according to claim 6, wherein 8. The arithmetic means is capable of performing a plurality of types of arithmetic processing, and selects a type of arithmetic processing from these plural types of arithmetic processing based on designation from the outside and selects the arithmetic processing type. 8. The A / D conversion device according to claim 6 or 7, wherein the A / D conversion device performs the arithmetic processing of the type described above. 9. A calculation result storage unit for storing a calculation result of the calculation unit is provided, and a value calculated by the calculation unit is a desired value out of a plurality of conversion results, and is calculated by the calculation unit. It is configured such that the desired value and a processing order of a plurality of conversion processes for the conversion process in which the desired value is obtained are written in the calculation result storage means. Item 9. The A / D conversion device according to any one of items 6 to 8. 10. The arithmetic means performs the predetermined arithmetic processing in response to the determination by the determination means that the A / D conversion processing has been performed the predetermined number of times. A / according to any one of claims 6 to 9.
D converter. 11. The arithmetic operation means performs the predetermined arithmetic processing every time the A / D conversion processing by the A / D conversion means is completed. The A / D conversion device according to the section. 12. An A / D conversion means for performing an A / D conversion process for converting an analog signal into a digital signal, and a count end signal indicating the end of the count when the count operation is completed and the count up to a predetermined count value is completed. Signal processing including timer means for outputting and a count end signal from the timer means, and A / D conversion control means for giving an instruction to start A / D conversion to the A / D conversion means. In the system, when the A / D conversion process by the A / D conversion unit is completed, a determination unit that determines whether or not the A / D conversion process has been performed a predetermined number of times, and the predetermined unit by the determination unit. And a restarting means for restarting the counting operation to the timer means in response to the judgment that the A / D conversion processing is not performed. Signal processing system characterized in that in response to an instruction from the restarting means, it is intended to resume the counting operation.