JP2019134410A - Semiconductor device, power supply management circuit and electronic apparatus - Google Patents

Abstract

To provide a semiconductor device capable of achieving low power consumption for a system.SOLUTION: A semiconductor device 100 is used together with a processor 4. An A/D converter 120 is constituted to be correctable. A logic circuit 130 regularly gives a correction trigger to the A/D converter 120 by a counting operation using an output of an oscillator 110.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device including an A / D converter.

  In various electronic devices, A / D converters that convert analog signals representing these states into digital signals are used to perform digital signal processing on the electrical state of internal circuits and the physical state of electronic devices.

  FIG. 1 is a block diagram of a semiconductor device 10 including an A / D converter. The semiconductor device 10 is mounted on the electronic device 2 together with the processor 4. The semiconductor device 10 includes an A / D converter 12, a logic circuit 14, and an interface circuit 16. The A / D converter 12 converts an analog signal A1 input from the outside or generated inside the semiconductor device 10 into a digital signal D1. The logic circuit 14 processes the digital signal D1. The data D2 obtained as a result of the processing is stored in a register and can be accessed from the processor 4 via the interface circuit 16.

  In applications where high resolution is required for the A / D converter 12, the amount of offset due to temperature change greatly affects the conversion result. Therefore, when receiving the calibration instruction from the processor 4, the logic circuit 14 instructs the A / D converter 12 to execute the calibration operation.

  For example, the processor 4 monitors the temperature and outputs a calibration instruction to the semiconductor device 10 on condition that an unacceptable temperature fluctuation has occurred.

JP 2014-230012 A

  In the circuit system of FIG. 1, the processor 4 must constantly monitor the temperature regardless of the operating state of the electronic device 2. Therefore, the processor 4 cannot be stopped (sleep, suspend, standby), which is one factor that hinders the reduction in power consumption.

  The present invention has been made in view of these problems, and one of exemplary objects of an aspect thereof is to provide a semiconductor device capable of reducing the power consumption of the system.

  One embodiment of the present invention relates to a semiconductor device used with a processor. The semiconductor device includes an oscillator, an A / D converter configured to be calibrated, and a logic circuit that periodically gives a calibration trigger to the A / D converter by a count operation using the output of the oscillator.

  Another aspect of the present invention is a power management circuit. The power management circuit receives a voltage from the battery and generates a power supply voltage to be supplied to the processor, an A / D converter that converts the current flowing through the battery into a digital value and is calibrated so as to be calibrated, A real-time clock that always operates and a count operation using the output of the real-time clock are performed, and an A / D conversion trigger is given to the A / D converter in the first period. And a logic circuit for providing a calibration trigger in two cycles.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to the present invention, power consumption can be reduced.

It is a block diagram of a semiconductor device provided with an A / D converter. 1 is a block diagram of an electronic device including a semiconductor device according to an embodiment. 3 is a time chart for explaining the operation of the semiconductor device of FIG. 2. It is a block diagram of a power management circuit. It is a block diagram of an electronic device provided with the semiconductor device which concerns on a 1st modification.

(Outline of the embodiment)
One embodiment disclosed in this specification relates to a semiconductor device. Semiconductor devices are used with processors. A semiconductor device includes an oscillator that oscillates at all times, an A / D converter configured to be calibrated, and a logic circuit that periodically gives a calibration trigger to the A / D converter by a count operation using the output of the oscillator. Prepare.

  According to this embodiment, since the A / D converter is periodically calibrated using the oscillator built in the semiconductor device itself, it is not necessary to determine the calibration condition by the processor. Therefore, in a situation where processing by the processor is unnecessary, the processor can be stopped, and power consumption can be reduced.

  The logic circuit receives a timing signal having a predetermined period based on the output of the oscillator, gives an A / D conversion trigger to the A / D converter in accordance with the timing signal, and counts a predetermined number of timing signals every time the timing signal is counted. A calibration trigger may be given to the D converter. By managing the A / D conversion operation and calibration based on a common signal, the circuit configuration can be simplified.

  The predetermined number may be set from the outside. Thereby, the frequency of calibration can be optimized according to the use of the semiconductor device.

  The semiconductor device may further include an RTC (Real Time Clock) circuit. The timing signal may be generated by an RTC circuit. Since the RTC circuit always operates and consumes very little power, the generation of a periodic calibration trigger is suitable for the use of the output.

  The semiconductor device may be connected to a battery of a device in which the semiconductor device is incorporated, and the A / D converter may convert the battery current into a digital value. The semiconductor device may integrate digital values. Thereby, the remaining amount of the battery can be detected.

  The semiconductor device may further include a power supply circuit that supplies a power supply voltage to the processor. The power supply circuit may stop supplying the power supply voltage when the processor is stopped.

  The A / D converter may be a ΔΣ type.

(Embodiment)
The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected to each other. Including the case of being indirectly connected through other members that do not substantially affect the state of connection, or do not impair the functions and effects achieved by the combination thereof. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as their electric It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.

  FIG. 2 is a block diagram of the electronic device 2 including the semiconductor device 100 according to the embodiment. The electronic device 2 includes a processor 4 and a battery 6 in addition to the semiconductor device 100. The type of the electronic device 2 is not limited, but examples include devices that require low power consumption, such as smartphones, tablet terminals, wearable terminals, electronic books, and fire alarms.

The semiconductor device 100 includes an oscillator 110, an A / D converter 120, a logic circuit 130, and an interface circuit 140, and is integrated on one semiconductor substrate. The semiconductor device 100 is constantly supplied with a voltage V _BAT from the battery 6 as a power source. The battery 6 may be either a primary battery or a secondary battery.

  The oscillator 110 constantly oscillates and generates a clock signal CK. The A / D converter 120 converts an analog signal A1 input from the outside into a digital signal D1. The A / D converter 120 may receive an internal signal of the semiconductor device 10 as an input.

  The logic circuit 14 processes the digital signal D1. The data D2 obtained as a result of the processing is stored in a register and can be accessed from the processor 4 via the interface circuit 140.

  The A / D converter 120 is configured to be calibrated. For example, in the calibration mode, the input of the A / D converter 120 is fixed, and the output at that time is acquired as an offset. When the A / D converter 120 includes a differential input, the two inputs are short-circuited and the output at that time is acquired. The calibration method for the A / D converter may be selected according to the method of the A / D converter.

The logic circuit 130 asserts the calibration signal CAL at a constant time interval (calibration period T _CAL ) by a counting operation using the output CK of the oscillator 110, and periodically gives a calibration trigger to the A / D converter 120. Further, the sampling signal SMP is asserted at a sampling cycle T _S (first cycle) shorter than the calibration cycle (referred to as the second cycle), and an A / D conversion instruction is given to the A / D converter 120.

  Preferably, the semiconductor device 100 includes an RTC circuit 112 and provides a clock function and a calendar function. The RTC circuit 112 continues to update the current time and date based on the clock signal CK. The time data and date data can be accessed from the processor 4 via the interface circuit 140.

  The RTC circuit 112 can generate a signal (called a timing signal) TM that is asserted every second. Therefore, the logic circuit 130 may generate the sampling period and the calibration period using the timing signal TM. For example, the sampling period may be the period of the timing signal TM (that is, 1 second). The calibration cycle may be a predetermined number N times the cycle of the timing signal TM. N may be a parameter that can be set from the outside. In this case, the calibration signal CAL can be calibrated by a counter that counts the timing signal TM.

The above is the configuration of the semiconductor device 100. Next, the operation will be described. FIG. 3 is a time chart for explaining the operation of the semiconductor device 100 of FIG. A / D converter 120 in response to the sampling signal SMP which is asserted for each predetermined sampling period T _S, converts the analog signals A1 to a digital value. The A / D converter 120 is set to the calibration mode in response to the calibration signal CAL asserted every predetermined calibration cycle _TCAL and outputs a digital value necessary for calibration.

  The above is the operation of the semiconductor device 100. According to the semiconductor device 100, the calibration of the A / D converter 120 is periodically performed using the oscillator 110 built in the semiconductor device 100 itself. Monitoring) becomes unnecessary. Therefore, in a situation where the processing by the processor 4 is unnecessary, such as when the electronic device 2A is not operating, the processor 4 can be stopped and power consumption can be reduced.

  Note that the generation of the calibration signal CAL by the logic circuit 130 may always be performed regardless of whether the processor 4 is stopped. In this case, there is an advantage that it is not necessary to incorporate processing or a circuit for determining the calibration condition on the processor 4 side.

  Next, the use of the semiconductor device 100 will be described. The architecture of the semiconductor device 100 can be suitably used for a power management circuit. FIG. 4 is a block diagram of the power management circuit 200. The power management circuit 200 is built in the electronic device 2 </ b> A together with the processor 4 and the battery 6.

  The power management circuit 200 is an IC (Integrated Circuit) that performs management related to power in the electronic device 2A.

The power management circuit 200 includes a power circuit 210 in addition to the circuit blocks (110, 112, 120, 130, 140) similar to those of the semiconductor device 100 described above. Power supply circuit 210 includes a DC / DC converter and a linear regulator, receives battery voltage _VBAT , and generates power supply voltage V _DD stabilized at a predetermined voltage level. The power supply voltage V _DD is supplied to the processor 4 from the voltage output terminal (VOUT).

  The power management circuit 200 may include a plurality of power supply circuits that supply a power supply voltage to loads other than the processor 4, but these are not shown because they are not related to the present invention.

The power management circuit 200 has a function (fuel gauge) for detecting the remaining battery level. As a method for detecting the remaining amount, there is a Coulomb count method in which the current I _BAT flowing through the battery 6 is integrated. The power management circuit 200 detects the amount of charge flowing out from the battery 6 based on the coulomb counting method.

The A / D converter 120 is used for detecting the current of the battery 6. A sense resistor Rs is connected in series with the battery 6, and a voltage drop V _SNS proportional to the battery current I _BAT is generated in the sense resistor Rs. The voltage drop V _SNS is input to the sense terminals SNSP and SNSN of the power management circuit 200. The A / D converter 120 converts the voltage drop _VSNS into a digital value D1. For example, a ΔΣ type is used for the A / D converter 120.

  The logic circuit 130 includes a coulomb counter circuit 132 that integrates a digital value D1 indicating the amount of current, and generates a coulomb count value CC. The coulomb count value CC is accessible from the processor 4. The coulomb counter circuit 132 can be constituted by an accumulator including a memory and an adder.

A sense amplifier that amplifies a minute voltage drop _VSNS may be provided at the input stage of the A / D converter 120.

  When the battery 6 is a secondary battery, the power management circuit 200 is further integrated with a charging circuit.

  The above is the configuration of the power management circuit 200. By adopting the architecture of the semiconductor device 100, the power management circuit 200 itself can periodically calibrate the A / D converter 120. Therefore, the processor 4 can be stopped when the electronic device 2A is stopped, thereby reducing power consumption. Can be lowered.

Further, when the processor 4 is stopped, the power management circuit 200 can stop supplying the power supply voltage V _DD . That is, since the operation of the power supply circuit 210 can be stopped, the power consumption of the power management circuit 200 can be further reduced.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

(First modification)
FIG. 5 is a block diagram of an electronic apparatus including the semiconductor device according to the first modification. In the first modification, the generation of the calibration signal CAL (internal calibration signal CAL _INT ) by the logic circuit 130 may be performed only when the processor 4 is in a sleep state. While the processor 4 is awake, the processor 4 determines the calibration condition. When the calibration condition is satisfied, the processor 4 gives a calibration trigger (external calibration signal CAL _EXT ) to the semiconductor device 100.

The external calibration signal CAL _EXT is input to the A / D converter 120 via the interface circuit 140. The A / D converter 120 may be given a logical sum of the external calibration signal CAL _EXT and the internal calibration signal CAL _INT . Alternatively, the external calibration signal CAL _EXT may be input to the logic circuit 130 via the interface circuit 140 so that the logic circuit 130 gives a calibration instruction to the A / D converter 120.

In many applications, the processor 4 can know various parameters (operating conditions) other than time including temperature. Therefore, the processor 4 can set the timing for calibrating the A / D converter 120 in consideration of parameters other than time. As a result, more appropriate calibration can be performed as compared with the case where the calibration timing is defined based only on the internal calibration signal CAL _INT .

(Second modification)
Already and length of the calibration period T _CAL and the sampling period T _S described, the method of generating the calibration signal CAL and the sampling signal SMP are merely illustrative, are determined according to the application of the monitoring target and the semiconductor device 100 of the A / D converter That's fine.

The sampling period _{T S} may be M s (M <N). In this case, the sampling signal SMP can also be constituted by a counter that counts timing signals asserted every second.

When the calibration cycle T _{CAL is set} to 60 seconds (1 minute), a timing signal that is asserted every minute provided by the RTC circuit 112 may be used as the calibration signal CAL. When the calibration cycle _TCAL is N minutes, the timing signal asserted every minute may be counted. If the amount of slowly changing as the temperature monitored, the sampling period T _S may be N times.

(Third Modification)
The application of the semiconductor device 100 is not limited to the power management IC. For example, the A / D converter 120 can receive the output of various sensing devices such as a temperature sensor.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 100 Semiconductor device 110 Oscillator 112 RTC circuit 120 A / D converter 130 Logic circuit 140 Interface circuit 2 Electronic device 4 Processor 6 Battery 200 Power supply management circuit 210 Power supply circuit

Claims (14)

A semiconductor device used with a processor,
An oscillator,
An A / D converter configured to be calibrated;
A logic circuit that periodically gives a calibration trigger to the A / D converter by a counting operation using the output of the oscillator;
A semiconductor device comprising:   The logic circuit receives a timing signal of a predetermined period based on the output of the oscillator, gives an A / D conversion trigger to the A / D converter according to the timing signal, and counts a predetermined number of the timing signals. 2. The semiconductor device according to claim 1, wherein the calibration trigger is given to the A / D converter each time.   The semiconductor device according to claim 2, wherein the predetermined number can be set.   4. The semiconductor device according to claim 2, further comprising an RTC (Real Time Clock) circuit, wherein the timing signal is generated by the RTC circuit. The semiconductor device is connected to a battery of a device in which the semiconductor device is incorporated, and the A / D converter can convert the current of the battery into a digital value,
The semiconductor device according to claim 1, wherein the semiconductor device integrates the digital values.   The semiconductor device according to claim 1, further comprising a power supply circuit that supplies a power supply voltage to the processor.   The semiconductor device according to claim 6, wherein the power supply circuit stops supply of the power supply voltage when the processor is stopped. The logic circuit generates the calibration trigger using the output of the oscillator while the processor is stopped.
8. The semiconductor device according to claim 1, wherein the processor generates a calibration trigger for the A / D converter during the operation of the processor.   The semiconductor device according to claim 1, wherein the A / D converter is a ΔΣ type.   The semiconductor device according to claim 1, wherein the semiconductor device is monolithically integrated on a single semiconductor substrate. A power supply circuit that receives a voltage from the battery and generates a power supply voltage to be supplied to the processor;
An A / D converter which converts the current flowing through the battery into a digital value and is calibrated so as to be calibrated;
RTC (Real Time Clock) circuit that always operates,
The count operation using the output of the RTC circuit is performed, and an A / D conversion trigger is given to the A / D converter in a first cycle, and the A / D converter is given a second cycle longer than the first cycle. A logic circuit for providing a trigger for the calibration;
A power management circuit comprising:   The power management circuit according to claim 11, further comprising a coulomb counter circuit that integrates outputs of the A / D converter. The logic circuit generates the calibration trigger using the output of the oscillator while the processor is stopped.
13. The power management circuit according to claim 11, wherein the processor generates a calibration trigger for the A / D converter during the operation of the processor.   An electronic apparatus comprising the power management circuit according to claim 11.

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