JPH09269870A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an A/D converter reducing the processing load on an external devices. SOLUTION: When data showing a conversion mode, etc., is supplied for each register 4a to 4d through a register 4, a sequencer 5 successively controls an analog multiplexer 1 to successively select an input channel. A register to store A/D converted data is selected from a result register 3. The A/D converter 2 A/D-converts a signal supplied from the analog multiplexer 1 to supply for the result register. When A/D-converted data is stored in each register ADCR0 to ADCR(P-1), the sequencer 5 supplies interruption requesting the reading of A/D-converted data to the external device and the external device responds to the interrupting request and reads A/D-converted data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D conversion device for A / D conversion by switching a plurality of analog inputs.

[0002]

2. Description of the Related Art There is known an A / D converter capable of measuring currents or voltages of a plurality of channels with one A / D converter by switching inputs using a multiplexer. Such an A / D conversion device is used for a microcontroller (hereinafter, referred to as a microcomputer) that controls devices and the like. Further, such an A / D conversion device includes a result register that holds the A / D conversion result. The number of result registers differs depending on the use, price, etc. of the A / D converter.

A / which has only one result register
When a plurality of channels are measured by the D converter, the channels to be A / D converted are switched at predetermined time intervals as shown in FIG. 2A, and the current or voltage of each channel is A / D converted. After that, an interrupt for requesting reading of A / D converted data is generated to an external device (microcomputer, personal computer, etc.) as shown in FIG. Therefore, the external device responds to the interrupt every time the A / D conversion of each channel is completed.
You need to capture the data from the converter. When such interrupts occur frequently, the overhead for interrupt processing significantly reduces the processing capability of the external device for processing other than A / D conversion.

On the other hand, in the case of using the A / D conversion device provided with the result registers for the number of channels of the multiplexer, the multiplexer is switched to complete the A / D conversion of all the channels, and then the A / D conversion data is obtained. Since an external device can be configured to generate an interrupt for instructing the reading of data from each result register and read the data of each channel from each result register, the frequency of interrupt occurrence can be reduced. It is possible to reduce a decrease in processing capacity of an external device.

However, in this case, since the result register is provided for every channel, the circuit scale increases as the number of channels increases, and not all channels of the multiplexer are used depending on the application. , The result register that is not used is wasted. Therefore, the cost of the A / D converter increases more than necessary.

Further, in the A / D conversion device provided with the number of result registers smaller than the number of channels of the Malplexer,
All channels are divided into several groups and handled. For example, in an A / D converter having a result register for four channels for 16-channel inputs, the input for 16 channels is divided into four groups (group 0 to group 3) as shown in FIG. .

For example, when the group 0 (channel 0 to channel 3) of these groups is designated, the A / D conversion apparatus having such a configuration has the group 0 as shown in FIG. 2 (A). Signals of channels 0 to 3 are sequentially subjected to A / D conversion, and after the last A / D conversion of channel 3, the reading of A / D converted data is requested as shown in FIG. After the interrupt is generated and the A / D conversion data is read from the result register by the external device, the A / D conversion of the signals of channel 0 to channel 3 is repeated. Such an operation is called a continuous mode.

In the continuous mode operation, only the channels of the same group are repeatedly A / D converted, so in order to A / D convert the signals of all the channels,
An external device needs to switch groups.

For example, when switching four groups (group 0 to group 3) each having four channels as described above for A / D conversion, as shown in FIG. The device is group 0 at time t0
A / D conversion is instructed. The A / D converter starts A / D conversion of the instructed group 0, performs A / D conversion of channels 0 to 3, and then performs A / D conversion at time t1 as shown in FIG. An interrupt requesting reading of D conversion data is generated to stop A / D conversion. The external device reads the A / D conversion data from the result register and instructs the A / D conversion of the next group, group 1. The A / D converter is in group 1 at time t2.
Start A / D conversion of the
A / D conversion is performed, an interrupt is generated as in the case of group 0, and A / D conversion is stopped. Similarly, A / D conversion of each group is sequentially performed, and A / D conversion of all channels is performed.

[0010]

As described above, when performing A / D conversion by switching a plurality of groups, the A / D conversion is performed each time the A / D conversion of the channels of each group is completed.
It is necessary to stop conversion once and switch groups. Therefore, the external device must switch the groups in addition to reading the A / D converted data for each group, which increases the processing load. Further, if the time for switching the group increases, it becomes an obstacle when it is desired to shorten the sampling cycle of A / D conversion.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an A / D conversion device capable of reducing the processing load of an external device.

[0012]

An A / D converter according to the present invention A / D converts input switching means for selecting a plurality of input channels and input signals of the input channels selected by the input switching means. A / D conversion means and A / D
A / D conversion means for holding the A / D conversion result of the conversion means, controlling a plurality of holding means having a smaller number of input channels of the input switching means and the input switching means, and sequentially selecting a predetermined number of input channels. And selection control means for instructing A / D conversion. Further, this A / D conversion device has a holding unit selecting unit that selects a holding unit that stores the A / D conversion result of the input channel selected by the selection control unit, and a predetermined number of holding units among the plurality of holding units. Read request means for requesting an external device to read the A / D conversion result from the holding means when the A / D conversion result is stored.

Further, by controlling the selection control means, the A / D conversion of each input channel is repeated at a predetermined cycle, and the A / D conversion is performed.
The conversion result may be updated, and the selection control means divides a predetermined number of input channels into a plurality of groups each having a predetermined number of holding means or less, and the input channels for each group. May be selected, and the read requesting means may make a read request for each A / D conversion result of each group.

Further, it is possible to further comprise an assigning means for assigning a predetermined number of the holding means to a specific input channel of the plurality of input channels. In this case, the holding section selecting means stores the A / D conversion result in the holding means assigned to the specific input channel when the input channel selected by the selection controlling means is the specific input channel, and When the selected input channel is not the specific input channel, the A / D conversion result is stored in the holding means other than the holding means assigned to the specific input channel.

Further, A / held by each holding means
It may be configured to include additional information adding means for adding additional information regarding the A / D converted data to the D converted data.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION A according to a first embodiment of the present invention
As shown in FIG. 1, the A / D converter has n input terminals A
An analog multiplexer 1 for selecting and outputting one of n channel signals input from I _{0 to} AI _n-1 ;
A / D signal supplied from analog multiplexer 1
An A / D converter 2 for converting and outputting, an A / D result register 3 for holding data after A / D conversion, and a register 4 to which operation instructions and the like are supplied from a CPU or the like via a bus There is. Further, this A / D converter is a sequencer 5 for controlling the analog multiplexer 1, the A / D converter 2, the A / D result register 3, etc. based on the value of the register, and the analog multiplexer according to the instruction from the sequencer 5, respectively. 1, and decoders 6 and 7 for controlling switching of the A / D result register 3. Further, this A / D conversion device is provided with an additional information adding section 8 which adds additional information to the A / D converted data from the A / D result register 3 and outputs it.

The analog multiplexer 1 is provided with n analog input terminals AI _{0 to} AI _n-1, and receives an input from a channel designated by the sequencer 5 via the decoder 6 as A.
Supply to the / D converter 2. The A / D converter 2
The analog signal is converted into a digital value having a predetermined number of bits under the control of the sequencer 5. The A / D conversion method of the A / D converter 2 is not particularly limited, and a general A / D converter is used.
A converter can be used. The A / D result register 3 includes p registers ADCR0 to ADCR (p-
1). The number p of the registers is smaller than the number n of the input channels of the analog multiplexer 1. In the following, for example, the number of input channels of the analog multiplexer 1 is 16 and the register ADC for 4 channels is used.
The case where R0, ADCR1, ADCR2, and ADCR3 are provided will be described.

The register 4 includes an A / D start / stop instruction register 4a for inputting A / D conversion start and stop instructions, a conversion clock number designation register 4b for designating the number of conversion clocks, and a conversion The conversion mode setting register 4c for setting the mode, the interrupt cycle setting register 4d for setting the interrupt cycle, and the like. Data indicating a conversion mode or the like is supplied to these registers from an external device via the bus 9.

The sequencer 5 includes a switching control section for controlling switching of the analog multiplexer 1, the A / D result register 3, etc., switching of the analog multiplexer 1 based on the clock CLK, and A / D of the A / D converter 2. A clock generation unit that generates a clock for controlling the timing of conversion, a conversion timing generation unit that controls the conversion timing of each bit of the A / D converter 2, and the like An interrupt processing unit for generating an interrupt requesting reading of A / D conversion data from the D result register, a mode setting unit for setting an operation mode, and the like are provided.

The modes set by the mode setting section of the sequencer 5 include a continuous scan mode and a specific channel designation mode. In the continuous scan mode, for example, the registers ADCR0 to 3 are assigned to all channels to be measured, and as shown in FIG. 5, the signals of the channels to be measured are A / D-converted for every four channels and obtained. Register A / D conversion data for 4 channels ADCR0
3 to 3 to generate an interrupt, and an external device stores the A / D in the registers ADCR0 to 3 in response to the interrupt.
Read the conversion data. It is not necessary to allocate all channels to all registers ADCR0 to ADCR3, and some channels may be allocated to some registers.

In the specific channel designation mode, a specific register, as shown in FIGS. 6 and 7, is a register ADC.
R0 is assigned to a specific channel, for example, channel 0, the remaining registers ADCR1 to ADCR1 to 3 are assigned to other channels, and A / D conversion is sequentially performed.
The converted data is stored in the register ADCR0, and the channel 0
Other than A / D conversion data, ADCR0 to 3 for each 3 channels
3 is stored.

The number of specific channels assigned to a specific register in the specific channel specification mode may be any number as long as it is equal to or smaller than the number of result registers. For example, it may be the same as the number of result registers. In this case, A / D
It operates in the same way as when registers are assigned to the channels to be converted. It can also be said that the continuous scan mode is a special mode of the specific channel fixed mode, that is, the case where no specific channel is designated.

In this specific channel designating mode, a C mode in which a signal of a specific channel (channel 0) is A / D converted at a frequency of once for each interrupt, and a signal of another channel is once each. There is a D mode in which a signal of a specific channel (channel 0) is A / D converted at a frequency while being A / D converted.

In the C mode, as shown in FIG. 6, the A / D conversion data of channel 0 is updated every time an interrupt occurs. Therefore, the sampling cycle of channel 0 is shorter than that of other channels. Such a mode is used, for example, when it is necessary to investigate the change of a specific channel in detail.

In the D mode, as shown in FIG.
When each interrupt occurs, only the A / D conversion data other than channel 0 is read, and until the A / D conversion data of all channels are read, for example, the reading of A / D conversion data of all other channels is completed. Later channel 0
The A / D conversion data of is read. Such a mode is used when it is difficult to read the A / D conversion data from all the registers ADCR0 to ADCR3 for each interrupt.

The sequencer 5 switches between these modes by referring to the register value set by an external device via the bus 9. Specifically, as shown in FIG. 8, the sequencer 5 functions as the above-mentioned mode selection unit by setting a specific channel designating unit 11 that sets a register to which a specific channel is assigned and an A / D conversion cycle of the specific channel. A frequency setting unit 12 that controls switching between the C mode and the D mode, a register exclusion control unit 13 that exclusively controls the registers set by the specific channel designating unit 11, and a channel that is allocated to a register other than the register to which the specific channel is allocated. , A / D conversion channel selecting unit 15 for selecting a channel to be A / D converted during A / D conversion, and A / D conversion result for selecting a register for storing the A / D conversion result. The storage register selecting unit 16 is provided.

The A / D converter having the above-described structure can be used in, for example, the microcontroller shown in FIG. This microcomputer has a CPU 21 and R
OM22, RAM23, serial I / F, parallel I
I / O control section 24 having an I / F and the like, and an A / D conversion section 25 configured similarly to the A / D conversion apparatus shown in FIG.
And a bus 26 to which the CPU 21 to the A / D converter 25 are connected. In addition, this microcomputer is CPU2
1, ROM 22 and part of RAM 23, I / O control unit 2
4, the A / D converter 25 and the like are formed as one element. In the configuration shown in FIG. 1, the A / D result register 3 corresponds to a part of the RAM 23 in FIG. 9, the bus 9 corresponds to the bus 26, and the other components are A / D.
It corresponds to the conversion unit 25. Further, in this case, the CPU 21 corresponds to the above-mentioned external device.

A control memory area as shown in FIG. 10 is provided in the memory space of the CPU 21. In the control memory space as described above, the above-mentioned I / O control unit 24 is provided.
A control register of about 256 bytes for controlling the operation of the serial I / F and the parallel I / F or the A / D conversion unit 25 is allocated. The above-mentioned result register 3 (registers ADCR1 to 3) and register 4
(A / D start register 4a to interrupt synchronization setting register 4d) are, for example, addresses F010 and later, F0 and
It is assigned after 20. Since the memory area that can be used for such a control register is limited, it is difficult to increase the number of registers when there are many other devices.

Further, when considering the development of a microcomputer family having a different number of channels of the A / D converter, if the number of control registers such as a result register and the configuration of register mapping are common, the A / D By changing only the configuration such as the number of channels of the analog multiplexer of the conversion unit 25, it is possible to easily design and manufacture a microcomputer having specifications suitable for the application. If the configuration such as the number of control registers such as the result register and the allocation position is common in this way, the software such as the compiler and the control program can be shared even in the microcomputers having different numbers of channels of the analog multiplexer. , The overall product cost can be reduced.

By executing a control program, such a microcomputer can control the A / D conversion device and execute a plurality of A / D conversion processes.

The case where A / D conversion is performed by such a microcomputer will be described below.

First, when performing A / D conversion, the CPU 21 of the microcomputer instructs the operation mode to the mode setting section of the A / D conversion section 25 via the bus 26. Specifically, when performing A / D conversion in the continuous scan mode, the CPU 21
Is used by the channel allocation unit 14 (FIG. 8) of the sequencer 5 via the bus 26 and the conversion mode setting register 4c (FIG. 1) that constitutes the A / D conversion unit 25 as a channel for A / D conversion. Instruct registers etc.

In the specific channel designation mode, CP
The U21 instructs the specific channel designating section 11 constituting the sequencer 5 to the specific channel to be fixed and the register to which the particular channel is allocated, and the channel allocating section 14
Indicate the channel to be A / D converted, the register to be used, etc. Further, when operating in the specific channel designation mode, the CPU 21 instructs the frequency setting unit 12 to operate in the C mode or the D mode.

Further, the CPU 21 instructs the clock generation section of the sequencer 5 through the conversion clock number designating register 4b shown in FIG. 1 to indicate the conversion cycle per channel of A / D conversion as the number of clock CLKs, for example. Further, the interrupt processing unit of the sequencer 5 is instructed to the interrupt processing unit of the sequencer 5 via the interrupt cycle setting register 4d, for example, as the number of channels and the number of clocks CLK, respectively.

When the setting of the operation mode is completed, the CPU
21 instructs the sequencer 5 to start A / D conversion via the A / D start / stop instruction register 4a shown in FIGS. When the start of the A / D conversion is instructed, the A / D conversion unit 25 operates independently under the control of the sequencer 5 until the CPU 21 instructs the stop of the A / D conversion. Therefore, the CPU 21 need only read the data held in each of the registers ADCR0 to 3 in response to the interrupt requesting the reading of the A / D conversion data supplied from the sequencer 5.

When the continuous scan mode is instructed, since no channel is set in the specific channel designating section 11, register exclusive control by the register exclusive control section 13 is not performed, and the A / D conversion channel is not set. The selection unit 15 supplies selection signals to the decoder 6 in FIG. 1 so that the signals of the channels set in the channel allocation unit 14 are sequentially selected based on the clock from the clock generation unit. As a result, the decoder 6 supplies the decode output of the selection signal to the analog multiplexer 1, and the decode output sequentially provides channel 0, channel 1, channel 2, channel 3, channel 3 as shown in FIG. 5A, for example. 4 ... is selected. At this time, the A / D conversion channel selection unit 15 sequentially notifies the A / D conversion result storage register selection unit 16 of the selected channels.

A / D conversion result storage register selecting section 16
Is notified of the currently selected channel from the A / D conversion channel selection unit 15, the A of the notified channel
The A / D conversion data is stored in the registers allocated by the channel allocation unit 14 in sequence so that
A selection signal indicating a register for storing / D converted data is supplied to the decoder 7 shown in FIG. As a result, the decoder 7 decodes the selection signal, and the decoded output causes
A register for storing the A / D conversion data is selected from the A / D result register 3, and for example, as shown in FIGS. 5C to 5F, channel 0, channel 1, channel 2, channel 3 are selected. , A / D conversion data of channel 4 ... Sequentially in registers ADCR0, ADCR1, ADCR
2, ADCR3, ADCR0, ADCR1 ...

Further, the A / D conversion result storage register selecting section 16 counts the number of channels notified from the A / D conversion channel selecting section 15, and according to the counting result, the usable registers ADCR0 to 3 can be used. When it is detected that all the A / D converted data are stored in, the interrupt processing unit is controlled to generate an interrupt requesting the reading of the A / D converted data. For example, as shown in FIG. 5A, the A / D conversion of channel 3 (or channel 7) is completed, and the register ADCR0 as shown in FIGS.
When channels 0 to 3 (or channels 4 to 7) are supplied to channels 3 to 3, an interrupt is generated as shown in FIG.

When an interrupt occurs, the CPU shown in FIG.
21 reads the data held in the registers ADCR0 to 3 in response to the interrupt, and A / Ds each channel.
Separate into converted data.

In such a continuous mode, after the mode is set as described above, if the start of A / D conversion is instructed, the A / D conversion section 25 operates independently. Therefore, CPU
The processing load of the CPU 21 can be significantly reduced as compared with the case where 21 controls the operation mode or the case where there is only one result register. Further, in such a continuous mode, since the sequencer 5 is configured to automatically switch the input channel, the A / D conversion is temporarily stopped as in the case where the CPU switches the input channel or the input channel group. Since it is not necessary to do so, it becomes easy to shorten the A / D conversion cycle.

Further, in this A / D converter, the circuit scale of the device can be reduced as compared with the case where the result register is provided for each input channel, and the device can be downsized.
The cost can be reduced easily.

On the other hand, when the specific channel designation mode is instructed from the CPU 21, the channel set in the specific channel fixing section 11 is assigned to a specific register, for example, the register ADCR0. Register exclusion controller 13
Controls the specific register ADCR0 not to be assigned to another channel in the A / D conversion result storage register selecting section 16.

When this specific channel designation mode is instructed, the A / D conversion channel selection section 15 refers to the frequency setting section 12 to confirm whether the C mode or the D mode is set. .

When the C mode is set, the A / D
Based on the clock from the clock generation unit, the conversion channel selection unit 15 causes the decoder 6 to sequentially select the signals of the channels set in the channel allocation unit 14 after the channel 0 is selected for each interrupt. Supply a selection signal.

As a result, the decoder 6 supplies the decode output of the selection signal to the analog multiplexer 1, and the decode output causes the decoder 6 to output, for example, as shown in FIG.
Channel 0, channel 1, channel 2, channel 3, channel 0, channel 4, channel 5, ... Are sequentially selected. At this time, the A / D conversion channel selection unit 1
5 sequentially notifies the A / D conversion result storage register selecting unit 16 of the selected channels.

A / D conversion result storage register selecting section 16
When the currently selected channel is notified from the A / D conversion channel selection unit 15, the A / D conversion data of the channel 0 which is a specific channel is stored in the register ADCR0, and the A / D conversion of the remaining channels is performed. A selection signal indicating a register for storing A / D conversion data is supplied to the decoder 7 so that the data is sequentially stored in the register allocated by the channel allocation unit 14. As a result, the decoder 7 decodes the selection signal, and the decoded output outputs A / D from the A / D result register 3.
A register for storing the D conversion data is selected, and as shown in FIGS. 6B to 6E, for example, channel 0, channel 1, channel 2, channel 3, channel 0, channel 4
The A / D conversion data of ... Are sequentially registered in the register ADCR
0, ADCR1, ADCR2, ADCR3, ADCR
0, ADCR1 ...

Further, the A / D conversion result storage register selecting section 16 counts the number of channels notified from the A / D conversion channel selecting section 15, and the usable registers ADCR0 to ADCR3 are counted according to the counting result. When it is detected that all the A / D converted data are stored in, the interrupt processing unit is controlled to generate an interrupt requesting the reading of the A / D converted data. For example, as shown in FIG. 6A, channel 3 (or channel 6, channel 9, channel 1
2, A / D conversion of channel 15) is completed and the same figure (B)
As shown in (E), channel 0 is in register ADCR0 and channels 1-3 are in registers ADCR1-3 (or channels 4-6, channels 7-9, channels 10-1).
2, when channels 13 to 15) are supplied, an interrupt is generated as shown in FIG.

When an interrupt occurs, the CPU 21 responds to the interrupt in the same manner as in the continuous scan mode described above, reads the data held in the registers ADCR0 to ADCR3, and separates the data into A / D conversion data for each channel.

The number of specific registers and the number of specific channels are not limited to one, and channel 0 is assigned to register ADCR0, channel 1 is assigned to register ADCR1, and so on.
It can be changed as appropriate.

In the C mode, the A / D conversion cycle of a specific channel can be shortened as compared with other channels as described above, so that the channel to be measured can be processed without increasing the processing load of the CPU 21. Measurements suitable for the characteristics of the signal can be performed. Also, two different A /
Since A / D conversion can be performed in the D conversion cycle,
The degree of freedom of the D conversion device can be improved.

When referring to the frequency setting unit 12, D
When the mode is set, the A / D conversion channel selection unit 15 is based on the clock from the clock generation unit,
A selection signal is supplied to the decoder 6 so that the signals of the channels set in the specific channel designation unit 11 and the channel allocation unit 14 are sequentially selected. As a result, for example, as shown in FIG. 7A, channel 0, channel 1, channel 2, channel 3, channel 4, ... Are sequentially selected. Note that this order is the same as in the above continuous scan mode. At this time, the A / D conversion channel selection unit 15
Notifies the A / D conversion result storage register selection unit 16 of the selected channels sequentially.

A / D conversion result storage register selecting section 16
When the currently selected channel is notified from the A / D conversion channel selection unit 15, the A / D conversion data of the channel 0 is registered in the register AD as in the case of the C mode.
A register for storing the A / D conversion data is selected so that the A / D conversion data of the remaining channels stored in CR0 are sequentially stored in the registers ADCR1 to ADCR1 to 3.
As a result, the A / D from the A / D result register 3
A register for storing the conversion data is selected, for example, as shown in FIG.
As shown in (B) to (E), the A / D conversion data of channel 0 is stored in the register ADCR0 as A / D of channel 1, channel 2, channel 3, channel 4, channel 5 ...
The D conversion data are sequentially registered in the registers ADCR1 and ADCR
2, ADCR3, ADCR1, ADCR2 ...

A / D conversion result storage register selecting section 16
Counts the number of channels notified from the A / D conversion channel selection unit 15, and when it detects that the A / D conversion data are all stored in the usable registers ADCR0 to 3 by the counting result. , The interrupt processing unit is controlled to generate an interrupt requesting reading of A / D conversion data.

When an interrupt occurs, the CPU 21 responds to the interrupt in the same manner as in the C mode described above, and registers the register ADC.
The data held in R0 to 3 is read and separated into A / D converted data for each channel.

Here, the register ADCR0 is set to the channel 0.
The contents of the register ADCR0 are not changed between the time the A / D conversion data of channel 0 is stored once and the time the A / D conversion data of channel 0 is stored next. . Therefore, the CPU 25 does not need to read the A / D conversion data held in the register ADCR0 when an interrupt occurs after the A / D conversion of the channel 3, channel 6, channel 9, and channel 12, and the other three registers ADCR1 A / held in ~ 3
Only D conversion data is read out, and A of the last channel 15 is read.
All registers AD only when an interrupt occurs after / D conversion
It is only necessary to read the A / D conversion data held in CR0-3.

In this D mode, the number of interrupts increases as compared with the continuous scan mode, but the number of data read from the register per interrupt decreases. Therefore, for example, because the speed of the bus 26 is slow, C
When the PU 21 does not have enough time to read the contents of all the registers at each interrupt, by setting this D mode, the number of registers read by one interrupt can be reduced. In the D mode, as described above, by reducing the number of channels read for each interrupt, it is possible to perform processing suitable for the processing capacity of the CPU 21, the performance of the bus 26, and the like.

Therefore, in the specific register designation mode consisting of the C mode and the D mode, different processing can be performed on the channel assigned to the specific register and the other channels, and the degree of freedom of A / D conversion is improved. Can be made.

Further, the above-mentioned additional information adding section 8 is shown in FIG.
As shown in FIG. 3, it is composed of a latch 32 which latches the channel selection data from the A / D conversion channel selection unit 15 of the sequencer 5 and supplies it to the result register 3 described above. An A / D completion signal indicating that the A / D conversion of the A / D converter 2 is completed is supplied from the sequencer 5 to the latch 32 as a latch timing input.

Further, the result register 3 is supplied with the output from the latch 31 which latches the 10-bit A / D conversion data from the A / D converter 2. Like the latch 32, the latch 31 is supplied with an A / D completion signal from the sequencer 5 as a latch timing input.

When performing A / D conversion as described above, A
The / D conversion channel selection unit 15 selects A / D conversion.
This selection data is supplied to the latch 32, and the A / D
When the conversion is completed, it is latched by the latch 32 according to the A / D conversion completion signal. Similarly, A / D converter 2
The A / D converted data from is latched by the latch 31.

The data latched by the latches 31 and 32 are supplied to the register selected by the selection signal from the A / D conversion result storage register selection section 16. As a result, each register ADCR0 of the result register 3 is
.. to ADCR (p-1) store A / D converted data and channel data (adjunct information) indicating the channel of this A / D converted data, as shown in FIG.

By thus adding the channel data indicating each channel to the A / D converted data of each channel, the CPU 21 can easily determine which channel the A / D converted data read from each register belongs to. can do. Therefore, the data of each channel can be reliably separated.

In the additional information adding section 8,
The additional information added to the A / D conversion data is information indicating the sampling cycle of A / D conversion, the sample hold time, the time stamp indicating the time, the operation mode, etc. in addition to the channel data indicating the above-mentioned channel. Good. Since these attached information are used inside the sequencer 5, the attached information is latched according to the A / D conversion completion signal and the latched output is supplied to the result register 3 as in the case of the channel data. do it.

When the data used in the sequencer 5 is added to the A / D conversion data,
A function can be added by a simple configuration change such as providing a latch as described above.

[0065]

In the A / D conversion device according to the present invention, the selection control means controls the input switching means to sequentially select a predetermined number of input channels, and instructs the A / D conversion means to perform A / D conversion. By selecting the holding unit for storing the A / D conversion result of the input channel selected by the holding unit selection unit by the selection control unit, the A / D conversion result of each channel is automatically stored in a predetermined number of holding units. To be done. Therefore, the external device only needs to read the A / D conversion result from the holding device in response to the read request from the read requesting device, and compared to the case where the external device controls the switching of the input channel, etc. The processing load on the device can be reduced.

If the selection control means is controlled to repeat the A / D conversion of each input channel at a predetermined cycle and update the A / D conversion result, the A / D conversion result is automatically obtained. Since it is updated, the processing load on the external device can be further reduced.

Further, the selection control means divides the predetermined number of input channels into a plurality of groups each of which is equal to or less than the predetermined number of holding means, selects an input channel for each group, and requests reading. If the means makes a read request for each A / D conversion result of each group,
It is possible to increase the number of input channels without increasing the number of holding units and the processing load of external devices.

The assigning means assigns a predetermined number of the holding means to a specific input channel, the remaining holding means to another input channel, and the holding section selecting means performs A / D conversion of the specific input channel. By storing the results in a predetermined number of holding units and storing the A / D conversion results of other input channels in the remaining holding units, different processing can be performed on a specific channel and other channels, The degree of freedom of A / D conversion can be improved.

Further, the A / D held by each holding means
If the additional information adding means for adding the additional information regarding the A / D converted data to the converted data is provided, the external device can easily identify the read A / D converted data.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an A / D conversion device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an A / D conversion operation of a conventional A / D conversion device.

FIG. 3 is a diagram showing allocation of channels to each group when channels to be measured are grouped in the conventional A / D converter.

FIG. 4 is a timing chart showing an A / D conversion operation of the conventional A / D conversion device.

FIG. 5 is a timing chart showing an operation when A / D conversion is performed in the continuous scan mode of the A / D conversion device according to the embodiment of the present invention.

FIG. 6 is a timing chart showing an operation when A / D conversion is performed in a specific channel designation mode of the A / D conversion device.

FIG. 7 is a timing chart showing an operation when A / D conversion is performed in the specific channel designation mode of the A / D conversion device.

FIG. 8 is a diagram showing a configuration of a mode selection unit that selects an operation mode in the A / D conversion device.

FIG. 9 is a block diagram showing a configuration of a microcomputer using the A / D conversion device.

FIG. 10 is a memory map showing a control memory area provided in a memory space of a CPU which constitutes the microcomputer.

FIG. 11 is a block diagram showing a configuration of an additional information adding unit which constitutes the A / D conversion device.

FIG. 12 is a diagram showing A / D conversion data to which additional information is added by the additional information adding unit.

[Explanation of symbols]

1 analog multiplexer, 2 A / D converter,
3 A / D result register, 4 register, 5 sequencer, 8 additional information adding section

Claims (5)

[Claims] 1. An input switching means for selecting a plurality of input channels, an A / D conversion means for A / D converting an input signal of the input channel selected by the input switching means, and the A / D conversion means. A plurality of holding means, which is smaller than the number of the input channels holding the A / D conversion result, and the input switching means are controlled to sequentially select a predetermined number of input channels, and the A / D conversion means performs A / D conversion. The selection control means for instructing, the holding section selection means for selecting the holding means for storing the A / D conversion result of the input channel selected by the selection control means, and the predetermined number of holding means among the plurality of holding means. An A / D conversion device, comprising: a read request unit that requests an external device to read the A / D conversion result from a holding unit when the A / D conversion result is stored. 2. Further, by controlling the selection control means,
Repeat A / D conversion of each input channel at a predetermined cycle,
The A / D conversion device according to claim 1, wherein the A / D conversion result is updated. 3. The selection control means divides the predetermined number of input channels into a plurality of groups each of which is less than or equal to the predetermined number of holding means, and selects an input channel for each group. The read request means performs a read request for each A / D conversion result of each group.
An A / D converter according to the item. 4. An assigning means for assigning a predetermined number of the holding means to a specific input channel of the plurality of input channels, wherein the holding section selecting means selects the input selected by the selection control means. A / when the channel is a specific input channel
The D conversion result is stored in the holding means assigned to the specific input channel, and when the input channel selected by the selection control means is not the specific input channel, the A / D conversion result is assigned to the specific input channel. The A / D conversion device according to claim 1, wherein the A / D conversion device is stored in a holding unit other than the holding unit. 5. The apparatus according to claim 1, further comprising additional information adding means for adding additional information relating to the A / D converted data to the A / D converted data held in each of the holding means. Item 4. The A / D conversion device according to item 4.