JPH05135184A - Signal processor - Google Patents

Abstract

PURPOSE:To lighten the load on a microcomputer by securely performing highly precise signal processing without any control by the microcomputer. CONSTITUTION:This signal processor is equipped with an analog-digital converter 1 which converts analog inputs V1-V1 inputted through respective switches SW1-SW4 into digital values, a storage circuit 2 which is temporarily stored with the digital values obtained by the converter 1, a timer circuit 4 which outputs a constant period signal at each predetermined period, a timing signal generator 5 which controls the converter 1 in response to the constant period signal to provide the digital conversion processing of the analog inputs V1-V1 of one channel inputted to the converter 1, and a switch selection control circuit 6 which counts the frequency of processing of the converter 1 each time the converter l finishes the digital conversion of the analog inputs V1-V1 of one channel and closes specific switches among the respective switches SW1-SW4 according to the counted value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device, and more particularly to a signal processing device for selecting a plurality of analog signals and performing digital conversion processing.

In recent years, there has been a trend toward digital signal processing by converting an analog signal into a digital signal for the purpose of high-accuracy signal processing and reduction of characteristic variations. Also,
In order to perform rational signal processing, one analog-digital converter is used for a plurality of types (multi-channels) of analog signals, and each analog signal is sequentially digital-converted by making an appropriate selection. In this case, it is indispensable to continuously perform signal processing at every certain period, and a high-level technology for performing analog / digital conversion for that is required.

[0003]

2. Description of the Related Art Conventionally, analog / digital conversion processing control in a semiconductor integrated circuit device has been performed by a microprocessor. As shown in FIG. 3, a central processing unit (hereinafter referred to as CP
A U) 31 executes a predetermined interrupt process based on a timer 32 at regular intervals, and operates an analog / digital converter 34 via a conversion commander 33. At the same time, the CPU 31 outputs a selection control signal to the selector 35.

The selector 35 turns on one of the switches SW1 to SW4 provided corresponding to the analog inputs V1 to V4 of each channel based on the selection control signal, and A / A via the turned on switch. The selected analog input is input to the D converter 34. A / D converter 3
The analog input input to 4 is digitally converted and output to the register 36, and the digital value temporarily stored in the register 36 is output to the data bus 37.

That is, the CPU 31 selects a predetermined analog input at regular intervals and causes the A / D converter 34 to execute digital conversion processing.

[0006]

However, since the CPU 31 is executed by the software program for the digital conversion processing of each channel, the load of the CPU 31 is heavy, and the creation of data such as the conversion processing timing of each channel is very complicated. And it was troublesome. The digital conversion process is executed by the interrupt processing operation of the CPU 31. Therefore, the overhead cycle at the time of interrupt processing is increased, and the processing speed of the entire microcomputer is reduced.

The present invention has been made in order to solve the above problems, and the purpose thereof is to be able to surely execute highly accurate signal processing without the control of a microcomputer, and reduce the load on the microcomputer. It is to provide a signal processing device capable of performing the above.

[0008]

FIG. 1 illustrates the principle of the present invention. The A / D converter 1 has switches SW1 to SW1 respectively.
Analog inputs V1 to V4 of each channel via SW4
Is entered. The storage circuit 2 stores the digital value of the analog input obtained by the A / D converter 1 through digital conversion, and the stored digital value is output to the bus 3.

The timer circuit 4 measures a predetermined time and outputs a constant cycle signal to the timing signal generator 5 at every predetermined cycle. The timing signal generator 5 controls the A / D converter 1 based on the constant period signal to execute the digital conversion processing operation of the analog input.

Based on the timing signal generator 5, the switch selection control circuit 6 counts the number of processing times of the analog / digital converter 1 every time the analog conversion of the analog input in one channel is completed, and Among the switches SW1 to SW4, the analog input switch for performing digital conversion next is closed based on the count value.

[0011]

The timing signal generator 5 controls the A / D converter 1 on the basis of the constant period signal output from the timer circuit 4 for each period, and digitalizes the analog input of the channel previously selected by the switch. Perform the conversion processing operation. When the A / D converter 1 completes the digital conversion of the analog input, the switch selection control circuit 6 counts the number of processing times of the converter 1, and inputs to the A / D converter 1 next based on the count value. Close the switch corresponding to the analog input of the desired channel.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. FIG. 2 shows an electric block circuit diagram of a signal processing device formed on a semiconductor chip. The A / D converter 11 receives analog inputs V1 to V4 from each channel (four channels in this embodiment) for each channel. Input is made via the provided analog switches SW1 to SW4. The digital conversion processing operation for one analog input of the A / D converter 11 is controlled by a series of control pulse signals from the timing signal generator 12. The timer circuit 13 is a circuit for activating the timing signal generator 12, and outputs a constant cycle signal to the signal generator 12 at every predetermined cycle. Then, when the timing signal generator 12 inputs a signal having a constant period, the A / D converter 1 performs a digital conversion processing operation for one analog input.
1 outputs a series of control pulse signals for execution. That is, the timing signal generator 12 outputs a series of control pulse signals for one digital conversion process every predetermined period.

A digital signal memory (hereinafter referred to as a FIFO) 14 is composed of a register group, a RAM or the like, and stores digital values sequentially converted by the A / D converter 11. And FIFO14
The digital values sequentially stored in are output to the bus 15.

The counter 16 is a 2-bit addition counter in this embodiment, and adds "1" in response to a completion signal output each time the A / D converter 11 completes one digital conversion process. When the count value reaches "4" by the decimal system, the count value is reset to "1" by the next completion signal. That is, the counter 16 repeats the count operation between “1” and “4” in response to the completion signal, and outputs the count value at each time to the decoder 17.

The decoder 17 closes one of the analog switches SW1 to SW4 and opens the other based on the count value of the counter 16. In this embodiment, the analog switch SW1 is used when the count value is "1", and the analog switch S is used when the count value is "2".
W2, analog switch SW when the count value is "3"
3, analog switch SW4 when the count value is "4"
Select each and close. That is, the decoder 17 closes a predetermined analog switch based on the count value of the counter 16 and enables digital conversion processing by the A / D converter 11 of an analog input input via the closed analog switch. To do.

Next, the operation of the signal processing device configured as described above will be described. Now, when the count value of the counter 16 is "1" and the first constant cycle signal is output based on the time counting operation of the timer circuit 13, the timing signal generator 12 causes the A / D converter 11 to output a series of signals. Outputs a control pulse signal. The A / D converter 11 inputs an analog input in response to the series of control pulse signals and executes a digital conversion processing operation. At this time, since the count value of the counter 16 is “1” and the decoder 17 closes the analog switch SW1, the analog input V is input to the A / D converter 11.
1 is output. Therefore, the A / D converter 11 digitally converts the analog input V1 and outputs the digital value to the FIF.
Output to O14.

When the digital conversion processing of the analog input V1 is completed, the A / D converter 11 outputs a completion signal to the counter 16
Output to. The counter 16 sets the count value to "2" based on this completion signal. Therefore, the decoder 17 closes the analog switch SW1 based on this count value and causes the A / D converter 11 to output the analog input V2. Eventually, when the next constant period signal is output based on the time counting operation of the timer circuit 13, the timing signal generator 12 outputs a series of control pulse signals to the A / D converter 11 as described above. The A / D converter 11 inputs the analog input V2 at that time in response to the series of control pulse signals, performs digital conversion in the same manner as described above, and converts the digital value into the FIFO 14
Output to.

When the digital conversion processing of the analog input V2 is completed, the A / D converter 11 outputs a completion signal to the counter 16
To the counter 16 and set the count value of the counter 16 to "3",
It waits for the operation of the next digital conversion processing of the analog input V3. Then, thereafter, each time a constant period signal is output from the timer circuit 13, the analog input of each channel is sequentially converted into a digital signal.

As described above, in the signal processing apparatus of this embodiment, the timing signal generator 12 causes the A / D converter 11 to output each time a constant period signal is output from the timer circuit 13.
The digital input of the analog input V1 to V4 is performed on the basis of the counter 16 and the decoder 17 while performing the digital conversion processing operation by
Since the A / D converter 11 is sequentially selected from the above, the digital conversion processing and the selection of the analog input to be converted can be executed without the control of the microcomputer as in the conventional case. it can.

Therefore, the load of the microcomputer formed on the semiconductor chip is reduced accordingly, the overhead cycle at the time of interrupt processing is significantly reduced, and the processing speed of the microcomputer as a whole is increased. Further, since a control program for the A / D conversion processing is unnecessary, it is possible to simplify the creation of the program data for that amount.

The present invention is not limited to the above-mentioned embodiment. For example, in the above-mentioned embodiment, the number of channels, that is, four analog inputs V1 to V4, is used. May be carried out.

[0022]

As described in detail above, according to the present invention, it is possible to surely execute highly accurate signal processing without the control of the microprocessor, and to reduce the load on the microcomputer. is there.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of a signal processing device according to the present invention.

FIG. 2 is an electric block circuit diagram of a signal processing device showing an embodiment of the present invention.

FIG. 3 is an electric block circuit diagram of a conventional signal processing device.

[Explanation of symbols]

 1 A / D converter 2 memory circuit 3 bus 4 timer circuit 5 timing signal generator 6 switch selection control circuit SW1 to SW4 switches V1 to V4 analog input

Claims (1)

[Claims] 1. An analog input (V1 to V) of each channel
4) corresponding switches (SW1 to SW)
4) and the analog inputs (V1 to V4) of the respective channels can be input via the respective switches (SW1 to SW4), and the analog input (V1 to V4) is converted into a digital value. A digital converter (1), a storage circuit (2) for temporarily storing the digital value converted by the analog-to-digital converter (1), and a timer circuit (4) for outputting a constant cycle signal for each predetermined cycle Controlling the analog-to-digital converter (1) in response to the constant period signal to execute digital conversion processing of analog inputs (V1 to V4) in one channel input to the converter (1). Timing signal generator (5)
Each time the analog-to-digital converter (1) completes the digital conversion of the analog inputs (V1 to V4) in one channel, the number of processing times of the converter (1) is counted, and based on the count value, Switch (SW1 to SW4)
And a switch selection control circuit (6) for closing predetermined switches (SW1 to SW4) of the signal processing device.