JP3165777B2 - Step-up motor slow-up / down control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a slow-up / down control device for a stepping motor mounted on a facsimile machine, a printer or the like.

[0002]

2. Description of the Related Art Generally, when a stepping motor is operated at a high speed, the operation is started at a low speed in order to prevent the temperature of the motor from rising and the like, and the rotation is gradually increased to obtain a required constant speed rotation. So-called slow-up is used. In addition, when the motor is stopped, even if the motor is suddenly stopped, the motor is not stopped as desired by the inertial force. In such a slow-up and a slow-down, a smooth start and stop can be obtained as the number of speed switching steps increases.

In a conventional driving device for a stepping motor, the number of drive pulses per second for phase switching output to the motor, the so-called pulse frequency (PPS: pulse per second), is gradually increased by hardware. A slow-up or a slow-down is realized by increasing or decreasing the speed, and a slow-up or a slow-down is realized by switching the output timing of the drive pulse by software under program control of a central processing unit. There was something you did.

[0004]

However, when the slow-up and the slow-down are all constituted by hardware, there is a problem that the circuit configuration becomes complicated and the circuit scale becomes large, so that the size cannot be reduced. Further, when slow-up and slow-down are realized by program control by the central processing unit, the load on the central processing unit increases, so that the speed switching step must be reduced to reduce the load, and smooth start-up is performed. And could not be stopped.

The present invention has been made in view of such circumstances, and aims to simplify and reduce the size of the configuration, and to achieve a smooth start-up without increasing the load on the central processing unit. An object of the present invention is to provide a slow-up / down control device for a stepping motor that can be stopped.

[0006]

SUMMARY OF THE INVENTION The present invention provides a motor driver for supplying a drive pulse to a stepping motor at the input timing of a control signal, and a first and second register group comprising a plurality of registers connected in series. A register group selecting means for selecting one of the first and second register groups as a write target register and selecting the other as a read target register group; and storing slow-up or slow-down data in each register of the write target register group. Data writing means for writing, a counter for loading data of a register at the last stage of a register group to be read each time a load signal is input, and counting from the data; and a counter for reading in response to a load signal to the counter A shift means for shifting the data of each register of the target register group to the next stage, and a counter full Load signal output means for outputting a load signal to a counter in response to a motor driver control signal output by a counter, control signal detection means for detecting a motor driver control signal, and a motor driver control signal to be read by the detection means Register group switching means for switching the register group to be selected by the register group selecting means each time the number of registers constituting the register group is detected.

[0007]

In the present invention having such a configuration, when the stepping motor is stopped, one register group is selected as a register to be written by the register group selecting means. As a result, slow-up data for the number of registers is written by the data writing means into each of the registers constituting this one register group.

Next, when the operation of the stepping motor is started, one register group is selected as a read target register by the register group selecting means, and the other register group is selected as a write target register. As a result, the leading data stored in the last register of one of the register groups is loaded into the counter, and the counter starts counting from the data. At this time, the data of each register of one register group is shifted to the next stage.

Thereafter, when the counter counts full and the motor driver control signal is output, the second data which has been shifted to the last register of one of the register groups is loaded into the counter, and the counter restarts counting from the data. I do. At this time, the data of each register of one register group is shifted to the next stage.

In this manner, the above processing is repeated until the motor driver control signals output by the full count of the counter are detected for the number of registers in one of the register groups. In the meantime, the remaining slow-up data is sequentially written into each of the registers constituting the other register group by the number of registers by the data writing means.

When the motor driver control signals for the number of registers are detected by the control signal detecting means,
The other register group switches to the read target register, and one register group switches to the write target level group. As a result, the data stored in the last register of the other register group is loaded into the counter, and the counter starts counting from the data. At this time, the data of each register in the other register group is shifted to the next stage.

Thereafter, when the counter counts up and the motor driver control signal is output, the data shifted to the last register of the other register group is loaded into the counter, and the counter restarts counting from the data. At this time, the data of each register in the other register group is shifted to the next stage.

The above process is repeated until the motor driver control signals output by the full count of the counter are detected by the number of registers of the other register group. In the meantime, the remaining slow-up data is sequentially written into each of the registers constituting one of the register groups by the number of registers by the data writing means.

When the motor driver control signals for the number of registers are detected by the control signal detecting means,
One register group is switched to a register to be read, and the other register group is switched to a level group to be written, and operates in the same manner as described above.

As a result, the drive pulse is output from the motor driver to the stepping motor at the input timing of the control signal, so that the stepping motor performs a slow-up operation.

On the other hand, when the operation of the stepping motor is stopped, the operation is the same as described above except that the slowdown data is used instead of the slowup data. In short, slowdown data is alternately written to the first register group and the second register group, and when one register group is to be written, the data stored in the other register group is sequentially loaded into the counter to count. Then, a drive pulse is output to the stepping motor at the timing of the control signal output every full count, and the stepping motor performs a slowdown operation.

[0017]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing the main configuration of the stepping motor-equipped device according to this embodiment. The stepping motor 1 supplies a drive pulse to the stepping motor 1 at the input timing of a carry signal CR as a control signal. A driver 2, a motor control circuit 3 for sending the carry signal CR to the motor driver 2, a central processing unit (hereinafter abbreviated as CPU) 4, which constitutes a control unit main body of the stepping motor mounted device, and a CPU 4
(Read only memory) 5 for storing fixed data such as program data for controlling the RAM, and RAM (random access memory) for storing variable data
6 and so on. Then, the CPU 4 and the ROM 5
The RAM 6 and the motor control circuit 3 are connected by a bus line 7 such as an address bus and a data bus.

The RAM 6 stores, in advance, a slow-up table 6a in which, in particular, slow-up data for each step determined based on a pulse frequency (pulse frequency per second: PPS) that increases stepwise during the slow-up control. And a slowdown table 6b in which slowdown data for each step determined based on the pulse frequency that decreases stepwise during the slowdown control is set in advance.

FIG. 1 is a detailed block diagram of the motor control circuit 3. This motor control circuit 3 includes m1, m2, m
A first register group 11 in which five registers 3, 3, m5, and m5 are connected in series; and n1, n2, n3, n4, n
And a second register group 12 in which five registers of No. 5 are connected in series. Data is externally written to the first stage register m1 of the first register group 11 via the first selector 13. The first selector n1 of the second register group 12 includes the second selector 14
The data is written from outside via the. On the other hand, the final stage register m of each of the register groups 11 and 12
5, n5 are selectively sent to the counter 1 via a third selector 15 constituting a register group selecting means.
6 is loaded. Each register m1
m5, n1 to n5 are FIFO (first-in, first-out) type registers, which shift previous data to the next register when writing data in synchronization with the write signals AW, BW, respectively.

The first selector 13 always selects the b input, and temporarily selects the a input in synchronization with the rise of the selection signal AS. The data bus line 7a from the CPU 4 is connected to the a input, and the bus line 17 for the data output from the last register m5 of the first register group 11 is connected to the b input. The second selector 14 also selects the b input at all times, and temporarily selects the a input in synchronization with the rise of the selection signal BS.
Select input. The data bus line 7a from the CPU 4 is connected to the a input, and the second bus is connected to the b input.
Are connected to a bus line 18 for data output from the last-stage register n5 of the register group 12 of FIG.

The third selector 15 outputs a selection signal RS
Is low level "L", the a input is selected, and when the selection signal RS is high level "H", the b input is selected. The bus line 17 is connected to the a input,
The bus line 18 is connected to the b input. Here, the register group on the side selected by the third selector is a register to be read, and the other register group is a register to be written.

The counter 16 synchronizes the data of the bus lines 17 and 18 on the side selected by the third selector 15 in synchronization with the rising of the counter clock signal CLK when the load signal RD is at the low level “L”. The data is loaded, and counting is started from the data in synchronization with the rise of the counter clock signal CLK. A carry signal CR serving as a control signal to the motor driver 2 is output as soon as the count becomes full (for example, FFH in the case of an 8-bit counter). The counter clock signal CLK is supplied from the CPU 4 so that the CPU 4 can set the frequency division value of the counter 16.

The carry signal CR is input to the motor driver 2. The motor driver 2 sequentially drives the four-phase drive pulses A, / A, B, / B to the stepping motor 1 at the input timing of the carry signal CR. To be supplied.

The carry signal CR is also supplied to a load output circuit 19 as load signal output means and a carry detection circuit 20 as control signal detection means. The load output circuit 19 temporarily changes the load signal RD to a low level “L” in synchronization with the rise of the carry signal CR.
And then return to high level "H". CPU4
Accordingly, the level of the load signal RD is similarly switched at the rise of the motor start signal MS for instructing the start of the operation of the stepping motor 1.

The carry detection circuit 20 detects the carry signal CR, and the number of detections is determined by each register group 11,
Each time the number of registers constituting “12” reaches “5”, a trigger signal is output to the trigger terminal T of the T flip-flop 21.

The T flip-flop 21 resets in synchronization with the rise of the motor start signal MS input to the reset terminal R, sets the normal output Q to a high level "H", and sets the inverted output / Q to a low level. Set to level “L”.
Thereafter, each time a trigger signal is input from the carry detection circuit 20 to the trigger terminal T, the normal output Q and the inverted output /
The signal level of Q is switched. This T flip-flop 2
The normal output Q and the inverted output / Q of 1 are both input to the register group control circuit 22.

The register group control circuit 22 includes a non-inverted output Q and an inverted output / Q of the T flip-flop 21;
A load signal RD from the load output circuit 19;
The write signal WR from the U4 is input to each of the first to third selectors 13, 14, and 15, and
S, BS, RS, and the first and second register groups 1
These output the write signals AW and BW to the registers 1 and 12, respectively, and constitute register group switching means.

More specifically, the register group control circuit 22
As shown in FIG. 3, the non-inverted output Q of the T flip-flop 21 is supplied to the third selector 15 by a selection signal RS.
Output as Further, the first AND gate 2 of negative logic which takes the logical product of the forward output Q and the write signal WR.
3 and outputs the output of the first AND gate 23 as a selection signal BS to the second selector 14. Further, a second AND gate 24 of negative logic which takes the logical product of the inverted output / Q of the T flip-flop 21 and the write signal WR is provided, and the output of the second AND gate 24 is supplied to the first selector 13. Is output as a selection signal AS corresponding to.

The register group control circuit 22 has a
A fourth selector 25 that selects one of the load signal RD to the input and the write signal WR to the b input and outputs the selected signal as a write signal BW to the second selector 14; Selecting one of the write signal WR and the load signal RD to the b input,
And a fifth selector 26 that outputs a write signal AW to the first selector 13. The fourth
Selector 25 selects the a input when the non-inverting output Q of the T flip-flop 21 is at a high level “H”, and selects the b input when the non-inverted output Q is at a low level “L”. On the other hand, the fifth
Selector 26 selects the a input when the inverted output / Q of the T flip-flop 21 is at a low level “L”, and selects the b input when the inverted output / Q is at a high level “H”.

In the present embodiment configured as described above, the slow-up data for each step determined based on the pulse frequency that increases stepwise during the slow-up control is set in the slow-up table 6a in advance. In addition, slowdown data for each step determined based on a pulse frequency that decreases stepwise during slowdown control is set in the slowdown table 6b.

FIG. 5 shows an example of an increase curve of the pulse frequency which increases in each step during the slow-up operation. FIG. 6 shows an example of a decrease curve of the pulse frequency that decreases in each step during the slowdown operation.
Further, the pulse frequency [PPS] of the increase curve shown in FIG.
And the clock count of each step of the counter 16 required to obtain the pulse frequency [PPS] of the decreasing curve shown in FIG. It is shown in [Table 1].

[0032]

[Table 1] That is, the initial value of the counter 16 may be set for each step so that the slow-up data and the slow-down data become full when the counter 16 counts the clock count number corresponding to each step.

In the initial state where the stepping motor 1 is stopped, as shown in FIG.
5 is low level “L”, the first
Is selected as a register to be read, and the second register group 12 is selected as a register to be written. However, the data of the registers m1 to m5 and n1 to n5 of the register groups 11 and 12 are cleared to “0”.

In this state, prior to the start of the operation of the stepping motor 1, the CPU 4 reads out five slow-up data B1, B2, B3, B4, and B5 from the first step to the fifth step from the slow-up table 6a, and reads the data in the order of steps. While sending it out to the data bus line 7a,
Five pulses of the write signal WR are transmitted.

Then, the write signal WR becomes a write signal BW to the second register group 12 and is applied to each of the registers n1 to n5. Each of the registers n1 to n5 repeats data writing and shifting five times. Thereby, the first step slow-up data B1 is written into the register n5, the second step slow-up data B2 is written into the register n4, and the third step slow-up data B3 is written into the register n3. , The slow-up data B4 of the fourth step is written into the register n2,
Register n1 has the slow-up data B of the fifth step.
5 is written. Therefore, the data B1 of the register n5 at the last stage is output to the data bus line 18 of the second register group 12.

Next, the CPU 4 raises the motor start signal MS at time t0 in FIG.
Command to start operation. Then, the T flip-flop 21 is reset and the selection signal RS rises. As a result, the third selector 15 switches, and the first register group 11 becomes a register to be written, and the second register group 12 becomes a register to be read. The load signal RD falls in synchronization with the rise of the motor start signal MS, and the counter 16 outputs the output data B1 from the second register group 12 which is the register to be read to the counter 16 in synchronization with the rise of the counter clock signal CLK thereafter. Is loaded, and the counter 16 starts counting from this data B1.

Thereafter, when the load signal RD returns to the high level "H", the write signal BW to the second register group 12 accesses each of the registers n1 to n5 in synchronization with its rise, and The data of n5 is shifted to the next stage. As a result, the data B2 of the last register n5 is output to the data bus line 18 of the second register group 12. At this time, the data B1 shifted from the last-stage register n5 via the second selector 14 is written in the first-stage register n1.

When the counter 16 fully counts and the carry signal CA rises at time t1 in FIG. 4, a driving pulse is output from the motor driver 2 to the stepping motor 1. Load signal RD falls in synchronization with the rise of carry signal CA, and counter 16 synchronizes with the subsequent rise of counter clock signal CLK.
Is loaded with the output data B2 from the second register group 12, and the counter 16 restarts counting from this data B2.

Thereafter, when the load signal RD returns to the high level "H", the carry signal CA falls in synchronization with its rise. Further, the write signal BW to the second register group 12 accesses each of the registers n1 to n5 in synchronization with the rise of the load signal RD, and shifts the data of each of the registers n1 to n5 to the next stage. As a result, the data B3 of the last-stage register n5 is output to the data bus line 18 of the second register group 12. At this time, the data B2 shifted from the last-stage register n5 is written into the first-stage register n1 via the second selector 14.

Thereafter, the above operation is repeated each time the counter 16 fully counts and the carry signal CA rises. Thus, at time t2 in FIG.
When the fifth carry signal CA corresponding to the number of registers constituting 2 is transmitted, the carry detection circuit 20 outputs a trigger signal. As a result, the signal levels of the outputs Q and / Q of the T flip-flop 21 are inverted to cause the selection signal RS to fall, the third selector 15 is switched, and the first register group 11 becomes a register to be read, and Are the write target registers.

During the period from t0 to t1 from the start of the operation of the stepping motor 1 to the output of the fifth carry signal, the CPU 4 reads the five slow-up data A1 from the sixth step to the tenth step from the slow-up table 6a. . A2. A3. A4. A5 is read and transmitted to the data bus line 7a in the order of steps, and five pulses of the write signal WR are transmitted.

Then, the write signal WR becomes a write signal AW to the first register group 11, which is a register to be written, and is given to each of the registers m1 to m5. Each of the registers m1 to m5 writes and shifts data. Repeat 5 times. Thereby, the slow-up data A1 of the sixth step is written to the register m5, the slow-up data A2 of the seventh step is written to the register m4, and the slow-up data A3 of the eighth step is written to the register m3. , The ninth step slow-up data A4 is written in the register m2, and the tenth step slow-up data A5 is written in the register m1. Therefore, when the fifth carry signal is output, the first
The data A1 of the register m5 at the last stage is output to the data bus line 17 of the register group 11 of FIG.

Therefore, when the load signal RD falls in synchronization with the fifth rise of the carry signal CA, the counter 16 outputs the output from the first register group 11 to the counter 16 in synchronization with the subsequent rise of the counter clock signal CLK. Data A
1 is loaded, and the counter 16 restarts counting from this data A1.

Thereafter, when the load signal RD returns to the high level "H", the carry signal CA falls in synchronization with its rise. The write signal AW to the first register group 11 accesses each of the registers m1 to m5 in synchronization with the rise of the load signal RD, and shifts the data of each of the registers m1 to m5 to the next stage. As a result, the data A2 of the last register m5 is output to the data bus line 17 of the first register group 11. At this time, the data A1 shifted from the last-stage register m5 via the first selector 13 is written in the first-stage register m1.

At time t3 in FIG. 4, when the counter 16 fully counts and the sixth carry signal CA rises, a drive pulse is output from the motor driver 2 to the stepping motor 1. The load signal RD falls in synchronization with the rise of the carry signal CA, and the output data A2 from the first register group 11 is supplied to the counter 16 in synchronization with the subsequent rise of the counter clock signal CLK.
Is loaded, and the counter 16 restarts counting from this data A2.

Thereafter, when the load signal RD returns to the high level "H", the carry signal CA falls in synchronization with its rise. The write signal AW to the first register group 11 accesses each of the registers m1 to m5 in synchronization with the rise of the load signal RD, and shifts the data of each of the registers m1 to m5 to the next stage. As a result, the data A3 of the last register m5 is output to the data bus line 17 of the first register group 11. At this time, the data A2 shifted from the last-stage register m5 via the first selector 13 is written in the first-stage register m1.

Thereafter, the above operation is repeated each time the counter 16 performs a full count and the carry signal CA rises. After the register to be read is switched to the first register group 11 in this manner, a fifth time (a total of ten times) corresponding to the number of registers constituting the first register group 11 is performed.
Is transmitted, the carry detection circuit 20 outputs a trigger signal. As a result, the signal levels of the outputs Q and / Q of the T flip-flop 21 are again inverted and the selection signal RS rises, and the third selector 15
Are switched, the first register group 11 becomes a register to be written, and the second register group 12 becomes a register to be read.

By the way, during the period from the output of the fifth carry signal CA to the output of the tenth carry signal CA, the CPU 4 outputs five throws from the eleventh step to the fifteenth step from the throw-up table 6a. Updater B6. B7. B8. B9. B10 is read and transmitted to the data bus line 7a in the order of steps, and five pulses of the write signal WR are transmitted.

Then, the write signal WR becomes a write signal BW to the second register group 12, which is a register to be written, and is given to each of the registers n1 to n5. Each of the registers n1 to n5 performs writing and shifting of data. Repeat 5 times. Thereby, the slow-up data B6 of the eleventh step is written to the register n5, the slow-up data B7 of the twelfth step is written to the register n4,
The slow-up data B8 of the thirteenth step is written to the register n3, the slow-up data B9 of the fourteenth step is written to the register n2, and the slow-up data B10 of the fifteenth step is written to the register n1. Therefore, when the tenth carry signal CA is output, the data B6 of the last-stage register n5 is output to the data bus line 18 of the second register group 12.

Therefore, when the load signal RD falls in synchronization with the tenth rise of the carry signal CA, the counter 16 outputs the output from the second register group 12 to the counter 16 in synchronization with the subsequent rise of the counter clock signal CLK. The data B6 is loaded, and the counter 16 restarts counting from this data B6.

Thereafter, the above operation is repeated. As a result, the slow-up data of each step set in the slow-up table 6a is stored in the CPU 4 by the CPU 5.
The first register group 11 and the second
Are written alternately with the register group 12 of the first row. While data is being written to one of the register groups, the data of the previous five steps set in each register in order from the other register group is stored in the counter 1 by one step.
6 and starts counting each time. Every time a full count is performed, a carry signal CA is output, and a drive pulse is output from the motor driver 2 to the stepping motor 1 at the output timing. When all the data for the five steps set in the register group to be read are loaded into the counter 16, the register to be read and the register to be written are switched.

As a result, the rotation speed of the stepping motor 1 is gradually increased based on the slow-up data of each step set in the slow-up table 6a, and a desired constant speed rotation is obtained by performing the slow-up operation.

The motor control circuit 3 operates in the same manner as in the slow-up operation even after the rotation at the constant speed. However, the CPU 4 writes the data of the final step of the slow-up table 6a into one register group, and after the one register group to be written is switched to the register to be read, the CPU 4 sets the data at the preset constant rotation speed. The constant speed data calculated based on the pulse frequency is transferred to the data bus line 7.
a and 5 pulses of the write signal WR. As a result, the constant-speed data is written in common to the registers of the other register group to be written. When the group of registers to be written and the group of registers to be read are subsequently switched, the CPU 4 sends out the constant speed data to the data bus line 7a again and sends out five pulses of the write signal WR. This allows
The constant speed data is also written in common to the registers of the other register group to be written. Then the CPU
No. 4 does not write data into the register groups 11 and 12 until the stop of the stepping motor 1 is commanded.

As described above, the data loaded into the counter 16 from the register group to be read is also written to the first register of the register group. Therefore, the registers m1 to m5, n1 to n5 of the register groups 11 and 12
If the constant speed data is written only once each time, the common constant speed data is always set in the counter 16 and the stepping motor 1 maintains the constant speed rotation. Therefore, C
The PU 4 does not need to write data to the register groups 11 and 12 until the PU 4 instructs the stepping motor 1 to stop.

On the other hand, when stopping the operation of the stepping motor 1, the CPU 4 stores the data in the slowdown table 6b in the first register group 11 and the second Are alternately written to the register group 12 of FIG. In this way, when one register group is to be written, the data of the previous five steps stored in the other register group is loaded into the counter 16 one step at a time, and counting is started each time. Each time the carry signal CA is output, a drive pulse is output from the motor driver 2 to the stepping motor 1 at the output timing.

As a result, the rotation speed of the stepping motor 1 is gradually reduced based on the slowdown data of each step set in the slowdown table 6b, and the stepping motor 1 performs a slowdown operation and stops.

As described above, according to the present embodiment, during the slow-up and slow-down control, the CPU 4 stores the five-step slow-up data or slow-down data in one of the register groups until the phase of the stepping motor 1 changes five times. Since it is sufficient to write down data, the load on the CPU 4 can be reduced as compared with the conventional configuration in which the timing at which the phase of the stepping motor 1 changes by program control is determined. In other words, the number of steps can be increased up to the permissible load of the CPU 4, and smooth start and stop can be performed.

At the time of constant speed operation, if the constant speed data common to each of the register groups 11 and 12 is written only twice in the initial stage, no control is required thereafter.
The load on U4 is reduced.

Also, the hardware configuration is simple,
It is easy to reduce the size.

In the above embodiment, each register group 11,
Although the number of registers constituting 12 is five, the number is not limited to five.

[0061]

As described above in detail, according to the present invention, the structure of the stepping motor can be simplified and downsized, and the step-up motor can be started and stopped smoothly without increasing the load on the central processing unit.・ A down control device can be provided. In addition, at the time of constant-speed operation, if the constant-speed data common to each register group is written only twice at the beginning, control becomes unnecessary after that, so that the effect of reducing the load on the central processing unit is also achieved.

[Brief description of the drawings]

FIG. 1 is a detailed block diagram of a motor control circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a main part of the device equipped with a stepping motor according to the embodiment;

FIG. 3 is a detailed block diagram of a register control circuit shown in FIG. 1;

FIG. 4 is a timing chart used to explain the operation of the embodiment.

FIG. 5 is a graph showing an example of an increase curve of a pulse frequency that increases for each step during a slow-up operation.

FIG. 6 is a graph showing an example of a decrease curve of a pulse frequency that decreases for each step during a slowdown operation.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Stepping motor 2 ... Motor driver 3 ... Motor drive circuit 4 ... CPU (Central processing unit) 6a ... Slow-up table 6b ... Slow-down table 11 ... 1st register group 12 ... 2nd register group 13-15 ... 1st to 3rd selectors 16 ... Counter 19 ... Load output circuit 20 ... Carry detection circuit 21 ... T flip-flop 22 ... Register group control circuit

Claims (2)

(57) [Claims] 1. A motor driver for supplying a drive pulse to a stepping motor at an input timing of a control signal, a first and second register group formed by connecting a plurality of registers in series, and a first and second register group. Register group selecting means for selecting one of the register groups as a write target register group and selecting the other as a read target register group; and data writing means for writing slow-up or slow-down data to each register of the write target register group. A counter for loading data of the register at the last stage of the group of registers to be read each time a load signal is input and starting counting from the data; and a counter for loading the group of registers to be read in response to a load signal to the counter. Shift means for shifting the data of each register to the next stage, and a full count of the counter A load signal output means for outputting the load signal to the counter in response to the motor driver control signal output by the control circuit; a control signal detection means for detecting the motor driver control signal; A register group switching means for switching a register group to be selected by the register group selecting means each time a signal is detected by the number of registers constituting the read target register group,・ Down control device. 2. The data writing means writes the data of the final step of the slow-up data to one of a group of registers to be written, and the group of registers is switched to a group of registers to be read by a register group switching means. The constant-speed data set in advance is written in common to the respective registers of the other register group, and then, when the register group to be selected by the register group selecting means is switched by the register group switching means, the data is written. 2. The data writing method according to claim 1, wherein the constant-speed data is written in common to the registers of the other register group, and thereafter, the data is not written to each register group until a command to stop the stepping motor is issued. Slow-up / down control device for stepping motor.