JP2003197966A - Gallium nitride-based compound semiconductor element - Google Patents

Gallium nitride-based compound semiconductor element

Info

Publication number
JP2003197966A
JP2003197966A JP2001392002A JP2001392002A JP2003197966A JP 2003197966 A JP2003197966 A JP 2003197966A JP 2001392002 A JP2001392002 A JP 2001392002A JP 2001392002 A JP2001392002 A JP 2001392002A JP 2003197966 A JP2003197966 A JP 2003197966A
Authority
JP
Japan
Prior art keywords
compound semiconductor
gallium nitride
based compound
electrode
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001392002A
Other languages
Japanese (ja)
Inventor
Susumu Nishimura
晋 西村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Tottori Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Tottori Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP2001392002A priority Critical patent/JP2003197966A/en
Publication of JP2003197966A publication Critical patent/JP2003197966A/en
Pending legal-status Critical Current

Links

Abstract

<P>PROBLEM TO BE SOLVED: To provide a gallium nitride-based compound semiconductor element that can be improved in light emitting efficiency and yield. <P>SOLUTION: In the gallium nitride-based compound semiconductor element, an Au electrode 9 is formed on the upper surface of a wafer provided with a gallium nitride-based compound semiconductor layer 4 having a p-n junction on the upper surface of a sapphire substrate 2. In addition, an Al/Si/Ni/Au electrode 10 is formed on the lower surface of the wafer so that the electrode 10 may come into contact with at least a part of the semiconductor layer 4 exposed by removing an arbitrary portion of the sapphire substrate 2 from the lower surface to the semiconductor layer 4. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、窒化ガリウム系化
合物半導体素子に関し、基板に絶縁性基板、例えばサフ
ァイア基板を用いている窒化ガリウム系化合物半導体素
子に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gallium nitride compound semiconductor device, and more particularly to a gallium nitride compound semiconductor device using an insulating substrate, for example, a sapphire substrate.

【0002】[0002]

【従来の技術】従来のサファイア基板を用いた窒化ガリ
ウム系化合物半導体素子としては、図6に示すようなも
のが一般的である。
2. Description of the Related Art A conventional gallium nitride-based compound semiconductor device using a sapphire substrate is shown in FIG.

【0003】この窒化ガリウム系化合物半導体素子10
1の製造手順について説明する。まず、サファイア基板
102上に、所定の膜圧でn型GaNバッファ層103、
n型窒化ガリウム系化合物半導体層104、n型Ga1-yA
lyN(0<y<1)クラッド層105、n型InzGa1-zN(0<z<1)活
性層106、p型Ga1-xAlxN(0<x<0.5)クラッド層10
7、p型GaN層コンタクト層108を順に積層してウェ
ーハを作製する。
This gallium nitride compound semiconductor device 10
The manufacturing procedure of No. 1 will be described. First, on the sapphire substrate 102, the n-type GaN buffer layer 103 with a predetermined film pressure,
n-type gallium nitride compound semiconductor layer 104, n-type Ga 1-y A
l y N (0 <y <1) cladding layer 105, n-type In z Ga 1-z N (0 <z <1) active layer 106, p-type Ga 1-x Al x N (0 <x <0.5) Clad layer 10
7 and the p-type GaN layer contact layer 108 are sequentially stacked to produce a wafer.

【0004】そして、ウェーハの上面からp型コンタク
ト層108、p型クラッド層107、n型活性層106
及びn型クラッド層105の一部を接合方向にエッチン
グして、ウェーハの上面側にn型窒化ガリウム系化合物
半導体層104を露出させる。
Then, from the top surface of the wafer, the p-type contact layer 108, the p-type cladding layer 107, and the n-type active layer 106 are formed.
Also, a part of the n-type cladding layer 105 is etched in the bonding direction to expose the n-type gallium nitride compound semiconductor layer 104 on the upper surface side of the wafer.

【0005】その後、p型コンタクト層108上にp側
のAu電極109、n型窒化ガリウム系化合物半導体層1
04上にn側のAl電極110をそれぞれ透明電極として
設けることにより、窒化ガリウム系化合物半導体素子1
01が完成する。この際、一対の電極109,110は
電流拡散を考慮し、図7のようにウェーハ上面の対角線
上もしくは図8のように対面に相当する位置に配置され
るのが通常である。
After that, on the p-type contact layer 108, the p-side Au electrode 109 and the n-type gallium nitride compound semiconductor layer 1 are formed.
By providing Al electrodes 110 on the n-side as transparent electrodes on 04, gallium nitride-based compound semiconductor device 1
01 is completed. At this time, the pair of electrodes 109 and 110 are usually arranged on a diagonal line on the upper surface of the wafer as shown in FIG. 7 or at a position corresponding to the opposite surface as shown in FIG. 8 in consideration of current diffusion.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、このよ
うな窒化ガリウム系化合物半導体素子101の構造は、
次のような問題を引き起こす。即ち、発光素子において
は、ウェーハ下面(従って、サファイア基板102の下
面)側への発光漏れ、受光素子においては、サファイア
基板102の下面側への透過ロスを生じてしまう。
However, the structure of such a gallium nitride-based compound semiconductor device 101 is as follows.
It causes the following problems. That is, in the light emitting element, light emission leaks to the lower surface of the wafer (hence, the lower surface of the sapphire substrate 102) side, and in the light receiving element, transmission loss to the lower surface side of the sapphire substrate 102 occurs.

【0007】また、ウェーハ上面にn側とp側の双方の
電極109,110を設けているので、有効な発光領域
もしくは受光領域が狭くなり、それぞれの効率が低下し
てしまうという問題があった。しかも、ウェーハ上面側
の静電耐圧が非常に低くなり、組立工程においても、歩
留まりの低下を招いてしまう。さらに、組立の最終工程
で電極109,110のそれぞれに2本の配線をつなぐ
必要があり、作業工程が多く製造に手間がかかるという
問題もあった。
Further, since both the n-side and p-side electrodes 109 and 110 are provided on the upper surface of the wafer, the effective light emitting region or light receiving region is narrowed, and there is a problem that the efficiency of each is lowered. . In addition, the electrostatic breakdown voltage on the upper surface side of the wafer becomes extremely low, and the yield is reduced in the assembly process. Further, it is necessary to connect two wires to each of the electrodes 109 and 110 in the final step of assembly, and there is a problem that there are many working steps and manufacturing is troublesome.

【0008】ところで、この窒化ガリウム系化合物半導
体素子101は、図9に示すように、フレーム111に
ボンディングすることにより、発光デバイスに加工され
ることがある。この場合、ウェーハ上面の段差のある2
つの電極109,110を金バンプ112を介してフレ
ーム111上に直接ボンディングする必要があるため、
高精度の組立技術が必要となる。それにともない、組立
における歩留まりが低下し、製品単価の高騰を招いてし
まう。
By the way, the gallium nitride-based compound semiconductor element 101 may be processed into a light emitting device by bonding it to a frame 111 as shown in FIG. In this case, there are two
Since it is necessary to directly bond the two electrodes 109 and 110 to the frame 111 via the gold bumps 112,
Highly accurate assembly technology is required. Along with that, the yield in the assembly is lowered, and the unit price of the product is soared.

【0009】さらに、フレーム111上における窒化ガ
リウム系化合物半導体素子101の位置ずれも起こりや
すく、品質の低下にもつながる。しかも、前述のよう
に、電流拡散を考慮して、n側とp側の電極109,1
10を対角線上もしくは対面位置に近接して配置してい
るため、ボンディングの時、マイグレーション等を誘発
しやすく、さらに品質を低下させる原因になっていた。
Further, the gallium nitride-based compound semiconductor device 101 is likely to be displaced on the frame 111, which leads to deterioration in quality. Moreover, as described above, in consideration of current diffusion, the electrodes 109 and 1 on the n-side and the p-side are formed.
Since 10 is arranged on a diagonal line or close to the facing position, migration or the like is easily induced during bonding, which further causes deterioration of quality.

【0010】本発明は、このような問題に鑑みてなされ
たものであり、発光効率の向上と歩留まりの上昇が見込
まれる窒化ガリウム系化合物半導体素子を提供すること
を目的とする。
The present invention has been made in view of the above problems, and an object of the present invention is to provide a gallium nitride-based compound semiconductor device which is expected to have improved luminous efficiency and increased yield.

【0011】[0011]

【課題を解決するための手段】上記目的を達成するため
に本発明の窒化ガリウム系化合物半導体素子は、絶縁性
基板上にp−n接合を有する窒化ガリウム系化合物半導
体層を備えたウェーハの上面に正又は負の電極を形成す
るとともに、前記絶縁性基板の下面の任意の箇所が前記
窒化ガリウム系化合物半導体層に達する深さまで除去さ
れ、それによって露出した窒化ガリウム系化合物半導体
層部分に少なくとも一部が接触するように負又は正の電
極を前記ウェーハの下面に形成したことを特徴としてい
る。
In order to achieve the above object, a gallium nitride compound semiconductor device of the present invention is an upper surface of a wafer provided with a gallium nitride compound semiconductor layer having a pn junction on an insulating substrate. A positive or negative electrode is formed on the insulating substrate, and any part of the lower surface of the insulating substrate is removed to a depth reaching the gallium nitride compound semiconductor layer, thereby exposing at least one part of the exposed gallium nitride compound semiconductor layer portion. The negative or positive electrode is formed on the lower surface of the wafer so that the parts contact each other.

【0012】この構成によると、p−n接合面に対して
垂直な方向から電流注入が行われるため、電流の流れが
スムーズになり、窒化ガリウム系化合物半導体素子の発
光効率もしくは受光効率が良くなる。
According to this structure, since the current is injected from the direction perpendicular to the pn junction surface, the current flow becomes smooth and the luminous efficiency or the light receiving efficiency of the gallium nitride compound semiconductor device is improved. .

【0013】また本発明は、前記ウェーハの下面に形成
された電極が、前記絶縁性基板の全面積の50%以上を覆
っていることを特徴としている。
Further, the present invention is characterized in that the electrodes formed on the lower surface of the wafer cover 50% or more of the total area of the insulating substrate.

【0014】この構成によると、ウェーハの下面の電極
が反射膜もしくは透過阻止膜としても機能し、ウェーハ
上面の発光効率もしくは受光効率がさらに向上する。
With this structure, the electrode on the lower surface of the wafer also functions as a reflection film or a transmission blocking film, and the light emission efficiency or the light reception efficiency on the upper surface of the wafer is further improved.

【0015】なお、前記絶縁性基板としては、サファイ
ア基板を好適に使用することができる。
A sapphire substrate can be preferably used as the insulating substrate.

【0016】[0016]

【発明の実施の形態】以下に本発明の実施形態を説明す
る。図1は、窒化ガリウム系化合物半導体素子を示す断
面図である。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. FIG. 1 is a sectional view showing a gallium nitride-based compound semiconductor device.

【0017】この窒化ガリウム系化合物半導体素子1の
製造手順について図1を参照して説明する。まず、絶縁
性基板としてのサファイア基板2を反応管内において、
クリーニングを行った後、成長温度を510℃とし、キャ
リアガスとして水素、原料ガスとしてアンモニアとトリ
メチルガリウム(TMG)を用い、サファイア基板2上
にGaNバッファ層3を約200オングストローム成長させ
る。GaNバッファ層3の形成後、TMGのみ留め、温度
を1030℃まで上昇させる。1030℃において原料ガスとし
てTMGとアンモニアガス、ドーパントガスとしてシラ
ンガスを用い、Siをドープしたn型GaN層4を4μm成長
させる。Siドープn型GaN層4を形成後、原料ガス、ド
ーパントガスを留め、温度を800℃にして、原料ガスと
してTMGとTMA(トリメチルアルミニウム)とアン
モニアガス、ドーパントガスとしてシランガスを用い、
n型クラッド層としてSiドープn型Ga0.85Al0.14N層5
を0.15μm成長させる。
A procedure for manufacturing the gallium nitride-based compound semiconductor device 1 will be described with reference to FIG. First, in the reaction tube, the sapphire substrate 2 as an insulating substrate is
After cleaning, the growth temperature is set to 510 ° C., hydrogen is used as a carrier gas, ammonia and trimethylgallium (TMG) are used as a source gas, and a GaN buffer layer 3 is grown on the sapphire substrate 2 by about 200 angstroms. After forming the GaN buffer layer 3, only TMG is stopped and the temperature is raised to 1030 ° C. At 1030 ° C., TMG and ammonia gas are used as a source gas, and silane gas is used as a dopant gas, and an n-type GaN layer 4 doped with Si is grown to 4 μm. After forming the Si-doped n-type GaN layer 4, the source gas and the dopant gas are stopped, the temperature is set to 800 ° C., TMG and TMA (trimethylaluminum) and ammonia gas are used as the source gas, and silane gas is used as the dopant gas.
Si-doped n-type Ga 0.85 Al 0.14 N layer 5 as the n-type cladding layer
Are grown to 0.15 μm.

【0018】次に、原料ガス、ドーパントガスを留め、
温度を800℃にして、キャリアガスを窒素に切替え、原
料ガスとしてTMGとTMI(トリメチルインジウム)
とアンモニアガス、ドーパントガスとしてシランガスを
用い、n型活性層としてSiドープn型In0.01Ga0.99N層6
を100オングストローム成長させる。更に、原料ガス、
ドーパントガスを留め、再び1020℃まで上昇させ、原料
ガスとしてTMGとTMAとアンモニアガス、ドーパン
トガスとしてCp2Mg(ジシクロペンチルマグネシウム)
を用い、p型クラッド層としてMgドープp型Ga0.85Al
0.14N層7を0.15μm成長させる。そして、TMAを留
め、p型コンタクト層として、Mgドープp型GaN層8を
0.4μm成長させる。
Next, the source gas and the dopant gas are stopped,
The temperature is set to 800 ° C, the carrier gas is switched to nitrogen, and TMG and TMI (trimethylindium) are used as raw material gases.
And ammonia gas, silane gas as dopant gas, and Si-doped n-type In 0.01 Ga 0.99 N layer 6 as n-type active layer 6
Grow 100 Angstroms. In addition, raw material gas,
Stop the dopant gas, raise it to 1020 ℃ again, and use TMG, TMA and ammonia gas as the source gas and Cp 2 Mg (dicyclopentyl magnesium) as the dopant gas.
Mg-doped p-type Ga 0.85 Al as a p-type cladding layer
A 0.14 N layer 7 is grown to 0.15 μm. Then, the TMA is stopped and the Mg-doped p-type GaN layer 8 is used as the p-type contact layer.
Grow 0.4 μm.

【0019】次いで、このサファイア基板2を反応管よ
り取り出し、アニーリング装置にて窒素雰囲気中、700
℃、20分間アニーリングを行い、Mgドープp型Ga0.85Al
0.14N層7とMgドープp型GaN層8の低抵抗化を行う。
Next, the sapphire substrate 2 was taken out from the reaction tube and was annealed at 700 ° C. in a nitrogen atmosphere.
Annealed at ℃ for 20 minutes, Mg-doped p-type Ga 0.85 Al
The resistance of the 0.14 N layer 7 and the Mg-doped p-type GaN layer 8 is reduced.

【0020】このようにして得られたウェーハ上面(従
って、Mgドープp型GaN層8の上面)にAu電極9を一方
(正)の電極として形成する。その後、ウェーハの下面
(従って、サファイア基板2の下面)をレーザー照射な
どにより部分的にエッチングし、Siドープn型GaN層4
に達する深さまでサファイア基板2及びGaNバッファ層
3を除去し、Siドープn型GaN層4を露出させる。その
後、ウェーハ下面にAl/Si/Ni/Au電極10を他方(負)
の電極として形成する。このとき、少なくとも露出した
Siドープn型GaN層4が被覆されるようにする。
On the upper surface of the wafer thus obtained (therefore, the upper surface of the Mg-doped p-type GaN layer 8), the Au electrode 9 is formed as one (positive) electrode. After that, the lower surface of the wafer (hence, the lower surface of the sapphire substrate 2) is partially etched by laser irradiation or the like, and the Si-doped n-type GaN layer 4 is formed.
The sapphire substrate 2 and the GaN buffer layer 3 are removed to a depth reaching 1 to expose the Si-doped n-type GaN layer 4. After that, the Al / Si / Ni / Au electrode 10 is placed on the other side (negative) on the lower surface of the wafer.
Is formed as an electrode. At this time, at least exposed
The Si-doped n-type GaN layer 4 is covered.

【0021】さらに、500℃で再度アニーリングを行
い、Al/Si/Ni/Au電極10とSiドープn型GaN層4とをな
じませる。最後に、このウェーハ−電極一体品をチップ
にカットし、窒化ガリウム系化合物半導体素子1が完成
する。
Further, annealing is performed again at 500 ° C. to make the Al / Si / Ni / Au electrode 10 and the Si-doped n-type GaN layer 4 conform to each other. Finally, this wafer-electrode integrated product is cut into chips to complete the gallium nitride-based compound semiconductor device 1.

【0022】図2にサファイア基板2の中央部の一部を
円形に除去し、電極10を形成した例の窒化ガリウム系
化合物半導体素子1の下面図を示す。この図2は、図1に
示す素子の下面図に相当する。
FIG. 2 is a bottom view of a gallium nitride-based compound semiconductor device 1 in which a part of the central portion of the sapphire substrate 2 is circularly removed to form the electrode 10. This FIG. 2 corresponds to a bottom view of the device shown in FIG.

【0023】次に。図3に数カ所で円形にサファイア基
板2を除去し、電極10を形成した例の窒化ガリウム系
化合物半導体素子1の下面図を示す。このようにすれ
ば、電極10に複数の凹凸が形成されるので、光を広範
囲に反射することができる。また、電極10と層4との
接触個所を複数形成することができ、電気的な接続を確
実にすることができる。
Next, FIG. 3 shows a bottom view of the gallium nitride-based compound semiconductor device 1 of the example in which the electrode 10 is formed by removing the sapphire substrate 2 in a circular shape at several places. By doing so, since a plurality of irregularities is formed on the electrode 10, light can be reflected in a wide range. Further, a plurality of contact points between the electrode 10 and the layer 4 can be formed, so that electrical connection can be ensured.

【0024】そして、図4に十字にサファイア基板2を
除去し、電極10を形成した例の窒化ガリウム系化合物
半導体素子1の下面図を示す。このような形状であれ
ば、レーザー照射以外にも、ダイシングによって基板2
を除去することができ、複数の製造方法に対応すること
ができる。
Then, FIG. 4 shows a bottom view of the gallium nitride-based compound semiconductor device 1 of the example in which the electrode 10 is formed by removing the sapphire substrate 2 in a cross shape. With such a shape, the substrate 2 can be formed by dicing in addition to laser irradiation.
Can be removed, and a plurality of manufacturing methods can be supported.

【0025】いずれの場合も、ウェーハ下面の電極10
は、サファイア基板2の全面積の50%以上を覆うように
設けられている。したがって、ウェーハの下面側に向か
う光の大部分が電極10に反射され、ウェーハ上面側か
ら効率良く発光させることができる。
In any case, the electrode 10 on the lower surface of the wafer
Are provided so as to cover 50% or more of the entire area of the sapphire substrate 2. Therefore, most of the light traveling toward the lower surface of the wafer is reflected by the electrode 10, and light can be efficiently emitted from the upper surface of the wafer.

【0026】図5は、上記の窒化ガリウム系化合物半導
体素子1をフレーム11上に搭載した発光デバイスを示
す断面図である。このデバイスの製造手順としては、ま
ず、窒化ガリウム系化合物半導体素子1を導電性接着剤
13によりフレーム11上に接着し、ウェーハ上面の電
極9とフレームリード12とを配線14により接続す
る。最後に、透明樹脂(図示せず)等によりモールドさ
れ、発光デバイスが完成する。
FIG. 5 is a sectional view showing a light emitting device in which the gallium nitride compound semiconductor element 1 is mounted on a frame 11. As a manufacturing procedure of this device, first, the gallium nitride-based compound semiconductor element 1 is adhered onto the frame 11 with the conductive adhesive 13, and the electrode 9 on the upper surface of the wafer and the frame lead 12 are connected with the wiring 14. Finally, a light emitting device is completed by molding with a transparent resin (not shown) or the like.

【0027】したがって、この発光デバイスの組立に必
要な配線14は1本で済み、作業工数を削減できる。ま
た、発光効率に関しても、ウェーハ上面には電極9が1
つとなり、発光領域が実質的に拡大する。しかも、電流
注入がp−n接合面に対して垂直な方向から起こり、効
率良く活性層であるSiドープn型In0.01Ga0.99N層6に
電流注入することが可能となり、それにともない、静電
耐圧も向上する。さらに、発光した光は、サファイア基
板2の下面に形成した電極10により反射され、ウェー
ハ上面側へ光の取り出しが効率良く行え、発光デバイス
全体の発光効率がさらに向上することになる。
Therefore, only one wiring 14 is required for assembling this light emitting device, and the number of working steps can be reduced. Also, regarding the luminous efficiency, the electrode 9 is 1 on the upper surface of the wafer.
As a result, the light emitting region is substantially expanded. Moreover, current injection occurs from the direction perpendicular to the pn junction surface, and it becomes possible to efficiently inject current into the Si-doped n-type In 0.01 Ga 0.99 N layer 6 which is the active layer, and accordingly, the electrostatic discharge. Withstand voltage is also improved. Further, the emitted light is reflected by the electrode 10 formed on the lower surface of the sapphire substrate 2, the light can be efficiently extracted to the upper surface side of the wafer, and the light emitting efficiency of the entire light emitting device is further improved.

【0028】なお、上記の説明では、基板としてサファ
イヤを用いたが、本発明は比較的抵抗が大きくて絶縁性
を示す炭化ケイ素(SiC)などの半導体基板や、他の
絶縁基板を用いる場合にも適用することができる。
Although sapphire is used as the substrate in the above description, the present invention is applicable to the case where a semiconductor substrate such as silicon carbide (SiC) having a relatively large resistance and exhibiting an insulating property or another insulating substrate is used. Can also be applied.

【0029】また、上記の説明では発光素子を例に説明
したが、本発明は受光素子においても同様の効果が得ら
れる。また、本発明は、基板上に形成する半導体とし
て、窒化ガリウム系化合物半導体素子以外の化合物半導
体素子を用いる場合にも適用することができる。
Further, although the light emitting element has been described as an example in the above description, the same effect can be obtained in the light receiving element according to the present invention. The present invention can also be applied to the case where a compound semiconductor element other than a gallium nitride-based compound semiconductor element is used as the semiconductor formed on the substrate.

【0030】[0030]

【発明の効果】以上説明したように本発明の窒化ガリウ
ム系化合物半導体素子によると、ウェーハ上面の発光領
域が実質的に拡大するとともに、電流注入をp−n接合
面に対して垂直な方向から効率良く行える。
As described above, according to the gallium nitride compound semiconductor device of the present invention, the light emitting region on the upper surface of the wafer is substantially expanded, and the current injection is performed from the direction perpendicular to the pn junction surface. It can be done efficiently.

【0031】また、ウェーハの下面側の電極は、サファ
イア基板の全面積の50%以上を覆うように設けているの
で、下面側に向かう光の大部分が電極に反射され、ウェ
ーハ上面から効率良く発光させることができる。
Further, since the electrode on the lower surface side of the wafer is provided so as to cover 50% or more of the total area of the sapphire substrate, most of the light traveling toward the lower surface side is reflected by the electrode, and the upper surface of the wafer is efficiently supplied. It can emit light.

【0032】そして、この窒化ガリウム系化合物半導体
素子をフレーム等に装着したデバイスでは、組立に必要
な配線は1本で済むため、作業工数が削減され、製品単
価の低減と歩留まりの上昇が見込まれる。
In the device in which the gallium nitride-based compound semiconductor element is mounted on the frame or the like, only one wiring is required for assembling, so that the number of work steps can be reduced, the unit price of the product can be reduced, and the yield can be increased. .

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明に係る窒化ガリウム系化合物半導体素
子を示す断面図である。
FIG. 1 is a cross-sectional view showing a gallium nitride-based compound semiconductor device according to the present invention.

【図2】 同上窒化ガリウム系化合物半導体素子のファ
イア基板の一部を円形に除去し、電極を形成した例を示
す下面図である。
FIG. 2 is a bottom view showing an example in which an electrode is formed by removing a part of a fire substrate of a gallium nitride-based compound semiconductor device in the same manner as above.

【図3】 同上窒化ガリウム系化合物半導体素子のファ
イア基板の数カ所を円形に除去し、電極を形成した例を
示す下面図である。
FIG. 3 is a bottom view showing an example in which electrodes are formed by circularly removing several places of the fire substrate of the gallium nitride-based compound semiconductor device.

【図4】 同上窒化ガリウム系化合物半導体素子のサフ
ァイア基板を十字に除去し、電極を形成した例を示す下
面図である。
FIG. 4 is a bottom view showing an example in which an electrode is formed by removing the sapphire substrate of the gallium nitride-based compound semiconductor device in a cross shape in the same manner.

【図5】 同上窒化ガリウム系化合物半導体素子をフレ
ーム上に搭載した発光デバイスを示す断面図である。
FIG. 5 is a cross-sectional view showing a light emitting device in which a gallium nitride compound semiconductor element is mounted on a frame.

【図6】 従来の一般的なサファイア基板を用いた窒化
ガリウム系化合物半導体素子の断面図である。
FIG. 6 is a cross-sectional view of a gallium nitride-based compound semiconductor device using a conventional general sapphire substrate.

【図7】 同上窒化ガリウム系化合物半導体素子のウェ
ーハ上面の対角線上に一対の電極を配置した例を示す平
面図である。
FIG. 7 is a plan view showing an example in which a pair of electrodes are arranged on a diagonal line on the upper surface of the wafer of the same gallium nitride-based compound semiconductor device.

【図8】 同上窒化ガリウム系化合物半導体素子のウェ
ーハ上面の対面に相当する位置に一対の電極を配置した
例を示す平面図である。
FIG. 8 is a plan view showing an example in which a pair of electrodes are arranged at positions corresponding to the upper surface of the wafer of the gallium nitride-based compound semiconductor device.

【図9】 同上窒化ガリウム系化合物半導体素子をフレ
ームに装着した発光デバイスを示す断面図である。
FIG. 9 is a cross-sectional view showing a light emitting device in which a gallium nitride compound semiconductor element is mounted on a frame.

【符号の説明】[Explanation of symbols]

1 窒化ガリウム系化合物半導体素子 2 サファイア基板 3 GaNバッファ層 4 Siドープn型GaN層(窒化ガリウム系化合物半導
体層) 5 Siドープn型Ga0.85Al0.14N層 6 Siドープn型In0.01Ga0.99N層 7 Mgドープp型Ga0.85Al0.14N層 8 Mgドープp型GaN層 9 Au電極 10 Al/Si/Ni/Au電極
1 gallium nitride-based compound semiconductor device 2 sapphire substrate 3 GaN buffer layer 4 Si-doped n-type GaN layer (gallium nitride-based compound semiconductor layer) 5 Si-doped n-type Ga 0.85 Al 0.14 N layer 6 Si-doped n-type In 0.01 Ga 0.99 N Layer 7 Mg-doped p-type Ga 0.85 Al 0.14 N layer 8 Mg-doped p-type GaN layer 9 Au electrode 10 Al / Si / Ni / Au electrode

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5F041 AA03 CA12 CA40 CA57 CA75 CA85 CA92 CA93 CB15 5F045 AA04 AB14 AB17 AC08 AC12 AC19 AD09 AD12 AD14 AF04 AF05 AF09 HA13 HA16    ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F041 AA03 CA12 CA40 CA57 CA75                       CA85 CA92 CA93 CB15                 5F045 AA04 AB14 AB17 AC08 AC12                       AC19 AD09 AD12 AD14 AF04                       AF05 AF09 HA13 HA16

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性基板上にp−n接合を有する窒化
ガリウム系化合物半導体層を備えたウェーハの上面に正
又は負の電極を形成するとともに、前記絶縁性基板の下
面の任意の箇所が前記窒化ガリウム系化合物半導体層に
達する深さまで除去され、それによって露出した窒化ガ
リウム系化合物半導体層部分に少なくとも一部が接触す
るように負又は正の電極を前記ウェーハの下面に形成し
たことを特徴とする窒化ガリウム系化合物半導体素子。
1. A positive or negative electrode is formed on the upper surface of a wafer having a gallium nitride-based compound semiconductor layer having a pn junction on the insulating substrate, and an arbitrary portion of the lower surface of the insulating substrate is formed. The negative or positive electrode is formed on the lower surface of the wafer so that the negative electrode is removed to a depth reaching the gallium nitride compound semiconductor layer, and at least a portion of the gallium nitride compound semiconductor layer exposed by the gallium nitride compound semiconductor layer is in contact therewith. Gallium nitride compound semiconductor device.
【請求項2】 前記ウェーハの下面に形成された電極
が、前記絶縁性基板の全面積の50%以上を覆っているこ
とを特徴とする請求項1に記載の窒化ガリウム系化合物
半導体素子。
2. The gallium nitride-based compound semiconductor device according to claim 1, wherein the electrode formed on the lower surface of the wafer covers 50% or more of the total area of the insulating substrate.
【請求項3】 前記絶縁性基板にサファイア基板を用い
たことを特徴とする請求項1又は2に記載の窒化ガリウ
ム系化合物半導体素子。
3. The gallium nitride-based compound semiconductor device according to claim 1, wherein a sapphire substrate is used as the insulating substrate.
JP2001392002A 2001-12-25 2001-12-25 Gallium nitride-based compound semiconductor element Pending JP2003197966A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001392002A JP2003197966A (en) 2001-12-25 2001-12-25 Gallium nitride-based compound semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001392002A JP2003197966A (en) 2001-12-25 2001-12-25 Gallium nitride-based compound semiconductor element

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Publication Number Publication Date
JP2003197966A true JP2003197966A (en) 2003-07-11

Family

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Family Applications (1)

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Country Status (1)

Country Link
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100638823B1 (en) 2005-05-19 2006-10-27 삼성전기주식회사 Vertical nitride light emitting diode and a method of producing the same
KR101125339B1 (en) 2006-02-14 2012-03-27 엘지이노텍 주식회사 Nitride compound based light-emitting semiconductor and fabricating method thereof
US8168996B2 (en) 2006-04-17 2012-05-01 Nichia Corporation Semiconductor light emitting device
KR101229830B1 (en) * 2006-04-14 2013-02-04 서울옵토디바이스주식회사 Light emitting diode for an alternating current and method for fabricating the same
JP2017534185A (en) * 2014-11-06 2017-11-16 コーニンクレッカ フィリップス エヌ ヴェKoninklijke Philips N.V. Light emitting device having a trench below the top contact

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100638823B1 (en) 2005-05-19 2006-10-27 삼성전기주식회사 Vertical nitride light emitting diode and a method of producing the same
KR101125339B1 (en) 2006-02-14 2012-03-27 엘지이노텍 주식회사 Nitride compound based light-emitting semiconductor and fabricating method thereof
US8368111B2 (en) 2006-02-14 2013-02-05 Lg Innotek Co., Ltd. Semiconductor light emitting device and method for manufacturing thereof
US8659051B2 (en) 2006-02-14 2014-02-25 Lg Innotek Co., Ltd. Semiconductor light emitting device and method for manufacturing thereof
KR101229830B1 (en) * 2006-04-14 2013-02-04 서울옵토디바이스주식회사 Light emitting diode for an alternating current and method for fabricating the same
US8168996B2 (en) 2006-04-17 2012-05-01 Nichia Corporation Semiconductor light emitting device
US8362516B2 (en) 2006-04-17 2013-01-29 Nichia Corporation Semiconductor light emitting device
JP2017534185A (en) * 2014-11-06 2017-11-16 コーニンクレッカ フィリップス エヌ ヴェKoninklijke Philips N.V. Light emitting device having a trench below the top contact

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