JP2003194882A - Ａｃ結合システムにおいてｅｘｔｅｓｔを実施可能にするための装置 - Google Patents

Ａｃ結合システムにおいてｅｘｔｅｓｔを実施可能にするための装置

Info

Publication number
JP2003194882A
JP2003194882A JP2002312482A JP2002312482A JP2003194882A JP 2003194882 A JP2003194882 A JP 2003194882A JP 2002312482 A JP2002312482 A JP 2002312482A JP 2002312482 A JP2002312482 A JP 2002312482A JP 2003194882 A JP2003194882 A JP 2003194882A
Authority
JP
Japan
Prior art keywords
jtag
signal
logic circuit
receiving
extest
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002312482A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003194882A5 (enExample
Inventor
Charles E Moore
チャールズ・イー・ムーア
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of JP2003194882A publication Critical patent/JP2003194882A/ja
Publication of JP2003194882A5 publication Critical patent/JP2003194882A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318577—AC testing, e.g. current testing, burn-in
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2002312482A 2001-11-01 2002-10-28 Ａｃ結合システムにおいてｅｘｔｅｓｔを実施可能にするための装置 Pending JP2003194882A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/035,654 2001-11-01
US10/035,654 US6662134B2 (en) 2001-11-01 2001-11-01 Method and apparatus for enabling extests to be performed in AC-coupled systems

Publications (2)

Publication Number Publication Date
JP2003194882A true JP2003194882A (ja) 2003-07-09
JP2003194882A5 JP2003194882A5 (enExample) 2005-10-27

Family

ID=21883980

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002312482A Pending JP2003194882A (ja) 2001-11-01 2002-10-28 Ａｃ結合システムにおいてｅｘｔｅｓｔを実施可能にするための装置

Country Status (4)

Country Link
US (1) US6662134B2 (enExample)
JP (1) JP2003194882A (enExample)
DE (1) DE10241389A1 (enExample)
SG (1) SG107102A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100838808B1 (ko) 2006-11-14 2008-06-17 주식회사 준마엔지니어링 제이테그를 이용한 테스트 시스템 및 그 제어방법

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6763486B2 (en) * 2001-05-09 2004-07-13 Agilent Technologies, Inc. Method and apparatus of boundary scan testing for AC-coupled differential data paths
US6813737B1 (en) * 2001-10-31 2004-11-02 Cisco Technology, Inc. Short circuited capacitor detection in AC coupled links using boundary scan test methodology
US7089463B1 (en) * 2002-02-20 2006-08-08 Cisco Technology Inc. Test buffer design and interface mechanism for differential receiver AC/DC boundary scan test
US7877652B1 (en) * 2003-03-31 2011-01-25 Qualcomm Incorporated Detection circuit and method for AC coupled circuitry
US7222278B2 (en) * 2003-09-17 2007-05-22 Avago Technologies General Ip (Singapore) Pte. Ltd. Programmable hysteresis for boundary-scan testing
US7149943B2 (en) * 2004-01-12 2006-12-12 Lucent Technologies Inc. System for flexible embedded Boundary Scan testing
CN103426288A (zh) * 2012-05-15 2013-12-04 苏州工业园区新宏博通讯科技有限公司 多功能交流电能采集终端
CN103424636A (zh) * 2012-05-15 2013-12-04 苏州工业园区新宏博通讯科技有限公司 多功能交直流电能采集终端
CN112285446B (zh) * 2019-07-12 2024-05-31 瑞昱半导体股份有限公司 执行多种测试的测试系统、传送装置与接收装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3372052B2 (ja) * 1991-06-06 2003-01-27 テキサス インスツルメンツ インコーポレイテツド 境界走査集積回路
US5497378A (en) * 1993-11-02 1996-03-05 International Business Machines Corporation System and method for testing a circuit network having elements testable by different boundary scan standards
US6000051A (en) * 1997-10-10 1999-12-07 Logic Vision, Inc. Method and apparatus for high-speed interconnect testing
US6601189B1 (en) * 1999-10-01 2003-07-29 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6594802B1 (en) * 2000-03-23 2003-07-15 Intellitech Corporation Method and apparatus for providing optimized access to circuits for debug, programming, and test

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100838808B1 (ko) 2006-11-14 2008-06-17 주식회사 준마엔지니어링 제이테그를 이용한 테스트 시스템 및 그 제어방법

Also Published As

Publication number Publication date
SG107102A1 (en) 2004-11-29
US20030083841A1 (en) 2003-05-01
DE10241389A1 (de) 2003-05-22
US6662134B2 (en) 2003-12-09

Similar Documents

Publication Publication Date Title
US5134314A (en) Automatic pin circuitry shutoff for an integrated circuit
EP1064560B1 (en) Compensating for the effects of round-trip delay in automatic test equipment
JP2004135337A (ja) バウンダリ・スキャン・テスト技法と協働するｓｅｒｄｅｓ
JP2003194882A (ja) Ａｃ結合システムにおいてｅｘｔｅｓｔを実施可能にするための装置
GB2100448A (en) Digital in-circuit tester
US6763486B2 (en) Method and apparatus of boundary scan testing for AC-coupled differential data paths
DE60021129D1 (de) Verfahren und Vorrichtung zur Prüfung einer elektronischen Vorrichtung
EP1014582A1 (en) Digital signal transmitter and receiver using source based reference logic levels
US6255843B1 (en) Semiconductor integrated circuit testing apparatus and composite semiconductor integrated circuit testing apparatus
US4973904A (en) Test circuit and method
US6877121B1 (en) Boundary scan cell for testing AC coupled line using phase modulation technique
EP0685075B1 (en) Device for testing connections provided with pulling resistors
US20030212843A1 (en) Method and apparatus for selectively providing data pre-emphasis based upon data content history
JP2001281304A (ja) 半導体装置およびそのテスト方式
US20020172159A1 (en) Receiver-end supplementary circuit for boundary scan in data transmission with differential signals
JP3109329B2 (ja) クランプ回路およびこれを用いたｉｃテスタ
US6119256A (en) Apparatus for testing a fixed logic value interconnection between integrated circuits
JP3025551B2 (ja) 直流特性試験回路
US6496544B1 (en) Digital computing system having adaptive communication components
US6988207B2 (en) Scan insertion testing of ASICs
JP3179773B2 (ja) 半導体試験装置
JPH0843488A (ja) 半導体試験装置
US7511506B2 (en) Semiconductor testing system and testing method
KR100492911B1 (ko) 출력 버퍼 전류를 자동적으로 제어하기 위한 장치, 그제어 방법 및 이를 이용한 집적회로
JP2003344492A (ja) Ｉｃテスタのアダプタ装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050906

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050906

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20060629

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20060913

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061129

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20071106

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080221

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080226

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20080715