JP2003179176A - Wiring board - Google Patents

Wiring board

Info

Publication number
JP2003179176A
JP2003179176A JP2001379150A JP2001379150A JP2003179176A JP 2003179176 A JP2003179176 A JP 2003179176A JP 2001379150 A JP2001379150 A JP 2001379150A JP 2001379150 A JP2001379150 A JP 2001379150A JP 2003179176 A JP2003179176 A JP 2003179176A
Authority
JP
Japan
Prior art keywords
region
connection pad
wiring
layer
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001379150A
Other languages
Japanese (ja)
Other versions
JP3808357B2 (en
Inventor
Hidenori Tanaka
秀憲 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001379150A priority Critical patent/JP3808357B2/en
Publication of JP2003179176A publication Critical patent/JP2003179176A/en
Application granted granted Critical
Publication of JP3808357B2 publication Critical patent/JP3808357B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that a wiring board cannot be bonded rigidly to an external electric circuit board due to the solder creeping up. <P>SOLUTION: The wiring board 7 comprises an insulating substrate 1 having an electronic component mounting part and a frame-like metal layer 3 surrounding the mounting part on the upper surface and a connection pad 4 at the outer circumferential part of the lower surface, and a castellation conductor 5 formed on the side face of the insulating substrate 1 and connecting the connection pad 4 with the frame-like metal layer 3. The castellation conductor 5 has a first region 5b being led out from the connection pad 4, and a second region 5c being led out from the frame-like metal layer 3 wherein the first region 5b and the second region 5c are shifted in the widthwise direction on the side face of the insulating substrate 1 and connected through a wiring layer 10 formed in the insulating substrate 1. Furthermore, a nickel layer 11 having mean crystal particle diameter of 100 nm or above is applied to the surface of the connection pad 4 and the first region 5b. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子や圧電
振動子等の電子部品を搭載するための配線基板に関する
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board for mounting electronic components such as semiconductor elements and piezoelectric vibrators.

【0002】[0002]

【従来の技術】従来、半導体素子や圧電振動子等の電子
部品を搭載するための配線基板は、一般に、略四角板状
のセラミックス材料から成り、上面に電子部品搭載部を
有する絶縁基体と、該絶縁基体の電子部品搭載部より絶
縁基体内部を介して側面に導出されている複数個の配線
層と、前記絶縁基体の上面で、前記電子部品搭載部を取
り囲むように形成されている枠状の金属層と、前記絶縁
基体の下面外周部に形成されている複数個の接続パッド
と、前記絶縁基体の側面に形成され、各配線層と各接続
パッドとを電気的に接続する複数個のキャスタレーショ
ン導体とにより構成されており、絶縁基体の電子部品搭
載部に電子部品を搭載するとともに、電子部品の信号
用、接地用等の各電極を各配線層にボンディングワイヤ
等の導電性接続部材を介して電気的に接続し、しかる
後、絶縁基体上面の枠状金属層に電子部品を覆うように
して鉄−ニッケル−コバルト合金や鉄−ニッケル合金等
から成る金属製の蓋体をロウ材等を介して接合し電子部
品を封止することによって電子装置となる。
2. Description of the Related Art Conventionally, a wiring board for mounting electronic components such as semiconductor elements and piezoelectric vibrators is generally made of a substantially rectangular plate-shaped ceramic material, and an insulating substrate having an electronic component mounting portion on its upper surface. A plurality of wiring layers led out from the electronic component mounting portion of the insulating substrate to the side surface through the inside of the insulating substrate, and a frame shape formed so as to surround the electronic component mounting portion on the upper surface of the insulating substrate. A metal layer, a plurality of connection pads formed on the outer peripheral surface of the lower surface of the insulating base, and a plurality of connection pads formed on the side surface of the insulating base for electrically connecting each wiring layer and each connection pad. An electronic component is mounted on the electronic component mounting portion of the insulating base, and each electrode for signal and ground of the electronic component is connected to each wiring layer by a conductive connecting member such as a bonding wire. After that, the metal lid made of iron-nickel-cobalt alloy or iron-nickel alloy is brazed to the frame-shaped metal layer on the upper surface of the insulating substrate so as to cover the electronic parts. An electronic device is obtained by joining the components through the above and sealing the electronic component.

【0003】かかる電子装置は、絶縁基体下面の外周部
に形成した接続パッドとキャスタレーション導体の一部
を外部電気回路基板の配線導体に錫−鉛半田等の半田を
介し接続することによって外部電気回路基板に実装さ
れ、同時に電子部品の各電極は配線層とキャスタレーシ
ョン導体と接続パッドとを介して外部電気回路に電気的
に接続されることとなる。
In such an electronic device, a connection pad formed on the outer peripheral portion of the lower surface of the insulating substrate and a part of the castellation conductor are connected to a wiring conductor of an external electric circuit board through solder such as tin-lead solder or the like. The electrodes of the electronic component are mounted on the circuit board, and at the same time, the electrodes of the electronic component are electrically connected to the external electric circuit via the wiring layer, the castellation conductor, and the connection pads.

【0004】なお、前記キャスタレーション導体のう
ち、少なくとも電子部品の接地用の電極が接続されるも
の(通常、全接続パッド中約20〜50%)は、一部が
絶縁基体上面に形成されている枠状の金属層まで導出さ
れており、枠状金属層を接地できるようになっている。
Of the castellation conductors, at least the electrode for grounding the electronic component is connected (usually about 20 to 50% of all the connection pads), a part of which is formed on the upper surface of the insulating substrate. The frame-shaped metal layer is also led out so that the frame-shaped metal layer can be grounded.

【0005】また前記各キャスタレーション導体は絶縁
基体の側面に垂直方向に形成されており、枠状金属層と
接続されるキャスタレーション導体は絶縁基体の側面で
下面部から上面部にかけて形成されている。
The castellation conductors are formed vertically on the side surfaces of the insulating base, and the castellation conductors connected to the frame-shaped metal layer are formed on the side surfaces of the insulating base from the lower surface to the upper surface. .

【0006】更に前記各接続パッドおよびキャスタレー
ション導体の表面には、通常、半田との接続強度を高く
するために、ニッケル層がめっき用電力の供給を不要と
する無電解法によって被着形成されており、かかるニッ
ケル層は無電解めっき液中の還元剤の分解生成物である
ホウ素成分やリン成分の共析によりニッケルの結晶成長
が阻害されて結晶の平均粒径が20nm未満の小さいも
のになっている。
Further, a nickel layer is usually deposited and formed on the surface of each of the connection pads and the castellation conductor by an electroless method that does not require supply of plating power in order to increase the connection strength with solder. The nickel layer has a small average grain size of less than 20 nm because the nickel crystal growth is hindered by the co-deposition of the boron component and the phosphorus component which are decomposition products of the reducing agent in the electroless plating solution. Has become.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、近時、
各種電子装置は環境、人体に対する悪影響を防止するた
め従来使用されている錫−鉛半田に代わり、錫−銀−ビ
スマス系、錫−銀−銅−ビスマス系等、鉛を含有しな
い、いわゆる鉛フリー半田を用いて外部電気回路基板に
接続されるようになってきており、かかる鉛フリー半田
は、従来の錫−鉛半田に比べて溶融時に流れやすいため
電子装置を外部電気回路基板に実装するとき、半田がキ
ャスタレーション導体を伝って絶縁基体上面の枠状金属
層や枠状金属層に取着されている金属製蓋体にまで這い
上がり、その結果、絶縁基体の接続パッドと、外部電気
回路の配線導体との間に介在する半田の量が極めて少量
となり、電子装置を外部回路基板に強固に実装すること
ができないという欠点を有していた。
However, in recent years,
Various electronic devices do not contain lead, such as tin-silver-bismuth type and tin-silver-copper-bismuth type, so-called lead-free, instead of tin-lead solder that is conventionally used to prevent adverse effects on the environment and human body. It is becoming more common to use solder to connect to an external electric circuit board, and lead-free solder is more likely to flow when melted than conventional tin-lead solder, so when mounting electronic devices on an external electric circuit board. , The solder propagates along the castellation conductor and crawls up to the frame-shaped metal layer on the upper surface of the insulating substrate or the metal lid attached to the frame-shaped metal layer, and as a result, the connection pad of the insulating substrate and the external electric circuit. However, the amount of solder intervening between the wiring conductor and the wiring conductor is extremely small, so that the electronic device cannot be firmly mounted on the external circuit board.

【0008】また錫−銀−ビスマス系等の鉛フリー半田
は、従来の錫−鉛半田に比べて、ビスマス等の成分が偏
析し易いこと、接続パッドやキャスタレーション導体の
表面被着形成されているニッケル層の結晶の平均粒径が
20nm未満と小さくビスマスとの反応性が低いこと、
配線基板の小型化により接続パッドおよびキャスタレー
ション導体も小さくなり、半田接合の面積が小さくなっ
てきていること等から、外部電気回路基板の配線導体に
電子装置の接続パッドとキャスタレーション導体の一部
を錫−銀−ビスマス系等の鉛フリー半田を介して接続し
た際、鉛フリー半田のビスマス等の成分が偏析して接続
が弱いものとなり、その結果、電子装置と外部電気回路
基板とに熱が作用し、電子装置の絶縁基体と外部電気回
路基板との間に両者の熱膨張係数の相違に起因する熱応
力が発生した場合、この熱応力によって鉛フリー半田が
接続パッドやキャスタレーション導体より剥離してしま
い、電子装置の外部回路基板に対する接続信頼性が低い
ものとなってしまう欠点も有していた。
In addition, lead-free solder such as tin-silver-bismuth-based solder tends to segregate components such as bismuth as compared with conventional tin-lead solder, and is formed on the surface of the connection pad or castellation conductor. The average grain size of the crystals of the nickel layer is as small as less than 20 nm and the reactivity with bismuth is low,
The size of the wiring board has reduced the size of the connection pads and castellation conductors, and the area of solder joints has become smaller. When lead-free solder such as tin-silver-bismuth-based solder is connected, the components such as bismuth of the lead-free solder segregate and the connection becomes weak.As a result, heat is generated between the electronic device and the external electric circuit board. When a thermal stress occurs due to the difference in thermal expansion coefficient between the insulating base of the electronic device and the external electric circuit board, the thermal stress causes lead-free solder to move from the connection pad or castellation conductor. There is also a disadvantage that the reliability of the connection of the electronic device to the external circuit board is low due to peeling.

【0009】本発明は、上記欠点に鑑み案出されたもの
であり、その目的は、接続パッドを外部電気回路基板の
配線導体に鉛フリー半田を介して強固に接合し、それに
より外部電気回路基板に強固にかつ高信頼性で実装する
ことが可能な配線基板を提供することにある。
The present invention has been devised in view of the above-mentioned drawbacks, and an object thereof is to firmly bond a connection pad to a wiring conductor of an external electric circuit board via lead-free solder, whereby an external electric circuit is formed. An object of the present invention is to provide a wiring board that can be mounted on the board firmly and with high reliability.

【0010】[0010]

【課題を解決するための手段】本発明は、上面に電子部
品搭載部および該搭載部を取り囲む枠状の金属層を有
し、下面の外周部に接続パッドを有する絶縁基体と、前
記絶縁基体の側面に形成され、前記接続パッドと枠状の
金属層とを接続するキャスタレーション導体とを具備す
る配線基板であって、前記キャスタレーション導体は接
続パッドから導出する第1領域と、枠状の金属層から導
出する第2領域とから成り、前記第1領域と第2領域は
絶縁基体側面の幅方向に位置がずれているとともに前記
絶縁基体内部に形成された内部配線層を介して接続され
ており、かつ前記接続パッドおよび/または第1領域の
表面に、結晶の平均粒径が100nm以上のニッケル層
が被着されていることを特徴とするものである。
According to the present invention, there is provided an insulating base having an electronic component mounting portion and a frame-shaped metal layer surrounding the mounting portion on an upper surface and a connection pad on an outer peripheral portion of a lower surface, and the insulating base. And a castellation conductor formed on the side surface of the connection pad for connecting the connection pad and the frame-shaped metal layer, wherein the castellation conductor has a first region extending from the connection pad and a frame-shaped A second region extending from the metal layer, wherein the first region and the second region are misaligned in the width direction of the side surface of the insulating base and are connected via an internal wiring layer formed inside the insulating base. And a nickel layer having an average crystal grain size of 100 nm or more is deposited on the surface of the connection pad and / or the first region.

【0011】また本発明の配線基板は、前記接続パッド
および/または第1領域の表面に被着したニッケル層の
厚さが2μm以上であることを特徴とするものである。
Further, the wiring board of the present invention is characterized in that the thickness of the nickel layer deposited on the surface of the connection pad and / or the first region is 2 μm or more.

【0012】本発明の配線基板によれば、絶縁基体上面
に形成されている枠状金属層と絶縁基体下面に形成され
ている接続パッドとを電気的に接続するキャスタレーシ
ョン導体を、接続パッドから導出する第1領域と、金属
層から導出する第2領域とにより構成するとともに、前
記第1領域と第2領域を絶縁基体側面の幅方向に位置を
ずらせたことから接続パッドと外部電気回路の配線導体
とを鉛フリー半田を用いて接続したとしても、鉛フリー
半田がキャスタレーション導体を伝って枠状金属層や金
属製蓋体にまで這い上がることはなく、その結果、接続
パッドと外部電気回路基板の配線導体との間に十分な量
の半田を介在させることができ、配線基板(電子装置)
を外部電気回路基板に極めて強固に接続することができ
る。
According to the wiring board of the present invention, the castellation conductor for electrically connecting the frame-shaped metal layer formed on the upper surface of the insulating base and the connection pad formed on the lower surface of the insulating base is provided from the connection pad. The connecting pad and the external electric circuit are composed of the first region to be led out and the second region to be led out from the metal layer, and the first region and the second region are displaced in the width direction of the side surface of the insulating substrate. Even if the lead conductor is connected to the wiring conductor using lead-free solder, the lead-free solder does not crawl up through the castellation conductor to the frame-shaped metal layer or metal lid, and as a result, the connection pad and external electrical A sufficient amount of solder can be interposed between the wiring conductor of the circuit board and the wiring board (electronic device).
Can be connected extremely firmly to the external electric circuit board.

【0013】また、本発明の配線基板によれば、接続パ
ッドおよび/またはキャスタレーション導体の第1領域
の表面に、結晶の平均粒径を100nm以上とし鉛フリ
ー半田中のビスマス成分との反応性を良くしたニッケル
層を、例えば2μm以上の厚に被着させたことから接続
パッドと該接続パッドから導出するキャスタレーション
導体の第1領域の表面とを外部電気回路の配線導体に鉛
フリー半田を用いて接続した際、鉛フリー半田中のビス
マス成分が偏析しようとしても、このビスマス成分はニ
ッケルとの間で金属間化合物を生成しビスマス成分が効
果的に吸収されて偏析が有効に防止され、その結果、配
線基板の接続パッド及びキャスタレーション導体の第1
領域と外部電気回路基板の配線導体とは錫−銀−ビスマ
ス系等の鉛フリー半田を介して強固に接続され、配線基
板と外部電気回路基板に熱が作用し、両者間に両者の熱
膨張係数の相違に起因する熱応力が発生したとしても該
熱応力によって鉛フリー半田が接続パッドやキャスタレ
ーション導体より剥離することはなく、接続パッドを外
部電気回路基板の配線導体に強固に、かつ高信頼性で接
続させることが可能となる。
Further, according to the wiring board of the present invention, on the surface of the first region of the connection pad and / or the castellation conductor, the average grain size of the crystal is 100 nm or more and the reactivity with the bismuth component in the lead-free solder is provided. The nickel layer having improved heat resistance is deposited to a thickness of, for example, 2 μm or more, so that the connection pad and the surface of the first region of the castellation conductor derived from the connection pad are lead-free soldered to the wiring conductor of the external electric circuit. When connected using, even if the bismuth component in the lead-free solder tries to segregate, this bismuth component forms an intermetallic compound with nickel and the bismuth component is effectively absorbed and segregation is effectively prevented, As a result, the connection pads of the wiring board and the first of the castellation conductors are
The area and the wiring conductor of the external electric circuit board are firmly connected via lead-free solder such as tin-silver-bismuth system, heat is applied to the wiring board and the external electric circuit board, and thermal expansion of both occurs. Even if thermal stress is generated due to the difference in the coefficient, the lead-free solder is not separated from the connection pad or the castellation conductor by the thermal stress, and the connection pad is firmly and highly connected to the wiring conductor of the external electric circuit board. It is possible to connect with reliability.

【0014】[0014]

【発明の実施の形態】次に、本発明を添付図面に基づき
詳細に説明する。図1(a)乃至(c)は、本発明の配
線基板を半導体素子を収容する半導体素子収納用パッケ
ージに適用した場合の一実施例を示し、1は絶縁基体、
2は配線層、3は枠状金属層、4は接続パッド、5はキ
ャスタレーション導体である。この絶縁基体1、配線層
2、枠状金属層3、接続パッド4及びキャスタレーショ
ン導体5により半導体素子6を搭載するための配線基板
7が形成される。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the accompanying drawings. 1 (a) to 1 (c) show an embodiment in which the wiring board of the present invention is applied to a semiconductor element housing package for housing a semiconductor element, 1 is an insulating base,
Reference numeral 2 is a wiring layer, 3 is a frame-shaped metal layer, 4 is a connection pad, and 5 is a castellation conductor. The insulating substrate 1, the wiring layer 2, the frame-shaped metal layer 3, the connection pads 4, and the castellation conductors 5 form a wiring board 7 for mounting the semiconductor element 6.

【0015】前記絶縁基体1は、酸化アルミニウム質焼
結体、窒化アルミニウム質焼結体、ムライト質焼結体、
ガラスセラミック焼結体等の電気絶縁材料から成り、そ
の上面に半導体素子6を搭載する搭載部を有し、該搭載
部に半導体素子6がガラス、樹脂、ロウ材等の接着材を
介して接着固定される。
The insulating substrate 1 is made of an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body,
It is made of an electrically insulating material such as a glass ceramic sintered body, and has a mounting portion on which the semiconductor element 6 is mounted, and the semiconductor element 6 is bonded to the mounting portion via an adhesive material such as glass, resin, or brazing material. Fixed.

【0016】前記絶縁基体1は、例えば、酸化アルミニ
ウム質焼結体から成る場合には、酸化アルミニウム、酸
化珪素、酸化カルシウム、酸化マグネシウム等の原料粉
末に適当な有機バインダー、溶剤を添加混合して泥漿状
のセラミックスラリーとなし、次に前記セラミックスラ
リーを従来周知のドクターブレード法やカレンダーロー
ル法等のシート成形技術によりシート状となして所定形
状のセラミックグリーンシート(セラミック生シート)
を得る、最後に前記セラミックグリーンシートを複数枚
積層するとともに還元雰囲気中、約1600℃の温度で
焼成することによって製作される。
When the insulating substrate 1 is made of, for example, an aluminum oxide sintered body, an appropriate organic binder and solvent are added to and mixed with raw material powders of aluminum oxide, silicon oxide, calcium oxide, magnesium oxide and the like. A ceramic green sheet (ceramic green sheet) which is not formed into a slurry-like ceramic slurry, and is then formed into a sheet shape by a conventionally known sheet forming technique such as a doctor blade method or a calendar roll method.
Finally, a plurality of the ceramic green sheets are laminated and fired at a temperature of about 1600 ° C. in a reducing atmosphere.

【0017】また前記絶縁基体1はその上面の半導体素
子6が搭載される搭載部周囲から絶縁基体1の内部を介
し側面にかけて複数個の配線層2が形成されており、該
配線層2は半導体素子6の信号用、接地用の各電極を接
続パッド4に接続するための導電路として作用し、搭載
部側の一端には半導体素子6の信号用、接地用等の電極
がボンディングワイヤ8を介して電気的に接続される。
A plurality of wiring layers 2 are formed on the upper surface of the insulating substrate 1 from around the mounting portion on which the semiconductor element 6 is mounted to the side surface through the inside of the insulating substrate 1 and the wiring layer 2 is a semiconductor. The signal and ground electrodes of the element 6 act as conductive paths for connecting to the connection pads 4, and the signal and ground electrodes of the semiconductor element 6 have bonding wires 8 at one end on the mounting portion side. Electrically connected via.

【0018】前記配線層2はタングステン、モリブデ
ン、マンガン、銅、銀、金、パラジウム等の金属粉末か
ら成り、タングステン等の金属粉末に適当な有機バイン
ダーや溶剤を添加混合して得た金属ペーストを絶縁基体
1となるセラミックグリーンシートに予め従来周知のス
クリーン印刷法により所定パターンに印刷塗布しておく
ことによって絶縁基体1の上面から絶縁基体1の内部を
介し側面にかけて被着形成される。
The wiring layer 2 is made of metal powder such as tungsten, molybdenum, manganese, copper, silver, gold and palladium. A metal paste obtained by adding and mixing a suitable organic binder or solvent to the metal powder such as tungsten. The ceramic green sheet to be the insulating substrate 1 is printed and applied in advance in a predetermined pattern by a conventionally known screen printing method, so that the ceramic green sheet is adhered and formed from the upper surface of the insulating substrate 1 to the side surface through the inside of the insulating substrate 1.

【0019】また前記絶縁基体1はその上面で、半導体
素子6が搭載される搭載部を取り囲むようにして枠状の
金属層3が被着されており、該枠状の金属層3は後述す
る金属製蓋体9を絶縁基体1に取着させる際の下地金属
層として作用し、タングステン、モリブデン、マンガ
ン、銅、銀、金、パラジウム等の金属粉末により形成さ
れている。
A frame-shaped metal layer 3 is deposited on the upper surface of the insulating substrate 1 so as to surround a mounting portion on which the semiconductor element 6 is mounted. The frame-shaped metal layer 3 will be described later. It acts as a base metal layer when attaching the metallic lid 9 to the insulating substrate 1, and is formed of a metal powder such as tungsten, molybdenum, manganese, copper, silver, gold, or palladium.

【0020】前記枠状金属層3には金属製蓋体9が金−
錫等のロウ材を介してロウ付け取着され、これによって
絶縁基体1の半導体素子搭載部に搭載されている半導体
素子6は大気から気密に封止されることとなる。
The frame-shaped metal layer 3 has a metal lid 9 made of gold.
The semiconductor element 6 mounted on the semiconductor element mounting portion of the insulating substrate 1 is hermetically sealed from the atmosphere by being brazed and attached via a brazing material such as tin.

【0021】なお、前記枠状金属層3は前述の配線層2
と同様の方法によって絶縁基体1の上面で、半導体素子
搭載部を取り囲むように形成される。
The frame-shaped metal layer 3 is the wiring layer 2 described above.
It is formed on the upper surface of the insulating base 1 so as to surround the semiconductor element mounting portion by a method similar to.

【0022】更に前記絶縁基体1の下面外周部には複数
個の接続パッド4が形成されており、該接続パッド4は
外部電気回路基板の配線導体に鉛フリー半田を介して接
続され、半導体素子6の信号用、接地用の各電極を外部
電気回路に電気的に接続する作用をなす。
Further, a plurality of connecting pads 4 are formed on the outer peripheral portion of the lower surface of the insulating substrate 1, and the connecting pads 4 are connected to the wiring conductors of the external electric circuit board via lead-free solder, and the semiconductor element is formed. 6 serves to electrically connect the signal and ground electrodes 6 to an external electric circuit.

【0023】前記接続パッド4は、タングステン、モリ
ブデン、マンガン、銅、銀、金、パラジウム等の金属粉
末より成り、前述の配線層2と同様の方法によって絶縁
基体1の下面外周部に所定形状に形成される。
The connection pad 4 is made of metal powder such as tungsten, molybdenum, manganese, copper, silver, gold, palladium, etc. It is formed.

【0024】また更に前記絶縁基体1はその側面に複数
個のキャスタレーション導体5(絶縁基体1の側面に断
面半円状の凹部を設け、該凹部内に形成されている導
体)が被着されており、該キャスタレーション導体5は
配線層2と接続パッド4とを電気的に接続する作用をな
す。
Further, a plurality of castellation conductors 5 (conductors formed in the recesses having a semicircular cross section on the side surfaces of the insulating base 1 and formed in the recesses) are attached to the side surface of the insulating base 1. The castellation conductor 5 serves to electrically connect the wiring layer 2 and the connection pad 4.

【0025】前記キャスタレーション導体5はタングス
テン、モリブデン、マンガン、銅、銀、金、パラジウム
等の金属粉末より成り、絶縁基体1となるセラミックグ
リーンシートの側面に打ち抜き加工法により半円形の凹
部を形成するとともに該凹部内にタングステン等の金属
粉末に適当な有機バインダーや溶剤を添加混合して得た
金属ペーストを予め従来周知のスクリーン印刷法により
所定パターンに印刷塗布しておくことによって絶縁基体
1の側面に所定形状に形成される。
The castellation conductor 5 is made of a metal powder such as tungsten, molybdenum, manganese, copper, silver, gold, palladium, etc., and a semicircular recess is formed on the side surface of the ceramic green sheet to be the insulating substrate 1 by a punching method. In addition, a metal paste obtained by adding and mixing a suitable organic binder or solvent to a metal powder such as tungsten is mixed and printed in a predetermined pattern by a conventionally known screen printing method in the concave portion of the insulating substrate 1. The side surface is formed in a predetermined shape.

【0026】前記キャスタレーション導体5はまた半導
体素子6の接地用の電極と導通する配線層2に接続され
るものについては一部が絶縁基体1上面の枠状金属層3
にまで導出されており、枠状金属層3を接地するように
なっている。
The castellation conductor 5 is partially connected to the wiring layer 2 which is electrically connected to the ground electrode of the semiconductor element 6, and a part thereof is the frame-shaped metal layer 3 on the upper surface of the insulating substrate 1.
And the frame-shaped metal layer 3 is grounded.

【0027】なお、前記配線層2および枠状の金属層3
は、その露出する表面に、ニッケル、金等の耐蝕性やボ
ンディングワイヤ8のボンディング性、ロウ材の濡れ性
等が良好な金属から成るめっき層を被着させておくと配
線層2や枠状の金属層3等の酸化腐食を有効に防止する
ことができるとともに枠状金属層3への金属製蓋体9の
取着等が確実、強固となる。従って、前記配線層2およ
び枠状の金属層3は、その露出する表面に、ニッケル、
金等の耐蝕性やボンディング性、ロウ材の濡れ性等が良
好な金属をめっき法により被着させておくことが好まし
く、特に、例えば、厚さ1〜10μmのニッケルめっき
層、0.05〜3μmの厚さの金めっき層を順次被着さ
せておくことが好ましい。
The wiring layer 2 and the frame-shaped metal layer 3
The wiring layer 2 or the frame-like structure is formed by depositing a plating layer made of a metal having good corrosion resistance such as nickel or gold, bonding property of the bonding wire 8 and wettability of the brazing material on the exposed surface. It is possible to effectively prevent the oxidative corrosion of the metal layer 3 and the like, and securely and firmly attach the metal lid 9 to the frame-shaped metal layer 3. Therefore, the wiring layer 2 and the frame-shaped metal layer 3 have nickel, nickel,
It is preferable to deposit a metal having good corrosion resistance such as gold, bonding property, and wettability of a brazing material by a plating method. Particularly, for example, a nickel plating layer having a thickness of 1 to 10 μm, 0.05 to It is preferable to successively deposit a gold plating layer having a thickness of 3 μm.

【0028】この場合、金めっき層の厚みは、被着する
部位や金めっき層の結晶配向等に応じて異なる厚みとし
てもよく、例えば、金めっき層のX線回折における結晶
配向を極力(111)面に揃えるようにするとともに、
ボンディングワイヤ8が接続される領域も含め、全域で
約0.3〜1μmとするようにしてもよく、ロウ付け用
の領域のみ約0.3μm以下の薄いものとし、錫−金の
脆い金属間化合物の生成を抑えてロウ付けの信頼性をよ
り一層高めるようにしてもよい。
In this case, the thickness of the gold plating layer may be different depending on the part to be deposited, the crystal orientation of the gold plating layer, etc. For example, the crystal orientation in the X-ray diffraction of the gold plating layer is (111) as much as possible. ) Make sure that it is aligned with the surface,
The entire area including the area to which the bonding wire 8 is connected may be set to about 0.3 to 1 μm, and only the brazing area should be thin, about 0.3 μm or less. It is also possible to suppress the formation of the compound and further improve the reliability of brazing.

【0029】かくして本発明の配線基板7によれば、絶
縁基体1上面の搭載部に半導体素子6を搭載するととも
に半導体素子6の信号用、接地用の各電極を配線層2に
ボンディングワイヤ8を介して接続し、しかる後、絶縁
基体1上面の枠状金属層3に鉄−ニッケル−コバルト合
金や鉄−ニッケル合金等からなる金属製蓋体9をロウ材
等を介して接合させ、金属製蓋体9で半導体素子6を気
密に封止することによって製品としての電子装置(半導
体装置)が完成する。
Thus, according to the wiring board 7 of the present invention, the semiconductor element 6 is mounted on the mounting portion on the upper surface of the insulating substrate 1, and the signal and ground electrodes of the semiconductor element 6 are provided with the bonding wires 8 on the wiring layer 2. After that, a metal lid 9 made of an iron-nickel-cobalt alloy, an iron-nickel alloy or the like is joined to the frame-shaped metal layer 3 on the upper surface of the insulating substrate 1 via a brazing material, An electronic device (semiconductor device) as a product is completed by hermetically sealing the semiconductor element 6 with the lid 9.

【0030】かかる半導体装置は絶縁基体1下面外周部
の接続パッド4を外部電気回路基板の配線導体に鉛フリ
ー半田を介して接続することによって外部電気回路基板
上に実装され、同時に半導体素子6の信号用、接地用の
各電極が外部電気回路基板の配線導体に電気的に接続さ
れる。
The semiconductor device is mounted on the external electric circuit board by connecting the connection pads 4 on the outer peripheral surface of the lower surface of the insulating substrate 1 to the wiring conductors of the external electric circuit board via lead-free solder, and at the same time, the semiconductor element 6 is mounted. The signal and ground electrodes are electrically connected to the wiring conductors of the external electric circuit board.

【0031】本発明の配線基板7においてはキャスタレ
ーション導体5のうち枠状金属層3と接続パッド4とを
接続しているキャスタレーション導体5aを図2に示す
ように接続パッド4から導出する第1領域5bと、枠状
の金属層3から導出する第2領域5cとに分け、第1領
域5bと第2領域5cとを絶縁基体1側面の幅方向に位
置をずらせておくとともに絶縁基体1内部で内部配線層
10を介して電気的に接続しておくことが重要である。
In the wiring board 7 of the present invention, of the castellation conductors 5, the castellation conductors 5a connecting the frame-shaped metal layer 3 and the connection pads 4 are led out from the connection pads 4 as shown in FIG. The first region 5b is divided into the first region 5b and the second region 5c derived from the frame-shaped metal layer 3, and the first region 5b and the second region 5c are displaced in the width direction of the side surface of the insulating substrate 1 and the insulating substrate 1 is formed. It is important to be electrically connected internally via the internal wiring layer 10.

【0032】前記枠状金属層3と接続パッド4とを接続
しているキャスタレーション導体5aを接続パッド4か
ら導出する第1領域5bと、枠状金属層3から導出する
第2領域5cとに分け、各々を絶縁基体1側面の幅方向
に位置をずらせておくと接続パッド4と外部電気回路の
配線導体とを鉛フリー半田を用いて接続したとしても、
鉛フリー半田がキャスタレーション導体を伝って枠状金
属層3や金属製蓋体9にまで這い上がることはなく、そ
の結果、接続パッド4と外部電気回路基板の配線導体と
の間に十分な量の半田を介在させることができ、配線基
板(電子装置)を外部電気回路基板に極めて強固に接続
することができる。
The castellation conductor 5a connecting the frame-shaped metal layer 3 and the connection pad 4 is divided into a first region 5b extending from the connection pad 4 and a second region 5c extending from the frame-shaped metal layer 3. Separately, if the respective positions are shifted in the width direction of the side surface of the insulating substrate 1, even if the connection pad 4 and the wiring conductor of the external electric circuit are connected by using lead-free solder,
The lead-free solder does not reach the frame-shaped metal layer 3 and the metal lid 9 along the castellation conductor, and as a result, a sufficient amount is provided between the connection pad 4 and the wiring conductor of the external electric circuit board. The solder can be interposed, and the wiring board (electronic device) can be connected extremely firmly to the external electric circuit board.

【0033】なお、前記枠状金属層3と接続パッド4と
を接続しているキャスタレーション導体5aの第1領域
5bと第2領域5cとの分割位置は、使用する半田の種
類や、絶縁基体1の厚さ、配線層2の設計上の都合等に
応じて適宜決めるようにすればよく、例えば、キャスタ
レーション導体5aが直径0.3mm〜0.7mmの半
円状で、半田として錫−銀−ビスマス系半田を用いる場
合であれば、第1領域5bの長さを0.3mm〜1mm
の範囲とすればよい。
The division position between the first region 5b and the second region 5c of the castellation conductor 5a connecting the frame-shaped metal layer 3 and the connection pad 4 is determined by the type of solder used and the insulating substrate. The thickness of the wiring layer 2 and the design convenience of the wiring layer 2 may be appropriately determined. For example, the castellation conductor 5a has a semi-circular shape with a diameter of 0.3 mm to 0.7 mm, and tin is used as solder. If silver-bismuth solder is used, set the length of the first region 5b to 0.3 mm to 1 mm.
The range may be.

【0034】また本発明においては図3に示すごとく、
接続パッド4および/またはキャスタレーション導体5
のうち接続パッド4から導出する第1領域5bの表面
に、結晶の平均粒径が100nm以上のニッケル層11
を被着させておくことが重要である。
In the present invention, as shown in FIG.
Connection pad 4 and / or castellation conductor 5
Of the nickel layer 11 having an average crystal grain size of 100 nm or more on the surface of the first region 5b derived from the connection pad 4
It is important to keep it on.

【0035】このように接続パッド4やキャスタレーシ
ョン導体5の第1領域5bの表面に結晶の平均粒径が1
00nm以上と大きいニッケル層11を被着形成してお
くと該結晶の平均粒径が大きいニッケル層11は接続パ
ッド4と該接続パッド4から導出するキャスタレーショ
ン導体5の第1領域5bの表面とを外部電気回路の配線
導体に鉛フリー半田を用いて接続する際、鉛フリー半田
中のビスマス成分が偏析しようとしても、このビスマス
成分はニッケルとの間で金属間化合物を生成しビスマス
成分が効果的に吸収されて偏析が有効に防止され、その
結果、配線基板7の接続パッド4及びキャスタレーショ
ン導体5の第1領域5bと外部電気回路基板の配線導体
とは錫−銀−ビスマス系等の鉛フリー半田を介して強固
に接続され、配線基板7と外部電気回路基板に熱が作用
し、両者間に両者の熱膨張係数の相異に起因する熱応力
が発生したとしても該熱応力によって鉛フリー半田が接
続パッド4やキャスタレーション導体5の第1領域5b
より剥離することはなく、接続パッド4を外部電気回路
基板の配線導体に強固に、かつ高信頼性で接続させるこ
とが可能となる。
Thus, the average grain size of the crystal is 1 on the surface of the connection pad 4 and the first region 5b of the castellation conductor 5.
When the nickel layer 11 having a large size of 00 nm or more is deposited, the nickel layer 11 having a large average grain size of the crystal is formed on the surface of the connection pad 4 and the surface of the first region 5b of the castellation conductor 5 derived from the connection pad 4. When the lead-free solder is connected to the wiring conductor of the external electric circuit using the bismuth component in the lead-free solder, the bismuth component forms an intermetallic compound with nickel and the bismuth component is effective. Are effectively absorbed and segregation is effectively prevented. As a result, the connection pad 4 of the wiring board 7 and the first region 5b of the castellation conductor 5 and the wiring conductor of the external electric circuit board are made of a tin-silver-bismuth system or the like. It is firmly connected via lead-free solder, heat acts on the wiring board 7 and the external electric circuit board, and thermal stress is generated between them due to the difference in thermal expansion coefficient between them. The first region 5b lead-free solder of the connection pads 4 and castellation conductor 5 by heat stress
The connection pad 4 can be firmly and highly reliably connected to the wiring conductor of the external electric circuit board without further peeling.

【0036】なお、前記結晶の平均粒径が100nm以
上のニッケル層11は、例えば、ホウ素系還元剤を使用
する無電解めっき法で粒径が100nm未満(通常は2
0nm未満)のニッケル層を接続パッド4およびキャス
タレーション導体5の表面に被着させた後、このニッケ
ル層を約800℃で熱処理し結晶を成長させること等に
よって形成することができる。
The nickel layer 11 having an average crystal grain size of 100 nm or more has a grain size of less than 100 nm (usually 2 nm by an electroless plating method using a boron-based reducing agent).
It can be formed by depositing a nickel layer (less than 0 nm) on the surfaces of the connection pad 4 and the castellation conductor 5 and then heat treating the nickel layer at about 800 ° C. to grow crystals.

【0037】また前記ニッケル層11は結晶の平均粒径
が100nm未満であると鉛フリー半田中のビスマス等
の成分の偏析を有効に防止することができず、接続パッ
ド4を外部電気回路基板の配線導体に強固に、かつ高信
頼性で接続させることができない。従って、前記ニッケ
ル層11は結晶の平均粒径が100nm以上のものに特
定される。特に、ニッケル層11の結晶の平均粒径を2
00〜4000nm(0.2μm〜4μm)の範囲とし
ておくと、結晶面がより大きくなると同時に適度に粒界
が存在して、より一層確実にビスマス成分を吸収するこ
とができるとともに前記粒界でニッケル層11の内部応
力を緩和して接続パッド4やキャスタレーション導体5
に対してニッケル層11をより一層強固に被着させるこ
とができる。従って、前記ニッケル層11は、結晶の平
均粒径を200nm〜4000nm(0.2μm〜4μ
m)の範囲とすることが好ましい。
If the average grain size of crystals of the nickel layer 11 is less than 100 nm, segregation of components such as bismuth in the lead-free solder cannot be effectively prevented, and the connection pad 4 of the external electric circuit board is prevented. It cannot be firmly and reliably connected to the wiring conductor. Therefore, the nickel layer 11 is specified to have an average crystal grain size of 100 nm or more. In particular, the average grain size of the crystals of the nickel layer 11 is set to 2
When it is set to be in the range of 00 to 4000 nm (0.2 μm to 4 μm), the crystal plane becomes larger and at the same time, grain boundaries are appropriately present, so that the bismuth component can be more surely absorbed and at the grain boundaries, nickel can be absorbed. The connection pad 4 and the castellation conductor 5 are relieved by relaxing the internal stress of the layer 11.
On the other hand, the nickel layer 11 can be applied more firmly. Therefore, the nickel layer 11 has an average crystal grain size of 200 nm to 4000 nm (0.2 μm to 4 μm).
The range of m) is preferable.

【0038】更に前記ニッケル層11は、その厚みを2
μm以上としておくと鉛フリー半田中のビスマス等の成
分とニッケル層11のニッケルとが良好に金属間化合物
を生成して、鉛フリー半田中のビスマス等の成分の偏析
を有効に防止することができ、これによって接続パッド
4を外部電気回路基板の配線導体に強固に、かつ高信頼
性で接続させることができる。従って、前記ニッケル層
11はその厚みを2μm以上としておくことが好まし
い。
Further, the nickel layer 11 has a thickness of 2
If it is set to be not less than μm, the components such as bismuth in the lead-free solder and nickel in the nickel layer 11 satisfactorily generate intermetallic compounds, and the segregation of the components such as bismuth in the lead-free solder can be effectively prevented. Therefore, the connection pad 4 can be firmly and highly reliably connected to the wiring conductor of the external electric circuit board. Therefore, it is preferable that the nickel layer 11 has a thickness of 2 μm or more.

【0039】また更に、前記ニッケル層11は、その露
出表面に金層(図示せず)を、例えば0.05〜3μm
の厚さで被着させておくと、酸化腐蝕を効果的に防止す
ることができ、鉛フリー半田等の接続の信頼性をより一
層良好にすることができる。従って、前記ニッケル層1
1は、その露出表面に金層を、例えば0.05〜3μm
の厚さで被着させておくことが好ましい。
Furthermore, the nickel layer 11 has a gold layer (not shown) on its exposed surface, for example, 0.05 to 3 μm.
If it is adhered with a thickness of 1, the oxidation and corrosion can be effectively prevented, and the reliability of connection of lead-free solder or the like can be further improved. Therefore, the nickel layer 1
1 is a gold layer on its exposed surface, for example 0.05-3 μm
It is preferable to apply the same thickness.

【0040】更にまた前記キャスタレーション導体5の
接続パッド4から導出する第1領域5bは、図4に示す
ように、その内側に突出する突出部12を形成しておけ
ば接続パッド4を外部電気回路基板の配線導体に半田を
介して接合するとき、前記突出部12が半田の中に食い
込むようにして接合されて接合強度がより一層強固とな
る。従って、前記キャスタレーション導体5の接続パッ
ド4から導出する第1領域5bは、図4に示すように、
その内側に突出する突出部12を形成しておくことが好
ましい。
Furthermore, as shown in FIG. 4, the first region 5b extending from the connection pad 4 of the castellation conductor 5 is formed with a protruding portion 12 protruding inward, so that the connection pad 4 is electrically connected to the outside. When the wiring conductors of the circuit board are joined via solder, the protrusions 12 are joined so as to dig into the solder, and the joining strength is further strengthened. Therefore, the first region 5b derived from the connection pad 4 of the castellation conductor 5 is, as shown in FIG.
It is preferable to form a protrusion 12 that protrudes inward.

【0041】なお、本発明は上述の実施例に限定される
ものではなく、本発明の要旨を逸脱しない範囲であれば
種々の変更は可能であり、例えば、上述の実施例では本
発明の配線基板を半導体素子を収容する半導体素子収納
用パッケージに適用したが、混成集積回路基板等の他の
用途に適用してもよい。
The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. For example, in the above-mentioned embodiments, the wiring of the present invention is used. Although the substrate is applied to the semiconductor element housing package that houses the semiconductor element, it may be applied to other applications such as a hybrid integrated circuit board.

【0042】[0042]

【発明の効果】本発明の配線基板によれば、絶縁基体上
面に形成されている枠状金属層と絶縁基体下面に形成さ
れている接続パッドとを電気的に接続するキャスタレー
ション導体を、接続パッドから導出する第1領域と、金
属層から導出する第2領域とにより構成するとともに、
前記第1領域と第2領域を絶縁基体側面の幅方向に位置
をずらせたことから接続パッドと外部電気回路の配線導
体とを鉛フリー半田を用いて接続したとしても、鉛フリ
ー半田がキャスタレーション導体を伝って枠状金属層や
金属製蓋体にまで這い上がることはなく、その結果、接
続パッドと外部電気回路基板の配線導体との間に十分な
量の半田を介在させることができ、配線基板(電子装
置)を外部電気回路基板に極めて強固に接続することが
できる。
According to the wiring board of the present invention, the castellation conductor for electrically connecting the frame-shaped metal layer formed on the upper surface of the insulating base and the connection pad formed on the lower surface of the insulating base is connected. The first region is derived from the pad and the second region is derived from the metal layer, and
Since the first region and the second region are displaced in the width direction of the side surface of the insulating substrate, the lead-free solder is castellated even if the connection pad and the wiring conductor of the external electric circuit are connected by using the lead-free solder. It does not crawl along the conductor to the frame-shaped metal layer or metal lid, and as a result, a sufficient amount of solder can be interposed between the connection pad and the wiring conductor of the external electric circuit board, The wiring board (electronic device) can be connected extremely firmly to the external electric circuit board.

【0043】また、本発明の配線基板によれば、接続パ
ッドおよび/またはキャスタレーション導体の第1領域
の表面に、結晶の平均粒径を100nm以上とし鉛フリ
ー半田中のビスマス成分との反応性を良くしたニッケル
層を、例えば2μm以上の厚に被着させたことから接続
パッドと該接続パッドから導出するキャスタレーション
導体の第1領域の表面とを外部電気回路の配線導体に鉛
フリー半田を用いて接続した際、鉛フリー半田中のビス
マス成分が偏析しようとしても、このビスマス成分はニ
ッケルとの間で金属間化合物を生成しビスマス成分が効
果的に吸収されて偏析が有効に防止され、その結果、配
線基板の接続パッド及びキャスタレーション導体の第1
領域と外部電気回路基板の配線導体とは錫−銀−ビスマ
ス系等の鉛フリー半田を介して強固に接続され、配線基
板と外部電気回路基板に熱が作用し、両者間に両者の熱
膨張係数の相異に起因する熱応力が発生したとしても該
熱応力によって鉛フリー半田が接続パッドやキャスタレ
ーション導体より剥離することはなく、接続パッドを外
部電気回路基板の配線導体に強固に、かつ高信頼性で接
続させることが可能となる。
Further, according to the wiring board of the present invention, on the surface of the first region of the connection pad and / or the castellation conductor, the average grain size of the crystal is 100 nm or more, and the reactivity with the bismuth component in the lead-free solder is obtained. The nickel layer having improved heat resistance is deposited to a thickness of, for example, 2 μm or more, so that the connection pad and the surface of the first region of the castellation conductor derived from the connection pad are lead-free soldered to the wiring conductor of the external electric circuit. When connected using, even if the bismuth component in the lead-free solder tries to segregate, this bismuth component forms an intermetallic compound with nickel and the bismuth component is effectively absorbed and segregation is effectively prevented, As a result, the connection pads of the wiring board and the first of the castellation conductors are
The area and the wiring conductor of the external electric circuit board are firmly connected via lead-free solder such as tin-silver-bismuth system, heat is applied to the wiring board and the external electric circuit board, and thermal expansion of both occurs. Even if a thermal stress caused by the difference in the coefficient is generated, the lead-free solder is not separated from the connection pad or the castellation conductor by the thermal stress, the connection pad is firmly attached to the wiring conductor of the external electric circuit board, and It is possible to connect with high reliability.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)(b)(c)は本発明の配線基板の一実
施例を示す側面図、平面図、底面図である。
1A, 1B and 1C are a side view, a plan view and a bottom view showing an embodiment of a wiring board of the present invention.

【図2】本発明の配線基板の要部拡大斜視図である。FIG. 2 is an enlarged perspective view of a main part of the wiring board of the present invention.

【図3】本発明の配線基板の要部拡大断面図である。FIG. 3 is an enlarged cross-sectional view of a main part of the wiring board of the present invention.

【図4】本発明の配線基板の他の実施例の要部拡大図で
ある。
FIG. 4 is an enlarged view of a main part of another embodiment of the wiring board according to the present invention.

【符号の説明】[Explanation of symbols]

1・・・・・絶縁基体 2・・・・・配線層 3・・・・・枠状の金属層 4・・・・・接続パッド 5・・・・・キャスタレーション導体 5a・・・・接続パッドと枠状金属層とを接続している
キャスタレーション導体 5b・・・・第1領域 5c・・・・第2領域 6・・・・・半導体素子 7・・・・・配線基板 8・・・・・ボンディングワイヤ 9・・・・・蓋体 10・・・・内部配線層 11・・・・ニッケル層 12・・・・突出部
1 ... Insulating substrate 2 ... Wiring layer 3 ... Frame-shaped metal layer 4 ... Connection pad 5 ... Castellation conductor 5a ... Castellation conductor 5b connecting the pad and the frame-shaped metal layer ... First region 5c ... Second region 6 ... Semiconductor element 7 ... Wiring substrate 8 ... ... Bonding wire 9 ... Lid 10 ... Internal wiring layer 11 ... Nickel layer 12 ... Projection

フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H05K 3/46 H01L 23/12 L Fターム(参考) 5E317 AA22 BB04 BB11 CC22 CC31 CC52 CD21 CD31 GG07 5E338 AA03 AA18 BB02 BB19 BB63 BB65 BB75 CC01 CC04 CC06 CD02 CD32 EE51 5E346 AA12 AA15 AA41 BB01 BB16 CC17 CC31 CC32 CC35 CC37 CC38 CC39 DD02 DD22 DD34 EE24 FF42 GG03 GG06 GG08 GG10 HH07 Front page continuation (51) Int.Cl. 7 Identification code FI theme code (reference) H05K 3/46 H01L 23/12 LF term (reference) 5E317 AA22 BB04 BB11 CC22 CC31 CC52 CD21 CD31 GG07 5E338 AA03 AA18 BB02 BB19 BB63 BB65 BB75 CC01 CC04 CC06 CD02 CD32 EE51 5E346 AA12 AA15 AA41 BB01 BB16 CC17 CC31 CC32 CC35 CC37 CC38 CC39 DD02 DD22 DD34 EE24 FF42 GG03 GG06 GG08 GG10 HH07

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】上面に電子部品搭載部および該搭載部を取
り囲む枠状の金属層を有し、下面の外周部に接続パッド
を有する絶縁基体と、前記絶縁基体の側面に形成され、
前記接続パッドと枠状の金属層とを接続するキャスタレ
ーション導体とを具備する配線基板であって、前記キャ
スタレーション導体は接続パッドから導出する第1領域
と、枠状の金属層から導出する第2領域とから成り、前
記第1領域と第2領域は絶縁基体側面の幅方向に位置が
ずれているとともに前記絶縁基体内部に形成された内部
配線層を介して接続されており、かつ前記接続パッドお
よび/または第1領域の表面に、結晶の平均粒径が10
0nm以上のニッケル層が被着されていることを特徴と
する配線基板。
1. An insulating base having an electronic component mounting portion on the upper surface and a frame-shaped metal layer surrounding the mounting portion, and a connection pad on the outer peripheral portion of the lower surface, and formed on a side surface of the insulating base.
A wiring board comprising a castellation conductor that connects the connection pad and a frame-shaped metal layer, wherein the castellation conductor is a first region derived from the connection pad and a first region derived from the frame-shaped metal layer. Two regions, the first region and the second region are displaced from each other in the width direction of the side surface of the insulating base, and are connected through an internal wiring layer formed inside the insulating base, and the connection is made. On the surface of the pad and / or the first region, the average crystal grain size is 10
A wiring board having a nickel layer of 0 nm or more deposited thereon.
【請求項2】前記接続パッドおよび/または第1領域の
表面に被着したニッケル層の厚さが2μm以上であるこ
とを特徴とする請求項1記載の配線基板。
2. The wiring board according to claim 1, wherein the thickness of the nickel layer deposited on the surface of the connection pad and / or the first region is 2 μm or more.
JP2001379150A 2001-12-12 2001-12-12 Wiring board Expired - Fee Related JP3808357B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001379150A JP3808357B2 (en) 2001-12-12 2001-12-12 Wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001379150A JP3808357B2 (en) 2001-12-12 2001-12-12 Wiring board

Publications (2)

Publication Number Publication Date
JP2003179176A true JP2003179176A (en) 2003-06-27
JP3808357B2 JP3808357B2 (en) 2006-08-09

Family

ID=19186646

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001379150A Expired - Fee Related JP3808357B2 (en) 2001-12-12 2001-12-12 Wiring board

Country Status (1)

Country Link
JP (1) JP3808357B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003249590A (en) * 2002-02-25 2003-09-05 Kyocera Corp Wiring board
JP2009505442A (en) * 2005-08-19 2009-02-05 ハネウェル・インターナショナル・インコーポレーテッド 3D printed circuit board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003249590A (en) * 2002-02-25 2003-09-05 Kyocera Corp Wiring board
JP2009505442A (en) * 2005-08-19 2009-02-05 ハネウェル・インターナショナル・インコーポレーテッド 3D printed circuit board

Also Published As

Publication number Publication date
JP3808357B2 (en) 2006-08-09

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