JP2003163277A - Capacitor, semiconductor device, electrooptical device, electronic apparatus, method of manufacturing capacitor, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitor provided with a dielectric layer having a high breakdown voltage even when it is formed at relatively low temperatures, a semiconductor device, an electrooptical device, an electronic apparatus, a method of manufacturing the capacitor, and a method of manufacturing the semiconductor device. <P>SOLUTION: In a capacitor 600 formed in a semiconductor device 300A, a dielectric layer 330 comprises a tantalum oxide film 331 formed by oxidizing a tantalum film at the temperature of 300-400°C and under the pressure of 0.5-2 MPa, and it has a high breakdown voltage. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor, a semiconductor device including the capacitor, an electro-optical device using the semiconductor device as an active matrix substrate, an electronic device including the electro-optical device, a capacitor and a semiconductor device. The present invention relates to a manufacturing method. More specifically, it relates to a technique for forming a dielectric layer used for a capacitor.

[0002]

2. Description of the Related Art Generally, when forming a capacitor on a substrate in various semiconductor devices, a lower electrode, a dielectric layer and an upper electrode are laminated in this order. Here, a silicon oxide film or a tantalum oxide film is used for the dielectric layer. In order to form a silicon oxide film having a high withstand voltage among such oxide films, conventionally, the silicon film is heated at a temperature of about 1000 ° C to about 1 ° C.
A method of thermal oxidation under the condition of 300 ° C. is used.
Further, in order to form the tantalum oxide film, a method of anodizing the tantalum film has been conventionally used.

[0003]

Here, the tantalum oxide film has an advantage that it has a high dielectric constant, but in order to form the tantalum oxide film by anodic oxidation, the power supply wiring for the anodic oxidation is formed. TF on the same substrate because it is necessary
There is a problem in that the degree of freedom in designing a semiconductor device in which T and the like are formed is largely lost. Also,
It is also possible to obtain a tantalum oxide film by thermally oxidizing the tantalum film in the atmosphere at atmospheric pressure, but such a tantalum oxide film has a problem of low withstand voltage.

In view of the above problems, the object of the present invention is to
A capacitor including a dielectric layer having a high withstand voltage even when formed at a relatively low temperature, a semiconductor device including the capacitor on a substrate, an electro-optical device using the semiconductor device as an active matrix substrate, and the electro-optical device An object of the present invention is to provide an electronic device, a method for manufacturing a capacitor, and a method for manufacturing a semiconductor device using the.

[0005]

In order to solve the above problems, according to the present invention, in a capacitor in which a lower electrode, a dielectric layer, and an upper electrode are laminated in this order, the dielectric layer contains an atmosphere containing water vapor. High Pressure Annealing that anneals under high pressure in a vacuum
l) An oxide film formed by oxidizing the dielectric layer forming metal film by the treatment is included.

In the present invention, the dielectric layer may be formed of only the oxide film or may have a multilayer structure of the oxide film and another insulating film.

Further, according to the present invention, in a method of manufacturing a capacitor having a lower electrode, a dielectric layer and an upper electrode, after forming a dielectric layer forming metal film, annealing is performed under a high pressure in an atmosphere containing water vapor. The high-pressure annealing treatment described above oxidizes the metal film for forming the dielectric layer to generate an oxide film, and the oxide film is used as the dielectric layer or a part of the dielectric layer.

In the present invention, the high-pressure annealing treatment is performed, for example, at a temperature of 600 ° C. or lower. For example, the high-pressure annealing treatment has a temperature of 300 ° C. to 40 ° C.
It is performed at 0 ° C. and a pressure of 0.5 MPa to 2 MPa.

In the present invention, the dielectric layer forming metal film is a tantalum (Ta) film or a tantalum alloy film.

In the present invention, the dielectric layer of the capacitor is
Since the tantalum oxide film produced by the high-pressure annealing treatment is included, the dielectric layer has a high withstand voltage. Further, in the present invention, since the tantalum oxide film is formed by high-pressure annealing treatment instead of anodic oxidation, it is not necessary to form a power supply wiring for performing anodic oxidation. Therefore, T on the same substrate
The degree of freedom in design is large in a semiconductor device in which FT and the like are also formed. Further, since the treatment is performed under pressure, a highly uniform tantalum oxide film can be obtained. In addition, there is an advantage that a large number of substrates can be collectively processed. Moreover, since the temperature of the high-pressure annealing treatment is 600 ° C. or lower, more preferably 300 ° C. to 400 ° C., there is no problem even when a glass substrate is used as the substrate. Further, even when the aluminum wiring is formed during the high-pressure annealing treatment, under such temperature conditions, the aluminum wiring is not deteriorated unless the aluminum wiring is exposed on the substrate surface.

In the present invention, the lower electrode is made of the same metal as the dielectric layer forming metal film at least on the side in contact with the dielectric layer, or is made of a material different from the dielectric layer forming metal film. Either case may be used.

In the capacitor having such a structure, in the high-pressure annealing treatment, only the surface of the dielectric layer forming metal film is oxidized to generate the oxide film, and the oxide film is used as the dielectric layer or the dielectric film. A method of using as a part of a layer and using the remaining dielectric layer forming metal film as the lower electrode or a part of the lower electrode, or forming the lower electrode on the lower layer side of the dielectric layer forming metal film. In the high-pressure annealing treatment, the entire metal film for forming the dielectric layer is oxidized to generate the oxide film, and the oxide film is used as the dielectric layer or a part of the dielectric layer. Can be manufactured.

In the present invention, it is preferable to perform the annealing treatment under normal pressure or under reduced pressure after performing the high pressure annealing treatment. By performing such an annealing treatment, the water content contained in the tantalum oxide film or the like can be removed and the crystallinity is improved, so that the withstand voltage is further improved.

The capacitor according to the present invention is suitable for constituting a semiconductor device in which other semiconductor elements are formed on the same substrate. An example of such a semiconductor device is an active matrix substrate used in an electro-optical device such as an active matrix liquid crystal device. In this active matrix substrate, the capacitor to which the present invention is applied is used as a storage capacitor in each pixel, for example.

The electro-optical device according to the present invention can be used as a display unit of electronic equipment such as a mobile phone and a mobile computer. Further, the electro-optical device according to the invention can be used as a light valve of a projection type display device (electronic device).

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described with reference to the drawings. In the following description, first, a semiconductor device including a capacitor to which the present invention is applied and a manufacturing method thereof will be described as Embodiments 1, 2, and 3, and then the present invention is applied to an active matrix substrate of a liquid crystal device. An example will be described.

[First Embodiment] FIGS. 1A and 1B are cross-sectional views schematically showing a structure of a semiconductor device according to a first embodiment of the present invention and a modification thereof.

In FIG. 1A, in a semiconductor device 300A of the present embodiment, a capacitor 600 and other semiconductor elements (not shown) are formed on a substrate 310,
This capacitor 600 has a lower electrode 3 made of a tantalum film.
20, a dielectric layer 330, and an upper electrode 350 made of an impurity-doped silicon film or metal film.

The lower electrode 320 is entirely composed of a tantalum film, and the dielectric layer 330 is composed of a tantalum oxide film 331 formed by oxidizing the surface of this tantalum film.

In manufacturing the semiconductor device 300A having such a structure, in this embodiment, after forming a tantalum film (metal film for forming a dielectric layer) on the substrate 310, water vapor is formed on the surface of the tantalum film. A high-pressure annealing process is performed in which the annealing is performed under a high pressure in an atmosphere containing. Here, the condition of the high-pressure annealing treatment is that the temperature is 600 ° C. or lower, for example,
Temperature is 300 ° C to 400 ° C, pressure is 0.5 MPa to 2M
Pa. As a result, only the surface of the tantalum film is oxidized to form the tantalum oxide film 331. Therefore, this tantalum oxide film 331 is used as the dielectric layer 330, and the remaining tantalum film is used as the lower electrode 320.

In the capacitor 600 of the semiconductor device 300A thus configured, the dielectric layer 330 uses the tantalum oxide film 331 produced by the high-pressure annealing process, and thus the dielectric layer 330 has a high withstand voltage. Also,
Since anodization is not performed when forming the tantalum film 331, it is not necessary to form a power supply wiring for performing anodization. Therefore, in the semiconductor device 300A in which TFTs and the like are formed on the same substrate, the degree of freedom in designing is great. In addition, there is an advantage that a large number of substrates 310 can be collectively processed. Further, since the temperature of the high-pressure annealing treatment is sufficient to be 600 ° C. or lower, further 300 ° C. to 400 ° C., there is no problem even when a glass substrate is used as the substrate. Furthermore, when performing high-pressure annealing treatment,
Even if the aluminum wiring is formed, under such temperature conditions, the aluminum wiring is not deteriorated unless the aluminum wiring is exposed on the substrate surface.

Here, since the dielectric layer 330 includes the tantalum oxide film 331, the withstand voltage is improved. Therefore, for example, as shown in FIG. 1B, the dielectric layer 330 is a tantalum film. Tantalum oxide film 33 obtained by high-pressure annealing treatment
1 may be provided on the lower layer side, and the silicon oxide film 332 formed by the sputtering method or the like may be provided on the upper layer side.

After the high-pressure annealing treatment, if the annealing treatment is performed at a temperature of 200 ° C. to 500 ° C. under normal pressure or reduced pressure, moisture is removed from the tantalum oxide film 331 and the crystallinity is improved. , Tantalum oxide film 331
Withstand voltage is further improved.

[Second Embodiment] FIGS. 2A and 2B are sectional views schematically showing a structure of a semiconductor device according to a second embodiment of the present invention and a modification thereof, respectively.

In FIG. 2A, in a semiconductor device 300B of this embodiment, a capacitor 600 and other semiconductor elements (not shown) are formed on a substrate 310,
The capacitor 600 includes a lower electrode 320 and a dielectric layer 3
30 and an upper electrode 350 made of a silicon film or a metal film doped with impurities.

Here, the lower electrode 320 includes a lower electrode layer 321 made of a metal film such as an aluminum film or a chromium film, or a silicon film doped with impurities.
The lower electrode layer 321 is composed of an upper electrode layer 322 made of a tantalum film laminated on the upper side.
The dielectric layer 330 is a tantalum oxide film 33 formed by oxidizing the surface of the tantalum film forming the upper electrode layer 322.
It is composed of 1.

In manufacturing the semiconductor device 300B having such a structure, in this embodiment, after the lower electrode layer 321 is formed on the substrate 310, the tantalum film (dielectric layer) is formed so as to cover the lower electrode layer 321. Forming metal film). Next, the surface of this tantalum film is subjected to a high-pressure annealing treatment in which it is annealed under a high pressure in an atmosphere containing water vapor. Here, the condition of the high-pressure annealing treatment is that the temperature is 6
The temperature is not higher than 00 ° C, for example, the temperature is 300 ° C to 400 ° C and the pressure is 0.5 MPa to 2 MPa. As a result, only the surface of the tantalum film is oxidized to form the tantalum oxide film 331. Therefore, the tantalum oxide film 331 is formed on the dielectric layer 33.
The remaining tantalum film is used as the upper electrode layer 322 of the lower electrode 320.

Also in the capacitor 600 of the semiconductor device 300B thus configured, the dielectric layer 330 uses the tantalum oxide film 331 produced by the high-pressure annealing process, and therefore the dielectric layer 330 has a high withstand voltage. Such,
The same effect as that of the first embodiment is achieved. In addition, in this embodiment, the lower electrode 320 has a two-layer structure including a lower electrode layer 321 and an upper electrode layer 322. Therefore, as long as a tantalum film is used for the upper electrode layer 322, any conductive film can be used for the lower electrode layer 321. Therefore, if an aluminum film having a low electric resistance is used for the lower electrode layer 321, the electric resistance of the lower electrode 320 can be reduced.

Also in this embodiment, if the dielectric layer 330 includes the tantalum oxide film 331, the withstand voltage is improved, so that, for example, as shown in FIG.
However, the tantalum oxide film 331 obtained by high-pressure annealing the tantalum film may be provided on the lower layer side, and the silicon oxide film 332 formed by the sputtering method or the like may be provided on the upper layer side.

After the high pressure annealing process, if the annealing process is performed at a temperature of 200 ° C. to 500 ° C. under normal pressure or reduced pressure, moisture is removed from the tantalum oxide film 331 and the crystallinity is improved. , Tantalum oxide film 331
Withstand voltage is further improved.

[Third Embodiment] FIGS. 3A and 3B are cross-sectional views schematically showing a structure of a semiconductor device according to a third embodiment of the present invention and a modification thereof.

In FIG. 3A, in a semiconductor device 300C of this embodiment, a capacitor 600 and other semiconductor elements (not shown) are formed on a substrate 310,
The capacitor 600 includes a lower electrode 320 and a dielectric layer 3
30 and an upper electrode 350 made of a silicon film or a metal film doped with impurities.

Here, the lower electrode 320 is composed of a silicon film or a metal film doped with impurities, and the dielectric layer 33.
0 is a tantalum oxide film 331 formed by oxidizing the tantalum film.
It consists of

In manufacturing the semiconductor device 300C having such a structure, in this embodiment, after the lower electrode 320 is formed on the substrate 310, a tantalum film (metal film for forming a dielectric layer) is formed so as to cover the lower electrode 320. ) Is formed. next,
A high pressure annealing process is performed on the entire tantalum film under high pressure in an atmosphere containing water vapor. Here, the condition of the high-pressure annealing treatment is that the temperature is 600 ° C. or lower,
For example, the temperature is 300 ° C to 400 ° C and the pressure is 0.5MP.
It is a-2MPa. As a result, the entire tantalum film is oxidized to form the tantalum oxide film 331, so this tantalum oxide film 331 is used as the dielectric layer 330.

In the capacitor 600 of the semiconductor device 300C thus configured, the tantalum oxide film 331 produced by the high-pressure annealing process is used for the dielectric layer 330, so that the dielectric layer 330 has a high withstand voltage. The same effect as the first embodiment is obtained. In addition, in this embodiment,
Since the entire tantalum film formed so as to cover the lower electrode 320 is made into the tantalum oxide film 331 by the high-pressure annealing treatment, there is no restriction on the material of the lower electrode 320. Therefore,
If an aluminum film having a low electric resistance is used for the lower electrode layer 320, the electric resistance of the lower electrode 320 can be reduced.

Also in this embodiment, if the dielectric layer 330 includes the tantalum oxide film 331, the withstand voltage is improved, so that, for example, as shown in FIG.
However, the tantalum oxide film 331 obtained by high-pressure annealing the tantalum film may be provided on the lower layer side, and the silicon oxide film 332 formed by the sputtering method or the like may be provided on the upper layer side. Further, as shown in FIG. 3C, the dielectric layer 330 is provided with a silicon oxide film 332 formed by a sputtering method or the like on the lower layer side, and a tantalum film on the upper layer side thereof is obtained by high-pressure annealing. It may be configured to include the tantalum oxide film 331.

After the high-pressure annealing treatment, if the annealing treatment is performed at a temperature of 200 ° C. to 500 ° C. under normal pressure or reduced pressure, moisture is removed from the tantalum oxide film 331 and the crystallinity is improved. , Tantalum oxide film 331
Withstand voltage is further improved.

[Fourth Embodiment] Next, as an example of a semiconductor device and an electro-optical device, an active matrix substrate used for an active matrix type liquid crystal device will be described.
An example to which the present invention is applied will be described.

(Overall Structure of Liquid Crystal Device) First, the structure and operation of an active matrix type liquid crystal device (electro-optical device) will be described with reference to FIGS. 4, 5 and 6. FIG. 4 is an equivalent circuit diagram of various elements and wirings in a plurality of pixels formed in a matrix to form an image display area of the liquid crystal device. FIG. 5 is a plan view of adjacent pixels on an active matrix substrate on which data lines, scanning lines, pixel electrodes, etc. are formed.
FIG. 6 is an explanatory diagram showing a cross section at a position corresponding to the line AA ′ in FIG. 5 and a cross section in a state where liquid crystal as an electro-optical material is sealed between the active matrix substrate and the counter substrate. In these figures, the scales are different for each layer and each member in order to make each layer and each member recognizable in the drawings.

In FIG. 4, in the image display area of the liquid crystal device, a pixel electrode 9a and a pixel switching TFT 30 for controlling the pixel electrode 9a are formed in each of a plurality of pixels formed in a matrix. And
The data line 6a that supplies a pixel signal is electrically connected to the source of the TFT 30. The pixel signals S1, S2 ... Sn to be written to the data line 6a are line-sequentially supplied in this order. Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2 ... Gm are applied to the scanning line 3a in a pulse-wise manner in this order at a predetermined timing. Is configured. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the pixel signal S1, S2 ... Sn supplied from the data line 6a is generated by turning on the TFT 30 which is a switching element for a certain period. Is written in each pixel at a predetermined timing. In this way, the pixel electrode 9a
The pixel signal S of a predetermined level written in the liquid crystal through the
1, S2, ... Sn are held for a certain period of time with the counter electrode formed on the counter substrate described later.

Here, for the purpose of preventing the held pixel signal from leaking, a storage capacitor 70 (capacitor) is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. There is. The storage capacitor 70 holds the voltage of the pixel electrode 9a for a time that is, for example, three digits longer than the time when the source voltage is applied. As a result, the charge retention characteristic is improved, and a liquid crystal device capable of performing display with a high contrast ratio can be realized. The storage capacitor 70 may be formed either between the capacitor line 3b, which is a wiring for forming the capacitor, or between the preceding scanning line 3a. Good.

In FIG. 5, on the active matrix substrate 10 of the liquid crystal device, a plurality of transparent pixel electrodes 9a (area surrounded by a chain double-dashed line) are formed in a matrix for each pixel. A data line 6a (shown by a chain line), a scanning line 3a (shown by a solid line), and a capacitance line 3b (shown by a solid line) are formed along the vertical and horizontal boundary regions. Here, in the semiconductor layer 1a, the gate electrode 3 is formed from the scanning line 3a so as to face a channel forming region described later.
c is protruding.

As shown in FIG. 6, the liquid crystal device 100 comprises an active matrix substrate 10 and a counter substrate 20 arranged to face the active matrix substrate 10. The base of the active matrix substrate 10 is a transparent substrate 10b such as a quartz substrate or a heat resistant glass plate, and the substrate of the counter substrate 20 is also a transparent substrate 20b such as a quartz substrate or a heat resistant glass plate.
A pixel electrode 9a is formed on the active matrix substrate 10, and an alignment film 64 that has been subjected to a predetermined alignment process such as a rubbing process is formed on the pixel electrode 9a. The pixel electrode 9a is formed of, for example, ITO (Indium Tin O).
xide) film or other transparent conductive thin film. The alignment film 64 is made of an organic thin film such as a polyimide thin film.

On the active matrix substrate 10, a pixel switching TFT 30 (MI) for switching control of each pixel electrode 9a is provided at a position adjacent to each pixel electrode 9a.
S-type semiconductor element) is formed. TFT shown here
Reference numeral 30 denotes an inverted stagger type, which includes a gate electrode 3c (metal layer), a gate insulating layer 2 (insulating layer), and an intrinsic silicon film 1
The a (semiconductor layer) includes a MIS portion formed in this order from the lower layer side to the upper layer side. A channel stopper 8 made of a silicon oxide film or the like is formed on the upper layer side of the silicon film 1a, and a source region 1g made of a silicon film doped with an N-type impurity so that the end portion overlaps the channel stopper 8, And a drain region 1h is formed. The data line 6a is formed on the upper layer side of the source region 1g, and the pixel electrode 9a is formed on the upper layer side of the drain region 1h. Further, a protective film 66 and an alignment film 64 are formed in this order on the upper layer side of the pixel electrode 9a.

Further, in this embodiment, the storage capacitor 70 (capacitor) using the insulating layer of the same layer as the gate insulating layer 2 of the TFT 30 as the dielectric layer 71 is formed. In this storage capacitor 70, the capacitance line 3b (lower electrode), the dielectric layer 71, and the drain electrode 6b (upper electrode) are formed in this order from the lower layer side to the upper layer.

On the other hand, a counter electrode 21 is formed over the entire surface of the counter substrate 20, and an alignment film 65 subjected to a predetermined alignment treatment such as rubbing treatment is formed on the surface thereof. The counter electrode 21 is also made of, for example, a transparent conductive thin film such as an ITO film. In addition, the alignment film 6 of the counter substrate 20
5 is also an organic thin film such as a polyimide thin film. On the counter substrate 20, counter substrate side light-shielding films 23 are formed in a matrix shape in regions other than the opening region of each pixel. Therefore, incident light from the counter substrate 20 side does not reach the channel formation region 1a 'of the semiconductor layer 1a of the TFT 30.
Further, the light shielding film 23 on the side of the counter substrate 20 has a function of improving contrast.

The active matrix substrate 10 and the counter substrate 20 thus configured are arranged so that the pixel electrode 9a and the counter electrode 21 face each other, and a space between these substrates is surrounded by a sealing material described later. A liquid crystal 50 as an electro-optical substance is enclosed and sandwiched in the enclosed space. The liquid crystal 50 has a predetermined alignment state by the alignment film in a state where the electric field from the pixel electrode 9a is not applied. Liquid crystal 50
Is composed of, for example, a mixture of one or several kinds of nematic liquid crystals. The sealing material is an adhesive made of a photo-curing resin or a thermosetting resin for bonding the active matrix substrate 10 and the counter substrate 20 around their periphery, and the distance between the substrates is set to a predetermined value. Gap material such as glass fiber or glass beads is blended.

(Structures of Gate Insulating Layer 2 and Dielectric Layer 71) In the liquid crystal device 100 having the above structure, the MO of the TFT 30 is formed on the active matrix substrate 10.
The S section and the storage capacitor 7 are configured as described below.

First, in the present embodiment, both the scanning line 3a and the gate electrode 3c are made of a tantalum film, and the tantalum oxide film 201 formed by oxidizing the surface of this tantalum film.
Are used as a part of the gate insulating layer 2. That is, the gate insulating layer 2 includes the scanning line 3 a and the gate electrode 3.
A tantalum oxide film 201 formed by oxidizing the surface of the tantalum film used for c, and a silicon oxide film 202 formed on the surface of the tantalum oxide film 201 by a CVD method or the like.
It consists of and.

Further, in the present embodiment, the capacitance line 3b constituting the storage capacitor 70 is also made of a tantalum film, and the tantalum oxide film 201 formed by oxidizing the surface of this tantalum film constitutes a part of the dielectric layer 71. is doing. That is, the storage capacity 7
The dielectric layer 71 forming 0 is similar to the gate insulating layer 2
It is composed of a tantalum oxide film 201 formed by oxidizing the surface of the tantalum film used for the capacitance line 3b, and a silicon oxide film 202 formed on the surface of the tantalum oxide film 201 by a CVD method or the like.

Here, in forming the tantalum oxide film 201 by oxidizing the tantalum film, as described later,
After forming the tantalum film as the metal film for forming the dielectric layer,
The surface of this tantalum film is subjected to a high-pressure annealing treatment in which it is annealed under a high pressure in an atmosphere containing water vapor. Here, the condition of the high-pressure annealing treatment is that the temperature is 600 ° C. or lower,
For example, the temperature is 300 ° C to 400 ° C and the pressure is 0.5MP.
It is a-2MPa. As a result, only the surface of the tantalum film is oxidized to form the tantalum oxide film 201,
This tantalum oxide film 201 is used as a part of the gate insulating layer 2 and the dielectric layer 71, and the remaining tantalum film is used as the scanning line 3a, the gate electrode 3c, and the capacitance line 3b.

As described above, in the active matrix substrate 10 of this embodiment, the gate insulating layer 2 which constitutes the TFT 30 is formed.
Is the tantalum oxide film 20 formed by the high pressure annealing process.
1 is included, the withstand voltage of the gate insulating layer 2 is high. In addition, the dielectric layer 71 that constitutes the storage capacitor 70,
Since the tantalum oxide film 201 generated by the high-pressure annealing process is included, the dielectric layer 71 has a high withstand voltage. Also,
Since the anodic oxidation is not performed when forming the tantalum film 201, it is not necessary to form the power supply wiring for performing the anodic oxidation. Therefore, the layout of the active matrix substrate 10 in which the TFTs 30 and the like are formed on the same substrate does not need to be significantly changed from the conventional one. Further, the high-pressure annealing treatment has an advantage that a large number of active matrix substrates 10 can be collectively treated. Moreover, the temperature of the high-pressure annealing treatment is 600 ° C.
Hereinafter, since 300 ° C to 400 ° C is sufficient,
There is no problem even when a glass substrate is used as the substrate. Further, since the pressure is applied to the processing, the uniform tantalum oxide film 201 can be formed. Further, even when the aluminum wiring is formed during the high-pressure annealing treatment, under such temperature conditions, the aluminum wiring is not deteriorated unless the aluminum wiring is exposed on the substrate surface.

(Manufacturing Method of Active Matrix Substrate 10) A manufacturing method of the active matrix substrate 10 for a liquid crystal display device having such a structure will be described with reference to FIGS. 7 and 8.

7 and 8 are process sectional views showing a method of manufacturing the active matrix substrate 10 of this embodiment.
It corresponds to a cross section taken along line A '.

As shown in FIG. 7A, first, a transparent substrate 10b which is a base of the active matrix substrate 10 is prepared, and then a tantalum film 3 (metal film for forming a dielectric layer) is sputtered on the entire surface of the transparent substrate 10b. The tantalum film 3 is formed by a photolithography technique, and the scanning line 3 is formed.
Patterning is performed along the formation pattern of a, the gate electrode 3c, and the capacitance line 3b.

Next, the surface of the tantalum film 3 is subjected to a high pressure annealing treatment in which it is annealed under a high pressure in an atmosphere containing water vapor. Here, the condition of the high-pressure annealing treatment is, for example, a temperature of 600 ° C. or lower, for example, a temperature of 300 ° C. to 4 ° C.
The temperature is 00 ° C. and the pressure is 0.5 MPa to 2 MPa. As a result, as shown in FIG. 7B, since only the surface of the tantalum film 3 is oxidized to form the tantalum oxide film 201,
This tantalum oxide film 201 is used as a part of the gate insulating layer 2 and the dielectric layer 71, and the remaining tantalum film is used as the scanning line 3a, the gate electrode 3c, and the capacitance line 3b.

After performing the high-pressure annealing treatment, if the annealing treatment is performed at a temperature of 200 ° C. to 500 ° C. under normal pressure or reduced pressure, moisture is removed from the tantalum oxide film 201 and the crystallinity is improved. Tantalum oxide film 201
The film quality is improved.

Next, as shown in FIG. 7C, TEOS
(Tetra-ethyl-ortho-silicate) gas, TEB
The transparent substrate 10b is formed by using a (tetra-ethyl borate) gas, a TMOP (tetra-methyl oxy-foslate) gas, or the like by an atmospheric pressure or a reduced pressure CVD method.
A silicon oxide film 202 is formed on the entire surface of. As a result, the gate insulating layer 2 including the tantalum oxide film 201 and the silicon oxide film 202 and the dielectric layer 71 are formed.

Next, in a relatively low temperature environment of about 450 ° C. to about 550 ° C., preferably about 500 ° C., a flow rate of about 400 cc.
/ Min to about 600 cc / min by a low pressure CVD method using a monosilane gas, a disilane gas or the like, after forming an amorphous silicon film over the entire surface of the transparent substrate 10b, patterning is performed by using a photolithography technique,
As shown in FIG. 7D, an island-shaped silicon film 1 a is formed on the upper side of the gate insulating layer 2. At this time, for example, about 6
The amorphous silicon film 1 may be solid-phase grown on the polysilicon film by performing the annealing treatment at 00 ° C. for about 1 hour to about 10 hours in a nitrogen atmosphere.

Next, a silicon oxide film or the like is formed on the entire surface of the transparent substrate 10b on the upper layer side of the silicon film 1 and then patterned by using a photolithography technique, as shown in FIG. The etching stopper 8 is formed on the upper layer side of the semiconductor film 1a.

Next, the transparent substrate 10b is formed by the CVD method or the like.
A silicon film doped with N-type impurities is formed on the entire surface of, and then patterned by using photolithography technique. As shown in FIG. 8B, a source region 1g whose end overlaps with the channel stopper 8 is formed. , And the drain region 1h are formed.

Next, a conductive film such as an aluminum film is formed on the entire surface of the transparent substrate 10b by sputtering or the like on the upper layers of the source region 1g and the drain region 1h, and then patterned by photolithography. As shown in FIG. 8C, a data line 6a and a drain electrode 6b which overlap with each of the source region 1g and the drain region 1h are formed. At this time, the drain electrode 6
About b, a part thereof is formed as an upper electrode so as to overlap with the capacitance line 3b (lower electrode). As a result, the TFT 30,
And a storage capacitor 70 is formed.

Next, the transparent substrate 10 is formed by the sputtering method or the like.
After forming an ITO film on the entire surface of b, patterning is performed using a photolithography technique to form a pixel electrode 9a as shown in FIG. 8D.

Thereafter, as shown in FIG. 6, the active matrix substrate 10 is completed by forming the protective film 66 and the alignment film 64 on the upper layer side of the pixel electrode 9a.

[Fifth Embodiment] With reference to FIGS. 9, 10, and 11, an active matrix substrate for a liquid crystal device will be described as a semiconductor device according to a fifth embodiment of the present invention. In addition, this embodiment and each of the sixth embodiments described later,
Since the active matrix substrates 7, 8, and 9 and the liquid crystal device using the same have the same basic configuration as that of the fourth embodiment, the portions having common functions are designated by the same reference numerals. The detailed description of is omitted.

FIG. 9 is a sectional view when the liquid crystal device according to the fifth embodiment of the present invention is cut at a position corresponding to the line AA ′ in FIG. 10A to 10E and FIG.
9A to 9D are process cross-sectional views showing a method for manufacturing the active matrix substrate shown in FIG.

In the fourth embodiment, the TFT 30 is used.
Gate insulating film 2 and the dielectric layer 71 of the storage capacitor 70.
In each of the above cases, the tantalum oxide film 201 and the silicon oxide film 202 are included. However, in the present embodiment, the gate insulating film 2 includes the tantalum oxide film 201 and the silicon oxide film 202 as described in FIG. On the other hand, the dielectric layer 71 is composed only of the tantalum oxide film 201.

That is, in this embodiment, the gate insulating layer 2 is similar to the fourth embodiment in that the tantalum oxide film 201 formed by oxidizing the surface of the tantalum film used for the scanning line 3a and the gate electrode 3c and the tantalum oxide film 201. Silicon oxide film 2 formed on the surface of film 201 by the CVD method or the like
02.

On the other hand, the capacitance line 3b (lower electrode) that constitutes the storage capacitor 70 is also made of a tantalum film, and the surface of the tantalum film that constitutes the capacitance line 3b has a high voltage on the upper layer side of the capacitance line 3b. Although the tantalum oxide film 201 formed by oxidation by the annealing process is formed, the opening 208 is formed by removing a part of the silicon oxide film 202 in the region where the capacitance line 3b is formed. Therefore, only the tantalum oxide film 201 is interposed as the dielectric layer 71 between the capacitance line 3b and the drain electrode 6b (upper electrode). Therefore, in this embodiment, since the dielectric constant of the dielectric layer 71 is high, the storage capacitor 70 having a large capacitance can be formed. Even on the upper layer side of the capacitance line 3b, it is preferable to leave the silicon oxide film 202 at the intersection of the capacitance line 3b and the data line 6a in consideration of the withstand voltage there.

Since the other structure is the same as that of the fourth embodiment, the parts having the common functions are designated by the same reference numerals and shown in FIG. 9, and the description thereof will be omitted.

In manufacturing the active matrix substrate 10 having such a structure, first, as shown in FIG. 10A, a transparent substrate 10b which is a base of the active matrix substrate 10 is prepared, and then the entire surface of the transparent substrate 10b is prepared. A tantalum film 3 (metal film for forming a dielectric layer) is formed on the substrate by a sputtering method or the like. Pattern.

Next, the surface of the tantalum film 3 is subjected to a high pressure annealing process in which it is annealed under a high pressure in an atmosphere containing water vapor. Here, the condition of the high-pressure annealing treatment is, for example, a temperature of 600 ° C. or lower, for example, a temperature of 300 ° C. to 4 ° C.
The temperature is 00 ° C. and the pressure is 0.5 MPa to 2 MPa. As a result, as shown in FIG. 10B, since only the surface of the tantalum film 3 is oxidized to form the tantalum oxide film 201, the remaining tantalum film is scanned with the scanning line 3a, the gate electrode 3c, and the gate electrode 3c.
And used as the capacitance line 3b.

After the high-pressure annealing process, if the annealing process is performed at a temperature of 200 ° C. to 500 ° C. under normal pressure or reduced pressure, moisture is removed from the tantalum oxide film 201 and the crystallinity is improved. Tantalum oxide film 201
The film quality is improved.

Next, as shown in FIG. 10C, a silicon oxide film 202 is formed on the entire surface of the transparent substrate 10b by a normal pressure or low pressure CVD method or the like. As a result, the gate insulating layer 2 including the tantalum oxide film 201 and the silicon oxide film 202 is formed.

Next, as shown in FIG. 10D, the silicon film 20 formed above the capacitance line 3b of the silicon oxide film 202 is formed by using the photolithography technique.
2 is removed to form the opening 208. Then, only the tantalum oxide film 201 left on the upper layer side of the capacitance line 3b is used as the dielectric layer 71 of the storage capacitor 70.

After that, as in the fourth embodiment, after forming an amorphous silicon film on the entire surface of the transparent substrate 10b, patterning is performed by using the photolithography technique, and the gate is formed as shown in FIG. An island-shaped silicon film 1a is formed on the upper layer side of the insulating layer 2. Next, after forming a silicon oxide film or the like on the entire surface of the transparent substrate 10b,
Patterning is performed using photolithography technology, and FIG.
As shown in FIG. 1A, the etching stopper 8 is formed on the upper layer side of the semiconductor film 1a. Next, a silicon film doped with N-type impurities is formed on the entire surface of the transparent substrate 10b by the CVD method or the like, and then patterned by using a photolithography technique, as shown in FIG.
A source region 1g and a drain region 1h are formed.

Next, the transparent substrate 10 is formed by the sputtering method or the like.
After forming a conductive film such as an aluminum film on the entire surface of b, patterning using a photolithography technique,
As shown in FIG. 11C, the data line 6a and the drain electrode 6b are formed. At this time, the drain electrode 6b is formed so that a part thereof overlaps the capacitance line 3b. As a result, the TFT 30 and the storage capacitor 70 are formed. Next, after forming an ITO film on the entire surface of the transparent substrate 10b by a sputtering method or the like, patterning is performed using a photolithography technique to form a pixel electrode 9a as shown in FIG. 11D. Thereafter, as shown in FIG. 9, the active matrix substrate 10 is completed by forming the protective film 66 and the alignment film 64 on the upper layer side of the pixel electrode 9a.

[Sixth Embodiment] An active matrix substrate for a liquid crystal device will be described as a semiconductor device according to a sixth embodiment of the present invention with reference to FIGS. 12, 13 and 14.

FIG. 12 is a cross-sectional view of the liquid crystal device according to the sixth embodiment of the present invention taken along the line AA ′ in FIG. 13A to 13D, and FIG.
4A to 4D are process cross-sectional views showing a method for manufacturing the active matrix substrate shown in FIG.

As shown in FIG. 12, the liquid crystal device 1 of the present embodiment.
00 also includes an active matrix substrate 10 and a counter substrate 20 arranged to face the active matrix substrate 10. A pixel switching TFT 30 is formed on the active matrix substrate 10 at a position adjacent to each pixel electrode 9a.
The FT 30 includes a MOS portion in which the gate electrode 3c, the gate insulating layer 2, and the intrinsic silicon film 1a are formed in this order from the lower layer side to the upper layer side. Further, in the active matrix substrate 10 of this embodiment, a storage capacitor 70 using an insulating layer that is the same layer as the gate insulating layer 2 of the TFT 30 as a dielectric layer 71 is formed. In the storage capacitor 70, the capacitance line 3b, the gate insulating layer 2, and the drain electrode 6b are formed in this order from the lower layer side to the upper layer. It should be noted that the counter electrode 21 is formed over the entire surface of the counter substrate 20.
Is formed, and an alignment film 65 that has been subjected to a predetermined alignment treatment such as a rubbing treatment is formed on the surface thereof.

In the liquid crystal device 100 configured as described above, in the present embodiment, the scanning lines 3a, the gate electrodes 3c, and the capacitance lines 3b are not limited to tantalum films, but are formed of various metal films, for example, aluminum films. Has been done. Further, a tantalum oxide film 201 is formed on the entire surface of the transparent substrate 10b above the scanning lines 3a, the gate electrodes 3c, and the capacitance lines 3b.
It is used as a part of the gate insulating layer 2 of the TFT 30 and the dielectric layer 71 of the storage capacitor 70. That is, both the gate insulating layer 2 and the dielectric layer 71 are the tantalum oxide film 201 and the silicon oxide film 2 formed on the surface of the tantalum oxide film 201 by the CVD method or the like.
02.

To form such a tantalum oxide film 201, in this embodiment, as will be described later, after forming a tantalum film as a dielectric layer forming metal film on the entire surface of the transparent substrate 10b, this tantalum film is formed. The whole is subjected to a high-pressure annealing treatment in which it is annealed under a high pressure in an atmosphere containing water vapor to oxidize the tantalum film. The conditions of the high-pressure annealing treatment performed here are a temperature of 600 ° C. or lower, for example, a temperature of 300 ° C. to 400 ° C. and a pressure of 0.5 MPa to.
It is 2 MPa.

Therefore, in the active matrix substrate 10 of this embodiment, the gate insulating layer 2 and the dielectric layer 71 are
Since the tantalum oxide film 201 generated by the high-pressure annealing process is included, the same effects as those of the fourth embodiment such as high withstand voltage of the gate insulating layer 2 and the dielectric layer 71 are obtained.

Further, in forming the tantalum oxide film 201, the entire tantalum film formed on the entire surface of the transparent substrate 10b is oxidized by a high pressure annealing process to form a tantalum film, which is used as the gate insulating layer 2 and the dielectric layer 71. Used as a part. Therefore, unlike the fourth and fifth embodiments, the gate electrode 3c and the like can be made of a metal other than the tantalum film. Therefore, since aluminum wiring can be used for the scanning lines 3a and the like, the electrical resistance of the scanning lines 3a can be reduced.

In manufacturing the active matrix substrate 10 for a liquid crystal display device having such a structure, first, as shown in FIG. 13A, after preparing a transparent substrate 10b which is a base of the active matrix substrate 10, An aluminum film is formed on the entire surface of the transparent substrate 10b by a sputtering method or the like, and the aluminum film is patterned using a photolithography technique to scan lines 3a and gate electrodes 3.
c and the capacitance line 3b are formed.

Next, a tantalum film 205 (metal film for forming a dielectric layer) is formed on the entire surface of the transparent substrate 10b on the upper layers of the scanning lines 3a, the gate electrodes 3c, and the capacitance lines 3b by a sputtering method or the like. To do.

Next, the entire tantalum film 205 is subjected to a high pressure annealing process in which it is annealed under a high pressure in an atmosphere containing water vapor. Here, the condition of the high-pressure annealing treatment is that the temperature is 600 ° C. or lower, for example, the temperature is 300 ° C. to 400 ° C.
C. and pressure are 0.5 MPa to 2 MPa. as a result,
The entire tantalum film 205 is oxidized to form a tantalum oxide film 201 as shown in FIG. 13 (B).

After the high-pressure annealing treatment, if the annealing treatment is performed at a temperature of 200 ° C. to 500 ° C. under normal pressure or reduced pressure, moisture is removed from the tantalum oxide film 201 and the crystallinity is improved. Tantalum oxide film 201
The film quality is improved.

Next, as shown in FIG. 13C, CVD
A silicon oxide film 202 is formed on the entire surface of the transparent substrate 10b by a method such as a method. As a result, the tantalum oxide film 20
1 and the silicon oxide film 202, the gate insulating layer 2 and the dielectric layer 71 are formed.

After that, as in the fourth embodiment, after forming an amorphous silicon film on the entire surface of the transparent substrate 10b, patterning is performed by using the photolithography technique, and as shown in FIG. An island-shaped silicon film 1a is formed on the upper layer side of the insulating layer 2. Next, after forming a silicon oxide film or the like on the entire surface of the transparent substrate 10b,
Patterning is performed using photolithography technology, and FIG.
As shown in FIG. 4A, the etching stopper 8 is formed on the upper layer side of the semiconductor film 1a. Next, a silicon film doped with N-type impurities is formed on the entire surface of the transparent substrate 10b by the CVD method or the like, and then patterned by using a photolithography technique, as shown in FIG.
A source region 1g and a drain region 1h are formed.

Next, the transparent substrate 10 is formed by the sputtering method or the like.
After forming a conductive film such as an aluminum film on the entire surface of b, patterning using a photolithography technique,
As shown in FIG. 14C, the data line 6a and the drain electrode 6b are formed. At this time, the drain electrode 6b is formed so that a part thereof overlaps the capacitance line 3b. As a result, the TFT 30 and the storage capacitor 70 are formed. Next, after forming an ITO film on the entire surface of the transparent substrate 10b by a sputtering method or the like, patterning is performed by using a photolithography technique to form a pixel electrode 9a as shown in FIG. 14 (D). Thereafter, as shown in FIG. 12, the active matrix substrate 10 is completed by forming the protective film 66 and the alignment film 64 on the upper layer side of the pixel electrode 9a.

[Seventh Embodiment] With reference to FIGS. 15, 16 and 17, an active matrix substrate for a liquid crystal device will be described as a semiconductor device according to a seventh embodiment of the present invention.

FIG. 15 is a sectional view when the liquid crystal device according to the seventh embodiment of the present invention is cut at a position corresponding to the line AA ′ in FIG. 16A to 16E, and FIG.
7A to 7D are process cross-sectional views showing a method for manufacturing the active matrix substrate shown in FIG.

In the sixth embodiment, the TFT 30 is used.
Gate insulating film 2 and the dielectric layer 71 of the storage capacitor 70.
Are both tantalum oxide film 201 and silicon oxide film 2.
However, in the present embodiment, as shown in FIG. 15, the gate insulating film 2 includes the tantalum oxide film 201.
And the silicon oxide film 202, the dielectric layer 71 is composed only of the tantalum oxide film 201.

That is, in this embodiment, as for the gate insulating layer 2, the tantalum oxide film formed by oxidizing the entire tantalum film formed in the upper layer of the scanning line 3a and the gate electrode 3c by the high-pressure annealing treatment, as in the sixth embodiment. 201
And a silicon oxide film 202 formed on the surface of the tantalum oxide film 201 by a CVD method or the like.

On the other hand, in the storage capacitor 70, the tantalum oxide film formed by oxidizing the entire tantalum film formed on the upper side of the capacitance line 3b by the high-pressure annealing process is formed on the upper layer of the capacitance line 3b (lower electrode). 201 is formed,
In the region where the capacitance line 3b is formed, a part of the silicon oxide film 202 is removed and an opening 208 is formed. Therefore, the tantalum oxide film 2 is formed as the dielectric layer 71 between the capacitance line 3b and the drain electrode 6b (upper electrode).
Only 01 intervenes. Therefore, in this embodiment, since the dielectric layer 71 has a high dielectric constant, the storage capacitor 70 having a large capacitance is used.
Can be formed. Even on the upper layer side of the capacitance line 3b,
At the intersection of the capacitance line 3b and the data line 6a, it is preferable to leave the silicon oxide film 202 in consideration of the withstand voltage there. Since other configurations are the same as those of the sixth embodiment, parts having common functions are denoted by the same reference numerals and shown in FIG. 12, and the description thereof will be omitted.

In manufacturing the active matrix substrate 10 having such a structure, first, as shown in FIG. 16A, after preparing the transparent substrate 10b which is the base of the active matrix substrate 10, the entire surface of the transparent substrate 10b is prepared. An aluminum film is formed on the substrate by a sputtering method or the like, and the aluminum film is patterned by using a photolithography technique to scan the scanning lines 3a, the gate electrodes 3c, and the capacitance lines 3.
b is formed.

Next, a tantalum film 205 (metal film for forming a dielectric layer) is formed on the entire surface of the transparent substrate 10b on the upper layers of the scanning lines 3a, the gate electrodes 3c, and the capacitance lines 3b by a sputtering method or the like. To do.

Next, the entire tantalum film 205 is subjected to a high pressure annealing process in which it is annealed under a high pressure in an atmosphere containing water vapor. Here, the condition of the high-pressure annealing treatment is that the temperature is 600 ° C. or lower, for example, the temperature is 300 ° C. to 400 ° C.
C. and pressure are 0.5 MPa to 2 MPa. as a result,
The entire tantalum film 205 is oxidized to form a tantalum oxide film 201 as shown in FIG.

After the high-pressure annealing treatment, if the annealing treatment is performed at a temperature of 200 ° C. to 500 ° C. under normal pressure or reduced pressure, moisture is removed from the tantalum oxide film 201 and the crystallinity is improved. Tantalum oxide film 201
The film quality is improved.

Next, as shown in FIG. 16C, a silicon oxide film 202 is formed on the entire surface of the transparent substrate 10b by the atmospheric pressure or reduced pressure CVD method or the like. As a result, the gate insulating layer 2 including the tantalum oxide film 201 and the silicon oxide film 202 is formed.

Next, as shown in FIG. 16D, the silicon film 20 formed on the upper layer of the capacitance line 3b of the silicon oxide film 202 is formed by the photolithography technique.
2 is removed to form the opening 208. Then, only the tantalum oxide film 201 left on the upper layer side of the capacitance line 3b is used as the dielectric layer 71 of the storage capacitor 70.

After that, as in the case of the fourth embodiment, after forming an amorphous silicon film on the entire surface of the transparent substrate 10b, patterning is performed using the photolithography technique, and the gate is formed as shown in FIG. An island-shaped silicon film 1a is formed on the upper layer side of the insulating layer 2. Next, after forming a silicon oxide film or the like on the entire surface of the transparent substrate 10b,
Patterning is performed using photolithography technology, and FIG.
As shown in FIG. 7A, the etching stopper 8 is formed on the upper layer side of the semiconductor film 1a. Next, a silicon film doped with N-type impurities is formed on the entire surface of the transparent substrate 10b by a CVD method or the like, and then patterned by using a photolithography technique, as shown in FIG.
A source region 1g and a drain region 1h are formed.

Next, the transparent substrate 10 is formed by the sputtering method or the like.
After forming a conductive film such as an aluminum film on the entire surface of b, patterning using a photolithography technique,
As shown in FIG. 17C, the data line 6a and the drain electrode 6b are formed. At this time, the drain electrode 6b is formed so that a part thereof overlaps the capacitance line 3b. As a result, the TFT 30 and the storage capacitor 70 are formed. Next, after forming an ITO film on the entire surface of the transparent substrate 10b by a sputtering method or the like, patterning is performed using a photolithography technique to form a pixel electrode 9a as shown in FIG. 17D. Then, as shown in FIG. 15, the active matrix substrate 10 is completed by forming the protective film 66 and the alignment film 64 on the upper layer side of the pixel electrode 9a.

In the fourth, fifth, sixth and seventh embodiments, as in the second embodiment, the lower electrode layer such as aluminum may be formed under the tantalum film. .

[Embodiment 8] Embodiments 4, 5, 6 and
In Example 7, an inverted stagger type TFT is formed as a non-linear element for pixel switching, but the present invention is applied to an active matrix substrate using a positive stagger type TFT as a non-linear element for pixel switching as in this embodiment. May be. Since the active matrix substrate of this embodiment and the liquid crystal device using the same have the same basic configuration as that of the fourth embodiment, parts having common functions are designated by the same reference numerals. Detailed description is omitted.

(Structure of Active Matrix Substrate) FIG.
FIG. 8 is a plan view of pixels adjacent to each other on the active matrix substrate on which data lines, scanning lines, pixel electrodes and the like are formed. FIG. 19 is an explanatory diagram showing a cross section at a position corresponding to a line BB ′ in FIG. 18, and a cross section in a state where liquid crystal as an electro-optical substance is sealed between the active matrix substrate and the counter substrate. . In these figures, the scales are different for each layer and each member in order to make each layer and each member recognizable in the drawings.

In FIG. 18, on the active matrix substrate 10 of the liquid crystal device 100, a plurality of transparent pixel electrodes 9a (region surrounded by a chain double-dashed line) are formed in a matrix for each pixel, and the pixel electrodes 9a are arranged vertically and horizontally. Along the boundary area of the data line 6a (indicated by a chain line) and the scanning line 3a (metal layer /
Solid lines) and capacitance lines 3b (metal layer / shown by solid lines) are formed. The data line 6a is connected to the semiconductor layer 1a made of a polysilicon film through the contact hole 56.
Of these, it is electrically connected to the source region described later,
The pixel electrode 9a is electrically connected to a later-described drain region of the semiconductor layer 1a via the contact hole 57. In addition, the scanning line 3a passes through the semiconductor layer 1a so as to face a channel forming region described later.

As shown in FIG. 19, the liquid crystal device 100 is
An active matrix substrate 10 and a counter substrate 20 arranged to face the active matrix substrate 10 are provided. The base of the active matrix substrate 10 is a transparent substrate 10b such as a quartz substrate or a heat resistant glass plate, and the substrate of the counter substrate 20 is also a transparent substrate 20b such as a quartz substrate or a heat resistant glass plate. A pixel electrode 9a is formed on the active matrix substrate 10, and an alignment film 64 that has been subjected to a predetermined alignment process such as a rubbing process is formed on the pixel electrode 9a. The pixel electrode 9a is made of, for example, a transparent conductive thin film such as an ITO film. The alignment film 64 is made of an organic thin film such as a polyimide thin film.

On the active matrix substrate 10, a pixel switching TFT 30 for switching control of each pixel electrode 9a is formed at a position adjacent to each pixel electrode 9a. The TFT 30 shown here is an LDD (Lig
a scanning line 3a, a channel forming region 1a '(semiconductor layer) of the semiconductor film 1a in which a channel is formed by an electric field of a scanning signal supplied from the scanning line 3a, and the scanning line 3a. Insulating layer 2 which insulates semiconductor layer 1a from data line 6a, low-concentration source region 1b and low-concentration drain region 1c of semiconductor layer 1a, and high-concentration source region 1 of semiconductor layer 1a.
d and the high-concentration drain region 1e.

An interlayer insulating film 4 is formed on the upper layer side of the scanning line 3a, and a data line 6a is formed on the upper layer of the interlayer insulating film 4. Therefore, the data line 6a is electrically connected to the high concentration source region 1d through the contact hole 56 formed in the interlayer insulating film 4. Also, the data line 6a
An interlayer insulating film 7 is formed on the upper layer side, and a pixel electrode 9a is formed on the upper layer side of the interlayer insulating film 7. Therefore,
The pixel electrode 9a is connected to the high-concentration drain region 1e through the interlayer insulating films 4 and 7 and the contact hole 57 formed in the gate insulating layer 2.

Here, the TFT 30 preferably has the LDD structure as described above, but has the offset structure in which the impurity ions are not implanted into the regions corresponding to the low concentration source region 1b and the low concentration drain region 1c. May be. Further, the TFT 30 may be a self-aligned type TFT in which high-concentration source and drain regions are formed in a self-aligned manner by implanting impurity ions at a high concentration using the gate electrode 3a as a mask.

Further, in this embodiment, the gate insulating layer 2 of the TFT 30 is extended from the position facing the gate electrode 3a to be used as the dielectric layer 71, and the semiconductor film 1a is extended to be the lower electrode 1f. Capacitance line 3 facing these
The storage capacitor 70 is formed by using b as the upper electrode. That is, the high-concentration drain region 1 of the semiconductor 1a
e is a lower electrode 1f of the storage capacitor 70, which is arranged to face the capacitance line 3b via the gate insulating layer 2.

On the other hand, a counter electrode 21 is formed over the entire surface of the counter substrate 20, and an alignment film 65 which has been subjected to a predetermined alignment treatment such as a rubbing treatment is formed on the surface thereof. The counter electrode 21 is also made of, for example, a transparent conductive thin film such as an ITO film. In addition, the alignment film 6 of the counter substrate 20
5 is also an organic thin film such as a polyimide thin film. On the counter substrate 20, counter substrate side light-shielding films 23 are formed in a matrix shape in regions other than the opening region of each pixel.

In the liquid crystal device 100 thus configured, the gate insulating layer 2 is formed on the upper side of the semiconductor film 1a by CVD.
Oxide film 202 formed by a method such as
And a tantalum oxide film 201 formed by oxidizing a tantalum film formed on the upper layer side of the silicon oxide film 202. The dielectric layer 71 is also a tantalum oxide film formed by oxidizing the silicon oxide film 202 formed on the upper layer side of the semiconductor film 1a by a method such as the CVD method and the tantalum film formed on the upper layer side of the silicon oxide film 202. Membrane 201
It consists of and.

In forming the tantalum oxide film 201, in this embodiment, as will be described later, a metal film for forming a dielectric layer is formed on the entire surface of the transparent substrate 10b with respect to the upper layer side of the silicon oxide film 202. After the tantalum film is formed, the whole tantalum film is subjected to a high pressure annealing process in which it is annealed under a high pressure in an atmosphere containing water vapor to oxidize the tantalum film. The condition of the high-pressure annealing treatment performed here is that the temperature is 600 ° C. or lower, for example, the temperature is 300 ° C.
C. to 400.degree. C., and pressure is 0.5 MPa to 2 MPa.

Therefore, in the active matrix substrate 10 of this embodiment, the gate insulating layer 2 and the dielectric layer 71 are
Since the tantalum oxide film 201 generated by the high-pressure annealing process is included, the same effects as those of the fourth embodiment such as high withstand voltage of the gate insulating layer 2 and the dielectric layer 71 are obtained.

When forming the tantalum oxide film 201, the entire tantalum film formed on the entire surface of the transparent substrate 10b is oxidized by high pressure annealing to form a tantalum film, which is used as the gate insulating layer 2 and the dielectric layer 71. Used as a part. That is, the tantalum oxide film 201
Does not mean that only the surface of the tantalum film is oxidized.
Therefore, since the tantalum film does not remain after the tantalum oxide film 201 is formed, the gate insulating layer 2 and the dielectric layer 71 can include the tantalum oxide film 201 also in the positive stagger type TFT 30. Further, the scanning line 3a is not limited to the tantalum film, and an arbitrary metal film can be used. Therefore, a metal film having a low electric resistance such as an aluminum film can be used.

(Manufacturing Method of Active Matrix Substrate)
A method of manufacturing the active matrix substrate 10 for a liquid crystal display device configured as described above will be described with reference to FIGS.
2 will be described.

20 to 22 are process cross-sectional views showing the method for manufacturing the active matrix substrate 10 of this embodiment, which correspond to the cross section taken along the line BB 'of FIG.

As shown in FIG. 20A, first, after forming a base protective film (not shown) on the entire surface of the transparent substrate 10b which is the base of the active matrix substrate 10, the base protective film is formed on the upper side of the base protective film. Under a temperature condition of about 450 ° C. to about 550 ° C., a reduced pressure C using monosilane gas, disilane gas, etc.
An amorphous silicon film is formed by the VD method or the like. Next, an annealing process is performed at about 600 ° C. for about 1 hour to about 10 hours in a nitrogen atmosphere to solid-phase grow the polysilicon film, which is then patterned using photolithography technology to form islands. The silicon film 1a is formed.

Next, as shown in FIG. 20 (B), CVD
Silicon on the entire surface of the transparent substrate 10b by a method such as
The film 202 is formed. Next, in the silicon film 1a, the storage
For example, P is provided in the extended portion that becomes the lower electrode 1f of the storage capacitor 70.
Ion dose about 3 × 10 ¹²/ Cm² Doped with low
Make it resistance.

Next, as shown in FIG. 20C, a tantalum film 205 (metal film for forming an insulating film) is formed on the entire surface of the transparent substrate 10b by sputtering or the like on the upper layer side of the silicon oxide film 202. Form.

Next, the entire tantalum film 205 is subjected to a high pressure annealing process in which it is annealed under a high pressure in an atmosphere containing water vapor. Here, the condition of the high-pressure annealing treatment is that the temperature is 600 ° C. or lower, for example, the temperature is 300 ° C. to 400 ° C.
C. and pressure are 0.5 MPa to 2 MPa. as a result,
The entire tantalum film 205 is oxidized to form a tantalum oxide film 201 as shown in FIG. 20D, and the silicon oxide film 202 and the gate insulating layer 2 including the tantalum oxide film 201 and the dielectric layer 71 are removed. It is formed.

After the high-pressure annealing process, if the annealing process is performed at a temperature of 200 ° C. to 500 ° C. under normal pressure or reduced pressure, moisture is removed from the tantalum oxide film 201, and the crystallinity is improved. Tantalum oxide film 201
The film quality is improved.

Next, with respect to the upper layer side of the gate insulating layer 2,
After forming an aluminum film on the entire surface of the transparent substrate 10b by a sputtering method or the like, patterning is performed by using a photolithography technique to form a scanning line 3a and a capacitance line 3b as shown in FIG.

Next, when the TFT 30 is an N-channel type TFT having an LDD structure, the scanning line 3a is used as a diffusion mask to form the low concentration source region 1b and the low concentration drain region 1c in the semiconductor layer 1a. As a dopant of a V group element such as P at a low concentration (for example, P
Ions are doped at a dose of 1 × 10 ¹³ / cm ^{2 to} 3 × 10 ¹³ / cm ² . As a result, the semiconductor layer 1a below the scanning line 3a becomes the channel formation region 1a '.

Next, as shown in FIG. 21B, the TFT
In order to form the high-concentration source region 1d and the high-concentration drain region 1e of 30, a resist mask 202 is formed on the scanning line 3a with a mask wider than the scanning line 3a, and then a group V element such as P is also added. Dopant 201 is highly doped. Note that an offset structure TFT may be used without performing low-concentration doping, and a self-aligned TFT may be formed by an ion implantation technique using P ions, B ions, etc., using the scanning line 3a (gate electrode) as a mask. good.

Next, as shown in FIG. 21C, an interlayer insulating film 4 made of a silicon oxide film is formed so as to cover the scanning lines 3a and the capacitance lines 3. Next, a contact hole 56 is formed in the interlayer insulating film 4 by dry etching such as reactive ion etching or reactive ion beam etching, or wet etching.

Next, after forming an aluminum film on the entire surface of the transparent substrate 10b on the upper layer side of the interlayer insulating film 4,
Patterning is performed by using the photolithography technique to form the data 6a as shown in FIG.

Next, as shown in FIG. 22A, an interlayer insulating film 7 made of a silicon oxide film is formed so as to cover the data lines 6a. Next, the contact holes 57 are formed in the interlayer insulating films 7 and 4 and the gate insulating layer 2 by dry etching such as reactive ion etching or reactive ion beam etching, or wet etching.

Next, with respect to the upper layer side of the interlayer insulating film 7, ITO is formed on the entire surface of the transparent substrate 10b by sputtering or the like.
After forming the film, patterning is performed by using the photolithography technique, and as shown in FIG.
a is formed.

Thereafter, as shown in FIG. 19, after applying a coating liquid of a polyimide-based alignment film on the upper layer side of the pixel electrode 9a, a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction. Thus, the alignment film 64 is formed, and the active matrix substrate 10 is completed.

[Ninth Embodiment] FIGS. 23, 24 and 2
5 and FIG. 26, an active matrix substrate for a liquid crystal device will be described as a semiconductor device according to the ninth embodiment of the present invention.

FIG. 23 is a sectional view of the liquid crystal device according to the ninth embodiment of the present invention, taken along the line BB ′ in FIG. 24 (A) to (E), FIG.
FIGS. 26A to 26D and FIGS. 26A and 26B are process cross-sectional views showing the method for manufacturing the active matrix substrate shown in FIG.

In the eighth embodiment, the TFT 30 is used.
Gate insulating film 2 and the dielectric layer 71 of the storage capacitor 70.
Are both tantalum oxide film 201 and silicon oxide film 2.
However, in the present embodiment, as shown in FIG. 23, the gate insulating film 2 includes the tantalum oxide film 201.
And the silicon oxide film 202, the dielectric layer 71 is composed only of the tantalum oxide film 201.

That is, in this embodiment, the gate insulating layer 2
Is a silicon oxide film 202 formed on the surface of the semiconductor film 1a by the CVD method or the like as in the eighth embodiment.
And a tantalum oxide film 201 formed by oxidizing the entire tantalum film formed on the silicon film 202 by high pressure annealing.

On the other hand, in the storage capacitor 70, the tantalum oxide film 201 formed by oxidizing the entire tantalum film formed on the upper layer of the silicon film 202 by the high-pressure annealing treatment is formed, but the lower electrode 1f is formed. Part of the silicon oxide film 202 is removed and the opening 2
08 is formed. Therefore, only the tantalum oxide film 201 is interposed as the dielectric layer 71 between the lower electrode 1f and the capacitance line 3b (upper electrode). Therefore, in this embodiment, since the dielectric constant of the dielectric layer 71 is high, the storage capacitor 70 having a large capacitance can be formed. Even on the lower layer side of the capacitance line 3b, the cross-section of the capacitance line 3b and the data line 6a is taken into consideration in consideration of the withstand voltage of the silicon oxide film 20.
It is preferable to leave 2. Since other configurations are the same as those of the eighth embodiment, portions having common functions are denoted by the same reference numerals and shown in FIG. 23, and description thereof will be omitted.

In manufacturing the active matrix substrate 10 having such a structure, as shown in FIG. 24A, first, a base protective film (not shown) is formed on the entire surface of the transparent substrate 10b which is the base of the active matrix substrate 10. No.) is formed, and then an amorphous silicon film is formed on the upper layer side of this base protective film. Next, an annealing process is performed at about 600 ° C. for about 1 hour to about 10 hours in a nitrogen atmosphere to solid-phase grow the polysilicon film, which is then patterned using photolithography technology to form islands. The silicon film 1a is formed.

Next, as shown in FIG. 24 (B), CVD
Silicon on the entire surface of the transparent substrate 10b by a method such as
The film 202 is formed. Next, in the silicon film 1a, the storage
For example, P is provided in the extended portion that becomes the lower electrode 1f of the storage capacitor 70.
About 3 × 10 ions¹²/ Cm ² Dope with a dose of
Keep the resistance low.

Next, as shown in FIG. 24C, the silicon film 20 formed on the lower electrode 1f of the silicon oxide film 202 is formed by photolithography.
2 is removed to form the opening 208.

Next, as shown in FIG. 24D, a tantalum film 205 (insulating film forming metal film) is formed on the entire surface of the transparent substrate 10b by sputtering or the like on the upper layer side of the silicon oxide film 202. Form.

Next, the entire tantalum film 205 is subjected to a high pressure annealing process in which it is annealed under a high pressure in an atmosphere containing water vapor. Here, the condition of the high-pressure annealing treatment is that the temperature is 600 ° C. or lower, for example, the temperature is 300 ° C. to 400 ° C.
C. and pressure are 0.5 MPa to 2 MPa. as a result,
The entire tantalum film 205 is oxidized to form a tantalum oxide film 201 as shown in FIG. Therefore, the gate insulating layer 2 including the silicon oxide film 202 and the tantalum oxide film 201 is formed, and the dielectric layer 71 including only the tantalum film 201 is formed.

After the high-pressure annealing treatment, if the annealing treatment is performed at a temperature of 200 ° C. to 500 ° C. under normal pressure or reduced pressure, moisture is removed from the tantalum oxide film 201 and the crystallinity is improved. Tantalum oxide film 201
The film quality is improved.

After that, as in the case of the eighth embodiment, after forming an aluminum film on the entire surface of the transparent substrate 10b on the upper layer side of the gate insulating layer 2 by a sputtering method or the like,
Patterning is performed by using the photolithography technique, and as shown in FIG. 25A, the scanning line 3a and the capacitor line 3 are formed.
b is formed. Next, using the scanning line 3a as a diffusion mask, N
After doping the type impurities, as shown in FIG. 25B, a resist mask 202 is formed on the scanning lines 3a with a mask wider than the scanning lines 3a, and the N type impurities are also doped. Next, as shown in FIG. 25C, after forming the interlayer insulating film 4 made of a silicon oxide film so as to cover the scanning lines 3 a and the capacitance lines 3, a contact hole 56 is formed in the interlayer insulating film 4. To do. Next, after forming an aluminum film on the entire surface of the transparent substrate 10b on the upper layer side of the interlayer insulating film 4, patterning is performed using a photolithography technique, and as shown in FIG.
a is formed. Next, as shown in FIG. 26A, after forming an interlayer insulating film 7 made of a silicon oxide film so as to cover the data lines 6a, contact holes 57 are formed in the interlayer insulating films 7 and 4 and the gate insulating layer 2. To form. Next, on the upper layer side of the interlayer insulating film 7, an ITO film is formed on the entire surface of the transparent substrate 10b by a sputtering method or the like, and then patterned by using a photolithography technique.
As shown in (B), the pixel electrode 9a is formed. Then, as shown in FIG. 23, a coating liquid of a polyimide-based alignment film is applied to the upper layer side of the pixel electrode 9a, and then a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction. 64 is formed, and the active matrix substrate 10 is completed.

[Other Embodiments] Although tantalum (Ta) is used as the metal film for forming the dielectric layer in the above embodiment, a tantalum alloy may be used. Further, if an oxide film can be formed by high-pressure annealing, niobium (Nb), molybdenum (Mo) may be used as the dielectric layer forming metal.
Other metals such as titanium (Ti) or alloys thereof may be used.

In the above embodiment, the silicon oxide film is used as the insulating film laminated with the tantalum oxide film, but a silicon nitride film may be used.

Further, in the above embodiment, the active matrix type liquid crystal device using the TFT element as the non-linear element for pixel switching has been described as an example, but the present invention is not limited to this, and various circuits are configured in other semiconductor devices. The present invention may be applied when forming a capacitor, and various modifications can be made within the scope of the invention described in the claims. The scope of the present invention naturally includes an active matrix type liquid crystal device using a TFD element as a non-linear element for switching. Further, the present invention provides
It is needless to say that the present invention is also applicable to electroluminescence (EL), digital micromirror device (DMD), or electro-optical devices using various electro-optical elements using plasma emission or fluorescence due to electron emission. .

[Structure of Liquid Crystal Device] Embodiments 4 to 9
The overall configuration of the liquid crystal device 100 using the active matrix substrate 10 manufactured by will be described with reference to FIGS. 27 and 28. 27 is a plan view of the liquid crystal device 100 together with the components formed thereon as viewed from the counter substrate 20 side, and FIG. 28 is a H-H view of FIG. 27 including the counter substrate 20. ′ It is a cross-sectional view.

In FIG. 27, a sealing material 52 is provided along the edge of the active matrix substrate 10 of the liquid crystal device 100, and a frame 53 made of a light shielding material is formed in the inner area thereof. Has been done. Seal material 52
In the region outside of, the data line driving circuit 101 and the mounting terminals 102 are provided along one side of the active matrix substrate 10, and the scanning line driving circuit 104 is formed along two sides adjacent to this one side. ing. It goes without saying that the scanning line driving circuit 104 may be provided on only one side if the delay of the scanning signal supplied to the scanning line does not matter. Further, the data line driving circuits 101 may be arranged on both sides along the side of the image display area 10a. For example, the odd-numbered data lines supply an image signal from a data line driving circuit arranged along one side of the image display area 10a,
The data lines in the even-numbered columns may be supplied with an image signal from a data line driving circuit arranged along the opposite side of the image display area 10a. By thus driving the data lines in a comb shape, the formation area of the data line driving circuit 101 can be expanded, so that a complicated circuit can be configured. Furthermore, the active matrix substrate 10
A plurality of wirings 1 for connecting between the scanning line driving circuits 104 provided on both sides of the image display area 10a are provided on the remaining one side.
05 is provided, and a precharge circuit and a test circuit may be provided under the frame 53. In addition, at least one of the corners of the counter substrate 20
At the location, a vertical conduction member 1 for electrically connecting the active matrix substrate 10 and the counter substrate 20.
06 is formed.

Then, as shown in FIG. 28, the counter substrate 20 having substantially the same contour as that of the sealing material 52 shown in FIG.
Is stuck to. In this counter substrate 20, a light-shielding film 23 called a black matrix or a black stripe is formed in a region facing the vertical and horizontal boundary regions of the pixel electrodes 9a formed on the active matrix substrate 10.
Is formed, and the counter electrode 21 made of an ITO film is formed on the upper side thereof. An alignment film (not shown) made of a polyimide film is formed on the upper layer side of the counter electrode 21, and the alignment film is a film obtained by rubbing the polyimide film.

Instead of forming the data line driving circuit 101 and the scanning line driving circuit 104 on the active matrix substrate 10, for example, a TAB (tape automated, bonding) substrate on which a driving LSI is mounted is used as an active matrix. You may make it electrically and mechanically connect to the terminal group formed in the peripheral part of the board | substrate 10 through an anisotropic conductive film. Further, on the light incident side surface or the light emitting side of the counter substrate 20 and the active matrix substrate 10, the type of the liquid crystal 50 used,
That is, TN (Twisted Nematic) mode,
A polarizing film, a retardation film, a polarizing plate, etc. are arranged in a predetermined direction depending on the operation mode such as STN (super TN) mode and the normally white mode / normally black mode.

The electro-optical device thus formed is used, for example, in a projection type liquid crystal display device (liquid crystal projector) described later. In this case, three liquid crystal devices 1
00 is used as a light valve for RGB, and the light of each color decomposed through the dichroic mirror for RGB color separation enters each of the liquid crystal devices 100 as projection light. Therefore, the color filter is not formed in the liquid crystal device 100 of each of the above-described embodiments.

However, in the counter substrate 20, each pixel electrode 9
By forming an RGB color filter together with its protective film in a region facing a, a mobile computer, a mobile phone, and
It can be used as a color liquid crystal display device for electronic devices such as liquid crystal televisions.

Furthermore, by forming a microlens on the counter substrate 20 so as to correspond to each pixel,
Since the efficiency of collecting incident light on the pixel electrode 9a can be improved, bright display can be performed. Furthermore, by stacking a number of interference layers having different refractive indexes on the counter substrate 20, a dichroic filter that produces RGB colors may be formed by utilizing the interference effect of light. According to the counter substrate with the dichroic filter, brighter color display can be performed.

[Application to Electronic Equipment] Next, examples of electronic equipment including an electro-optical device will be described with reference to FIGS. 29, 30, and 31.
And it demonstrates with reference to FIG.

First, FIG. 29 is a block diagram showing the configuration of an electronic apparatus including a liquid crystal device 100 having the same configuration as the electro-optical device according to each of the above embodiments.

In FIG. 29, the electronic equipment includes a display information output source 1000, a display information processing circuit 1002, and a drive circuit 1.
004, the liquid crystal device 100, the clock generation circuit 1008,
And a power supply circuit 1010. The display information output source 1000 is a ROM (Read Only Me
memory), RAM (Random AccessMe)
memory), a memory such as an optical disk, a tuning circuit that tunes and outputs a picture signal of a television signal, and the like, and processes an image signal of a predetermined format based on a clock from a clock generation circuit 1008 to display information. Output to the processing circuit 1002. This display information output circuit 10
Reference numeral 02 denotes a well-known processing circuit such as an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, or a clamp circuit, which is a digital signal based on display information input based on a clock signal. Drive circuit 1 together with the clock signal CLK.
Output to 004. The drive circuit 1004 is used for the liquid crystal device 10.
Drive 0. The power supply circuit 1010 supplies a predetermined power supply to each of the above circuits. The drive circuit 1004 may be formed on the active matrix substrate that constitutes the liquid crystal device 100, and in addition to this, the display information processing circuit 100
2 may also be formed on the active matrix substrate.

FIG. 3 shows an electronic device having such a configuration.
Projection type liquid crystal display device (liquid crystal projector), multimedia compatible personal computer (PC), and engineering workstation (EWS), pager, mobile phone, word processor, television, viewfinder type or Examples include a monitor direct-view video tape recorder, an electronic notebook, an electronic desk calculator, a car navigation device, a POS terminal, and a touch panel. The present invention also provides an electronic device including an electro-optical device using electroluminescence (EL), a digital micromirror device (DMD), or various electro-optical elements that use plasma emission, fluorescence due to electron emission, or the like. It goes without saying that it is also applicable.

A projection type liquid crystal display device 1100 shown in FIG.
Prepares three liquid crystal modules including the liquid crystal device 100 in which the drive circuit 1004 is mounted on the active matrix substrate, and the light valves 100R for RGB respectively.
It is configured as a projector used as 100G and 100B. In this liquid crystal projector 1100, a lamp unit 1 for a white light source such as a metal halide lamp is used.
When light is emitted from 102, three mirrors 1106 and two dichroic mirrors 1108
The light components R, G, and B corresponding to the three primary colors R, G, and B are separated (light separating means), and the corresponding light valves 100R and
100G and 100B (liquid crystal device 100 / liquid crystal light valve), respectively. At this time, the light component B has a long optical path, and thus is guided through the relay lens system 1121 including the entrance lens 1122, the relay lens 1123, and the exit lens 1124 in order to prevent light loss. Then, the light components R, G, and B respectively corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 1112 (light combining means) from three directions, are combined again, and are then projected onto the projection lens. It is projected as a color image on the screen 1120 or the like via 1114.

FIG. 31 shows a mobile personal computer which is an embodiment of the electronic apparatus according to the present invention. The personal computer shown here includes a main body 82 having a keyboard 81 and a liquid crystal display unit 83.
Have and. The liquid crystal display unit 83 is configured to include the liquid crystal device 100 described above.

FIG. 32 shows a mobile phone which is another embodiment of the electronic apparatus according to the present invention. The mobile phone 90 shown here has a plurality of operation buttons 91 and a liquid crystal device 100.
have.

[0163]

As described above, according to the present invention, the dielectric layer of the capacitor contains the tantalum oxide film formed by the high-pressure annealing treatment, so that the dielectric layer has a high withstand voltage.
Further, in the present invention, since the tantalum oxide film is formed by the high pressure annealing treatment, it is not necessary to form the power supply wiring for performing the anodic oxidation. Therefore, TFT on the same substrate
The degree of freedom of design is great in a semiconductor device in which the above is formed. In addition, there is an advantage that a large number of substrates can be collectively processed. Moreover, since the temperature of the high-pressure annealing treatment is 600 ° C. or lower, more preferably 300 ° C. to 400 ° C., there is no problem even when a glass substrate is used as the substrate. Further, even when the aluminum wiring is formed during the high-pressure annealing treatment, under such temperature conditions, the aluminum wiring is not deteriorated unless the aluminum wiring is exposed.

[Brief description of drawings]

1A and 1B are cross-sectional views each schematically showing a configuration of a semiconductor device according to a first embodiment of the present invention and a modification thereof.

2A and 2B are cross-sectional views each schematically showing a configuration of a semiconductor device according to a second embodiment of the present invention and a modified example thereof.

3 (A), (B), and (C) are cross-sectional views each schematically showing a configuration of a semiconductor device according to a second embodiment of the present invention and a modification thereof.

FIG. 4 is an equivalent circuit diagram of various elements and wirings formed in a plurality of pixels arranged in a matrix in an image display area of a liquid crystal device to which the present invention is applied.

5 is a plan view showing a configuration of each pixel formed on the active matrix substrate according to Embodiment 4 of the present invention in the liquid crystal device shown in FIG. 2. FIG.

6 is a cross-sectional view of the liquid crystal device shown in FIG. 5 taken along the line AA ′ in FIG.

7A to 7D are respectively FIG. 5 and FIG.
FIG. 6 is a process cross-sectional view showing the method for manufacturing the active matrix substrate shown in FIG.

8A to 8D are respectively FIG. 5 and FIG.
8 is a process cross-sectional view of a process performed subsequent to the process shown in FIG. 7 in the manufacturing process of the active matrix substrate shown in FIG.

FIG. 9 shows a liquid crystal device according to a fifth embodiment of the present invention.
FIG. 6 is a cross-sectional view when cut at a position corresponding to the line AA ′ in FIG.

10A to 10E are process cross-sectional views showing a method for manufacturing the active matrix substrate shown in FIG.

11A to 11D are process cross-sectional views of a process performed subsequent to the process shown in FIG. 10 in the manufacturing process of the active matrix substrate shown in FIG. 9.

12 is a cross-sectional view of the liquid crystal device according to Embodiment 6 of the present invention when cut at a position corresponding to line AA ′ in FIG.

13A to 13D are process cross-sectional views showing a method for manufacturing the active matrix substrate shown in FIG.

14A to 14D are process cross-sectional views of a process performed subsequent to the process shown in FIG. 13 in the manufacturing process of the active matrix substrate shown in FIG.

15 is a cross-sectional view of the liquid crystal device according to Embodiment 7 of the present invention when cut at a position corresponding to line AA ′ in FIG.

16A to 16E are process cross-sectional views showing a method for manufacturing the active matrix substrate shown in FIG.

17A to 17D are process cross-sectional views of a process performed subsequent to the process shown in FIG. 16 in the manufacturing process of the active matrix substrate shown in FIG.

FIG. 18 is a plan view showing the configuration of each pixel formed on the active matrix substrate used in the liquid crystal device according to Embodiment 8 of the present invention.

FIG. 19 shows a liquid crystal device according to an eighth embodiment of the present invention.
8 is a cross-sectional view when cut at a position corresponding to line BB 'of FIG.

20A to 20D are process cross-sectional views showing a method for manufacturing the active matrix substrate shown in FIGS. 18 and 19, respectively.

21A to 21D are process cross-sectional views of a process performed subsequent to the process shown in FIG. 20 in the manufacturing process of the active matrix substrate shown in FIGS. 18 and 19.

22A and 22B are process cross-sectional views of a process performed subsequent to the process shown in FIG. 21 in the manufacturing process of the active matrix substrate shown in FIGS. 18 and 19.

23 is a cross-sectional view of the liquid crystal device according to Embodiment 9 of the present invention when cut at a position corresponding to line BB ′ in FIG. 18.

24A to 24E are process cross-sectional views showing a method for manufacturing the active matrix substrate shown in FIG. 23.

25A to 25D are process cross-sectional views of a process performed subsequent to the process shown in FIG. 24 in the manufacturing process of the active matrix substrate shown in FIG. 23.

26A and 26B are process cross-sectional views of a process performed subsequent to the process shown in FIG. 25 in the manufacturing process of the active matrix substrate shown in FIG. 23.

FIG. 27 is a plan view of the liquid crystal device when viewed from the counter substrate side.

28 is a cross-sectional view taken along the line HH ′ of FIG. 27.

FIG. 29 is a block diagram showing a circuit configuration of an electronic device using the liquid crystal device according to the present invention as a display unit.

FIG. 30 is a cross-sectional view showing a configuration of an optical system of a projection type electro-optical device as an example of an electronic apparatus using the liquid crystal device according to the invention.

FIG. 31 is an explanatory diagram showing a mobile personal computer as one embodiment of an electronic apparatus using the liquid crystal device according to the present invention.

FIG. 32 is an explanatory diagram of a mobile phone as an embodiment of an electronic device using the liquid crystal device according to the invention.

[Explanation of symbols]

1a semiconductor layer 1a 'channel formation region 2 Gate insulation layer 3a scanning line 3b Capacitance line 3c gate electrode 6a data line 9a Pixel electrode 10 Active matrix substrate (semiconductor device) 10b transparent substrate 20 Counter substrate 30 pixel switching TFT 50 Liquid crystal (electro-optical material) 70 Storage capacity (capacitor) 71, 330 Dielectric layer 100 Liquid crystal device (electro-optical device) 201,331 Tantalum oxide film 202, 332 Silicon oxide film 205 Tantalum film (metal film for forming dielectric layer) 208 opening 300A, 300B, 300C semiconductor device 310 substrate 320 lower electrode 350 upper electrode 600 capacitors

Continued front page    F term (reference) 2H092 GA18 JB69 KA22 KB28 MA23                       MA29                 5F038 AC05 AC15 AC16 AC18 EZ17                       EZ20                 5F058 BA01 BC03 BF53 BF54 BF58                       BF63 BH01                 5F110 AA12 AA30 BB01 BB20 CC02                       CC07 DD02 DD03 EE03 EE04                       EE14 EE44 FF01 FF02 FF03                       FF09 FF22 FF29 FF32 FF36                       GG02 GG13 GG35 GG47 HJ01                       HJ04 HJ13 HK07 HK09 HK21                       HL03 HL07 HM15 NN01 NN02                       NN12 NN23 NN72 NN73 PP10                       QQ11 QQ30

Claims (17)

[Claims] 1. A capacitor in which a lower electrode, a dielectric layer, and an upper electrode are laminated in this order, wherein the dielectric layer is formed by a high-pressure annealing process of annealing under high pressure in an atmosphere containing water vapor. A capacitor including an oxide film formed by oxidizing a metal film for use in a capacitor. 2. The semiconductor device according to claim 1, wherein the dielectric layer is composed of only the oxide film. 3. The semiconductor device according to claim 1, wherein the dielectric layer has a multilayer structure of the oxide film and another insulating film. 4. The method according to any one of claims 1 to 3,
The semiconductor device, wherein the dielectric layer forming metal film is a tantalum film or a tantalum alloy film. 5. The method according to any one of claims 1 to 4,
The lower electrode is made of the same metal as the dielectric layer forming metal film at least on a side in contact with the dielectric layer. 6. The method according to any one of claims 1 to 4,
The lower electrode is made of a material different from that of the dielectric layer forming metal film. 7. A semiconductor device comprising a capacitor as defined in any one of claims 1 to 6. 8. An electro-optical device comprising the semiconductor device as defined in claim 7 as an active matrix substrate, wherein the capacitor is used as a storage capacitor in each pixel of the active matrix substrate. Electro-optical device. 9. An electronic apparatus using the electro-optical device defined in claim 8. 10. A method of manufacturing a capacitor having a lower electrode, a dielectric layer, and an upper electrode, wherein a high-pressure annealing treatment is performed after forming a metal film for forming a dielectric layer, and then annealing at high pressure in an atmosphere containing water vapor. A method for manufacturing a capacitor, characterized in that the metal film for forming a dielectric layer is oxidized to produce an oxide film, and the oxide film is used as the dielectric layer or a part of the dielectric layer. 11. The method of manufacturing a capacitor according to claim 10, wherein the dielectric layer forming metal film is a tantalum film or a tantalum alloy film. 12. The high-pressure annealing process according to claim 10, wherein only the surface of the dielectric layer forming metal film is oxidized to generate the oxide film, and the oxide film is used as the dielectric layer or the dielectric film. A method for manufacturing a capacitor, which is used as a part of a body layer and uses the remaining metal film for forming a dielectric layer as the lower electrode or a part of the lower electrode. 13. The lower electrode is formed on a lower layer side of the dielectric layer forming metal film according to claim 10, and the entire dielectric layer forming metal film is oxidized in the high pressure annealing treatment. Then, the oxide film is generated, and the oxide film is used as the dielectric layer or a part of the dielectric layer. 14. The method of manufacturing a capacitor according to claim 10, wherein the high-pressure annealing treatment is performed under a condition of a temperature of 600 ° C. or lower. 15. The high pressure annealing process according to claim 10, wherein a temperature of 300 ° C. to 40 ° C.
A method for manufacturing a semiconductor device, which is performed under conditions of 0 ° C. and a pressure of 0.5 MPa to 2 MPa. 16. The method of manufacturing a capacitor according to claim 10, wherein after the high-pressure annealing treatment is performed, the annealing treatment is performed under normal pressure or reduced pressure. 17. A method of manufacturing a semiconductor device, characterized in that a capacitor is manufactured on a substrate by the manufacturing method defined in any one of claims 10 to 16.