JP2003160395A - Warp resistant silicon wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide silicon wafer having excellent mechanical strength and substantially free from warpage due to heat shock by effectively suppressing the warpage of silicon wafer caused by heat shock or dead weight in a heat treatment process of silicon wafer. <P>SOLUTION: This silicon wafer contains, in the single crystal of silicon, germanium (Ge) at a concentration of 5×10<SP>19</SP>to 1.5×10<SP>20</SP>atoms/cm<SP>3</SP>and oxygen at a concentration of 11×10<SP>17</SP>to 18×10<SP>17</SP>atoms/cm<SP>3</SP>(OLD ASTM), or contains germanium (Ge) at a concentration of 2×10<SP>18</SP>to 1.5×10<SP>20</SP>atoms/cm<SP>3</SP>, oxygen at a concentration of 11×10<SP>17</SP>to 18×10<SP>17</SP>atoms/cm<SP>3</SP>(OLD ASTM) and boron (B) at a concentration of 1×10<SP>18</SP>to 2×10<SP>20</SP>atoms/cm<SP>3</SP>. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon wafer used for manufacturing semiconductors, optical devices, etc.,
More specifically, the present invention relates to a silicon wafer which is effectively suppressed from being warped due to thermal shock in a device processing step, is substantially free from warpage due to thermal shock, and has excellent mechanical strength.

[0002]

2. Description of the Related Art Silicon wafers used as semiconductor materials for ICs, LSIs, etc. are mainly made of silicon single crystals produced by the Czochralski method (hereinafter referred to as "CZ method").

In general, a silicon wafer has a desired concentration of boron and a dopant such as phosphorus, arsenic, antimony or the like added to a silicon single crystal to control the electrical properties of the silicon wafer.

Silicon wafers become products after undergoing various heat treatment processes in device manufacturers. In this heat treatment step, non-uniformity of temperature in the silicon wafer that occurs when the silicon wafer is taken in and out of the heat treatment furnace,
There is a problem in that the silicon wafer is warped due to thermal shock when the temperature is raised or lowered in the heat treatment furnace, the focus is blurred during pattern transfer, and the product yield is reduced. In particular, in the case of a large-diameter silicon wafer of 8 inches (diameter 200 mmφ) or more, during heat treatment, the stress generated due to the weight of the silicon wafer causes the silicon wafer to warp, significantly lowering the product yield,
It was a problem.

As a solution to the above, conventionally, the interstitial oxygen concentration in the silicon wafer is controlled to be constant, the mechanical strength of the silicon wafer is kept within a certain range by the action of the interstitial oxygen, and the warp of the silicon wafer due to thermal shock occurs. Was suppressed, but a sufficient warp suppressing effect could not be obtained.

Japanese Unexamined Patent Publication No. 62-72595 discloses a silicon semiconductor substrate material and a method of manufacturing the same. It is described in the specification that the strength of a silicon substrate material is increased by adding a high concentration of germanium (hereinafter referred to as “Ge”) as an impurity to a silicon melt. At least 8,000 Ge atoms per 1 million atoms, or 5
It is described that by adding x10 ²⁰ atoms / cm ³ or more, a silicon substrate used for most purposes can be suitably strengthened.

However, as a result of additional tests by the present inventors, the mechanical strength does not increase at the Ge concentration described in Japanese Patent Laid-Open No. 62-72595, and conversely, the mechanical strength increases as the Ge concentration increases. It became clear that in the extreme case, the growth of a silicon single crystal became impossible.

Conventionally, as a method for suppressing the warp generated in a silicon wafer due to a thermal shock in a device processing step, a method of heat treating the silicon wafer at a low temperature, a method of delaying the loading / unloading of the silicon wafer into / from the heat treatment furnace, and a heat treatment furnace The method of taking in and out the silicon wafer after lowering the temperature of No. 2 or the method of slowing the rate of temperature increase / decrease during the heat treatment was adopted. However, this method has a problem of lowering productivity. there were. Moreover, it cannot be applied to a large-diameter silicon wafer of 8 inches or more.

Further, in consideration of the warp of the silicon wafer due to the thermal shock in the device processing process due to the insufficient mechanical strength of the silicon wafer, the device processing process is performed by using a silicon wafer thicker than the IC chip to be the product. After that, the back surface of the silicon wafer is re-polished and scraped off.
Although a method for producing a product has been adopted, this method has a problem that productivity is reduced due to an increase in processing steps, cost is increased, economic efficiency is poor, and a silicon ingot cannot be efficiently used. .

In the device processing process of silicon wafers, there has been a demand for a solution which has high productivity and which does not reduce the product yield and which can be applied to a silicon wafer having a large diameter of 8 inches or more.

[0011]

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems, effectively suppress the warpage of a silicon wafer due to thermal shock in the device processing step of the silicon wafer, and prevent the warpage due to thermal shock. It is an object of the present invention to provide a warpage resistant silicon wafer having substantially no mechanical strength.

[0012]

[Means for Solving the Problems]

The inventors of the present invention filed Japanese Patent Application No. 2001 previously filed.
No. 344136, a silicon wafer contains Ge as a high-concentration impurity and oxygen as a high-concentration impurity, or Ge as a high-concentration impurity, oxygen as a high-concentration impurity, and A silicon wafer containing a high concentration of boron (hereinafter referred to as “B”), which is an impurity, is formed by Ge-oxygen complex or Ge-oxygen-B complex formed in the silicon wafer.
It was proposed that slips and dislocations due to thermal shock can be effectively fixed in the micro range and a silicon wafer having high thermal shock resistance can be obtained.

The inventors of the present invention filed Japanese Patent Application No. 2001-34413.
Regarding the silicon wafer disclosed in No. 6, in addition to the thermal shock resistance that does not generate slips and dislocations due to thermal shock, as a result of diligent study on mechanical strength such as warpage of the silicon wafer caused by thermal shock, Japanese Patent Application No. 2001-34413 was found.
It was found that the silicon wafer disclosed in No. 6 is a warp-resistant silicon wafer having excellent mechanical strength, which effectively suppresses warpage of the silicon wafer due to thermal shock and is substantially free of warpage due to thermal shock. The present invention has been completed.

That is, the warpage-resistant silicon wafer according to claim 1 of the present invention is characterized in that the silicon wafer contains Ge, which is a high concentration impurity, and oxygen, which is a high concentration impurity. It is a feature.

The warpage resistant silicon wafer according to claim 2 has the Ge concentration of 5 × in the invention according to claim 1.
10 ^{19 to} 1.5 × 10 ²⁰ atoms / cm ³ and an oxygen concentration of 10 × 10 ¹⁷ to 18 × 10 ¹⁷
It is characterized in that it is atoms / cm ³ (OLD ASTM).

In the warpage resistant silicon wafer according to claim 3, the warpage due to thermal shock depends only on the concentrations of Ge and oxygen according to claim 2, and is independent of the types and concentrations of other dopants. It is characterized by.

In the warpage resistant silicon wafer according to claim 4, Ge which is a high concentration of impurities in the silicon wafer.
And oxygen, which is a high-concentration impurity, and B, which is a high-concentration impurity.

A warpage resistant silicon wafer according to claim 5.
In the invention according to claim 4, the Ge concentration is 2 ×
10¹⁸~ 1.5 × 10²⁰atoms / cm^ThreeAnd
And the oxygen concentration is 11 × 10¹⁷~ 18 × 10¹⁷
atoms / cm^Three(OLD ASTM), and
B concentration is 1 × 10¹⁸~ 2 x 10²⁰atoms / c
m ^ThreeIt is characterized by being.

In the warpage resistant silicon wafer according to claim 6, the warpage due to thermal shock depends only on the concentrations of Ge, oxygen and B according to claim 5, and is independent of the types and concentrations of other dopants. It is characterized by being.

The present invention will be described in detail below.

The warpage-resistant silicon wafer according to the first aspect of the present invention has a high concentration of Ge which is an impurity in the silicon wafer.
And a high concentration of oxygen, which is an impurity.

Ge formed by a high concentration impurity Ge and a high concentration impurity oxygen in a silicon wafer.
-Since the oxygen complex can effectively fix the slips and dislocations generated in the silicon wafer in the micro range and sufficiently suppress the warp of the silicon wafer caused by the thermal shock in the macro range, the silicon caused by the thermal shock can be suppressed. It is possible to realize a warp-resistant silicon wafer having substantially no mechanical warp and excellent mechanical strength.

Ge added to the silicon crystal is the same as silicon in Group IV of the Periodic Table of Elements, and the band gap (Eg) at room temperature is 0.66 eV for Ge and 1.12 eV for silicon, which is slightly different. Although different, G in the silicon crystal
Even if e is added, the electrical characteristics such as resistivity and conductivity of the silicon single crystal do not change, and since the silicon single crystal and the added Ge form a mixed crystal, the Ge concentration is continuously adjusted. It is possible to

Oxygen in the silicon single crystal is also contained in the conventional silicon wafer, and if the oxygen concentration is controlled to a constant value, there is no particular problem.

In the first embodiment, the Ge concentration in the silicon wafer is 5 × 10 ^{19 to} 1.5 × 10 ²⁰ atom.
s / cm ³ and the oxygen concentration is 11 × 10 ¹⁷
~ 18 × 10 ¹⁷ atoms / cm ³ (OLD AST
M).

Ge concentration is 5 × 10 ¹⁹ atoms / c
less than m ³ or oxygen concentration of 11 × 10 ¹⁷ atom
If it is less than s / cm ³ (OLD ASTM), the Ge-oxygen complex formed in the silicon wafer becomes too small, and the effect of suppressing warpage due to thermal shock becomes insufficient, which is inconvenient.

The Ge concentration in the silicon wafer is 5 × 10.
¹⁹~ 1.5 × 10²⁰atoms / cm^Three, And oxygen
Concentration is 11 × 10¹⁷~ 18 × 10¹⁷atoms /
cm ^ThreeWithin the range of (OLD ASTM)
Due to the Ge-oxygen complex formed in the roof,
Effectively suppress warpage of silicon wafers due to thermal shock
And is substantially free from warpage due to thermal shock
And has excellent mechanical strength.

However, the Ge concentration is 1.5 × 10 5.
^{If it} exceeds ²⁰ atoms / cm ³ , lattice distortion occurs in the silicon single crystal, and the effect of suppressing warpage due to thermal shock is drastically reduced. Further, at the time of growing the silicon single crystal, even if there is no other cause of dislocation, a slip is included in the silicon single crystal, and a dislocation-free silicon single crystal cannot be manufactured.

Further, the Ge concentration is increased to about 1 × 1.
When it becomes 0 ²¹ atoms / cm ³ , a composition supercooling phenomenon occurs during the growth of a silicon single crystal, and the growing single crystal changes to a polycrystal, so that a silicon single crystal cannot be obtained.

Ge concentration is 5 × 10 ¹⁹ atoms / c
less than m ³ , or oxygen concentration of 11 × 10 ¹⁷ atoms
If it is less than / cm ³ (OLD ASTM), the Ge-oxygen complex formed in the silicon wafer becomes too small, and the effect of suppressing warpage due to thermal shock becomes insufficient, which is inconvenient.

The oxygen concentration is 18 × 10 ¹⁷ ato
When it exceeds ms / cm ³ (OLD ASTM), a large amount of oxygen precipitates are generated as defects in the silicon wafer, and the silicon wafer is liable to warp due to thermal shock, which is inconvenient.

A silicon wafer containing Ge and oxygen within the above concentration range may have other dopants, such as B, phosphorus, arsenic, antimony, etc.
-It has nothing to do with the effect of slippage and dislocation fixation by the oxygen complex, and has no effect on the effect of suppressing warpage due to thermal shock.

The warpage-resistant silicon wafer according to the second aspect of the present invention has a high concentration of Ge which is an impurity in the silicon wafer.
And oxygen, which is a high-concentration impurity, and B, which is a high-concentration impurity.

In the second embodiment, the Ge concentration in the silicon wafer is 2 × 10 ^{18 to} 1.5 × 10 ²⁰ atom.
s / cm ³ , and the oxygen concentration is 11 × 10 ¹⁷ to
18 × 10 ¹⁷ atoms / cm ³ (OLD AST
M), and the B concentration is 1 × 10 ¹⁸ to 2 × 10.
^{It is 20} atoms / cm ³ .

In the second aspect, Ge in the first aspect
Even when the lower limit of the concentration is less than 5 × 10 ¹⁹ atoms / cm ³ , that is, the Ge concentration is 2 × 10 ¹⁸ atoms.
If it is / cm ³ or more, it is possible to obtain the same effect of suppressing warpage due to thermal shock as in the first aspect.

In the second embodiment in which B, which is a high-concentration impurity, is added together, Ge, oxygen, and B in the silicon wafer are added.
The Ge-oxygen-B complex formed by is more stable than the Ge-oxygen complex formed by Ge and oxygen of the first aspect, and slips and dislocations generated in the silicon wafer can be suppressed in the micro range. It is more effectively fixed, slip and dislocation caused by thermal shock are sufficiently suppressed in the macro range, and the effect of suppressing warpage caused by thermal shock is further enhanced.

In the second aspect, even if the Ge concentration is lower by one digit or more than the Ge concentration in the first aspect, the same effect of suppressing the warpage caused by thermal shock as in the first aspect can be obtained.

Ge concentration is 2 × 10¹⁸atoms / c
m^ThreeLess than, oxygen concentration is 11 × 10 ¹⁷atoms / c
m^ThreeLess than (OLD ASTM) or B concentration is 1 ×
10 ¹⁸atoms / cm^ThreeIf any of the following,
Ge− formed by Ge, oxygen and B in the silicon wafer
Oxygen-B complex is too small and is caused by thermal shock.
The effect of suppressing warpage is insufficient, which is inconvenient.

B concentration is 2 × 10 ²⁰ atoms / cm 2.
For ³ exceeds, during the growth of silicon single crystal, the composition supercooling, there is a risk of polycrystalline, the growth rate of the crystal, not have to very slow, productivity is significantly reduced, inconvenience Is.

A silicon wafer containing Ge, oxygen, and B within the above concentration range has a low concentration of Ge, oxygen, and antimony as other dopants.
-It has nothing to do with the effect of slip and dislocation fixation by the oxygen-B complex, and has no effect on the effect of suppressing warpage due to thermal shock.

The warpage resistant silicon wafer of the present invention is manufactured by the following method.

First, a predetermined amount of G is added to the silicon crystal.
e and oxygen, or a predetermined amount of Ge, oxygen, and B, respectively, and if necessary, other dopants are appropriately added, and a silicon single crystal is grown by using an ordinary single crystal growth method such as the CZ method. Grow crystals. Next, the grown silicon single crystal is processed by using a processing method that is usually used to produce a warpage resistant silicon wafer of the present invention.

The warpage-resistant silicon wafer of the present invention is effectively suppressed in warpage of the silicon wafer due to thermal shock in the device processing step, substantially free from warpage due to thermal shock, and excellent in mechanical strength. There is. Further, since the warpage due to the thermal shock in the device processing step and the weight of the silicon wafer is effectively suppressed, the workability and the productivity are excellent,
The product yield does not decrease.

The warpage resistant silicon wafer of the present invention is effectively suppressed from being warped due to thermal shock or the self-weight of the silicon wafer in the device processing step. Therefore, even a large diameter silicon wafer of 8 inches or more can be manufactured with high productivity. The product yield does not decrease.

Since the warpage resistant silicon wafer of the present invention has excellent mechanical strength and substantially no warpage due to thermal shock, it becomes a product in the device processing step as in the conventional case.
It is not necessary to use a silicon wafer that is thicker than the C chip,
A silicon wafer having a product thickness can be used as it is, which is excellent in productivity and economic efficiency, and a silicon ingot can be used efficiently and effectively.

[0047]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the invention will be described below based on Examples. The present invention, according to the embodiment,
There is no limitation.

Example 1 Density 0 (blank), 1 × 10 ¹⁹ to 2 × 10 ²⁰ at
Ge of oms / cm ³ and concentration 5 × 10 ¹⁷ to 18 × 1
O ¹⁷ atoms / cm ³ (OLD ASTM) and oxygen are added in combination as shown in Table 1,
After growing a 6-inch (diameter 150 mmφ) silicon single crystal by the CZ method, the thickness 6
A 25-μm 6-inch (100) mirror-surface test wafer was prepared.

Further, in addition to Ge and oxygen, as another dopant, B was added in an amount of about 10 ¹⁵ atoms / cm ³ or phosphorus was also added in an amount of about 10 ¹⁴ atoms / cm ³ , and the test wafer was similarly processed. It was made.

Warpage of manufactured test wafer (Warp)
Is measured by using a wafer check microscan device (Microscan 8300 manufactured by Japan AD Co., Ltd., abbreviated as “ADE” hereinafter), and a thermal shock warpage test is performed as shown below. It was

The warp of the wafer is defined as the difference between the maximum displacement and the minimum displacement of the wafer center plane from the reference plane on the back surface of the wafer, which is based on the plane calculated by the least square method at all the measurement points within the wafer plane. It

First, the warp of the taken-out test wafer was measured at room temperature, and the initial value of the warp of the test wafer before heat treatment was measured. Then, the test wafer was loaded into a heat treatment furnace at a temperature of 1100 ° C. at a loading rate (heating rate conversion) of 100 ° C./min in a wet oxidizing atmosphere, left for 2 hours, and then left in a heat treatment furnace for 3 types. Extraction speed (cooling speed conversion) 500, 2
The warp of the test wafer after the heat treatment was measured at 00 or 100 ° C./min. The difference between the measured value of the warp of the test wafer after the heat treatment and the initial value (the difference in the warp before and after the heat treatment) was obtained.

The difference in the warp of the test wafer before and after the heat treatment is 1
When the thickness was not less than μm, the test wafer was judged to have “substantially” the warp due to thermal shock, and when it was less than 1 μm, the warp due to the thermal shock was judged to be “substantially none”. The test results are shown in Table 1. In the table, warpage due to thermal shock is "substantially"
Is indicated by “×”, and “substantially none” is indicated by “◯”.

Example 2 A silicon crystal having a concentration of 4 × 10 ¹⁹ atoms / cm ³
Ge with a concentration of 1 × 10 ¹⁵ atoms / cm ³ (OL
DASTM) and oxygen are added, and 5 inches (diameter 125 m are obtained by a floating body method (hereinafter referred to as “FZ method”).
After growing the mφ) silicon single crystal, a 5-inch (100) mirror-surface test wafer having a thickness of 625 μm was produced by a known processing method.

The produced test wafer was subjected to a thermal shock warpage test using ADE in the same manner as in Example 1. The test results are shown in Table 1.

[0056]

[Table 1]

Table 1 shows that the test wafers produced by the CZ method or the FZ method while varying the concentrations of Ge and oxygen were left in a heat treatment furnace at a temperature of 1100 ° C. for 2 hours, and then the removal rate (cooling rate) was measured. Conversion) 500, 200 or 100 ℃
It is the result of a thermal shock warp test when taken out at a speed of 1 / min.

In Example 1, the Ge concentration was 1.5 ×
2 × 10 ²⁰ a, which is more than 10 ²⁰ atoms / cm ^3.
In the case of toms / cm ³ , in all thermal shock warpage tests, the difference in warpage before and after heat treatment was 1 μm or more,
Warpage due to thermal shock was “substantially present”.

The Ge concentration is 5 × 10 ^{19 to} 1.5 × 10.
²⁰ atoms / cm ³ and oxygen concentration of 11 × 10
^{17 ~18 × 10 17 atoms / cm} 3 (OLD A
STM), in all thermal shock warpage tests,
The difference between the warps before and after the heat treatment is less than 1 μm, the warpage due to thermal shock is “substantially none”, the warpage of the silicon wafer due to thermal shock is effectively suppressed, and it has excellent mechanical strength. It was confirmed.

Further, the Ge concentration is 5 × 10 ¹⁹ atom.
less than s / cm ³ or oxygen concentration of 11 × 10 ¹⁷ at
In the case of less than oms / cm ³ (OLD ASTM),
When taken out very slowly at an extraction rate (cooling rate conversion) of 100 ° C./min, the warpage due to thermal shock was “substantially none”. However, when taken out at a take-out rate (cooling rate conversion) of 200 ° C./min or 500 ° C./min, the warpage due to thermal shock was “substantially present”.

As another dopant, a low concentration of B is used.
Also, in a thermal shock warp test on a test wafer to which phosphorus was also added, the result was similar to that in the case where no other dopant was added.

In the thermal shock warpage test on the test wafer manufactured by the FZ method manufactured in Example 2, the same result as that of the test wafer manufactured by the CZ method of Example 1 was obtained.

Example 3 In Example 1, the Ge concentration was 1 × 10 ^{18 to} 1.5 ×.
Ge of 10 ²⁰ atoms / cm ³ and oxygen concentration of 5 ×
10 ¹⁷ to 18 × 10 ¹⁷ atoms / cm ³ (OLD
(ASTM) oxygen and B concentration is 5 × 10 ¹⁷ to 2 × 1
A test wafer was prepared by the CZ method in the same manner as in Example 1 except that B of 0 ²⁰ atoms / cm ³ was added in combination as shown in Table 2.

Further, in addition to Ge, oxygen, and B, phosphorus was also added as another dopant at about 10 ¹⁴ atoms / cm ³ , and a test wafer by the CZ method was prepared in the same manner as in Example 1. did.

The produced test wafer was subjected to a thermal shock warpage test using ADE in the same manner as in Example 1. The test results are shown in Table 2.

[0066]

[Table 2]

As shown in Table 2, the Ge concentration is 2 × 10.
¹⁸~ 1.5 × 10²⁰atoms / cm^Three, And oxygen
Concentration is 11 × 10¹⁷~ 18 × 10¹⁷atoms /
cm ^Three(OLD ASTM) and B concentration is 1 × 10
¹⁸~ 2 x 10²⁰atoms / cm^ThreeIn case of
Difference in warpage before and after heat treatment in all thermal shock warpage tests
Is less than 1 μm, and warpage due to thermal shock is “substantially
And the warp of the silicon wafer due to thermal shock.
However, it is effectively suppressed and has excellent mechanical strength.
It was confirmed.

Further, the Ge concentration is 2 × 10 ¹⁸ atom.
less than s / cm ³ , oxygen concentration is 11 × 10 ¹⁷ atom
If either less than s / cm ³ (OLD ASTM) or less than 1 × 10 ¹⁸ atoms / cm ³ B concentration, the removal rate (cooling rate conversion) is 100 ° C./min. The warpage due to thermal shock was "substantially none". However, when taken out at a take-out rate (cooling rate conversion) of 200 ° C / min or 500 ° C / min, there is "substantially" warpage due to thermal shock.
Met.

In the thermal shock warpage test of the test wafer to which a low concentration of phosphorus was also added as another dopant, the result was the same as that when the other dopant was not added.

From the results of Examples 1 to 3, FIG.
Oxygen concentration in the wafer is 11 × 10 ¹⁷~ 18 × 10
¹⁷atoms / cm^ThreeWithin the range of (OLD ASTM)
Then, when various concentrations of Ge and B were changed, thermal shock
Diagram showing the area where warpage is determined to be "substantially none"
Is.

In the figure, the shaded area indicates the range of the silicon wafer having excellent mechanical strength in which the warp of the silicon wafer due to the thermal shock is effectively suppressed and the warp due to the thermal shock is substantially absent. Shows.

[0072]

INDUSTRIAL APPLICABILITY The warpage resistant silicon wafer of the present invention effectively suppresses the warpage of the silicon wafer due to thermal shock in the device processing step, substantially eliminates the warpage due to thermal shock, and has a high mechanical strength. Are better. Further, since the warpage due to the thermal shock or the weight of the silicon wafer in the device processing step is effectively suppressed, the product yield is not lowered, and the workability and the productivity can be improved.

The warpage-resistant silicon wafer of the present invention effectively suppresses warpage due to thermal shock, the self-weight of the silicon wafer, etc. in the device processing step. Therefore, even a large-diameter silicon wafer of 8 inches or more can be manufactured with good productivity. It can be manufactured without lowering the product yield.

The warpage-resistant silicon wafer of the present invention has excellent mechanical strength and is substantially free from warpage due to thermal shock.
It is not necessary to use a silicon wafer that is thicker than the C chip,
A silicon wafer having a product thickness can be used as it is, which is excellent in productivity and economic efficiency, and a silicon ingot can be used efficiently and effectively.

[Brief description of drawings]

FIG. 1 shows that the oxygen concentration in a silicon wafer is 11 × 10.
^{17 ~18 × 10 17 atoms / cm} 3 (OLD A
It is a figure which shows the area | region where the warp by thermal shock was "substantially none" when the density | concentration of Ge and B was variously changed within the range of (STM).

Claims (6)

[Claims] 1. A warp-resistant silicon wafer comprising a silicon wafer containing germanium, which is a high concentration of impurities, and oxygen, which is a high concentration of impurities. 2. A germanium concentration of 5 × 10 ¹⁹ to
1.5 × 10 ²⁰ atoms / cm ³ and oxygen concentration of 11 × 10 ¹⁷ to 18 × 10 ¹⁷ atoms /
The warpage resistant silicon wafer according to claim 1, wherein the silicon wafer is cm ³ (OLD ASTM). 3. A warpage resistant silicon wafer, characterized in that the warpage due to thermal shock depends only on the concentrations of germanium and oxygen according to claim 2 and is independent of the types and concentrations of other dopants. 4. A warpage-resistant silicon wafer comprising a silicon wafer containing germanium, which is a high concentration impurity, oxygen, which is a high concentration impurity, and boron, which is a high concentration impurity. . 5. A germanium concentration of 2 × 10 ¹⁸ to
1.5 × 10 ²⁰ atoms / cm ³ and oxygen concentration of 11 × 10 ¹⁷ to 18 × 10 ¹⁷ atoms /
cm ³ (OLD ASTM) and the boron concentration is 1 × 10 ¹⁸ to 2 × 10 ²⁰ atoms / cm ³ , and the warpage resistant silicon wafer according to claim 4. 6. A warpage-resistant silicon wafer, characterized in that the warpage caused by thermal shock depends only on the concentrations of germanium, oxygen and boron according to claim 5, and is independent of the types and concentrations of other dopants. .