JP2003150080A - Active matrix type display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active matrix type display device whose power consumption is low and whose display quality is high. SOLUTION: This display device has auxiliary capacity electrodes which are arranged for every pixel area where a pixel electrode is formed and auxiliary capacities consisting of first and second auxiliary capacity lines which are arranged in accordance with a plurality of pixel electrodes and the display device can realize the so-called dot inversion drive through auxiliary capacity lines by performing display while applying either a first video signal voltage whose polarity is inverted for every one frame or a second video signal voltage having a polarity opposite to that of the first video signal voltage to the pixel electrodes via switching elements. As a result, the active matrix type display device whose power consumption is low and whose display quality is high is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type display device.

[0002]

2. Description of the Related Art In an active matrix display device in which video signals are supplied to independent pixel electrodes via switching elements such as thin film transistors (TFTs), an AC potential is applied to a counter electrode and an auxiliary capacitor. By AC drive, deterioration of the liquid crystal is prevented, and at the same time, the potential difference between positive and negative polarities of the video signal input to the drain driver is reduced, and the current and voltage of the drain driver are reduced to achieve low power consumption. Was.

However, a horizontal inversion counter AC which inverts the polarity of a video signal applied to each drain line every horizontal period.
In the driving, the polarities of the voltages of the counter electrode and all the auxiliary capacitance lines are inverted every horizontal period, so that the capacitive load on the counter electrode and all the auxiliary capacitance lines and the power consumption thereof are still large.

Therefore, in order to further reduce the power consumption, by inverting the polarity of the voltage of the auxiliary capacitor,
By setting the common electrode voltage to a constant voltage, the power consumption can be significantly reduced, and at the same time, the potential difference between the positive and negative polarities of the video signal can be reduced to reduce the current and voltage of the drain driver ( Hereinafter, it will be referred to as "SC drive") is disclosed in JP-A-12-81606. An active matrix type liquid crystal display device using SC drive will be described below.

FIG. 10 is an equivalent circuit diagram of a display panel in an active matrix type liquid crystal display device using SC driving. Drain line 105 and gate line 107
Are arranged so as to intersect with each other, and a TFT 109 which is a switching element, and a liquid crystal capacitor 112 and an auxiliary capacitor 1 in which one of the capacitor electrodes is connected to the TFT 109 are provided at the intersection.
10 has an auxiliary capacitance line 108 connected to the other of the capacitance electrodes of the auxiliary capacitance 110. Auxiliary capacitance line 108
Are arranged in parallel with the gate line 107 and are common to the auxiliary capacitors 110 connected to the same gate line 107. The other of the capacitance electrodes of the liquid crystal capacitance 112 is a TFT.
The counter electrode 111 is integrally provided on the substrate on the opposite side of the substrate on which the liquid crystal is sandwiched and the substrate on which 109 is provided.

FIG. 11 shows signal waveforms for driving a display panel focusing on one pixel. Here, the gate voltage V _G , the pixel voltage V _P , the source voltage V _S , and the video signal voltage V _{D are shown.} , The auxiliary capacitance voltage V _SC and the counter electrode voltage V _COM are shown. The gate voltage V _G is once O during one frame.
There are N periods. During the ON period of the gate, the gate voltage V _G applied to the gate line 107 is high (hereinafter, “H
"IG". ) Become a level. During this period, TF
When T109 is turned on and the drain and source are electrically connected, the source voltage V _S becomes the same level following the video signal voltage V _D applied to the drain line 105, and one of the liquid crystal capacitor 112 and the auxiliary capacitor 110 Applied to. During the OFF period of the gate, the gate voltage V _G is low (hereinafter,
It is called "Low". ) Level, the TFT 109 is turned off, the source voltage V _S is determined, and the level drops by ΔV _S with the fall of the gate voltage V _G.
It becomes _PL . The counter electrode voltage V _COM is a constant voltage, and is at a level lower than the center level Vc of the video signal voltage V _{D by} a drop amount ΔV _S of the source voltage V _S in advance.

An auxiliary capacitance voltage V _{SC which} is inverted after the gate voltage V _G applied to the corresponding gate line 107 falls is applied to each auxiliary capacitance line 108. The auxiliary capacitance voltage V _SC is inverted at two levels, V _SCH and V _SCL, that is, the source voltage V _S is the counter electrode voltage V _COM.
In the higher positive polarity period, after the gate voltage V _G falls, the low level V _SCL rises to the high level V _SCH . Therefore, the pixel voltage V _P , for which the gate voltage V _G has fallen and the source voltage V _S has once been determined, is increased by ΔV _P under the influence of the rise of the auxiliary capacitance voltage V _SC via the auxiliary capacitance 110. Pixel voltage V at this time
_P is held during the OFF period of the gate, that is, for one frame.

Auxiliary capacitance voltage V_SCBy the rise of
Charge redistribution occurs between the liquid crystal capacitor 112 and the auxiliary capacitor 110.
The pixel voltage V_PIs ΔV_P= V_PH-V_PLOnly rises.
Source voltage V_SIs the counter electrode voltage V_COMLower negative period
Then, conversely, the auxiliary capacitance voltage V _SCFalls from the positive side to the negative side
Therefore, the pixel voltage V_PIs ΔV_PJust descend. This conclusion
As a result, pixel voltage V_POf the liquid crystal capacitance 112 increases.
The voltage applied to can be increased. That is,
Auxiliary capacitance voltage V_SCBy reversing the two levels
Therefore, the counter electrode voltage V_COMVideo as a direct current
Signal voltage V_DThe amplitude of can be reduced.

Usually, the auxiliary capacitance 110 is a liquid crystal capacitance 112.
The pixel voltage change ΔV _P is 1
It is controlled by the variation V (V _SCH -V _SCL ) of the line auxiliary capacitance voltage. Therefore, even if the current flowing through the auxiliary capacitance line is small, a larger voltage is applied to the liquid crystal capacitance 112. That is, the amplitude of the video signal voltage V _D is reduced by changing the auxiliary capacitance voltage.

Now, with the increase in the number of pixels, a driving method is used in which a plurality of drain lines 105 are simultaneously turned on and a video signal voltage V _D is simultaneously applied to a plurality of liquid crystal capacitors 112 and auxiliary capacitors 110. ing. This makes it possible to secure a sufficient time for the drain line 105 to apply the video signal voltage V _D to the liquid crystal capacitor 112 and the auxiliary capacitor 110.

In particular, when driving a large-sized or high-definition display panel in a dot-sequential manner, dozens of drain lines 105 are used.
Are simultaneously turned on, and the video signal voltage V _D is simultaneously applied to several tens of liquid crystal capacitors 112 and auxiliary capacitors 110. Thus, when several tens of drain lines 105 are turned on at the same time, the drain lines 10 that are turned on
A large capacitive coupling occurs in the portion where 5 and the auxiliary capacitance line 108 overlap. Due to this capacitive coupling, the voltages of the auxiliary capacitance line 108 and the gate line 107 are affected by the voltage of the drain line 105 and fluctuate. Due to this voltage change, image unevenness may occur in units of drain lines 105 that are turned on at the same time.

[0012]

In order to prevent capacitive coupling and unevenness of an image caused by the capacitive coupling, voltages having different polarities are applied to pixel electrodes adjacent to each other in the gate line direction and the pixel electrodes adjacent to each other in the drain line direction are applied. Vertical inversion drive as shown in FIG. 12 (a) in which voltages of the same polarity are applied to pixel electrodes and dot inversion drive as shown in FIG. 12 (b) in which opposite polarities are applied to all vertically and horizontally adjacent pixels. Conceivable. In order to prevent the deterioration of the liquid crystal by either driving method, 1
A voltage having a polarity opposite to that of the previous frame is applied to each frame. In order to prevent the capacitive coupling more effectively, it is conceivable to reduce the number of adjacent pixel electrodes to which the voltages of the same polarity are applied as much as possible. Therefore, the present invention is
It is an object of the present invention to apply so-called dot inversion by applying voltages having different polarities to adjacent one or more pixel electrodes in SC driving.

[0013]

SUMMARY OF THE INVENTION The present invention has been made to achieve the above object, and a plurality of gate lines extending in the row direction and transmitting a gate voltage, and a plurality of extending in the column direction. A drain line transmitting a video signal voltage, a switching element arranged corresponding to an intersection of the gate line and the drain line, and a pixel electrode connected to the drain line via the switching element, A plurality of first and second auxiliary capacitance lines extending in the row direction corresponding to each row of the pixel electrodes, and being overlapped with either the first or second auxiliary capacitance line, the auxiliary capacitance It is an active matrix type display device in which electrodes are arranged.

Alternatively, a plurality of gate lines extending in the row direction and transmitting a gate voltage, a plurality of drain lines extending in the column direction and transmitting a video signal voltage, and an intersection of the gate line and the drain line. , A pixel electrode connected to the drain line via the switching element, and a plurality of first and second pixel electrodes extending in the row direction corresponding to each row of the pixel electrode. An active matrix having an auxiliary capacitance line, and the first and second auxiliary capacitance lines are supplied with first and second auxiliary capacitance voltages which are in opposite phases to each other and which change during the OFF period of the switching element. It is a type display device.

Alternatively, a plurality of gate lines extending in the row direction and transmitting a gate voltage, a plurality of drain lines extending in the column direction and transmitting a video signal voltage, and an intersection of the gate line and the drain line. , A pixel electrode connected to the drain line via the switching element, and a plurality of first and second pixel electrodes extending in the row direction corresponding to each row of the pixel electrode. An auxiliary capacitance line, and a counter electrode formed on a counter substrate facing the substrate on which the pixel electrode is formed,
A constant voltage is applied to the opposing electrode, first and second auxiliary capacitance lines having opposite phases to each other and changing during an OFF period of the switching element.
It is an active matrix type display device to which the auxiliary capacitance voltage is supplied.

Further, in the above-mentioned active matrix type display device, the first and second auxiliary capacitance lines alternately have auxiliary capacitance electrodes in units of a plurality of columns of the continuous pixel electrodes.

Further, in the above-mentioned active matrix type display device, the first and second auxiliary capacitance lines are overlapped with all the auxiliary capacitance electrodes arranged corresponding to each row of the pixel electrodes formed therein. .

Further, the auxiliary capacitance electrode has a dummy wiring which overlaps with one of the first or second auxiliary capacitance lines which does not form an auxiliary capacitance, and which is a dummy wiring. It is a type display device.

Further, in the pixel region where the pixel electrode is formed, the gate line is the active matrix type display device, which is arranged between the first and second auxiliary capacitance lines.

Further, in the pixel region, a gate electrode constituting the switching element is formed in the gate line in a region where the auxiliary capacitance electrode is arranged with the gate line as a boundary line. The above-mentioned active matrix type display device.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment will be described. FIG. 1 is a plan view of a display panel in an active matrix display device, FIG. 2 is a plan view of the display panel according to the first embodiment, and FIG. 3 is an equivalent circuit diagram thereof.

First, in FIG. 1, the display panel 1 has
The drain driver 2 is arranged in the row direction, and the gate driver 3 is arranged in the column direction. A display area 4 for displaying an image is arranged so as to be surrounded by the drain driver 2 and the gate driver 3.

In the display area 4, as shown in FIGS. 2 and 3, a plurality of drain lines 5 and a plurality of rectangular pixel electrodes 6 elongated in the column direction are arranged in the column direction, and a plurality of rectangular pixel electrodes 6 are arranged in the column direction. , A gate line 7, a first auxiliary capacitance line 8a and a second auxiliary capacitance line 8b are arranged. In the area where each pixel electrode 6 is arranged (hereinafter, referred to as “pixel area”), the TFT 9 and either the first auxiliary capacitance 10a or the second auxiliary capacitance 10b are arranged.
The TFT 9 includes a gate electrode 9g extending from the gate line 7, a drain region 9d of a semiconductor layer electrically connected to the drain line 5 via a contact, and a pixel electrode 6 electrically via a contact. The source region 9s of the connected semiconductor layer is formed. The first auxiliary capacitance 10a is formed of an auxiliary capacitance electrode 10x made of a semiconductor layer connected to the TFT 9 and an auxiliary capacitance electrode 10y extending from the first auxiliary capacitance line 8a. The second auxiliary capacitance 10b is the auxiliary capacitance electrode 10 described above.
x and an auxiliary capacitance electrode 10z formed extending from the second auxiliary capacitance line 8b. In addition, TFT9
The counter electrode 11 is provided on the substrate opposite to the substrate on which the liquid crystal is sandwiched, and constitutes an auxiliary capacitance electrode corresponding to the pixel electrode 6 of the liquid crystal capacitance 12.

As shown in FIG. 1, the drain driver 2 receives a first video signal voltage VDa and a second video signal voltage VDb having opposite polarities,
The drain line 5 is sequentially selected and either the first video signal voltage VDa or the second video signal voltage VDb is applied. The gate driver 3 has a gate line 7
Are sequentially selected and the gate signal GV is applied. The display area 4 has a plurality of pixel electrodes 6 and is an area for displaying an image. The drain line 5 has a first polarity having opposite polarities.
Of the video signal voltage VDa or the second video signal voltage VDb is transmitted to the TFT 9 through the contact. The pixel electrode 6 constitutes a pixel region which is a display unit, and together with the counter electrode 11, the drain line 5
Is an electrode for driving the liquid crystal by the video signal voltage VD transmitted from the TFT through the TFT 9. Gate line 7
When the gate signal GV is applied by being selected by the gate driver 3, the connected TFT 9 is turned on. The first auxiliary capacitance line 8a is formed in the same layer as the gate line 7 integrally with the auxiliary capacitance electrodes 10y arranged in the row direction, and connects the first auxiliary capacitances in each row to each other. The second auxiliary capacitance line 8b is integrated with the auxiliary capacitance electrodes 10z arranged in the row direction in the same layer as the gate line 7, and connects the second auxiliary capacitances of each row to each other. The first
Is supplied with a first auxiliary capacity voltage, and the second auxiliary capacity line 8b is supplied with a second auxiliary capacity voltage having a polarity opposite to that of the first auxiliary capacity voltage. It The TFT 9 is a semiconductor directly under the gate electrode 9g in either the direction from the source region 9s to the drain region 9d or the direction from the drain region 9d to the source region 9s only when a voltage is applied to the gate electrode 9g. A switching element in which a current flows in the channel region of a layer. First auxiliary capacitance 10a and second auxiliary capacitance 10b
Holds the charge due to the video signal voltage VD supplied from the drain line 5 through the TFT 9 for one frame period, and compensates for the charge loss of the liquid crystal capacitor 12. A constant voltage is applied to the counter electrode 11, and the liquid crystal is driven together with the pixel electrode 6 according to the video signal voltage VD applied to the pixel electrode 6. The liquid crystal capacitance 12 is a charge due to the video signal voltage VD supplied from the drain line 5 held by the liquid crystal through the TFT 9. However, the charges held in the liquid crystal capacitor 12 are not stored in the first auxiliary capacitor 10a or the second auxiliary capacitor 10a.
The charge is extremely smaller than the charge held by b, and easily leaks due to a leak due to an OFF operation of the TFT 9 or a leak from impurities in the liquid crystal, so that the first auxiliary capacitor 10a and the second auxiliary capacitor 10a
The charges are supplemented by the charges held by the auxiliary capacitor 10b.

Next, the driving method will be described. Figure 4
[FIG. 4] is a timing chart showing the relationship between signals on the display panel. This is the vertical start signal STV, the gate signals GV1, GV2, GV3, the horizontal start signal STH, and the horizontal clock signal CKH, the potential SCa of the first auxiliary capacitance line 8a, and the second auxiliary capacitance line 8b.
The timing of the voltage change at the potential SCb is shown.

First, the pulse of the gate signal GV1 rises in response to the fall of the pulse of the vertical start signal STV, the gate signal GV1 is supplied to the gate line 7 of the first row, and the TFT 9 connected thereto is turned on. . Then, the pulse of the horizontal start signal STH rises,
In synchronization with the fall of this pulse, the first horizontal clock signal CK is selected in the period in which the gate line 7 of the first row is selected.
The H pulse rises. While the gate signal GV1 is being supplied to the gate line 7 of the first row, the pulses of the horizontal clock signal CKH sequentially rise, and the drain lines 5 are sequentially selected in synchronization with the rising of these pulses, and the sequential video The signal voltage VD is applied to the pixel electrode 6, the first auxiliary capacitance 10a, and the second auxiliary capacitance 10b via the TFT 9. It should be noted that the first video signal voltage VDa corresponds to the pixel electrode 6 and the first auxiliary capacitance 10a.
In addition, the second video signal voltage VDb is applied to the pixel electrode 6 and the second auxiliary capacitance 10b. When the video signal voltage VD is applied to all the drain lines 5, the gate signal GV1 is not supplied to the gate line 7 of the first row,
The TFT 9 connected to this is turned off. Then, the pulses of the gate signal GV2 and the gate signal GV3 sequentially rise, and the gate signal GV2,
The gate signal GV3 is applied to the gate lines 7 in the third row, and the above operation is repeated. The TFT 9 connected to the gate line 7 is in the off state, that is,
During a period in which the gate signal GV is not supplied to the gate line 7, the polarities of the potential SCa of the first auxiliary capacitance line 8a and the potential SCb of the second auxiliary capacitance line 8b are inverted. Then, when the gate signal GV is supplied to all the gate lines 7, the pulse of the vertical start signal STV rises again, and the gate signal GV is supplied to the gate line 7 of the first row in synchronization therewith, and the same operation is performed. repeat.

FIG. 5 is a signal waveform diagram showing a driving method of the display device according to the first embodiment, and shows a signal waveform during one frame in pixel regions adjacent in the gate line direction. 5A shows the signal waveform of the first auxiliary capacitance 10a, and FIG. 5B shows the signal waveform of the second auxiliary capacitance 10b. The signal waveform shown in FIG. 5 (a) is almost the same as that in FIG. 11, but the signal waveform shown in FIG. 5 (b) has the polarity exactly inverted from that in FIG.

The active matrix display device according to the present embodiment is formed integrally with the auxiliary capacitor arranged in each pixel region where the pixel electrode is formed and the plurality of pixel electrodes arranged in the row direction, and arranged in the row direction. First and second auxiliary capacitance lines connecting every other auxiliary capacitance electrode,
Either the first video signal voltage whose polarity is inverted every one frame period or the second video signal voltage having the opposite polarity to the first video signal voltage is applied to the pixel electrode through the switching element. By performing display by applying the voltage, so-called dot inversion drive by the auxiliary capacitance line can be realized. The active matrix type display device supplies the first video signal voltage to the first auxiliary capacitance having the first auxiliary capacitance line at the same time as the second auxiliary capacitance while the switching element is on. A second video signal voltage is supplied to the second auxiliary capacitor having a line, but when the switching element is turned off, the voltage supplied to the first and second auxiliary capacitors flows out. I will end up. However, in this active matrix display device, the first auxiliary capacitance voltage whose level changes to the polarity of the voltage held by the first auxiliary capacitance is applied to the first auxiliary capacitance line while the switching element is off. The second auxiliary capacitance line is supplied with a second auxiliary capacitance voltage having a polarity opposite to that of the first auxiliary capacitance voltage and changing in level to the polarity of the voltage held by the first auxiliary capacitance. By supplying the voltage, it is possible to compensate for the voltages of the first and second auxiliary capacitors that have changed due to the OFF operation of the switching element, and further to amplify the voltage supplied to the first and second auxiliary capacitors. it can.

In the present embodiment, the dot inversion drive is performed to eliminate the influence of the adjacent video signal voltage and prevent the image unevenness due to capacitive coupling. Further, the amplitude of the video signal voltage is narrowed by applying either the first or second auxiliary capacitance voltage to the first and second auxiliary capacitance lines during the period when the switching element is off. Therefore, power consumption can be reduced.

In the present embodiment, in order to reduce image unevenness and flicker, the first and second auxiliary capacitance lines alternately have auxiliary capacitance electrodes in the row direction with one pixel electrode as a unit. Although it was configured,
The present invention is not limited to this, and a plurality of columns of continuous pixel electrodes may be used as a unit to alternately have auxiliary capacitance electrodes. For example, three pixel electrodes displaying the RGB primary colors may be set as one unit, and each unit may have an auxiliary capacitance electrode on either the first or second auxiliary capacitance line.

By the way, in the present embodiment, as shown in FIG. 2, the first auxiliary capacitance line 8a and the second auxiliary capacitance line 8b are formed so as to overlap all the auxiliary capacitance electrodes 10x. . Then, the auxiliary capacitance electrode 1 forming the second auxiliary capacitance line 8b and the second auxiliary capacitance 10b.
Only in the pixel region where 0z exists, a parasitic capacitance C _PAR is generated in the overlapping portion 13 where the first auxiliary capacitance line 8a and the semiconductor layer continuous with the auxiliary capacitance electrode 10z overlap.

Therefore, a second embodiment will be described.
It In the second embodiment, the parasitic capacitance C _PARIs the second auxiliary
Solve the problem caused by being formed only in quantity 10b
To decide. FIG. 6 is a table according to the second embodiment.
8 is a plan view of the display panel, and FIG. 7 is an equivalent circuit diagram thereof.
It The same numbers are used for the same configurations as in the first embodiment.
Is attached and the description is omitted.

The present embodiment differs from the first embodiment in that a dummy is formed in the pixel region having the auxiliary capacitance electrode 10y so as to extend from the auxiliary capacitance electrode 10y and overlaps with the second auxiliary capacitance line 8b. The point is that the wiring 14 is provided. The dummy wiring 14 forms the overlapping portion 13 ′ with the second auxiliary capacitance line 8 b that does not form the auxiliary capacitance, so that the parasitic capacitance in the overlapping portion 13 with the auxiliary capacitance electrode 10 z and the first auxiliary capacitance line 8 a. forming an equal C _PAR parasitic capacitance C _{PAR '.}

In the first embodiment, since the parasitic capacitance C _PAR is generated only in the overlapping portion 13 of the auxiliary capacitance electrode 10z and the first auxiliary capacitance line 8a, the second auxiliary electrode having the auxiliary capacitance electrode 10z is generated. Only the potential of the capacitor 10b was lowered. Therefore, a difference occurs in the magnitude of the optimum counter electrode voltage for the pixel electrode 6 in each pixel region between the pixel region in which the auxiliary capacitance electrode 10y is present and the pixel region in which the auxiliary capacitance electrode 10z is present. There were variations and flicker. However, in the present embodiment, by forming the dummy wiring 14 on the first auxiliary capacitance electrode 10x, the second auxiliary capacitance line 8b and the dummy wiring 14 which do not form an auxiliary capacitance with the first auxiliary capacitance electrode 10x are formed. An overlapping portion 13 ′ that overlaps was formed, and a parasitic capacitance C _{PAR ′} was generated there. As a result, the first auxiliary capacitance 10a and the second auxiliary capacitance 10a
By balancing the polarities among the auxiliary capacitors 10b, it is possible to eliminate the difference in the magnitude of the counter electrode voltage that is optimal for each pixel electrode 6, and eliminate the variations in contrast and flicker due to this difference. You can

Next, a third embodiment will be described.
FIG. 8 is a plan view of the display panel according to the third embodiment, and FIG. 9 is an equivalent circuit diagram thereof. The same numbers are given to the same configurations as those in the first embodiment, and the description thereof will be omitted. In this embodiment, the arrangement of the drain line 5 and the pixel electrode 6 is the same as in the first and second embodiments.

The present embodiment is different from the first and second embodiments in that the gate line 7 is located at the center of the pixel electrode between the first auxiliary capacitance line 8a and the second auxiliary capacitance line 8b. It is arranged so that it is sandwiched between. In each pixel region, the gate electrode that is integrally formed with the gate line 7 and forms the TFT 9 is formed in the region where the auxiliary capacitance electrode 10x is arranged with the gate line 7 as a boundary line. .

In the second embodiment, since dummy wirings are provided in addition to the auxiliary capacitance electrodes that are originally necessary, the pattern is complicated and the aperture ratio is lowered. However, in this embodiment, since the gate line 7 is arranged between the first auxiliary capacitance line 8a and the second auxiliary capacitance line 8b, all the auxiliary capacitance electrodes 10x form the auxiliary capacitance. Since it is superposed only on either the first auxiliary capacitance line 8a or the second auxiliary capacitance line 8b, it is possible to eliminate the superposed portion 13 and the superposed portion 13 'themselves and eliminate the parasitic capacitance C _PAR generated in the superposed portion. it can. Further, in the present embodiment, the second auxiliary capacitance line 8
It is possible to reduce the wiring resistance by shortening the distance between b and the TFT 9. Since the area of the semiconductor layer required for forming the auxiliary capacitance electrode 10z in the first embodiment and the dummy wiring 14 in the second embodiment can be reduced, the aperture ratio is improved.

In each embodiment, the double gate type TFT is exemplified, but the present invention is not limited to this.
The number of gate electrodes may be one or more. Further, although the auxiliary capacitance line is formed in the same layer as the gate line, the present invention can be implemented by forming the auxiliary capacitance line in a different layer from the gate line.

Furthermore, although the active matrix type liquid crystal display device has been illustrated in each of the embodiments, the present invention is not limited to this, and can be applied to an active matrix type EL display device.

[0040]

As described above, in the active matrix type display device of the present invention, a plurality of gate lines extending in the row direction and transmitting the gate voltage and a plurality of gate lines extending in the column direction and transmitting the video signal voltage are transmitted. A drain line, a switching element arranged corresponding to an intersection of the gate line and the drain line, a pixel electrode connected to the drain line via the switching element, and a row direction corresponding to each row of the pixel electrode. A plurality of extending first and second auxiliary capacitance lines, corresponding to the first and second auxiliary capacitance lines,
By arranging the auxiliary capacitance electrodes alternately in each column of the pixel electrodes, it is possible to supply signals having different polarities to the respective auxiliary capacitance lines. Therefore, these auxiliary capacitance lines cause different polarities for adjacent pixel electrodes. It is possible to realize so-called dot inversion drive in which the voltage is applied.

Then, the first and second auxiliary capacitance lines are supplied with the first and second auxiliary capacitance voltages which are in opposite phases to each other and change during the OFF period of the switching element, whereby the above-mentioned auxiliary capacitances are supplied. It is possible to realize dot inversion drive by lines and reduce the amplitude of the video signal voltage.

Further, there is an opposite electrode formed on the opposite substrate opposite to the substrate on which the pixel electrode is formed, and a constant voltage is applied to the opposite electrode to connect the first and second auxiliary capacitance lines. Are in mutually opposite phases, and alternating drive by the auxiliary capacitance line can be realized by supplying the first and second auxiliary capacitance voltages that change during the OFF period of the switching element.

Further, the first and second auxiliary capacitance lines have alternating auxiliary capacitance electrodes in units of a plurality of columns of continuous pixel electrodes, so that, for example, three primary colors R
By arranging pixel electrodes for displaying GB as one group and applying a voltage having an opposite polarity to each adjacent group, inversion driving can be realized in group units.

Further, the first and second auxiliary capacitance lines overlap with all auxiliary capacitance electrodes arranged corresponding to the respective rows of the pixel electrodes to be formed, so that the auxiliary capacitance line does not form an auxiliary capacitance. Since it is possible to balance the polarities of the parasitic capacitances generated in the region where the auxiliary capacitance electrodes overlap with each other, it is possible to prevent image unevenness.

Further, the auxiliary capacitance electrode has a dummy wiring which overlaps the auxiliary capacitance line of the first or second auxiliary capacitance line which does not form the auxiliary capacitance, whereby the first and second auxiliary capacitance lines are formed. Similarly, the line is to be overlapped with all the auxiliary capacitance electrodes, and it is possible to balance the polarities of the parasitic capacitances generated in the region where the auxiliary capacitance line not forming the auxiliary capacitance and the auxiliary capacitance electrode overlap. Image unevenness can be prevented.

Further, in the pixel region where the pixel electrode is formed, the gate line is arranged between the first and second auxiliary capacitance lines, so that the auxiliary capacitance line and the auxiliary capacitance electrode which do not form the auxiliary capacitance are formed. The overlapping area of
Since the parasitic capacitance generated there can be eliminated, it is possible to prevent image unevenness.

In the pixel region, the gate line forms a switching element in the region where the auxiliary capacitance electrode is arranged, with the gate line serving as a boundary line. Since it is possible to eliminate the area where the auxiliary capacitance line and the auxiliary capacitance electrode which are not formed and the parasitic capacitance generated there are eliminated, it is possible to prevent image unevenness.

As a result, an active matrix type display device having high display quality can be provided.

[Brief description of drawings]

FIG. 1 is a plan view of a display panel of an active matrix type display device.

FIG. 2 is a plan view of the display panel according to the first embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram of the display panel according to the first embodiment of the present invention.

FIG. 4 is a timing chart showing a relationship between signals in the display panel according to the first embodiment of the present invention.

FIG. 5 is a signal waveform diagram showing a driving method of the display device according to the first embodiment of the present invention.

FIG. 6 is a plan view of a display panel according to a second embodiment of the present invention.

FIG. 7 is an equivalent circuit diagram of a display panel according to a second embodiment of the present invention.

FIG. 8 is a plan view of a display panel according to a third embodiment of the present invention.

FIG. 9 is an equivalent circuit diagram of a display panel according to a third embodiment of the present invention.

FIG. 10 is an equivalent circuit diagram of a conventional display panel.

FIG. 11 is a signal waveform diagram showing a driving method of a conventional display device.

FIG. 12 is a conceptual diagram showing vertical inversion drive and dot inversion drive.

[Explanation of symbols]

1: Display panel 2: Drain driver 3: Gate driver 4: Display area 5: Drain line 6: Pixel electrode 7: Gate line 8a: First auxiliary capacitance line 8b: second auxiliary capacitance line 9: TFT 10a: first auxiliary capacitance 10b: second auxiliary capacitance 11: Counter electrode 12: Liquid crystal capacity 13, 13 ': superposed portion 14: Dummy wiring 105: drain line 107: Gate line 108: auxiliary capacitance line 109: TFT 110: auxiliary capacity 111: Counter electrode 112: Liquid crystal capacity

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 624 G09G 3/20 624B 624C 624Z 3/30 3/30 J 3/36 3/36 F term (Reference) 2H092 GA13 GA17 JA24 JB62 JB69 NA01 NA26 PA06 2H093 NA16 NA31 NA43 NC34 NC35 ND15 ND39 NE03 5C006 AC11 AC25 AC27 AF42 AF43 AF44 AF51 AF53 AF69 AF71 BB16 BB27 BC03 BC12 FA22 FA47 5C080 AA10 BB05 JJ05 DF05 DD05 DD05 DD05 DD05 DD05 DD05 DD05 DD05 DD05 DD05 DD05 DD05 DD05 DD05 DD05 DD05 DD05 DD05 DD05 DD05 DD05 DD05 DD05 DD06 DD06 AA07 AA13 AA22 AA24 AA53 AA56 BA03 BA43 CA19 DA09 DA13 DB01 DB04 EA04 EA10 FA01 FB12 FB14 FB15 GA10

Claims (8)

[Claims] 1. A gate line extending in a row direction for transmitting a gate voltage, a plurality of drain lines extending in a column direction for transmitting a video signal voltage, and an intersection of the gate line and the drain line. , A pixel electrode connected to the drain line via the switching element, and a plurality of first and second pixel electrodes extending in the row direction corresponding to each row of the pixel electrode. An active matrix type display device, comprising: an auxiliary capacitance line, and an auxiliary capacitance electrode is disposed so as to overlap with either the first or second auxiliary capacitance line. 2. A plurality of gate lines extending in a row direction and transmitting a gate voltage, a plurality of drain lines extending in a column direction, transmitting a video signal voltage, and an intersection of the gate line and the drain line. , A pixel electrode connected to the drain line via the switching element, and a plurality of first and second pixel electrodes extending in the row direction corresponding to each row of the pixel electrode. An auxiliary capacitance line, and the first and second auxiliary capacitance lines are supplied with first and second auxiliary capacitance voltages which are in opposite phases to each other and which change during the OFF period of the switching element. Characteristic active matrix type display device. 3. A gate line extending in the row direction for transmitting a gate voltage, a drain line extending in the column direction for transmitting a video signal voltage, and an intersection of the gate line and the drain line. , A pixel electrode connected to the drain line via the switching element, and a plurality of first and second pixel electrodes extending in the row direction corresponding to each row of the pixel electrode. A storage capacitor line and a counter electrode formed on a counter substrate that faces the substrate on which the pixel electrode is formed. A constant voltage is applied to the counter electrode, and the first and second counter electrodes are provided.
The active matrix type display device is characterized in that the auxiliary capacitance lines are supplied with first and second auxiliary capacitance voltages which have opposite phases to each other and which change during the OFF period of the switching element. 4. The first and second auxiliary capacitance lines are
The active matrix type display device according to claim 2 or 3, wherein auxiliary pixel electrodes are alternately provided in units of a plurality of columns of the continuous pixel electrodes. 5. The first and second auxiliary capacitance lines are
5. The active matrix display device according to claim 1, wherein the active matrix display device overlaps with all the auxiliary capacitance electrodes arranged corresponding to each row of the pixel electrodes formed. 6. The storage capacitor electrode according to claim 5, wherein the storage capacitor electrode has a dummy wiring that overlaps a storage capacitor line that does not form a storage capacitor of the first and second storage capacitor lines. The active matrix display device described. 7. The pixel line according to claim 1, wherein the gate line is arranged between the first and second auxiliary capacitance lines in a pixel region where the pixel electrode is formed. An active matrix type display device according to any one of the above. 8. In the pixel region, a gate electrode constituting the switching element is formed in the gate line, in a region where the auxiliary capacitance electrode is arranged, with the gate line serving as a boundary line. The active matrix type display device according to claim 7, wherein