JP2003142630A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2003142630A JP2003142630A JP2001335062A JP2001335062A JP2003142630A JP 2003142630 A JP2003142630 A JP 2003142630A JP 2001335062 A JP2001335062 A JP 2001335062A JP 2001335062 A JP2001335062 A JP 2001335062A JP 2003142630 A JP2003142630 A JP 2003142630A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- opening
- connection terminal
- semiconductor element
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子の底部
に形成されている各電極パッドに、半田バンプを介して
下部の基板上の接続端子との電気的接続が行われる所謂
フリップチップ接続の半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called flip chip connection in which each electrode pad formed on the bottom of a semiconductor element is electrically connected to a connection terminal on a lower substrate through a solder bump. The present invention relates to a semiconductor device.
【０００２】[0002]
【従来の技術】半導体装置の小型化及び高集積化を実現
する方法として、図３（Ａ）、（Ｂ）の半導体装置５０
に示すように、半導体素子５１の各電極パッドと回路基
板５２の接続端子との間を半田バンプ５３等によって接
続したフリップチップ接続が注目されている。このフリ
ップチップ接続によれば、従来のワイヤボンディングに
比較して実装面積を小さくすることができると共に、パ
ッケージの高さも小さくすることができるという特徴が
ある。なお、５４はポッティング樹脂を示す。2. Description of the Related Art As a method for realizing miniaturization and high integration of a semiconductor device, the semiconductor device 50 shown in FIGS.
As shown in FIG. 3, flip-chip connection in which each electrode pad of the semiconductor element 51 and the connection terminal of the circuit board 52 are connected by a solder bump 53 or the like is drawing attention. This flip-chip connection has a feature that the mounting area can be reduced and the height of the package can be reduced as compared with the conventional wire bonding. In addition, 54 shows potting resin.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、従来の
フリップチップ接続構造の半導体装置５０においては、
半導体素子５１と回路基板５２との接続後は、半田接合
部の状態を目視で確認できないために、接続状態の確認
は、オープンショート（ＯＳ）テストのみで行ってい
た。ここで、オープンショートテストは、通常樹脂封止
後に行われるので、接続不良が発見されたときは、既に
組立が完了した状態となってしまう。このため、半田接
合時において発生していた不良品は、そのまま後の工程
に搬送され、組立が行われてしまうので、この間の工程
費用、材料費用及び検査費用が無駄になるという問題が
あった。However, in the conventional semiconductor device 50 having the flip chip connection structure,
After the connection between the semiconductor element 51 and the circuit board 52, the state of the solder joint cannot be visually confirmed, so that the connection state was confirmed only by the open short (OS) test. Here, since the open short test is usually performed after resin sealing, when a connection failure is found, the assembly is already completed. For this reason, a defective product generated during soldering is conveyed to a subsequent process as it is and assembled, so that process cost, material cost, and inspection cost during this period are wasted. .
【０００４】更には、半田接合時には、部品及びパター
ン表面の酸化物除去、半田付け中の再酸化防止、並びに
溶融半田の表面張力を低下させる目的でフラックスを使
用し、半田付け性を向上させているが、半田付けが完了
した後は、フラックスを実質的に完全に洗浄及び除去し
ないと、フラックス成分の塩素等が原因で、半田や他の
金属の腐食あるいはマイグレーション等が起こり、ショ
ート障害の原因となることがある。フラックスの洗浄
は、浸漬洗浄、スプレー洗浄等が一般的だが、フリップ
チップ接続の場合、各半田バンプ間のギャップが狭いた
めに洗浄液の進入が困難となり、フラックスの十分な洗
浄が行えないという問題があった。本発明はかかる事情
に鑑みてなされたもので、半田の接合状態を目視で確認
することも可能で、かつ半田付け時に使用したフラック
スの洗浄も容易な半導体装置を提供することを目的とす
る。Further, at the time of solder joining, flux is used for the purpose of removing oxides on the surface of parts and patterns, preventing reoxidation during soldering, and reducing the surface tension of molten solder to improve solderability. However, after soldering is completed, if flux is not substantially completely cleaned and removed, chlorine or other components of the flux cause corrosion or migration of solder or other metals, which may cause a short-circuit failure. May be. Dip cleaning and spray cleaning are generally used for flux cleaning.However, in the case of flip-chip connection, it is difficult to enter the cleaning solution due to the narrow gap between solder bumps, and there is the problem that flux cannot be cleaned sufficiently. there were. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device in which the joining state of solder can be visually checked and the flux used during soldering can be easily washed.
【０００５】[0005]
【課題を解決するための手段】前記目的に沿う本発明に
係る半導体装置は、半導体素子の底部に形成されている
各電極パッドに半田バンプを設け、該半田バンプを介し
て、例えば下部の基板上の接続端子に電気的に接続され
た半導体装置において、前記接続端子の直下の基板材に
開口部を設け、しかも前記接続端子は前記開口部をブリ
ッジしている。これによって、開口部を底から覗けば、
接合された状態の半田バンプ又は電極パッドが見えるの
で、半田の接合状態を確認できる。更に、開口部を洗浄
液が通るので、半導体素子の底部や基板上の接続端子及
びその回りを洗浄できる。ここで、本発明に係る半導体
装置において、前記開口部は前記各半田バンプが接続さ
れる接続端子毎に設けられていてもよいし、前記半田バ
ンプが接続される前記接続端子は１又は２以上の群に分
けられ、各群毎に前記開口部が設けられていてもよい。A semiconductor device according to the present invention, which meets the above-mentioned object, is provided with a solder bump on each electrode pad formed on the bottom of a semiconductor element, and through the solder bump, for example, a lower substrate. In the semiconductor device electrically connected to the upper connection terminal, an opening is provided in the substrate material immediately below the connection terminal, and the connection terminal bridges the opening. With this, if you look into the opening from the bottom,
Since the solder bumps or electrode pads in the joined state can be seen, the joined state of the solder can be confirmed. Furthermore, since the cleaning liquid passes through the opening, the bottom of the semiconductor element, the connection terminals on the substrate, and the surroundings can be cleaned. Here, in the semiconductor device according to the present invention, the opening may be provided for each connection terminal to which each solder bump is connected, and the connection terminal to which the solder bump is connected has one or two or more. The above-mentioned opening may be provided for each group.
【０００６】[0006]
【発明の実施の形態】続いて、添付した図面を参照しつ
つ、本発明を具体化した実施の形態につき説明し、本発
明の理解に供する。ここに、図１（Ａ）は本発明の第１
の実施の形態に係る半導体装置の断面図、（Ｂ）は同底
面図、図２は本発明の第２の実施の形態に係る半導体装
置の説明図である。BEST MODE FOR CARRYING OUT THE INVENTION Next, referring to the attached drawings, an embodiment in which the present invention is embodied will be described to provide an understanding of the present invention. Here, FIG. 1A shows the first embodiment of the present invention.
2B is a bottom view of the semiconductor device according to the second embodiment of the present invention, and FIG. 2 is an explanatory view of the semiconductor device according to the second embodiment of the present invention.
【０００７】図１（Ａ）、（Ｂ）に示すように、本発明
の第１の実施の形態に係る半導体装置１０は、半導体素
子１１と、これが搭載されている基板１２とを有してい
る。半導体素子１１は、底部に複数の電極パッド１３が
形成されて、この電極パッド１３には半田バンプ１４が
それぞれ印刷されている。基板１２は、基板材１２ａと
その上の導体回路パターンとを備えている。基板材１２
ａはガラスエポキシ樹脂板又は耐熱樹脂シートからなっ
て、搭載される半導体素子１１の電極パッド１３に対応
する部分には、複数の電極パッド１３が覗く開口部１
５、１５ａが設けられ、その上に表面側に形成されてい
る導体回路パターンの一部である接続端子１６が例えば
２つの群に分けられて開口部１５、１５ａをそれぞれ跨
ぐように、即ち開口部１５、１５ａをブリッジするよう
にして配置されている。As shown in FIGS. 1A and 1B, a semiconductor device 10 according to the first embodiment of the present invention has a semiconductor element 11 and a substrate 12 on which the semiconductor element 11 is mounted. There is. A plurality of electrode pads 13 are formed on the bottom of the semiconductor element 11, and solder bumps 14 are printed on the electrode pads 13, respectively. The board 12 includes a board material 12a and a conductor circuit pattern formed thereon. Board material 12
a is made of a glass epoxy resin plate or a heat-resistant resin sheet, and the opening 1 through which the plurality of electrode pads 13 can be seen is located at a portion corresponding to the electrode pads 13 of the mounted semiconductor element 11.
5, 15a are provided, and the connection terminals 16 that are part of the conductor circuit pattern formed on the front surface side are divided into, for example, two groups so as to straddle the openings 15 and 15a, that is, the openings. The portions 15 and 15a are arranged so as to bridge each other.
【０００８】基板１２はこの実施の形態では半導体素子
１１より少し大きい程度となっているが、半導体素子１
１に比較して更に大きくなって、その他の半導体素子
や、抵抗、コンデンサ等の受動素子が搭載されるもので
あってもよい。基板材１２ａの表面側には半導体素子１
１に対応する導体回路が形成され、必要な場合には、基
板材１２ａに形成されたスルーホール等を介して裏面側
にも配線されている。半導体素子１１の外周部はポッテ
ィング樹脂１７によって封止され、最終的には必要な場
合に、開口部１５、１５ａも樹脂によって封止される。The substrate 12 is slightly larger than the semiconductor element 11 in this embodiment, but the semiconductor element 1
It may be larger than that of 1, and other semiconductor elements and passive elements such as resistors and capacitors may be mounted. The semiconductor element 1 is provided on the front surface side of the substrate material 12a.
A conductor circuit corresponding to No. 1 is formed and, if necessary, is also wired on the back surface side through a through hole or the like formed in the substrate material 12a. The outer peripheral portion of the semiconductor element 11 is sealed with the potting resin 17, and finally, the openings 15 and 15a are also sealed with the resin when necessary.
【０００９】この半導体装置１０の製造方法について説
明すると、予め所定広さの基板材１２ａを用意し、これ
にプレス加工又はエッチング加工によって開口部１５、
１５ａを形成する。次に薄い銅板を用意し、基板材１２
ａの表面側に貼着し、更にエッチング加工を行って、表
面側に導体回路パターンを形成した基板１２を製造す
る。導体回路パターンには開口部１５、１５ａを跨ぐ、
即ちブリッジする接続端子１６が含まれる。なお、接続
端子１６の表面には金めっき等の貴金属めっきをしてお
くのが好ましい。一方、半導体素子１１の裏面側に形成
されている電極パッド１３には半田バンプ１４を印刷す
る。印刷は所定の回数行って十分な高さを確保する。な
お、印刷の代わりにめっきを行って半田バンプを形成し
てもよい。半田バンプ１４の形成された半導体素子１１
を、接続端子１６を含む導体回路パターンを備えた基板
１２の所定位置に載せてリフロー炉に入れて２００℃前
後の加熱を行い、半田バンプ１４を溶解させて、電極パ
ッド１３と接続端子１６との電気的接合を行う。Explaining the method of manufacturing the semiconductor device 10, a substrate material 12a having a predetermined area is prepared in advance, and the opening 15 is formed by pressing or etching the substrate material 12a.
15a is formed. Next, a thin copper plate is prepared, and the substrate material 12
The substrate 12 having the conductor circuit pattern formed on the front surface side is manufactured by adhering it to the front surface side of a and further etching it. The conductor circuit pattern straddles the openings 15 and 15a,
That is, the connection terminal 16 that bridges is included. The surface of the connection terminal 16 is preferably plated with a precious metal such as gold. On the other hand, solder bumps 14 are printed on the electrode pads 13 formed on the back surface side of the semiconductor element 11. Printing is performed a predetermined number of times to ensure a sufficient height. Instead of printing, plating may be performed to form solder bumps. Semiconductor element 11 with solder bumps 14 formed
Is placed on a predetermined position of the substrate 12 having the conductor circuit pattern including the connection terminal 16 and placed in a reflow furnace to heat at about 200 ° C. to melt the solder bumps 14 to form the electrode pad 13 and the connection terminal 16. Electrical connection.
【００１０】この後、洗浄液にて半田バンプ１４周囲の
フラックスを洗浄し、乾燥して目視検査を行う。勿論、
目視検査に代えてテレビカメラ等を使用する画像処理に
よって検査を行ってもよい。この場合、基板１２の裏面
側から開口部１５、１５ａを介して半導体素子１１の電
極パッド部分を覗くようにする。異常がある場合には、
電極パッド１３と接続端子１６の接合がなされていない
か、隣り合う接続端子１６が半田等によってショートし
ていることになる。異常が発見されない場合には、半導
体素子１１の周囲をポッティング樹脂１７で封止する。
なお、開口部１５、１５ａの間から樹脂を流して半導体
素子１１と回路パターンとの間を封止するのが好まし
い。図１においては、基板（回路基板）１２の出力端子
は省略している。After that, the flux around the solder bumps 14 is washed with a cleaning liquid, dried and visually inspected. Of course,
The inspection may be performed by image processing using a television camera or the like instead of the visual inspection. In this case, the electrode pad portion of the semiconductor element 11 is viewed through the openings 15 and 15a from the back surface side of the substrate 12. If something is wrong,
Either the electrode pad 13 and the connection terminal 16 are not joined, or the adjacent connection terminals 16 are short-circuited by solder or the like. If no abnormality is found, the periphery of the semiconductor element 11 is sealed with the potting resin 17.
In addition, it is preferable to flow a resin from between the openings 15 and 15a to seal between the semiconductor element 11 and the circuit pattern. In FIG. 1, the output terminals of the board (circuit board) 12 are omitted.
【００１１】図２に示す本発明の第２の実施の形態に係
る半導体装置１９について説明するが、基板材２０に
は、半導体素子２１の電極パッド２２に対応する部分に
それぞれ開口部２３が設けられている。この開口部２３
はこの実施の形態では四角形であるが、内部の電極パッ
ド２２がある程度視認できる大きさであれば、丸、角い
ずれであってもよい。基板材２０の表面側には導体回路
パターンが形成され、この導体回路パターンには開口部
２３を横切る接続端子２４が設けられている。接続端子
２４の表面には金めっきがなされている。電極パッド２
２と接続端子２４とは予め各電極パッド２２の表面上に
形成された半田バンプ２５によって接合されている。こ
の半導体装置１９の製造は、第１の実施の形態に係る半
導体装置１０と同一であるので省略する。A semiconductor device 19 according to a second embodiment of the present invention shown in FIG. 2 will be described. The substrate material 20 is provided with openings 23 at portions corresponding to the electrode pads 22 of the semiconductor element 21. Has been. This opening 23
Although this is a quadrangle in this embodiment, it may be a circle or a corner as long as the internal electrode pad 22 can be seen to some extent. A conductor circuit pattern is formed on the front surface side of the substrate material 20, and the conductor circuit pattern is provided with a connection terminal 24 that crosses the opening 23. The surface of the connection terminal 24 is plated with gold. Electrode pad 2
2 and the connection terminal 24 are joined to each other by solder bumps 25 formed on the surface of each electrode pad 22 in advance. The manufacturing of this semiconductor device 19 is the same as that of the semiconductor device 10 according to the first embodiment, and therefore its description is omitted.
【００１２】前記実施の形態では、理解に容易にするた
め、少数の電極パッドを有する半導体素子に本発明を適
用した場合について記載したが、多数の電極パッドを有
する半導体素子に適用できることは当然である。また、
前記実施の形態においては、半導体素子の封止にはポッ
ティング樹脂を用いたが、トランスファ型のモールド樹
脂を使用する場合にも本発明は適用される。In the above-described embodiment, the case where the present invention is applied to a semiconductor device having a small number of electrode pads has been described for easy understanding, but it is needless to say that the present invention can be applied to a semiconductor device having a large number of electrode pads. is there. Also,
In the above embodiment, the potting resin was used for sealing the semiconductor element, but the present invention is also applicable to the case where a transfer type molding resin is used.
【００１３】[0013]
【発明の効果】請求項１〜３記載の半導体装置において
は、接続端子の直下の基板に開口部を設け、しかも接続
端子は開口部をブリッジしているので、半田接合後の状
態を非破壊で検査できる。また、開口部を通じて洗浄液
を内部に侵入させることができるので、フラックス等の
洗浄が容易となる。特に、請求項２記載の半導体装置に
おいては、開口部は各半田バンプが接続される接続端子
毎に設けられているので、導体回路パターンの支持が強
固となる。そして、請求項３記載の半導体装置において
は、半田バンプが接続される接続端子は１又は２以上の
群に分けられ、各群毎に開口部が設けられているので、
半田接合の状態の視認性が向上すると共に、洗浄液の流
れも良くなる。In the semiconductor device according to the present invention, since the opening is provided in the substrate immediately below the connection terminal, and the connection terminal bridges the opening, the state after soldering is not destroyed. Can be inspected. Further, since the cleaning liquid can enter the inside through the opening, cleaning of the flux and the like becomes easy. Particularly, in the semiconductor device according to the second aspect, since the opening is provided for each connection terminal to which each solder bump is connected, the conductor circuit pattern is strongly supported. Further, in the semiconductor device according to claim 3, the connection terminals to which the solder bumps are connected are divided into one or more groups, and the opening is provided for each group,
The visibility of the soldered state is improved and the flow of the cleaning liquid is improved.
【図１】（Ａ）は本発明の第１の実施の形態に係る半導
体装置の断面図、（Ｂ）は同底面図である。FIG. 1A is a sectional view of a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a bottom view of the same.
【図２】本発明の第２の実施の形態に係る半導体装置の
説明図である。FIG. 2 is an explanatory diagram of a semiconductor device according to a second embodiment of the present invention.
【図３】（Ａ）は従来例に係る半導体装置の断面図、
（Ｂ）は同底面図である。FIG. 3A is a cross-sectional view of a semiconductor device according to a conventional example,
(B) is a bottom view of the same.
１０：半導体装置、１１：半導体素子、１２：基板、１
２ａ：基板材、１３：電極パッド、１４：半田バンプ、
１５、１５ａ：開口部、１６：接続端子、１７：ポッテ
ィング樹脂、１９：半導体装置、２０：基板材、２１：
半導体素子、２２：電極パッド、２３：開口部、２４：
接続端子、２５：半田バンプ10: semiconductor device, 11: semiconductor element, 12: substrate, 1
2a: substrate material, 13: electrode pad, 14: solder bump,
15, 15a: opening, 16: connection terminal, 17: potting resin, 19: semiconductor device, 20: substrate material, 21:
Semiconductor element, 22: electrode pad, 23: opening, 24:
Connection terminal, 25: solder bump
Claims (3)
極パッドに半田バンプを設け、該半田バンプを介して基
板上の接続端子に電気的に接続された半導体装置におい
て、前記接続端子の直下の基板材に開口部を設け、しか
も前記接続端子は前記開口部をブリッジしていることを
特徴とする半導体装置。1. A semiconductor device in which a solder bump is provided on each electrode pad formed on the bottom of a semiconductor element and is electrically connected to a connection terminal on a substrate via the solder bump, directly below the connection terminal. 2. A semiconductor device, wherein an opening is provided in the substrate material, and the connection terminal bridges the opening.
記開口部は前記各半田バンプが接続される接続端子毎に
設けられていることを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein the opening is provided for each connection terminal to which each solder bump is connected.
記半田バンプが接続される前記接続端子は１又は２以上
の群に分けられ、各群毎に前記開口部が設けられている
ことを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein the connection terminals to which the solder bumps are connected are divided into one or more groups, and the opening is provided for each group. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001335062A JP2003142630A (en) | 2001-10-31 | 2001-10-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001335062A JP2003142630A (en) | 2001-10-31 | 2001-10-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003142630A true JP2003142630A (en) | 2003-05-16 |
Family
ID=19150094
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001335062A Pending JP2003142630A (en) | 2001-10-31 | 2001-10-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003142630A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109256359A (en) * | 2017-07-14 | 2019-01-22 | 格科微电子（上海）有限公司 | The encapsulating structure of imaging sensor |
-
2001
- 2001-10-31 JP JP2001335062A patent/JP2003142630A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109256359A (en) * | 2017-07-14 | 2019-01-22 | 格科微电子（上海）有限公司 | The encapsulating structure of imaging sensor |
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