JP2003141890A5 - - Google Patents
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- Publication number
- JP2003141890A5 JP2003141890A5 JP2002197395A JP2002197395A JP2003141890A5 JP 2003141890 A5 JP2003141890 A5 JP 2003141890A5 JP 2002197395 A JP2002197395 A JP 2002197395A JP 2002197395 A JP2002197395 A JP 2002197395A JP 2003141890 A5 JP2003141890 A5 JP 2003141890A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US30373601P | 2001-07-06 | 2001-07-06 | |
| US60/303736 | 2001-07-06 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2003141890A JP2003141890A (ja) | 2003-05-16 |
| JP2003141890A5 true JP2003141890A5 (ja) | 2005-10-27 |
| JP4262941B2 JP4262941B2 (ja) | 2009-05-13 |
Family
ID=23173459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002197395A Expired - Fee Related JP4262941B2 (ja) | 2001-07-06 | 2002-07-05 | アドレシング方法及び装置、記憶サイト読み出し方法及び装置、プログラミング方法及び装置、並びに、セル単位での消去方法及び装置 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6631088B2 (ja) |
| EP (1) | EP1274095A3 (ja) |
| JP (1) | JP4262941B2 (ja) |
| KR (1) | KR100929787B1 (ja) |
| TW (1) | TW565846B (ja) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3633537B2 (ja) * | 2001-09-27 | 2005-03-30 | トヨタ自動車株式会社 | 車両用内装部品の取付構造 |
| US6816412B2 (en) * | 2002-05-21 | 2004-11-09 | Broadcom Corporation | Non-volatile memory cell techniques |
| US6760270B2 (en) * | 2002-09-30 | 2004-07-06 | Motorola, Inc. | Erase of a non-volatile memory |
| JP3985689B2 (ja) * | 2003-02-21 | 2007-10-03 | セイコーエプソン株式会社 | 不揮発性半導体記憶装置 |
| US7589990B2 (en) * | 2004-12-03 | 2009-09-15 | Taiwan Imagingtek Corporation | Semiconductor ROM device and manufacturing method thereof |
| US7352033B2 (en) * | 2005-08-30 | 2008-04-01 | Halo Lsi Inc. | Twin MONOS array for high speed application |
| US7936604B2 (en) * | 2005-08-30 | 2011-05-03 | Halo Lsi Inc. | High speed operation method for twin MONOS metal bit array |
| US7388252B2 (en) * | 2005-09-23 | 2008-06-17 | Macronix International Co., Ltd. | Two-bits per cell not-and-gate (NAND) nitride trap memory |
| US8320191B2 (en) | 2007-08-30 | 2012-11-27 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
| US7567457B2 (en) * | 2007-10-30 | 2009-07-28 | Spansion Llc | Nonvolatile memory array architecture |
| US8125829B2 (en) * | 2008-05-02 | 2012-02-28 | Micron Technology, Inc. | Biasing system and method |
| US7796436B2 (en) * | 2008-07-03 | 2010-09-14 | Macronix International Co., Ltd. | Reading method for MLC memory and reading circuit using the same |
| TWI391947B (zh) * | 2008-08-06 | 2013-04-01 | Macronix Int Co Ltd | 多位階單元記憶體之讀取方法及應用其之讀取電路 |
| MX363787B (es) | 2013-03-13 | 2019-04-03 | Medimmune Ltd | Pirrolobenzodiazepinas y conjugados de los mismos. |
| US9361995B1 (en) * | 2015-01-21 | 2016-06-07 | Silicon Storage Technology, Inc. | Flash memory system using complementary voltage supplies |
| FR3036221B1 (fr) * | 2015-05-11 | 2017-04-28 | Stmicroelectronics Rousset | Structure d'interconnexion de cellules memoire jumelles |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6768165B1 (en) | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
| US5986934A (en) * | 1997-11-24 | 1999-11-16 | Winbond Electronics Corp.I | Semiconductor memory array with buried drain lines and methods therefor |
| US6134156A (en) | 1999-02-04 | 2000-10-17 | Saifun Semiconductors Ltd. | Method for initiating a retrieval procedure in virtual ground arrays |
| US6469935B2 (en) * | 1999-08-05 | 2002-10-22 | Halo Lsi Design & Device Technology, Inc. | Array architecture nonvolatile memory and its operation methods |
| US6248633B1 (en) | 1999-10-25 | 2001-06-19 | Halo Lsi Design & Device Technology, Inc. | Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory |
| JP4058232B2 (ja) * | 2000-11-29 | 2008-03-05 | 株式会社ルネサステクノロジ | 半導体装置及びｉｃカード |
| EP1246196B1 (en) | 2001-03-15 | 2010-02-17 | Halo, Inc. | Twin MONOS memory cell usage for wide program bandwidth |
-
2002
- 2002-07-05 TW TW091114930A patent/TW565846B/zh not_active IP Right Cessation
- 2002-07-05 EP EP02368072A patent/EP1274095A3/en not_active Withdrawn
- 2002-07-05 JP JP2002197395A patent/JP4262941B2/ja not_active Expired - Fee Related
- 2002-07-06 KR KR1020020039161A patent/KR100929787B1/ko not_active IP Right Cessation
- 2002-07-08 US US10/190,634 patent/US6631088B2/en not_active Expired - Lifetime