JP2003232838A5 - - Google Patents
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- Publication number
- JP2003232838A5 JP2003232838A5 JP2002364187A JP2002364187A JP2003232838A5 JP 2003232838 A5 JP2003232838 A5 JP 2003232838A5 JP 2002364187 A JP2002364187 A JP 2002364187A JP 2002364187 A JP2002364187 A JP 2002364187A JP 2003232838 A5 JP2003232838 A5 JP 2003232838A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US047344 | 2002-01-15 | ||
| US10/047,344 US6941497B2 (en) | 2002-01-15 | 2002-01-15 | N-squared algorithm for optimizing correlated events |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003232838A JP2003232838A (ja) | 2003-08-22 |
| JP2003232838A5 true JP2003232838A5 (ja) | 2006-01-26 |
Family
ID=21948424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002364187A Pending JP2003232838A (ja) | 2002-01-15 | 2002-12-16 | 相関処理事象を最適化するｎの二乗アルゴリズム |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6941497B2 (ja) |
| EP (1) | EP1327890B1 (ja) |
| JP (1) | JP2003232838A (ja) |
| KR (1) | KR100966010B1 (ja) |
| DE (1) | DE60204535T2 (ja) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040006447A1 (en) * | 2000-06-22 | 2004-01-08 | Jacky Gorin | Methods and apparatus for test process enhancement |
| US7167811B2 (en) * | 2001-05-24 | 2007-01-23 | Test Advantage, Inc. | Methods and apparatus for data analysis |
| US7395170B2 (en) * | 2001-05-24 | 2008-07-01 | Test Advantage, Inc. | Methods and apparatus for data analysis |
| US7225107B2 (en) * | 2001-05-24 | 2007-05-29 | Test Advantage, Inc. | Methods and apparatus for data analysis |
| US7904279B2 (en) * | 2004-04-02 | 2011-03-08 | Test Advantage, Inc. | Methods and apparatus for data analysis |
| JP4849798B2 (ja) * | 2004-12-28 | 2012-01-11 | 富士通株式会社 | 電子機器、記録制御方法及びプログラム |
| TW200724949A (en) * | 2005-08-19 | 2007-07-01 | Koninkl Philips Electronics Nv | Test sequence optimization method and design tool |
| US7596731B1 (en) * | 2006-04-07 | 2009-09-29 | Marvell International Ltd. | Test time reduction algorithm |
| US8180142B2 (en) * | 2008-12-02 | 2012-05-15 | International Business Machines Corporation | Test fail analysis on VLSI chips |
| US8484592B1 (en) | 2012-02-29 | 2013-07-09 | Umm Al-Qura University | Timing verification method for circuits |
| US9401222B1 (en) | 2015-11-23 | 2016-07-26 | International Business Machines Corporation | Determining categories for memory fail conditions |
| KR20210047127A (ko) | 2019-10-21 | 2021-04-29 | 삼성전자주식회사 | 반도체 회로를 검증하기 위한 최적화된 검증 벡터를 생성하는 전자 장치 및 그 동작 방법 |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0536802A (ja) * | 1991-07-31 | 1993-02-12 | Hitachi Ltd | 半導体集積回路補修診断方法 |
| JP2785901B2 (ja) * | 1992-03-27 | 1998-08-13 | 松下電器産業株式会社 | 検査系列生成方法および検査系列生成装置 |
| DE69333806T2 (de) | 1992-03-27 | 2005-10-06 | Matsushita Electric Industrial Co., Ltd., Kadoma | Verfahren und Gerät zur Prüfsequenzgenerierung |
| US5345450A (en) * | 1993-03-26 | 1994-09-06 | Vlsi Technology, Inc. | Method of compressing and decompressing simulation data for generating a test program for testing a logic device |
| JPH06282462A (ja) * | 1993-03-26 | 1994-10-07 | Toshiba Corp | 半導体試験装置制御プログラムデバッグ方式 |
| US5935264A (en) | 1997-06-10 | 1999-08-10 | Micron Technology, Inc. | Method and apparatus for determining a set of tests for integrated circuit testing |
| US6070131A (en) * | 1997-09-26 | 2000-05-30 | Micron Technology, Inc. | System for evaluating and reporting semiconductor test processes |
| KR100311013B1 (ko) * | 1998-07-04 | 2001-11-22 | 윤종용 | 테스트시퀀스데이터의압축방법 |
| US6810372B1 (en) * | 1999-12-07 | 2004-10-26 | Hewlett-Packard Development Company, L.P. | Multimodal optimization technique in test generation |
| US6782501B2 (en) * | 2001-01-23 | 2004-08-24 | Cadence Design Systems, Inc. | System for reducing test data volume in the testing of logic products |
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2002
- 2002-01-15 US US10/047,344 patent/US6941497B2/en not_active Expired - Lifetime
- 2002-11-26 EP EP02258130A patent/EP1327890B1/en not_active Expired - Fee Related
- 2002-11-26 DE DE60204535T patent/DE60204535T2/de not_active Expired - Lifetime
- 2002-12-16 JP JP2002364187A patent/JP2003232838A/ja active Pending
-
2003
- 2003-01-14 KR KR1020030002469A patent/KR100966010B1/ko active IP Right Grant