JP2003133475A - Support of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a support of semiconductor device in which a via electrode can be formed in a via hole in a short time by altering the structure of the support extremely simply and a high bonding reliability can be sustained by eliminating generation of a void in the via electrode. SOLUTION: The support of semiconductor device comprises a substrate 21 where a functional element, i.e., a capacitor 26, is formed on one side and circuit wiring is formed on the other side. Furthermore, a via hole 22 extends between the one side and the other side and a metal conductor via electrode 23 having hollow structure is formed on the inner wall face of the via hole 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI (larg).
e scale integrated circuit
t) and a semiconductor device such as a semiconductor package mounted on a mounting substrate, the present invention relates to an improvement of a support for a semiconductor device interposed between the semiconductor device and the mounting substrate.

[0002]

2. Description of the Related Art At present, semiconductor devices used in electronic equipment such as computers are being further promoted to have higher density and higher speed, and along with this, the mounting boards and peripheral circuit boards have high performance. There is a demand for realization of a device that can deal with higher density and higher speed operation.

Conventionally, when mounting an electronic component such as a semiconductor device, a support for the electronic component has been used. In that case, however, the front and back surfaces electrically connected to each other via a via formed in a substrate forming the support. Electrical connections between electronic components are made by circuit wiring.

However, since the ceramic substrate often used as a support is produced by stacking green sheets by applying a printing technique and firing it at a high temperature, shrinkage and voids occur. Therefore, it is difficult to deal with miniaturization and high density because of the problem.

Further, in a multilayer printed wiring board produced by the build-up method, when holes for forming vias are formed by laser processing, dirt is attached to the periphery of the holes and the shape of the holes. Is difficult to control with high precision.

In recent years, it has been proposed to use a substrate in which through holes are formed in a Si plate, that is, a through hole substrate, as a technique replacing the above-mentioned means. To manufacture this through hole substrate, a semiconductor manufacturing process is applied. It is possible to achieve miniaturization and high density, and the substrate of the semiconductor device mounted on the through hole substrate is also made of Si.
Therefore, there is an advantage that there is no concern about stress generation due to mismatch of thermal expansion coefficients between the device and the substrate.

7A and 7B are views for explaining a through-hole substrate made of Si, in which FIG.
FIGS. 3A and 3B are respectively cutaway side views for explaining a configuration when a through-hole substrate having a built-in thin film capacitor for a high frequency noise filter is mounted.

In FIG. 7A, only the through-hole substrate 1 and the via electrode 2 are shown, and other structures are omitted.

In FIG. 7B, 3 is a lower electrode forming a capacitor, 4 is a dielectric film forming a capacitor,
Reference numeral 5 is an upper electrode forming a capacitor, 6 and 7 are pads, 8 and 9 are solder balls, 10 is an LSI substrate, and 1
Reference numeral 1 denotes a mounting board, respectively.

Usually, the via electrode 2 has a structure in which a voltage line and a ground line are alternately arranged adjacent to each other, and a thin film capacitor is sandwiched between them, and the via electrode 2 is disposed on the upper part. The thin film capacitor thus formed is electrically connected to the wirings and electrodes arranged therebelow via the via electrode 2.

In the conventional support described with reference to FIG. 7, the via electrode 2 is formed by applying a plating method to the via hole formed in the through hole substrate 1 and filling the via hole with metal. Form.

The metal material used for the via electrode 2 is compatible with the material forming the electrode of the thin film capacitor, and
Considering that the thin film capacitor material is heat-treated in an oxidizing atmosphere, platinum (Pt) is usually used frequently.

Needless to say, the formation of such a via electrode 2 is intended to form a thin film capacitor and an electrode for solder bonding directly on the via electrode 2.

The via electrode 2 in the through-hole substrate 1 has a diameter of about 50 [μm] and a height (length) of about 300 [μm]. Takes a very long time to do so.

In addition, a void peculiar to plating is likely to remain inside the via electrode, and this void exhibits an irregular expansion / contraction behavior due to a temperature increase / decrease caused by repeated operation-stop.
This is a cause of lowering the reliability of solder joints.

[0016]

SUMMARY OF THE INVENTION According to the present invention, a via electrode can be formed within a via hole in a short time by making a very simple modification to the structure of a support, and the via electrode can be formed in a short time. No voids will be generated and high bonding reliability can be maintained.

[0017]

In a semiconductor device support according to the present invention, a functional element is fixedly provided on one surface and circuit wiring is formed on the other surface, and the functional element and the functional element are connected to each other. It is basically provided with a substrate in which a via hole connecting with a circuit wiring and a via electrode made of a hollow-structured metal conductor film covering an inner wall surface of the via hole are formed.

By adopting the above means, the time for forming the via electrode in the via hole in the substrate is greatly shortened, and the via electrode is a metal conductor film covering the inner wall surface of the via hole. No voids are generated, and the reliability of bonding is significantly improved.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory view showing a support for explaining the first embodiment of the present invention. FIG. , (B) show enlarged planes of the solder bonding electrodes provided on the back surface of the support.

In the figure, 21 is a Si substrate, 22 is a via hole, 23 is a via electrode made of a metal conductor film, 24 is a solder-bonding ring electrode electrically connected to the via electrode 23, and 25. Indicates a lead-out electrode for solder joint integrated with the ring-shaped electrode for solder joint 24, and 26 indicates a capacitor electrically connected to the via electrode 23.

The first feature of the illustrated support is, of course, that the via electrode 23 is formed of a metal conductor film that covers only the inner wall surface of the via hole 22, and this structure is adopted. As a result, the plating time for forming the via electrode 23 can be remarkably shortened as compared with the case of forming the via electrode that densely fills the via hole 22.

The second characteristic is that the electrode 24 electrically connected to the via electrode 23 has a ring shape, and the lead electrode 25 for actually solder-joining to the side of the ring electrode 24. In the configuration, the via hole 22 which is kept hollow can be electrically connected to the outside air. The ring-shaped electrode 24 may be covered with the solder resist film, but even in that case, the via hole 22 and the outside air can be maintained in communication by slightly processing the solder resist film. can do.

Furthermore, the third feature is that the lead-out electrode 25 to be soldered is led out laterally from the via electrode 23, and thus the ring-shaped electrode 24,
Since it is directly formed on the i-substrate 21, the extraction electrode 25 and the ring-shaped electrode 24 are stable against temperature changes, and high bonding reliability is obtained. Incidentally, in the conventional support, the electrode to be soldered is directly under the via electrode as seen in FIG. 7, and therefore the effect as in the support of the present invention cannot be expected.

FIG. 2 is an explanatory view showing a support for explaining the second embodiment of the present invention. FIG. 2A is a side view of a main part of the support, and FIG. Shows the cutting plane of the main part near the electrode on the back surface of the support, and (C)
Shows the enlarged side surface of the part circled in (A). The same symbols as those used in FIG. 1 represent the same parts or have the same meanings, and (B)
In the upper figure, the insulating film made of solder resist is removed, and in the lower figure, the insulating film made of solder resist is applied.

The difference between the second embodiment and the first embodiment is that a large area solder joint electrode 27 is integrally provided at the other end of the lead electrode 25 having one end coupled to the ring electrode 24. That is, the insulating film 28 made of, for example, a solder resist is formed so as to prevent the solder from flowing to an unnecessary portion.

When the insulating film 28 is formed in this way,
Since the via hole 22 is blocked, if left as it is, the air in the via hole 22 repeatedly expands and contracts due to the temperature increase and decrease caused by the repeated operation and stop of the thin film capacitor 26. Since stress is applied to the insulating film 28, as shown in (C), a hole 28A is formed at a position of the insulating film 28 corresponding to the via hole 22 to communicate the via hole 22 with the outside air. This prevents stress from being applied to the insulating film 28.

3 to 6 are side sectional views showing essential parts of a support in a process step for explaining an example of a process for manufacturing the support according to the present invention. Will be described with reference to.

See FIG. 3A. (1) By applying the thermal oxidation method, a thickness of 300 is obtained.
1000 μm thick on one surface of the Si substrate 31 of [μm]
The insulating film 32 made of SiO ₂ is formed.

Referring to FIG. 3B, (2) by applying a sputtering method, a Ti film having a thickness of 50 nm acting as a base is formed on the insulating film 32, and then a thickness of 200 nm is formed. ] Pt film is formed. For the sake of simplicity, in the figure, this Pt / Ti
The membrane is represented as a single layer and is labeled 33.

See FIG. 3C. (3) Resist process in lithography technology,
And by applying the ion milling method, Pt
The / Ti film 33 is etched to form an opening 33A.

See FIG. 3D. (4) The opening 33A is formed by applying the sputtering method or the sol-gel method after removing the resist film used as the mask when forming the opening 33A. A dielectric film 34 made of BST ((Ba, Sr) TiO ₃ ) is formed on the entire surface including the inside.

FIG. 3E (5) Resist process in lithography technology,
Then, by applying the ion milling method, the dielectric film 34 at the location corresponding to the selected opening 33A is etched to form an opening 34A larger than the opening 33A.

Since the opening 34A is larger than the opening 33A, Pt / T having the opening 33A in the opening 34A.
A part of the i film 33 is exposed.

As shown in FIG. 4A, (6) by removing the resist film used as the mask when the opening 34A is formed, and then applying the sputtering method, it acts as a base on the dielectric film 34. After forming a Ti film with a thickness of 50 [nm], a thickness of 200 [n]
m] of Pt film is formed. The Pt / T formed here
Like the Pt / Ti film 33, the i film is represented by a single layer and has a symbol 3
5 is given.

It goes without saying that the Pt / Ti film 35 formed here is electrically connected to the Pt / Ti film 33 at the location where the opening 34A exists.

4B and 4C (7) By applying a resist process in the lithography technique, the other surface of the Si substrate 31, that is, Pt.
A resist film 36 in which an opening 36A is formed is formed in a portion where a via hole is to be formed on the surface opposite to the surface on which the / Ti film 35 is formed.

Refer to FIGS. 4D and 4E. (8) DRIE (deep reactive ion)
By applying the etching method, the Si substrate 31 is etched using the resist film 36 as a mask to form a via hole 31A having a diameter of 50 [μm]. still,
This etching is gradually slowed down when the via hole 31A reaches the insulating film 32 made of SiO ₂ , and is automatically stopped. After that, the resist film 36 is removed.

Refer to FIG. 5A. (9) CVD (chemical vapor de
By applying the position method, S with a thickness of about 200 [nm] is formed on the entire surface including the inside of the via hole 31A.
forming an insulating film 37 made of iO _2.

See FIG. 5B. (10) By applying the selective RIE method, the insulating film 3 is formed.
Of the seven, only those on the bottom in the via hole 31A are removed to expose a part of the Pt / Ti film 35. still,
The selective RIE method applied here is a method in which F radical particles, which are etching particles, collide anisotropically vertically. More specifically, the pressure in the reaction chamber is lowered and the substrate bias application voltage is increased. Alternatively, plasma is generated on the back side of the substrate.

See FIG. 5C. (11) By applying the electroless plating method,
Pt / T is formed on the inner wall surface made of SiO ₂ in the hole 31A.
Depositing the i film and electrically coupling it to the Pt / Ti film 35 exposed on the bottom surface in the via hole 31A, and then applying a plating method using the Pt / Ti film as a seed. Therefore, Pt plating is performed so that the total thickness is about 10 [μ
m], a hollow via electrode 38 is formed.

In this case, the plating is via hole 31A.
Even if the diameter is 50 [μm], since the thickness of the hollow via electrode 38 is as thin as about 10 [μm], it is possible to form a film in a short time and voids do not occur. Needless to say, the via electrode 38 is electrically connected to the Pt / Ti film 33 at the tip toward the one surface of the substrate 31.

Referring to FIG. 5D, (12) when the via electrode 38 is formed by applying the resist process in the lithography technique and the dry etching method using chlorine gas as the etching gas. Then, the Pt film and the like formed on the surface are removed.

(13) By applying the resist process in the lithography technique and the dry etching method using chlorine gas as the etching gas, the Pt / Ti film 35 on the one surface side of the substrate 31 is applied. Selectively remove some of the.

Here, the part of the Pt / Ti film 35 to be removed is the part on the outermost surface and the opening 3 of the dielectric film 34.
4A (see FIG. 3 (E)), Pt /
Those existing in the opening 33A (see FIG. 3C) of the Ti film 33 are left.

Through the above steps, the Pt / Ti film 3
3, a thin film capacitor including the dielectric film 34 and the Pt / Ti film 35 is realized.

Referring to FIG. 6A, (14) By applying the vacuum filling printing method, the resist 39 is filled into the hollow portion of the via electrode 38, and hence the via hole 31A. The resist 39 is the insulating film 3
Do not attach near the surface of 7.

See FIG. 6B. (15) By applying the sputtering method while leaving the resist 39 filling the inside of the via hole 31A,
After forming a Ti film having a thickness of 50 [nm] on the insulating film 37, a Cu film having a thickness of 10 [μm] is plated to form a C film.
An electrode material film for soldering is formed of a u / Ti film. Here, for the sake of simplicity, the electrode material film made of the Cu / Ti film is also shown as a single layer.

(16) By applying a resist process in the lithography technique and a wet etching method using an ammonium persulfate system (for Cu) and a hydrofluoric acid system (for Ti) as etchants, the process (14) The electrode material film made of the Cu / Ti film formed in (4) is patterned to form the solder-bonding ring-shaped electrode 40 and the solder-bonding lead-out electrode 41.

(17) Immerse in a resist stripping solution to dissolve and remove the resist 39 filling the inside of the via hole 31A.

See FIG. 6C (18) A dry film 42 serving as a solder resist is attached to the entire surface including the solder-bonding ring-shaped electrode 40 and the solder-bonding lead-out electrode 41.

(19) By applying a resist process in the lithography technique and a wet etching method, the dry film 42 is etched to expose the lead-out electrode 41 for soldering, and at the same time the via
Small holes (see 28A in FIG. 2C) are also formed in the dry film 42 at locations corresponding to the holes 31A.

In the support thus prepared,
The operating characteristics of the thin film capacitor were unchanged compared to the thin film capacitor on the support prepared by the conventional technique.

FIG. 7 and FIG. 8 are side sectional views showing a main part of the support at a process step for explaining another example of the process for manufacturing the support according to the present invention. Will be described with reference to FIG. However, since the support manufacturing process described here is a modification of the support manufacturing process described with reference to FIGS. 5C to 5D, the steps (1) to (10) are performed. ) And the steps after the step (14) are exactly the same, so the description thereof will be omitted.

Referring to FIG. 7A, (1) When the step (10) described with reference to FIG. 5B is completed, the dry film resist film 51 is formed on the insulating film 37.

(2) The dry film resist film 51 is patterned by applying an ordinary lithography technique to form an opening exposing the via hole 31A.

Referring to FIG. 7B, (3) By applying the electroless plating method, the Pt / Ti film is deposited on the entire surface including the inner wall surface of SiO ₂ in the via hole 31A. The Pt / Ti film is electrically coupled to the Pt / Ti film 35 exposed on the bottom surface of the via hole 31A.

Referring to FIG. 8A, (4) the dry film resist film 51 is peeled off and removed together with the Pt / Ti film existing thereon.

See FIG. 8B. (5) By applying the plating method using the Pt / Ti film as a seed, the total thickness of the plated Pt is about 10
A hollow via electrode 38 having a thickness of [μm] is formed.

See FIG. 8C. (6) Resist process in lithography technology,
Further, a part of the Pt / Ti film 35 existing on the one surface side of the substrate 31 is selectively removed by applying a dry etching method using a chlorine-based gas as an etching gas.

Here, the part of the Pt / Ti film 35 to be removed is the part on the outermost surface and the dielectric film 3 as described above.
No. 4 opening 34A (see FIG. 3E), which is the opening 33A of the Pt / Ti film 33 (see FIG. 3C).
Keep what's inside.

Through the above steps, the Pt / Ti film 3
3, a thin film capacitor including the dielectric film 34 and the Pt / Ti film 35 is realized. After this, the same steps as those described with reference to FIG. 6 are performed to form the solder-bonding ring-shaped electrode 40, the solder-bonding lead-out electrode 41, and the like.

[0062]

In the support of the semiconductor device according to the present invention, the functional element is formed on one surface, the circuit wiring is formed on the other surface, and the one surface and the other surface are penetrated. The substrate is provided with a via hole and a via electrode made of a hollow-structured metal conductor attached to the inner wall surface of the via hole.

By adopting the above structure, the time for forming the via electrode in the via hole in the substrate is greatly shortened, and the via electrode is the metal conductor film covering the inner wall surface of the via hole. No voids are generated, and the reliability of bonding is significantly improved.

[Brief description of drawings]

FIG. 1 is an explanatory view showing a support for explaining a first embodiment of the present invention.

FIG. 2 is an explanatory view showing a support for explaining a second embodiment of the present invention.

FIG. 3 is a side sectional view showing an essential part of a support at a process step for explaining a process of manufacturing the support according to the present invention.

FIG. 4 is a side sectional view showing an essential part of the support at a process step for explaining a process for producing the support according to the present invention.

FIG. 5 is a cutaway side view showing a main part of a support at a process step for explaining a process of manufacturing the support according to the present invention.

FIG. 6 is a side sectional view showing an essential part of a support at a process key point for explaining a process of manufacturing the support according to the present invention.

FIG. 7 is a side sectional view showing an essential part of a support in a process key part for explaining a process of manufacturing the support according to the present invention.

FIG. 8 is a side sectional view showing an essential part of a support at a process step for explaining a process for producing the support according to the present invention.

FIG. 9 is a diagram illustrating a through-hole substrate made of Si as a material.

[Explanation of symbols]

31 Si substrate 31A Beer Hall 32 insulating film 33 Pt / Ti film 33A opening 34 Dielectric film 34A opening 35 Pt / Ti film 36 Resist film 36A opening 37 Insulation film 38 Hollow via electrode 39 resist 40 Solder ring-shaped electrode 41 Lead electrode for solder joint 42 dry film

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Osamu Taniguchi             4-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa             No. 1 within Fujitsu Limited

Claims (5)

[Claims] 1. A via hole having a functional element formed on one surface and circuit wiring formed on the other surface, and a via hole penetrating between the one surface and the other surface and an inner wall surface of the via hole. A support for a semiconductor device comprising a substrate on which a via electrode made of a metal conductor having a hollow structure is formed. 2. One end of a via electrode made of a metal conductor having a hollow structure is joined to a functional element formed on one surface of a substrate, and the other end is joined to a circuit wiring formed on the other surface of the substrate. A support for a semiconductor device. 3. In order to prevent solder inflow, a via hole on the surface of the other surface of the substrate on which circuit wiring is formed is blocked by an insulating material film having air permeability. A support for a semiconductor device according to claim 1, wherein the support is a semiconductor device. 4. A support for a semiconductor device according to claim 3, wherein the insulating material film is provided with ventilation holes for maintaining air permeability. 5. The support of the semiconductor device according to claim 3, wherein the insulating material film is a solder resist film.