JP2003133452A - Manufacturing method of electronic equipment - Google Patents

Manufacturing method of electronic equipment

Info

Publication number
JP2003133452A
JP2003133452A JP2001322294A JP2001322294A JP2003133452A JP 2003133452 A JP2003133452 A JP 2003133452A JP 2001322294 A JP2001322294 A JP 2001322294A JP 2001322294 A JP2001322294 A JP 2001322294A JP 2003133452 A JP2003133452 A JP 2003133452A
Authority
JP
Japan
Prior art keywords
substrate
electronic device
manufacturing
frame material
frame member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001322294A
Other languages
Japanese (ja)
Inventor
Seiya Yamaguchi
征也 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2001322294A priority Critical patent/JP2003133452A/en
Publication of JP2003133452A publication Critical patent/JP2003133452A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of electronic equipment that has easy manufacturing processes, and at the same time can achieve a desired airtight state. SOLUTION: The manufacturing method comprises the process of forming an electronic device 3 on a substrate 2, the process of installing a frame material 5a that surrounds the electronic device 3 on the substrate 2 and at the same time has a shape for securing a gas passage to outside atmosphere, the process of installing a lid material 7 on the frame material 5a while specific space is being secured at a portion to the electronic device 3 formed on the substrate 2, the process of reducing the pressure of the outside atmosphere of the substrate 2 to remove gas in the specific space via the gas passage, and the process of fusing the frame material 5a to block the gas passage and airtightly sealing the electronic device 3 on the substrate 2 into the specific space.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、例えば、気密封止
された電子素子を有する電子装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an electronic device having an electronic element hermetically sealed.

【0002】[0002]

【従来の技術】固体撮像素子、レーザ発光素子、受光素
子等の電子素子を有する基板を気密封止接合するために
は、一般的にガラスが蓋として使用され、基板と蓋に
は、空間的な隔たり(空洞)が必要とされる。また、素
子やガラスの蓋が結露すると電子素子の機能を損ねるた
め、気密封止が必要となる。
2. Description of the Related Art In general, glass is used as a lid for hermetically sealing and joining a substrate having electronic elements such as a solid-state image pickup element, a laser emitting element, and a light receiving element. A large gap (cavity) is required. Further, if dew condensation occurs on the element or the lid of the glass, the function of the electronic element is impaired, so that hermetic sealing is required.

【0003】以前は、この空洞を確保するために、セラ
ミックや樹脂等のパッケージ材料が使用されていたが、
これらを使用すると外形寸法が大きくなってしまい、素
子の微細化に対応できないという問題があった。また、
セラミック等は高価で材料費が高くなる上、セラミック
基板を複数張り合わせて空洞を作製するため、製造工程
数も多くなるため、コスト高になるという問題があっ
た。
In the past, packaging materials such as ceramics and resins were used to secure this cavity.
When these are used, the external dimensions become large, and there is a problem that it is not possible to cope with the miniaturization of the element. Also,
Ceramics and the like are expensive and the material cost is high. Further, since a plurality of ceramic substrates are bonded together to form a cavity, the number of manufacturing steps is increased, resulting in a high cost.

【0004】そこで、近年、電子素子が形成されたシリ
コン基板等に、電子素子を囲むようにはんだ枠材を設置
し、はんだ枠材を介して蓋を直接貼り付ける方法が導入
されつつある。
Therefore, in recent years, a method is being introduced in which a solder frame material is installed so as to surround the electronic element on a silicon substrate or the like on which the electronic element is formed, and a lid is directly attached via the solder frame material.

【0005】このパッケージを封止する際には、封止後
に空洞内に水分、酸素、有機ガス等が残留すると、電子
素子の特性に影響を与えるため、極力除外する必要があ
る。そのため、封止前の予備加熱工程において電子素子
を炉内にて加熱真空引きすることにより、基板などに付
着・吸着された水分、酸素、有機ガス等を除外してい
る。
When the package is sealed, moisture, oxygen, organic gas, etc., remaining in the cavity after the sealing will affect the characteristics of the electronic device, and therefore must be excluded as much as possible. Therefore, in the preheating step before sealing, the electronic element is heated and evacuated in a furnace to exclude water, oxygen, organic gas and the like attached / adsorbed to the substrate.

【0006】そして、封止後の空洞内の雰囲気を電子素
子の機能に合わせて減圧状態に保つ場合には、封止工程
において、炉内を減圧に保ちつつはんだの融点まで温度
を上げることにより、はんだ枠材を溶融させて気密封止
を完成させていた。
When the atmosphere in the cavity after sealing is kept in a depressurized state in accordance with the function of the electronic device, the temperature is raised to the melting point of the solder in the sealing step while keeping the pressure in the furnace at a reduced pressure. , The solder frame material was melted to complete hermetic sealing.

【0007】また、封止後の空洞内の雰囲気を電子素子
の機能に合わせて気体を封入する必要がある場合には、
上記の予備加熱工程の後に冷却後の空洞内の圧力を考慮
した所定の加熱状態および圧力設定にて、炉内に封入ガ
スを入れた後、封止工程において、はんだの融点まで温
度を上げることにより、はんだ枠材を溶融させて封止を
完成させていた。
Further, when it is necessary to fill the atmosphere in the cavity after the sealing with gas according to the function of the electronic element,
After the above preheating step, after filling the furnace with the gas to be filled in with a predetermined heating state and pressure setting that considers the pressure in the cavity after cooling, raise the temperature to the melting point of the solder in the sealing step. Thus, the solder frame material was melted to complete the sealing.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、上記の
ように、素子空洞内外のガスを交流させる必要があるた
め、一般的には、はんだ溶融により接合する直前まで
は、基板、はんだ枠材、蓋を重ねずに距離を設けてお
き、はんだ溶融により接合する直前に基板と蓋をはんだ
枠材を介して接触させる必要がある。
However, as described above, since it is necessary to exchange the gas inside and outside the element cavity with each other, in general, the substrate, the solder frame material, and the lid are kept until just before they are joined by solder melting. It is necessary to provide a distance without overlapping and to bring the substrate and the lid into contact with each other via the solder frame material immediately before joining by melting the solder.

【0009】このように、はんだ溶融前の予備加熱工程
等の加熱処理途中においては、基板および蓋の相対距離
を遠ざけておく作業が必要で、装置にもその作業を実現
させるための機能が必要であり、装置構成が複雑になっ
てしまうという問題があった。
As described above, during the heating process such as the preheating process before melting the solder, it is necessary to keep the relative distance between the substrate and the lid away from each other, and the apparatus is also required to have a function for realizing the work. Therefore, there is a problem that the device configuration becomes complicated.

【0010】また、封止工程においては、基板と蓋を密
着させる動作が必要となるため、装置の機構可動部等か
らの発塵が発生し、歩留りの低下が起きてしまうという
問題があった。
Further, in the sealing step, since it is necessary to bring the substrate and the lid into close contact with each other, there is a problem that dust is generated from the mechanism moving part of the apparatus and the yield is lowered. .

【0011】上記の問題を回避するために、素子空洞内
外のガスの交流を犠牲にしても、予備加熱の段階から、
基板、はんだ枠材、蓋を重ねてしまうこともある。この
場合は、はんだ枠材、基板、および蓋の反りや厚みのば
らつきからできるわずかな隙間を通して基板等に付着・
吸着された水分、酸素、有機ガス等を除外し、また、封
止すべきガスを空洞内に送りこんでいた。
In order to avoid the above-mentioned problems, even if the alternating current of the gas inside and outside the element cavity is sacrificed, from the preheating stage,
The board, solder frame material, and lid may overlap. In this case, the solder frame material, the board, and the lid are attached to the board, etc.
The adsorbed water, oxygen, organic gas, etc. are excluded, and the gas to be sealed is fed into the cavity.

【0012】しかしながら、この場合には、素子空洞内
外のガスの交流が犠牲となり、また、封止後の空洞内を
所定の減圧下に設定したい場合や、封止後の空洞内を所
定の湿度や封入ガス雰囲気下にしたい場合等に制限があ
り、電子素子の機能を十分に保持することが困難となっ
てしまう。
However, in this case, the alternating current of the gas inside and outside the element cavity is sacrificed, and when it is desired to set the inside of the sealed cavity under a predetermined reduced pressure, or when the inside of the sealed cavity has a predetermined humidity. However, there are restrictions when it is desired to keep the atmosphere of the enclosed gas, and it becomes difficult to sufficiently maintain the function of the electronic element.

【0013】本発明は上記の事情に鑑みてなされたもの
であり、その目的は、製造工程が容易で、かつ、所望の
気密状態を実現できる電子装置の製造方法を提供するこ
とにある。
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing an electronic device in which the manufacturing process is easy and a desired hermetic state can be realized.

【0014】[0014]

【課題を解決するための手段】上記の目的を達成するた
め、本発明の電子装置の製造方法は、基板に電子素子を
形成する工程と、前記基板の前記電子素子を囲み、か
つ、外部雰囲気へのガス通路を確保し得る形状の枠材を
前記基板上に設置する工程と、前記基板上に形成された
前記電子素子との間に所定の空間を確保した状態で、前
記枠材上に蓋材を設置する工程と、前記基板の外部雰囲
気を減圧して、前記ガス通路を介して前記所定の空間内
のガスを除去する工程と、前記枠材を溶融させて前記ガ
ス通路を塞ぎ、前記基板上の前記電子素子を前記所定の
空間内に気密封止する工程とを有する。
In order to achieve the above object, a method of manufacturing an electronic device of the present invention comprises a step of forming an electronic element on a substrate, surrounding the electronic element of the substrate, and an external atmosphere. A step of installing a frame material having a shape capable of ensuring a gas passage to the substrate, and a predetermined space between the electronic element formed on the substrate and a predetermined space is secured on the frame material. A step of installing a lid material, a step of decompressing an atmosphere outside the substrate to remove gas in the predetermined space through the gas passage, and a step of melting the frame material to close the gas passage, And hermetically sealing the electronic element on the substrate in the predetermined space.

【0015】前記枠材を前記基板上に設置する工程にお
いて、前記枠材と前記基板との接触部に前記ガス通路と
なる隙間が形成され得る形状の前記枠材を、前記基板上
に設置する。例えば、前記枠材を前記基板上に設置する
工程において、突起部が形成された枠材を前記基板上に
設置する。あるいは、前記枠材を前記基板上に設置する
工程において、肉厚差を有する枠材を前記基板上に設置
する。あるいは、前記枠材を前記基板上に設置する工程
において、平面方向において段差が形成された枠材を前
記基板上に設置する。
In the step of installing the frame member on the substrate, the frame member having a shape capable of forming a gap serving as the gas passage at a contact portion between the frame member and the substrate is installed on the substrate. . For example, in the step of installing the frame material on the substrate, the frame material having the protrusions is installed on the substrate. Alternatively, in the step of installing the frame member on the substrate, the frame members having a difference in wall thickness are installed on the substrate. Alternatively, in the step of installing the frame member on the substrate, the frame member having a step formed in the plane direction is installed on the substrate.

【0016】前記基板の外部雰囲気を減圧する工程にお
いて、前記枠材の融点を越えない範囲の加熱状態で外部
雰囲気を減圧する。
In the step of depressurizing the external atmosphere of the substrate, the external atmosphere is depressurized in a heated state within a range not exceeding the melting point of the frame material.

【0017】前記所定の空間内のガスを除去する工程の
後、前記電子素子を前記所定の空間内に気密封止する工
程の前に、前記基板の外部雰囲気を所定の封入ガス雰囲
気にして、前記ガス通路を介して前記所定の空間内に封
入ガスを入れる工程をさらに有する。
After the step of removing the gas in the predetermined space and before the step of hermetically sealing the electronic element in the predetermined space, the atmosphere outside the substrate is changed to a predetermined sealed gas atmosphere, The method further includes the step of introducing a sealed gas into the predetermined space via the gas passage.

【0018】前記枠材を前記基板上に設置する工程の前
に、前記枠材との接触箇所における前記基板上に、前記
基板および前記枠材との接着を確保し得る接着層を形成
する工程をさらに有する。
Before the step of placing the frame member on the substrate, a step of forming an adhesive layer on the substrate at the contact point with the frame member, which can secure the adhesion between the substrate and the frame member. Further has.

【0019】前記枠材上に蓋材を設置する工程の前に、
前記枠材との接触箇所における前記蓋材上に、前記蓋材
および前記枠材との接着を確保し得る接着層を形成する
工程をさらに有する。
Before the step of installing the lid material on the frame material,
The method further includes the step of forming an adhesive layer capable of ensuring adhesion between the lid member and the frame member on the lid member at a contact point with the frame member.

【0020】上記の本発明の電子装置の製造方法では、
電子素子が形成された基板上に、電子素子を囲み、か
つ、外部雰囲気へのガス通路を確保し得る形状の枠材を
設置し、蓋材の設置後、このガス通路を介して、所定の
空間内のガスが除去される。また、必要に応じて、ガス
通路を介して所定の空間内に封入ガスを入れた後、枠材
を溶融させてガス通路を塞ぎ、基板上の電子素子が所定
の空間内に気密封止される。
In the above method of manufacturing an electronic device of the present invention,
On the substrate on which the electronic element is formed, a frame member that surrounds the electronic element and has a shape that can secure a gas passage to the external atmosphere is installed, and after the lid member is installed, a predetermined amount is provided through the gas passage. The gas in the space is removed. Further, if necessary, after filling the predetermined space through the gas passage into the predetermined space, the frame material is melted to close the gas passage, and the electronic element on the substrate is hermetically sealed in the predetermined space. It

【0021】[0021]

【発明の実施の形態】以下に、本発明の電子装置の製造
方法の実施の形態について、図面を参照して説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a method for manufacturing an electronic device of the present invention will be described below with reference to the drawings.

【0022】図1(a)は本実施形態に係る電子装置の
製造方法によって製造される電子装置の平面図、図1
(b)は図1(a)のA−A’線における断面図であ
る。
FIG. 1A is a plan view of an electronic device manufactured by the method for manufacturing an electronic device according to the present embodiment.
FIG. 1B is a sectional view taken along the line AA ′ of FIG.

【0023】基板2は、素子形成面2aを有し、例え
ば、シリコン基板、GaAs基板あるいはガラス基板等
により構成される。なお、図中、素子形成面2aが凹部
となっている例を示すが、平坦であってもよい。
The substrate 2 has an element forming surface 2a and is made of, for example, a silicon substrate, a GaAs substrate, a glass substrate or the like. Although the element forming surface 2a is shown as a concave portion in the drawing, it may be flat.

【0024】基板2の素子形成面2aに、所望の機能を
有する電子素子3が形成されている。電子素子3は、公
知の半導体微細加工技術により、各種の膜を堆積および
パターニングすることにより形成されるものであり、例
えば、固体撮像素子、レーザ発光素子、受光素子等があ
る。また、電子素子3は、上記の他にも、MEMS(Mi
cro Electro Mechanical Systems) と称されるマイクロ
マシンのような半導体の微細加工技術を用いて作製され
るものであってもよい。
An electronic element 3 having a desired function is formed on the element forming surface 2a of the substrate 2. The electronic element 3 is formed by depositing and patterning various films by a known semiconductor microfabrication technique, and includes, for example, a solid-state image sensor, a laser light emitting element, a light receiving element, and the like. In addition to the above, the electronic element 3 is a MEMS (Mi
It may be manufactured by using a semiconductor microfabrication technique such as a micromachine called cro Electro Mechanical Systems).

【0025】基板2上には、上記の電子素子3を取り囲
むように、接着層4、はんだ枠材5、接着層6が形成さ
れている。
An adhesive layer 4, a solder frame material 5, and an adhesive layer 6 are formed on the substrate 2 so as to surround the electronic element 3 described above.

【0026】接着層4は、はんだ枠材5を基板2に直接
接合させることは難しいことから、はんだ枠材5と基板
2との間に設けられており、はんだ枠材5と基板2との
双方に接合しやすい材料により構成され、例えば、Ti
とNiとAuの積層膜により構成される。
Since it is difficult to directly bond the solder frame material 5 to the board 2, the adhesive layer 4 is provided between the solder frame material 5 and the board 2, and the solder frame material 5 and the board 2 are bonded together. It is made of a material that is easy to bond to both sides.
And a laminated film of Ni and Au.

【0027】はんだ枠材5は、基板2上の電子素子3を
取り囲むように形成されている。はんだ枠材5は、電子
素子3上に所定の空洞を確保し得る厚みに形成されてい
る。はんだ枠材5の材料には、特に限定はないが、例え
ば、AuSiや、AuSn等がある。
The solder frame material 5 is formed so as to surround the electronic element 3 on the substrate 2. The solder frame material 5 is formed to have a thickness that can secure a predetermined cavity on the electronic element 3. The material of the solder frame material 5 is not particularly limited, and examples thereof include AuSi and AuSn.

【0028】接着層6は、はんだ枠材5を蓋材7に直接
接合させることは難しいことから、はんだ枠材5と蓋材
7との間に設けられており、はんだ枠材5と蓋材7との
双方に接合しやすい材料により構成され、例えば、Ti
とNiとAuの積層膜により構成される。
Since it is difficult to directly bond the solder frame member 5 to the lid member 7, the adhesive layer 6 is provided between the solder frame member 5 and the lid member 7. It is composed of a material that can be easily bonded to both
And a laminated film of Ni and Au.

【0029】蓋材7は、基板2の素子形成面2aとの間
に所定の空間を確保した状態で、はんだ枠材5の上端部
に、接着層6を介して接合されている。蓋材7は、例え
ば、透明材料からなり、周知の中空パッケージ構造に採
用されているシールガラスと同様のもので、この蓋材7
により、はんだ枠材5の開口部を塞ぐことにより、所定
の空間内に電子素子3が気密封止されることとなる。
The lid member 7 is bonded to the upper end portion of the solder frame member 5 with an adhesive layer 6 in a state where a predetermined space is secured between the lid member 7 and the element forming surface 2a of the substrate 2. The lid member 7 is made of, for example, a transparent material, and is the same as the seal glass used in the well-known hollow package structure.
Thus, by closing the opening of the solder frame member 5, the electronic element 3 is hermetically sealed in the predetermined space.

【0030】はんだ枠材5および蓋材7によって気密封
止された素子形成面2aの外側における基板2上には、
電子素子3に電気的に接続するパッド8が複数形成され
ている。
On the substrate 2 outside the element forming surface 2a hermetically sealed by the solder frame material 5 and the lid material 7,
A plurality of pads 8 that are electrically connected to the electronic element 3 are formed.

【0031】図2は、上記構成の電子装置1を実装基板
に搭載後の断面図である。図2に示すように、上記の電
子装置1は、ガラスエポキシ樹脂等からなる実装基板1
0上に、例えば、ボンディング剤11を介して搭載され
る。
FIG. 2 is a cross-sectional view after mounting the electronic device 1 having the above structure on a mounting board. As shown in FIG. 2, the electronic device 1 includes a mounting substrate 1 made of glass epoxy resin or the like.
0, for example, via a bonding agent 11.

【0032】ボンディング剤11は、例えば、エポキシ
樹脂等の熱硬化性樹脂を主剤としたものが使用される。
導電性を必要とする場合は、銀(Ag)等の金属粉末を
所定の割合で混合することで所望の電気伝導性を確保
し、導電ペーストとして使用される。一方、導電性を必
要としない場合は、粘性、応力緩和等を考慮してシリ
カ、アルミナ等のフィラーを混合し、絶縁ペーストとし
て使用される。
As the bonding agent 11, for example, a material whose main component is a thermosetting resin such as an epoxy resin is used.
When conductivity is required, a desired electrical conductivity is secured by mixing metal powder such as silver (Ag) in a predetermined ratio, and the mixture is used as a conductive paste. On the other hand, when conductivity is not required, a filler such as silica or alumina is mixed in consideration of viscosity, stress relaxation, etc., and used as an insulating paste.

【0033】実装基板10には、図示しない領域に形成
された回路パターンに接続するパッド12が形成されて
いる。実装基板10のパッド12と基板2に形成された
パッド8とが、金線などからなるボンディングワイヤ1
3により結線されて、電子素子3が図示しない領域に形
成された回路パターンと電気的に接続され、所望の動作
を実現することとなる。
Pads 12 for connecting to a circuit pattern formed in a region (not shown) are formed on the mounting substrate 10. The bonding wire 1 in which the pad 12 of the mounting substrate 10 and the pad 8 formed on the substrate 2 are gold wires or the like
3 is connected to electrically connect the electronic element 3 to a circuit pattern formed in a region (not shown), thereby realizing a desired operation.

【0034】次に、上記構成の本実施形態に係る電子装
置の製造方法について、図3を参照して説明する。
Next, a method of manufacturing the electronic device having the above-described structure according to this embodiment will be described with reference to FIG.

【0035】まず、図3(a)に示すように、シリコ
ン、GaAs、あるいはガラス等からなる基板2に、公
知の半導体微細加工技術により、基板2の素子形成面2
aに電子素子3を作製する。そして、スパッタリング法
あるいは蒸着法により、基板2上にTiとNiとAuの
積層膜を形成し、リソグラフィー技術を用いたエッチン
グ加工によりパターニングして、基板2上のはんだ枠材
5の搭載領域のみに接着層4を形成する。
First, as shown in FIG. 3A, an element formation surface 2 of the substrate 2 is formed on a substrate 2 made of silicon, GaAs, glass or the like by a known semiconductor fine processing technique.
The electronic element 3 is manufactured in a. Then, a laminated film of Ti, Ni, and Au is formed on the substrate 2 by a sputtering method or a vapor deposition method, and is patterned by etching using a lithography technique so that only the mounting area of the solder frame material 5 on the substrate 2 is formed. The adhesive layer 4 is formed.

【0036】次に、基板2と蓋材7との間に、素子形成
面2aを取り囲む形状を有するはんだ枠材5aを挟み込
む。ここで、予め基板2と同様に蓋材7にも、はんだ枠
材5aとの接触部分に、同様の手法で、TiとNiとA
uの積層膜からなる接着層6をパターン形成しておく。
これにより、接着層4,6を介して、はんだ枠材5aが
基板2と蓋材7との間に挟まれることとなる。このと
き、図3(b)に示すように、はんだ枠材5aと接着層
4,6との間に隙間が形成されるような形状のはんだ枠
材5aを使用する。
Next, a solder frame material 5a having a shape surrounding the element forming surface 2a is sandwiched between the substrate 2 and the lid material 7. Here, in the same manner as in the case of the substrate 2, the lid member 7 is previously attached to the contact portion of the solder frame member 5a with Ti, Ni and A by the same method.
The adhesive layer 6 made of a laminated film of u is patterned.
As a result, the solder frame material 5a is sandwiched between the substrate 2 and the lid material 7 via the adhesive layers 4 and 6. At this time, as shown in FIG. 3B, the solder frame material 5a having a shape in which a gap is formed between the solder frame material 5a and the adhesive layers 4 and 6 is used.

【0037】上記の本実施形態において、使用するはん
だ枠材5aの形状の一例を図4〜図11に示す。例え
ば、図4に示すような4隅に突起部が形成されたはんだ
枠材5aや、図5に示すような段差が形成されたはんだ
枠材5aを使用する。あるいは、図6に示すような4隅
が折り曲げて形成されたはんだ枠材5aや、図7に示す
ような対向する2辺を折り曲げて形成されたはんだ枠材
5aを使用する。あるいは、図8および図9に示すよう
に肉厚差をもつはんだ枠材5aを使用する。あるいは、
図10に示すような所定の箇所のみを曲げることで隙間
を形成したはんだ枠材5aや、図11(a)およびその
B−B’断面図である図11(b)に示すような枠が角
柱でなく、その断面が所定の曲率で盛り上がった形状の
はんだ枠材5aを使用する。上記のはんだ枠材5aの形
状は、はんだ枠材5aのプレス成型や射出成型時に形成
しておく。上記のはんだ枠材5aを使用することによ
り、はんだ枠材5aと接着層4,6との間に、はんだ枠
材5aの突起や段差等の高さ分だけの隙間が形成され、
当該隙間が外部雰囲気とのガス通路となる。
An example of the shape of the solder frame material 5a used in the above embodiment is shown in FIGS. For example, a solder frame material 5a having protrusions formed at four corners as shown in FIG. 4 or a solder frame material 5a having steps as shown in FIG. 5 is used. Alternatively, a solder frame material 5a formed by bending four corners as shown in FIG. 6 or a solder frame material 5a formed by bending two opposite sides as shown in FIG. 7 is used. Alternatively, as shown in FIGS. 8 and 9, the solder frame material 5a having a difference in wall thickness is used. Alternatively,
A solder frame material 5a in which a gap is formed by bending only a predetermined portion as shown in FIG. 10 and a frame as shown in FIG. 11 (a) and FIG. 11 (b) which is a cross-sectional view taken along line BB ′ of FIG. Instead of the prism, the solder frame material 5a whose cross section is raised with a predetermined curvature is used. The shape of the solder frame material 5a is formed at the time of press molding or injection molding of the solder frame material 5a. By using the above-mentioned solder frame material 5a, a gap is formed between the solder frame material 5a and the adhesive layers 4 and 6 by the height of the protrusions or steps of the solder frame material 5a,
The gap serves as a gas passage to the external atmosphere.

【0038】次に、予備加熱工程として、電子素子3を
有する基板2を炉内にて、加熱真空引きすることによ
り、上述した隙間を介して基板2等に付着・吸着された
水分、酸素、有機ガス等を除外する。当該予備加熱工程
を行うのは、封止後に、空洞内に水分、酸素、有機ガス
等が残留すると、電子素子3の特性に影響を与えるた
め、これを極力除外する必要があるからである。当該工
程において、はんだ枠材5aの搭載に伴い、隙間が形成
されていることから、有効に空洞内の水分、酸素、有機
ガス等が除外されることとなる。
Next, in the preheating step, the substrate 2 having the electronic element 3 is heated and evacuated in a furnace to remove moisture, oxygen, and the like, which are attached and adsorbed to the substrate 2 and the like through the above-mentioned gap. Exclude organic gas, etc. The preheating step is performed because moisture, oxygen, organic gas, etc. remaining in the cavity after sealing affects the characteristics of the electronic element 3 and must be excluded as much as possible. In the process, since the gap is formed along with the mounting of the solder frame material 5a, moisture, oxygen, organic gas and the like in the cavity are effectively excluded.

【0039】次に、封止後の空洞内の雰囲気を電子素子
3の機能に合わせて減圧状態に保つ場合には、炉内を減
圧に保ちつつはんだの融点まで温度を上げることによ
り、はんだを溶融させて封止を行う。また、空洞内に電
子素子3の機能に合わせて気体を封入する場合には、冷
却後の空洞内の圧力を考慮した所定の加熱状態および圧
力設定にて、炉内に封入ガスを入れた後、はんだの融点
まで温度を上げることにより、封止を行う。そして、本
工程においても、はんだ溶融に伴う封止直前までは、空
洞部と外部雰囲気とのガスの交流が容易に行われ、はん
だ溶融に伴い隙間が塞がり、かつ、基板2および蓋材7
がはんだ枠材5を介して接合されることで、気密封止さ
れることとなる。
Next, when the atmosphere inside the cavity after sealing is kept in a reduced pressure state according to the function of the electronic element 3, the solder is heated by raising the temperature to the melting point of the solder while keeping the inside of the furnace in a reduced pressure. Melt and seal. In addition, when the gas is sealed in the cavity according to the function of the electronic element 3, after the sealed gas is put in the furnace in a predetermined heating state and pressure setting in consideration of the pressure in the cavity after cooling. The sealing is performed by raising the temperature to the melting point of the solder. Also in this step, gas exchange between the cavity and the external atmosphere is easily performed until the sealing immediately following the melting of the solder, the gap is closed with the melting of the solder, and the substrate 2 and the lid member 7 are closed.
Are joined together via the solder frame material 5 to be hermetically sealed.

【0040】なお、以降の工程としては、上記のように
して製造された電子装置1を実装基板10の電子装置搭
載部に、ボンディング剤11により固着して搭載し、電
子装置1のパッド8と実装基板10のパッド12とをボ
ンディングワイヤ13により結線することにより、実装
されることとなる。
In the subsequent steps, the electronic device 1 manufactured as described above is fixedly mounted on the electronic device mounting portion of the mounting board 10 with the bonding agent 11, and the electronic device 1 and the pad 8 are mounted. Mounting is performed by connecting the pads 12 of the mounting substrate 10 with the bonding wires 13.

【0041】上記の本実施形態に係る電子装置の製造方
法によれば、基板2と蓋材7との間に、はんだ枠材5a
の形状に起因する隙間を設けることで、はんだ溶融によ
る封止の直前まで素子空洞内外のガスを交流させること
ができ、従来のように、封止の直前に蓋材7と基板2と
を重ね合わせるといった作業が必要なくなり、その作業
を実現させるための装置の機能が不要になる。また、予
備加熱の段階から基板1、はんだ枠材5、および蓋材7
を重ねても、基板2などに付着・吸着された水分、酸
素、有機ガス等を除外したり、封入すべきガスを空洞内
に送りこむことが容易になることから、所望の気密状態
を確保することができ、電子素子3の品質や歩留りを向
上させることができる。また、工程が容易になることか
ら、コストが低減され電子装置の価格を下げることがで
きる。
According to the method of manufacturing an electronic device according to this embodiment described above, the solder frame material 5a is provided between the substrate 2 and the lid material 7.
By providing a gap due to the shape of the above, the gas inside and outside the element cavity can be exchanged until just before sealing by melting the solder, and the lid member 7 and the substrate 2 are superposed immediately before sealing as in the conventional case. There is no need for work such as matching, and the function of the device for realizing that work is unnecessary. Also, from the preheating stage, the substrate 1, the solder frame material 5, and the lid material 7
Even if the layers are stacked, it becomes easy to remove the moisture, oxygen, organic gas, etc. attached / adsorbed to the substrate 2 or to send the gas to be enclosed into the cavity, so that the desired airtight state is secured. Therefore, the quality and yield of the electronic elements 3 can be improved. Further, since the process is facilitated, the cost can be reduced and the price of the electronic device can be reduced.

【0042】本発明の電子装置の製造方法は、上記の実
施形態の説明に限定されない。例えば、本実施形態で
は、基板2と蓋材7との接合をはんだ枠材5を介して行
う例について示したが、これに限られるものでなく、例
えば、はんだ枠材5の代わりに、厚みに差をもたせたシ
ート状の接着材を使用することで同様の機能を実現する
こともできる。この場合には、その後の封止工程におい
て、加熱によるシート状の接着材の変形が十分な必要が
あり、不足する場合には、封止工程において外部からの
蓋材7および基板2への加重が必要になる。
The method for manufacturing the electronic device of the present invention is not limited to the above description of the embodiment. For example, in the present embodiment, an example in which the substrate 2 and the lid member 7 are joined via the solder frame member 5 is shown, but the present invention is not limited to this, and for example, instead of the solder frame member 5, the thickness may be changed. It is also possible to realize the same function by using a sheet-shaped adhesive material having a difference between the two. In this case, it is necessary that the sheet-shaped adhesive material is sufficiently deformed by heating in the subsequent sealing step, and if the deformation is insufficient, external load is applied to the lid member 7 and the substrate 2 in the sealing step. Will be required.

【0043】また、本実施形態においては、はんだ枠材
5aに突起部や段差を設けることにより、はんだ枠材5
aを基板2と蓋材7との間に挟んだ際に、隙間を確保す
ることとしたが、これに限られるものでなく、例えば、
プレス成型や射出成型においてはんだ枠材5aに貫通孔
を形成することで、当該貫通孔を外部とのガス通路とす
ることもできる。
Further, in the present embodiment, the solder frame member 5a is provided with protrusions and steps.
Although a gap is secured when a is sandwiched between the substrate 2 and the lid member 7, the invention is not limited to this.
By forming a through hole in the solder frame material 5a in press molding or injection molding, the through hole can be used as a gas passage to the outside.

【0044】また、本実施形態においては、基板2に一
体形成された電子素子3を気密封止した電子装置につい
て示したが、これに限られるものでなく、近年のマルチ
チップモジュールのように、基板2に一体形成された電
子素子3の他にも、他の機能を実現するために、例え
ば、チップ状の他の電子素子等をも搭載し、これらの複
数の電子素子を気密封止するようにしてもよい。その
他、本発明の要旨を逸脱しない範囲で、種々の変更が可
能である。
Further, in the present embodiment, the electronic device in which the electronic element 3 integrally formed on the substrate 2 is hermetically sealed has been shown, but the present invention is not limited to this, and as in recent multi-chip modules, In addition to the electronic element 3 formed integrally on the substrate 2, in order to realize other functions, for example, another electronic element in the form of a chip is also mounted, and these electronic elements are hermetically sealed. You may do it. Besides, various modifications can be made without departing from the scope of the present invention.

【0045】[0045]

【発明の効果】本発明によれば、製造工程が容易で、か
つ、所望の気密状態を確保した電子装置を製造すること
ができる。
According to the present invention, it is possible to manufacture an electronic device which is easy to manufacture and has a desired airtight state.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1(a)は本実施形態に係る電子装置の製造
方法によって製造される電子装置の平面図、図1(b)
は図1(a)のA−A’線における断面図である。
1A is a plan view of an electronic device manufactured by a method of manufacturing an electronic device according to an embodiment, FIG.
2 is a sectional view taken along the line AA ′ of FIG.

【図2】本実施形態に係る電子装置の製造方法によって
製造される電子装置を実装基板に搭載後の断面図であ
る。
FIG. 2 is a cross-sectional view after mounting the electronic device manufactured by the method of manufacturing an electronic device according to the present embodiment on a mounting substrate.

【図3】本実施形態に係る電子装置の製造方法における
製造工程を示す断面図である。
FIG. 3 is a cross-sectional view showing a manufacturing process in the method for manufacturing the electronic device according to the present embodiment.

【図4】本実施形態に係る電子装置の製造方法に使用す
るはんだ枠材の形状の一例を示す斜視図である。
FIG. 4 is a perspective view showing an example of the shape of a solder frame material used in the method for manufacturing an electronic device according to the present embodiment.

【図5】本実施形態に係る電子装置の製造方法に使用す
るはんだ枠材の形状の他の例を示す斜視図である。
FIG. 5 is a perspective view showing another example of the shape of the solder frame material used in the method for manufacturing an electronic device according to the present embodiment.

【図6】本実施形態に係る電子装置の製造方法に使用す
るはんだ枠材の形状の他の例を示す斜視図である。
FIG. 6 is a perspective view showing another example of the shape of the solder frame material used in the method for manufacturing an electronic device according to the present embodiment.

【図7】本実施形態に係る電子装置の製造方法に使用す
るはんだ枠材の形状の他の例を示す斜視図である。
FIG. 7 is a perspective view showing another example of the shape of the solder frame material used in the method for manufacturing an electronic device according to the present embodiment.

【図8】本実施形態に係る電子装置の製造方法に使用す
るはんだ枠材の形状の他の例を示す斜視図である。
FIG. 8 is a perspective view showing another example of the shape of the solder frame material used in the method for manufacturing an electronic device according to the present embodiment.

【図9】本実施形態に係る電子装置の製造方法に使用す
るはんだ枠材の形状の他の例を示す斜視図である。
FIG. 9 is a perspective view showing another example of the shape of the solder frame material used in the method for manufacturing an electronic device according to the present embodiment.

【図10】本実施形態に係る電子装置の製造方法に使用
するはんだ枠材の形状の他の例を示す斜視図である。
FIG. 10 is a perspective view showing another example of the shape of the solder frame material used in the method for manufacturing an electronic device according to the present embodiment.

【図11】図11(a)は、本実施形態に係る電子装置
の製造方法に使用するはんだ枠材の形状の他の例を示す
斜視図であり、図11(b)は図11(a)のB−B’
線における断面図である。
11A is a perspective view showing another example of the shape of the solder frame material used in the method for manufacturing an electronic device according to the present embodiment, and FIG. ) BB '
It is sectional drawing in a line.

【符号の説明】[Explanation of symbols]

1…電子装置、2…基板、2a…素子形成面、3…電子
素子、4…接着層、5,5a…はんだ枠材、6…接着
層、7…蓋材、8…パッド、10…実装基板、11…ボ
ンディング剤、12…パッド、13…ボンディングワイ
ヤ。
DESCRIPTION OF SYMBOLS 1 ... Electronic device, 2 ... Substrate, 2a ... Element formation surface, 3 ... Electronic element, 4 ... Adhesive layer, 5,5a ... Solder frame material, 6 ... Adhesive layer, 7 ... Lid material, 8 ... Pad, 10 ... Mounting Substrate, 11 ... Bonding agent, 12 ... Pad, 13 ... Bonding wire.

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】基板に電子素子を形成する工程と、 前記基板の前記電子素子を囲み、かつ、外部雰囲気への
ガス通路を確保し得る形状の枠材を前記基板上に設置す
る工程と、 前記基板上に形成された前記電子素子との間に所定の空
間を確保した状態で、前記枠材上に蓋材を設置する工程
と、 前記基板の外部雰囲気を減圧して、前記ガス通路を介し
て前記所定の空間内のガスを除去する工程と、 前記枠材を溶融させて前記ガス通路を塞ぎ、前記基板上
の前記電子素子を前記所定の空間内に気密封止する工程
とを有する電子装置の製造方法。
1. A step of forming an electronic element on a substrate, and a step of providing a frame member surrounding the electronic element of the substrate and having a shape capable of ensuring a gas passage to an external atmosphere on the substrate, A step of installing a lid material on the frame material in a state where a predetermined space is secured between the electronic element formed on the substrate, and depressurizing an external atmosphere of the substrate to form the gas passage. A step of removing the gas in the predetermined space through the step of melting the frame material to close the gas passage, and hermetically sealing the electronic element on the substrate in the predetermined space. Electronic device manufacturing method.
【請求項2】前記枠材を前記基板上に設置する工程にお
いて、前記枠材と前記基板との接触部に前記ガス通路と
なる隙間が形成され得る形状の前記枠材を、前記基板上
に設置する請求項1記載の電子装置の製造方法。
2. In the step of installing the frame member on the substrate, the frame member having a shape capable of forming a gap serving as the gas passage at a contact portion between the frame member and the substrate is provided on the substrate. The method for manufacturing an electronic device according to claim 1, wherein the electronic device is installed.
【請求項3】前記枠材を前記基板上に設置する工程にお
いて、突起部が形成された枠材を前記基板上に設置する
請求項2記載の電子装置の製造方法。
3. The method of manufacturing an electronic device according to claim 2, wherein in the step of installing the frame member on the substrate, the frame member having a protrusion is installed on the substrate.
【請求項4】前記枠材を前記基板上に設置する工程にお
いて、肉厚差を有する枠材を前記基板上に設置する請求
項2記載の電子装置の製造方法。
4. The method of manufacturing an electronic device according to claim 2, wherein in the step of installing the frame member on the substrate, a frame member having a difference in wall thickness is installed on the substrate.
【請求項5】前記枠材を前記基板上に設置する工程にお
いて、平面方向において段差が形成された枠材を前記基
板上に設置する請求項2記載の電子装置の製造方法。
5. The method of manufacturing an electronic device according to claim 2, wherein in the step of installing the frame member on the substrate, a frame member having a step formed in a plane direction is installed on the substrate.
【請求項6】前記基板の外部雰囲気を減圧する工程にお
いて、前記枠材の融点を越えない範囲の加熱状態で外部
雰囲気を減圧する請求項1記載の電子装置の製造方法。
6. The method of manufacturing an electronic device according to claim 1, wherein, in the step of reducing the pressure of the outside atmosphere of the substrate, the pressure of the outside atmosphere is reduced in a heating state within a range not exceeding the melting point of the frame material.
【請求項7】前記所定の空間内のガスを除去する工程の
後、前記電子素子を前記所定の空間内に気密封止する工
程の前に、前記基板の外部雰囲気を所定の封入ガス雰囲
気にして、前記ガス通路を介して前記所定の空間内に封
入ガスを入れる工程をさらに有する請求項1記載の電子
装置の製造方法。
7. After the step of removing the gas in the predetermined space and before the step of hermetically sealing the electronic element in the predetermined space, the atmosphere outside the substrate is changed to a predetermined enclosed gas atmosphere. The method of manufacturing an electronic device according to claim 1, further comprising the step of introducing an enclosed gas into the predetermined space via the gas passage.
【請求項8】前記枠材を前記基板上に設置する工程の前
に、前記枠材との接触箇所における前記基板上に、前記
基板および前記枠材との接着を確保し得る接着層を形成
する工程をさらに有する請求項1記載の電子装置の製造
方法。
8. An adhesive layer capable of ensuring adhesion between the substrate and the frame material is formed on the substrate at a contact position with the frame material before the step of installing the frame material on the substrate. The method of manufacturing an electronic device according to claim 1, further comprising:
【請求項9】前記枠材上に蓋材を設置する工程の前に、
前記枠材との接触箇所における前記蓋材上に、前記蓋材
および前記枠材との接着を確保し得る接着層を形成する
工程をさらに有する請求項1記載の電子装置の製造方
法。
9. Before the step of installing a lid member on the frame member,
2. The method of manufacturing an electronic device according to claim 1, further comprising: forming an adhesive layer on the cover material at a contact point with the frame material, the adhesive layer ensuring adhesion between the cover material and the frame material.
JP2001322294A 2001-10-19 2001-10-19 Manufacturing method of electronic equipment Pending JP2003133452A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Publications (1)

Publication Number Publication Date
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Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005342803A (en) * 2004-05-31 2005-12-15 Sony Corp Mems element, its manufacturing method, optical mems element, optical modulator, glv device and laser display
JP2007048994A (en) * 2005-08-11 2007-02-22 Akita Denshi Systems:Kk Semiconductor device and its manufacturing method
JP2008294783A (en) * 2007-05-25 2008-12-04 Epson Toyocom Corp Piezoelectric vibrator and manufacturing method therefor
JP2013041970A (en) * 2011-08-15 2013-02-28 Seiko Epson Corp Sealing method of package, housing of electronic device, and cell
JP2014123942A (en) * 2012-11-21 2014-07-03 Ricoh Co Ltd Method for manufacturing alkali metal cell and method for manufacturing atomic oscillator
JP2015185794A (en) * 2014-03-26 2015-10-22 日本電気株式会社 Hermetically sealed package, infrared detector and method for manufacturing them

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005342803A (en) * 2004-05-31 2005-12-15 Sony Corp Mems element, its manufacturing method, optical mems element, optical modulator, glv device and laser display
JP2007048994A (en) * 2005-08-11 2007-02-22 Akita Denshi Systems:Kk Semiconductor device and its manufacturing method
JP2008294783A (en) * 2007-05-25 2008-12-04 Epson Toyocom Corp Piezoelectric vibrator and manufacturing method therefor
JP2013041970A (en) * 2011-08-15 2013-02-28 Seiko Epson Corp Sealing method of package, housing of electronic device, and cell
JP2014123942A (en) * 2012-11-21 2014-07-03 Ricoh Co Ltd Method for manufacturing alkali metal cell and method for manufacturing atomic oscillator
JP2015185794A (en) * 2014-03-26 2015-10-22 日本電気株式会社 Hermetically sealed package, infrared detector and method for manufacturing them

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