JP2003100808A - Electronic component and manufacturing method thereof, and circuit board packaging the same - Google Patents

Electronic component and manufacturing method thereof, and circuit board packaging the same

Info

Publication number
JP2003100808A
JP2003100808A JP2001296842A JP2001296842A JP2003100808A JP 2003100808 A JP2003100808 A JP 2003100808A JP 2001296842 A JP2001296842 A JP 2001296842A JP 2001296842 A JP2001296842 A JP 2001296842A JP 2003100808 A JP2003100808 A JP 2003100808A
Authority
JP
Japan
Prior art keywords
protective layer
semiconductor wafer
electronic component
resin
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001296842A
Other languages
Japanese (ja)
Inventor
Junji Oishi
純司 大石
Takeochi Nagai
健生智 永井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2001296842A priority Critical patent/JP2003100808A/en
Publication of JP2003100808A publication Critical patent/JP2003100808A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/274Manufacturing methods by blanket deposition of the material of the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73101Location prior to the connecting process on the same surface
    • H01L2224/73103Bump and layer connectors
    • H01L2224/73104Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

Abstract

PROBLEM TO BE SOLVED: To increase productivity to packaging onto a substrate regarding electronic components to be packaged onto the substrate. SOLUTION: The electronic component has an IC chip 9 that is formed in a plate shape, a connection electrode 8 that is provided at the one surface side, and a salient electrode 10 that is connected to the connection electrode 8 of the IC chip 9. In this case, with the formation surface of the connection electrode 8 of the IC chip 9, the tip of the salient electrode 10 is exposed for covering with a protection layer 11 made of resin.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明はICチップを有する
電子部品とその製造方法とその電子部品を実装した回路
基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component having an IC chip, a method of manufacturing the same, and a circuit board on which the electronic component is mounted.

【0002】[0002]

【従来の技術】従来のこの種電子部品は図11に示すよ
うに板状のICチップ1の接続電極に突起電極2を接続
した構成となっていた。
2. Description of the Related Art A conventional electronic component of this type has a structure in which a projecting electrode 2 is connected to a connecting electrode of a plate-shaped IC chip 1 as shown in FIG.

【0003】そして図12に示すごとくこの電子部品を
基板3上に実装する時には、突起電極2を基板3上の実
装電極4上にはんだ5を介して接続することにより行っ
ていた。
As shown in FIG. 12, when the electronic component is mounted on the substrate 3, the protruding electrode 2 is connected to the mounting electrode 4 on the substrate 3 via the solder 5.

【0004】[0004]

【発明が解決しようとする課題】図12に示すごとく基
板3上に電子部品を実装した後にICチップ1と基板3
間には樹脂が注入され、それを硬化させて保護層6を形
成していた。
As shown in FIG. 12, after mounting electronic components on the substrate 3, the IC chip 1 and the substrate 3 are mounted.
A resin was injected in the gap and was cured to form the protective layer 6.

【0005】つまり保護層6を形成することで突起電極
2と実装電極4およびICチップ1の接続電極との接続
強度を高めているものである。
That is, by forming the protective layer 6, the connection strength between the protruding electrode 2 and the mounting electrode 4 and the connection electrode of the IC chip 1 is increased.

【0006】しかしながらこの保護層6は各電子部品を
基板3に実装後個々に行わなければならず、しかも近年
の小型化された基板上の作業は大変で、生産性の低いも
のになるという問題があった。
However, the protective layer 6 must be individually mounted after mounting each electronic component on the board 3, and the work on the miniaturized board in recent years is difficult and the productivity is low. was there.

【0007】そこで本発明は生産性を高めることを目的
とするものである。
Therefore, the present invention aims to increase productivity.

【0008】[0008]

【課題を解決するための手段】そしてこの目的を達成す
るために本発明の請求項1の発明は、板状で少なくとも
その一面側に接続電極が設けられたICチップと、この
ICチップの前記接続電極に接続された突起電極とを備
え、前記ICチップの接続電極形成面は突起電極の先端
を露出させて樹脂製の保護層で覆った電子部品であっ
て、ICチップの接続電極と突起電極の接続部、および
突起電極の下部を樹脂製の保護層で覆うので、両部分の
強度が強くなり、しかも各電子部品ごとにあらかじめ突
起電極部等を保護する保護層が形成されているので、基
板実装後の保護層形成が不要で、生産性がきわめて高く
なる。
In order to achieve this object, the invention of claim 1 of the present invention is an IC chip having a plate-like shape and provided with a connection electrode on at least one surface side thereof, and the IC chip described above. A projection electrode connected to a connection electrode, the connection electrode forming surface of the IC chip is an electronic component in which the tip of the projection electrode is exposed and covered with a protective layer made of resin. Since the connection part of the electrode and the lower part of the protruding electrode are covered with a protective layer made of resin, the strength of both parts becomes stronger, and a protective layer for protecting the protruding electrode part etc. is formed in advance for each electronic component. Therefore, it is not necessary to form a protective layer after mounting on the board, and the productivity is extremely high.

【0009】次に請求項2の発明は、突起電極の先端を
保護層から突出させた請求項1に記載の電子部品であっ
て、突起電極の先端が保護層から突出しているので、単
に突起電極の先端が保護層から露出しただけのものに比
較するとその表出面積が広くなることから、この電子部
品を回路基板に実装する時にはこの突起電極と回路基板
の実装電極との接続強度を強くすることができる。
Next, the invention according to claim 2 is the electronic component according to claim 1, wherein the tip of the projection electrode is projected from the protective layer, and since the tip of the projection electrode is projected from the protective layer, the projection is simply formed. The exposed area is wider than that of the electrode whose tip is only exposed from the protective layer.Therefore, when mounting this electronic component on a circuit board, increase the connection strength between this protruding electrode and the mounting electrode on the circuit board. can do.

【0010】次に請求項3の発明は、ICチップはシリ
コン基板上に回路パターンを設けた構成とし、保護層を
形成する樹脂には酸化ケイ素のフィラを混入させた請求
項1に記載の電子部品であって、樹脂に酸化ケイ素のフ
ィラを混入させることで、シリコン基板との熱膨張係数
が近くなり、よって熱的負荷が加わった際の突起電極と
ICチップの接続電極との接続部に対する損傷や、半導
体ウェハからの保護層の剥離が起きにくくすることがで
きる。
Next, the invention according to claim 3 is characterized in that the IC chip has a circuit pattern provided on a silicon substrate, and a filler of silicon oxide is mixed in the resin forming the protective layer. By adding a filler of silicon oxide to the resin, the coefficient of thermal expansion of the resin becomes close to that of the silicon substrate, and therefore the connection between the protruding electrode and the connection electrode of the IC chip when a thermal load is applied It is possible to prevent damage and peeling of the protective layer from the semiconductor wafer.

【0011】次に請求項4の発明は、保護層の外周の、
シリコン基板の反対側部分は、シリコン基板側から内方
に向かう傾斜を設けた請求項3に記載の電子部品であっ
て、保護層の外周部が欠けにくくなり、よってICチッ
プを回路基板に実装する際に保護層の脱落欠けらによる
実装不良が生じなくなる。
Next, the invention of claim 4 is such that:
The electronic component according to claim 3, wherein the opposite side portion of the silicon substrate is provided with an inward slope from the silicon substrate side, and the outer peripheral portion of the protective layer is less likely to be chipped, so that the IC chip is mounted on the circuit board. In doing so, the mounting failure due to the lacking of the protective layer does not occur.

【0012】次に請求項5の発明は、半導体ウェハに設
けた複数の接続電極にそれぞれ突起電極を接続し、次に
この半導体ウェハの接続電極形成面に樹脂を突起電極の
先端より下位まで供給し、その後この樹脂を硬化させて
突起電極の先端だけを突出させた保護層を形成し、次に
半導体ウェハを切断してICチップを形成する電子部品
の製造方法であって、各ICチップの接続電極と突起電
極および突起電極の下部を保護層で覆うので、これらの
部分の強度が強くなり、しかも各ICチップの保護層は
半導体ウェハの状態で一度が形成できるので、その生産
性はきわめて高くなる。
Next, a fifth aspect of the invention is to connect a plurality of connection electrodes to a plurality of connection electrodes provided on a semiconductor wafer, and then supply a resin to the connection electrode formation surface of the semiconductor wafer to a position lower than the tip of the projection electrode. Then, the resin is cured to form a protective layer in which only the tips of the protruding electrodes are projected, and then the semiconductor wafer is cut to form an IC chip. Since the connection electrode, the protruding electrode, and the lower portion of the protruding electrode are covered with the protective layer, the strength of these portions is increased, and moreover, the protective layer of each IC chip can be formed once in the state of the semiconductor wafer, so that the productivity is extremely high. Get higher

【0013】また突起電極の先端は樹脂供給時から覆わ
ず露出させているので、後で保護層を削って突起電極の
先端を露出させる工程が不要となり、生産性が高くな
る。
Further, since the tip of the bump electrode is exposed without being covered from the time of supplying the resin, a step of removing the tip of the bump electrode by exposing the tip of the protective layer later becomes unnecessary, and the productivity is increased.

【0014】次に請求項6の発明は、半導体ウェハはシ
リコン基板上に回路パターンを設けた構成とし、保護層
を形成する樹脂には酸化ケイ素のフィラを混入させた請
求項5に記載の電子部品の製造方法であって、樹脂に酸
化ケイ素のフィラを混入させることで、シリコン基板と
の熱膨張係数が近くなり、よって熱的負荷が加わった際
の突起電極とICチップの接続電極との接続部に対する
損傷や、半導体ウェハからの保護層の剥離を起きにくく
することができる。
Next, an invention according to claim 6 is characterized in that the semiconductor wafer has a circuit pattern provided on a silicon substrate, and a filler of silicon oxide is mixed in the resin forming the protective layer. In the method of manufacturing a component, by mixing a filler of silicon oxide into a resin, the coefficient of thermal expansion becomes close to that of the silicon substrate, so that the protruding electrode and the connection electrode of the IC chip when a thermal load is applied are formed. It is possible to prevent damage to the connection portion and peeling of the protective layer from the semiconductor wafer.

【0015】次に請求項7の発明は、樹脂の供給前に半
導体ウェハの樹脂供給面をプラズマによりクリーニング
する請求項5に記載の電子部品の製造方法であって、樹
脂供給面をクリーニングすることにより樹脂の流れがス
ムーズになり、この結果として半導体ウェハ上に略均一
な層厚の保護層を形成することができる。
Next, the invention of claim 7 is a method of manufacturing an electronic component according to claim 5, wherein the resin supply surface of the semiconductor wafer is cleaned by plasma before the resin supply. As a result, the resin flow becomes smooth, and as a result, a protective layer having a substantially uniform layer thickness can be formed on the semiconductor wafer.

【0016】次に請求項8の発明は、半導体ウェハへの
樹脂供給後樹脂を加熱する請求項7に記載の電子部品の
製造方法であって、樹脂を加熱することにより供給樹脂
が軟化することで半導体ウェハ上における樹脂の層厚が
均一化しやすくなる。
Next, the invention of claim 8 is the method of manufacturing an electronic component according to claim 7, wherein the resin is heated after the resin is supplied to the semiconductor wafer, wherein the supplied resin is softened by heating the resin. Thus, it becomes easy to make the resin layer thickness uniform on the semiconductor wafer.

【0017】次に請求項9の発明は、樹脂の加熱後半導
体ウェハを回転させる請求項8に記載の電子部品の製造
方法であって、樹脂を加熱し軟化させた後に半導体ウェ
ハを回転させることで、軟化した樹脂を広げてその層厚
を均一化しやすくなる。
Next, the invention of claim 9 is the method of manufacturing an electronic component according to claim 8, wherein the semiconductor wafer is rotated after heating the resin, wherein the semiconductor wafer is rotated after the resin is heated and softened. Then, it becomes easy to spread the softened resin to make the layer thickness uniform.

【0018】次に請求項10の発明は、樹脂の加熱後半
導体ウェハを振動させる請求項8に記載の電子部品の製
造方法であって、樹脂を加熱し軟化させた後に半導体ウ
ェハを振動させることで、軟化した樹脂を広げてその層
厚を均一化しやすくなる。
Next, the invention of claim 10 is a method of manufacturing an electronic component according to claim 8, wherein the semiconductor wafer is vibrated after the resin is heated, wherein the semiconductor wafer is vibrated after the resin is heated and softened. Then, it becomes easy to spread the softened resin to make the layer thickness uniform.

【0019】次に請求項11の発明は、樹脂はエポキシ
系とした請求項9、または10に記載の電子部品の製造
方法であって、エポキシ系の樹脂は加熱により温度を上
昇させれば軟化するがそれまでの低温加熱時には先ず軟
化するので、この状態で広げて均一な層厚とし、その後
さらに温度上昇させればこの均一層厚状態で硬化して保
護層を形成することができ、生産性の良いものとなる。
Next, the invention of claim 11 is the method of manufacturing an electronic component according to claim 9 or 10, wherein the resin is an epoxy resin, and the epoxy resin is softened by increasing the temperature by heating. However, when it is heated up to a low temperature until then, it softens first, so it can be spread in this state to give a uniform layer thickness, and if the temperature is further raised, it can be cured in this uniform layer thickness state to form a protective layer. It becomes a good one.

【0020】次に請求項12の発明は、保護層を透明体
とし、半導体ウェハ上には切断マークを設けた請求項5
に記載の電子部品の製造方法であって、保護層が透明体
なので半導体ウェハ上の切断マークが透視でき、したが
ってICチップへの切断が容易に行えるものとなる。
Next, the invention of claim 12 is characterized in that the protective layer is made of a transparent material and a cutting mark is provided on the semiconductor wafer.
In the method of manufacturing an electronic component described in (1) above, since the protective layer is a transparent body, the cutting mark on the semiconductor wafer can be seen through, and thus the cutting into the IC chip can be easily performed.

【0021】次に請求項13の発明は、半導体ウェハ
を、基台上に、この半導体ウェハを下面側、保護層を上
面側として設置し、保護層側から切断を行う請求項12
に記載の電子部品の製造方法であって、半導体ウェハを
下面側として基台上に設置したことにより切断時におけ
る平面度が維持しやすくなり、よってICチップへの切
断が正確に行いやすくなる。
Next, the invention of claim 13 is characterized in that a semiconductor wafer is placed on a base with the semiconductor wafer as the lower surface side and the protective layer as the upper surface side, and the cutting is performed from the protective layer side.
In the method of manufacturing an electronic component described in (3), since the semiconductor wafer is installed on the base as the lower surface side, it is easy to maintain the flatness at the time of cutting, and thus it is easy to accurately cut into IC chips.

【0022】次に請求項14の発明は、保護層の切断と
半導体ウェハの切断はそれぞれ別方向から切断刃を変え
て行う請求項13に記載の電子部品の製造方法であっ
て、保護層と半導体ウェハは硬度が異なるので、それぞ
れ別方向から切断刃を変えて行う方がスムーズな切断、
および各切断刃の損傷も起きにくくなる。
Next, the invention of claim 14 is the method of manufacturing an electronic component according to claim 13, wherein the cutting of the protective layer and the cutting of the semiconductor wafer are performed by changing the cutting blades from different directions. Since semiconductor wafers have different hardness, it is easier to cut by changing the cutting blade from different directions.
Also, damage to each cutting blade is less likely to occur.

【0023】次に請求項15の発明は、保護層を先ず切
断し、次に反転させて半導体ウェハを切断することと
し、前記保護層の切断時には半導体ウェハの外周部に切
欠マークを形成する請求項14に記載の電子部品の製造
方法であって、保護層が透明なので半導体ウェハ上の切
断マークを確認して保護層を切断することができ、また
反転しての半導体ウェハの切断も保護層切断時に半導体
ウェハ外周の不要部に設けていた切欠マークを確認して
適切な切断が行えることとなる。
Next, in the invention of claim 15, the protective layer is first cut and then inverted to cut the semiconductor wafer, and when the protective layer is cut, a notch mark is formed on the outer peripheral portion of the semiconductor wafer. Item 15. The method for manufacturing an electronic component according to Item 14, wherein the protective layer is transparent, so that the protective layer can be cut by checking the cut mark on the semiconductor wafer, and the protective layer can also be cut when the semiconductor wafer is inverted. Appropriate cutting can be performed by checking the notch marks provided in unnecessary portions on the outer periphery of the semiconductor wafer during cutting.

【0024】次に請求項16の発明は、保護層の切断刃
の幅を、半導体ウェハの切断刃の幅よりも厚くした請求
項12〜15のいずれか一つに記載の電子部品の製造方
法であって、保護層の切断刃の幅を厚くすることによ
り、保護層の外周には半導体ウェハ側から上方になるに
したがって内方に向かう傾斜が形成されることとなり、
これにより保護層の外周部が欠けにくくなり、よってI
Cチップを回路基板に実装する際に保護層の脱落欠けら
による実装不良が生じなくなる。
Next, a sixteenth aspect of the present invention is a method for manufacturing an electronic component according to any one of the twelfth to fifteenth aspects, wherein the width of the cutting blade of the protective layer is thicker than the width of the cutting blade of the semiconductor wafer. That is, by increasing the width of the cutting blade of the protective layer, the outer periphery of the protective layer will be inclined toward the inside as it goes upward from the semiconductor wafer side,
As a result, the outer peripheral portion of the protective layer is less likely to be chipped, and
When the C chip is mounted on the circuit board, the mounting failure due to the chipping of the protective layer does not occur.

【0025】次に請求項17の発明は、半導体ウェハに
設けた複数の接続電極にそれぞれ突起電極を接続し、次
にこの半導体ウェハの接続電極形成面に樹脂を突起電極
の先端より上位まで供給し、その後この樹脂を硬化させ
て保護層を形成し、次にこの保護層を削って突起電極の
先端を露出させ、その後前記半導体ウェハを切断してI
Cチップを形成する電子部品の製造方法であって、各I
Cチップの接続電極と突起電極および突起電極の下部を
保護層で覆うので、これらの部分の強度が強くなり、し
かも各ICチップの保護層は半導体ウェハの状態で一度
が形成できるので、その生産性はきわめて高くなる。
Next, in the invention of claim 17, the plurality of connection electrodes provided on the semiconductor wafer are respectively connected with the projection electrodes, and then the resin is supplied to the connection electrode formation surface of the semiconductor wafer from the tip of the projection electrodes to a higher level. Then, the resin is cured to form a protective layer, the protective layer is then shaved to expose the tips of the protruding electrodes, and then the semiconductor wafer is cut to form I.
A method of manufacturing an electronic component for forming a C chip, comprising:
Since the connection electrode of the C chip, the protruding electrode, and the lower part of the protruding electrode are covered with the protective layer, the strength of these parts is increased, and the protective layer of each IC chip can be formed once in the state of the semiconductor wafer. Sex is extremely high.

【0026】次に請求項18の発明は、保護層を研磨面
に当接させて削る請求項17に記載の電子部品の製造方
法であって、半導体ウェハの保護層を研磨面に当接させ
て削ることとすれば、この工程により露出した突起電極
の露出面には研磨にもとづく凹凸面が形成され、これに
より回路基板の実装電極との接続強度を高めることがで
きる。
Next, an eighteenth aspect of the present invention is a method for manufacturing an electronic component according to the seventeenth aspect, wherein the protective layer is brought into contact with the polishing surface to be ground, and the protective layer of the semiconductor wafer is brought into contact with the polishing surface. If it is shaved, an uneven surface due to polishing is formed on the exposed surface of the protruding electrode exposed by this step, and thereby the connection strength with the mounting electrode of the circuit board can be increased.

【0027】次に請求項19の発明は、半導体ウェハは
シリコン基板上に回路パターンを設けた構成とし、保護
層を形成する樹脂には酸化ケイ素のフィラを混入させた
請求項18に記載の電子部品の製造方法であって、樹脂
に酸化ケイ素のフィラを混入させることで、シリコン基
板との熱膨張係数が近くなり、よって熱的負荷が加わっ
た際の突起電極とICチップの接続電極との接続部に対
する損傷や、半導体ウェハからの保護層の剥離を起きに
くくすることができる。
Next, an invention according to claim 19 is characterized in that a semiconductor wafer has a circuit pattern provided on a silicon substrate, and a filler of silicon oxide is mixed in a resin forming a protective layer. In the method of manufacturing a component, by mixing a filler of silicon oxide into a resin, the coefficient of thermal expansion becomes close to that of the silicon substrate, so that the protruding electrode and the connection electrode of the IC chip when a thermal load is applied are formed. It is possible to prevent damage to the connection portion and peeling of the protective layer from the semiconductor wafer.

【0028】次に請求項20の発明は、樹脂の供給前に
半導体ウェハの樹脂供給面をプラズマによりクリーニン
グする請求項17に記載の電子部品の製造方法であっ
て、樹脂供給面をクリーニングすることにより樹脂の流
れがスムーズになり、この結果として半導体ウェハ上に
略均一な層厚の保護層を形成することができる。
Next, the invention of claim 20 is the method of manufacturing an electronic component according to claim 17, wherein the resin supply surface of the semiconductor wafer is cleaned with plasma before the resin supply. As a result, the resin flow becomes smooth, and as a result, a protective layer having a substantially uniform layer thickness can be formed on the semiconductor wafer.

【0029】次に請求項21の発明は、半導体ウェハへ
の樹脂供給後樹脂を加熱する請求項20に記載の電子部
品の製造方法であって、樹脂を加熱することにより供給
樹脂が軟化することで半導体ウェハ上における樹脂の層
厚が均一化しやすくなる。
Next, the invention of claim 21 is the method of manufacturing an electronic component according to claim 20, wherein the resin is heated after the resin is supplied to the semiconductor wafer, wherein the supplied resin is softened by heating the resin. Thus, it becomes easy to make the resin layer thickness uniform on the semiconductor wafer.

【0030】次に請求項22の発明は、樹脂の加熱後半
導体ウェハを回転させる請求項21に記載の電子部品の
製造方法であって、樹脂を加熱し軟化させた後に半導体
ウェハを回転させることで、軟化した樹脂を広げてその
層厚を均一化しやすくなる。
Next, the invention of claim 22 is the method of manufacturing an electronic component according to claim 21, wherein the semiconductor wafer is rotated after heating the resin, wherein the semiconductor wafer is rotated after the resin is heated and softened. Then, it becomes easy to spread the softened resin to make the layer thickness uniform.

【0031】次に請求項23の発明は、樹脂の加熱後半
導体ウェハを振動させる請求項21に記載の電子部品の
製造方法であって、樹脂を加熱し軟化させた後に半導体
ウェハを振動させることで、軟化した樹脂を広げてその
層厚を均一化しやすくなる。
Next, the invention of claim 23 is the method of manufacturing an electronic component according to claim 21, wherein the semiconductor wafer is vibrated after the resin is heated, wherein the semiconductor wafer is vibrated after the resin is heated and softened. Then, it becomes easy to spread the softened resin to make the layer thickness uniform.

【0032】次に請求項24の発明は、樹脂はエポキシ
系とした請求項22、または23に記載の電子部品の製
造方法であって、エポキシ系の樹脂は加熱により温度を
上昇させれば軟化するがそれまでの低温加熱時には先ず
軟化するので、この状態で広げて均一な層厚とし、その
後さらに温度上昇させればこの均一層厚状態で硬化して
保護層を形成することができ、生産性の良いものとな
る。
Next, the invention of claim 24 is the method for producing an electronic component according to claim 22 or 23, wherein the resin is an epoxy resin, and the epoxy resin is softened by increasing the temperature by heating. However, when it is heated up to a low temperature until then, it softens first, so it can be spread in this state to give a uniform layer thickness, and if the temperature is further raised, it can be cured in this uniform layer thickness state to form a protective layer. It becomes a good one.

【0033】次に請求項25の発明は、保護層を透明体
とし、半導体ウェハ上には切断マークを設けた請求項1
7に記載の電子部品の製造方法であって、保護層が透明
体なので半導体ウェハ上の切断マークが透視でき、した
がってICチップへの切断が容易に行えるものとなる。
Next, the invention of claim 25 is characterized in that the protective layer is made of a transparent material and a cutting mark is provided on the semiconductor wafer.
In the method of manufacturing an electronic component according to Item 7, since the protective layer is a transparent body, the cutting mark on the semiconductor wafer can be seen through, and thus the cutting into the IC chip can be easily performed.

【0034】次に請求項26の発明は、半導体ウェハ
を、基台上に、この半導体ウェハを下面側、保護層を上
面側として設置し、保護層側から切断を行う請求項25
に記載の電子部品の製造方法であって、半導体ウェハを
下面側として基台上に設置したことにより切断時におけ
る平面度が維持しやすくなり、よってICチップへの切
断が正確に行いやすくなる。
In a twenty-sixth aspect of the present invention, a semiconductor wafer is placed on a base with the semiconductor wafer as the lower surface side and the protective layer as the upper surface side, and cutting is performed from the protective layer side.
In the method of manufacturing an electronic component described in (3), since the semiconductor wafer is installed on the base as the lower surface side, it is easy to maintain the flatness at the time of cutting, and thus it is easy to accurately cut into IC chips.

【0035】次に請求項27の発明は、保護層の切断と
半導体ウェハの切断はそれぞれ別方向から切断刃を変え
て行う請求項26に記載の電子部品の製造方法であっ
て、保護層と半導体ウェハは硬度が異なるので、それぞ
れ別方向から切断刃を変えて行う方がスムーズな切断、
および各切断刃の損傷も起きにくくなる。
A thirty-seventh aspect of the present invention is the method of manufacturing an electronic component according to the twenty-sixth aspect, wherein the cutting of the protective layer and the cutting of the semiconductor wafer are performed by changing cutting blades from different directions. Since semiconductor wafers have different hardness, it is easier to cut by changing the cutting blade from different directions.
Also, damage to each cutting blade is less likely to occur.

【0036】次に請求項28の発明は、保護層を先ず切
断し、次に反転させて半導体ウェハを切断することと
し、前記保護層の切断時には半導体ウェハの外周部に切
欠マークを形成する請求項27に記載の電子部品の製造
方法であって、保護層が透明なので半導体ウェハ上の切
断マークを確認して保護層を切断することができ、また
反転しての半導体ウェハの切断も保護層切断時に半導体
ウェハ外周の不要部に設けていた切欠マークを確認して
適切な切断が行えることとなる。
In a twenty-eighth aspect of the present invention, the protective layer is first cut and then inverted to cut the semiconductor wafer, and a cut mark is formed on the outer peripheral portion of the semiconductor wafer when the protective layer is cut. Item 28. The method of manufacturing an electronic component according to Item 27, wherein the protective layer is transparent, so that the protective layer can be cut by confirming a cutting mark on the semiconductor wafer, and the semiconductor layer can be cut upside down when the protective layer is cut. Appropriate cutting can be performed by checking the notch marks provided in unnecessary portions on the outer periphery of the semiconductor wafer during cutting.

【0037】次に請求項29の発明は、保護層の切断刃
の幅を、半導体ウェハの切断刃の幅よりも厚くした請求
項25〜28のいずれか一つに記載の電子部品の製造方
法であって、保護層の切断刃の幅を厚くすることによ
り、保護層の外周には半導体ウェハ側から上方になるに
したがって内方に向かう傾斜が形成されることとなり、
これにより保護層の外周部が欠けにくくなり、よってI
Cチップを回路基板に実装する際に保護層の脱落欠けら
による実装不良が生じなくなる。
Next, the invention of claim 29 is a method of manufacturing an electronic component according to any one of claims 25 to 28, wherein the width of the cutting blade of the protective layer is thicker than the width of the cutting blade of the semiconductor wafer. That is, by increasing the width of the cutting blade of the protective layer, the outer periphery of the protective layer will be inclined toward the inside as it goes upward from the semiconductor wafer side,
As a result, the outer peripheral portion of the protective layer is less likely to be chipped, and
When the C chip is mounted on the circuit board, the mounting failure due to the chipping of the protective layer does not occur.

【0038】次に請求項30の発明は、表面に実装電極
が設けられた基板と、この基板の実装電極上にその突起
電極を接続した電子部品とを備え、前記電子部品は、板
状で少なくともその一面側に接続電極が設けられたIC
チップと、このICチップの前記接続電極に接続された
突起電極とを備え、前記ICチップの接続電極形成面は
突起電極の先端を露出させて樹脂製の保護層で覆った構
成とした回路基板であって、電子部品を構成するICチ
ップの接続電極と突起電極の接続部、および突起電極の
下部を樹脂製の保護層であらかじめ覆っているので、両
部分の強度が強く、よって基板への実装時や実装後にI
Cチップの接続電極から突起電極から外れたりすること
等が起きることがない。
[0038] Next, the invention of claim 30 is provided with a substrate having a mounting electrode provided on the surface thereof, and an electronic component in which the projecting electrode is connected to the mounting electrode of the substrate, wherein the electronic component is a plate. An IC provided with a connection electrode on at least one surface thereof
A circuit board having a chip and a projection electrode connected to the connection electrode of the IC chip, and a connection electrode formation surface of the IC chip having a tip of the projection electrode exposed and covered with a resin protective layer. In addition, since the connection portion between the connection electrode of the IC chip and the protruding electrode that constitutes the electronic component and the lower portion of the protruding electrode are covered with a protective layer made of resin in advance, the strength of both portions is strong, and therefore the substrate I during or after mounting
It does not occur that the connecting electrode of the C chip is disengaged from the protruding electrode.

【0039】次に請求項31の発明は、突起電極の先端
を保護層から突出させた請求項30に記載の回路基板で
あって、突起電極の先端が保護層から突出しているの
で、単に突起電極の先端が保護層から露出しただけのも
のに比較するとその表出面積が広くなることから、この
電子部品を回路基板に実装する時にはこの突起電極と回
路基板の実装電極との接続強度を強くすることができ
る。
A thirty-first aspect of the present invention is the circuit board according to the thirtieth aspect, wherein the tip of the protruding electrode is projected from the protective layer. Since the tip of the protruding electrode is projected from the protective layer, the protrusion is simply formed. The exposed area is wider than that of the electrode whose tip is only exposed from the protective layer.Therefore, when mounting this electronic component on a circuit board, increase the connection strength between this protruding electrode and the mounting electrode on the circuit board. can do.

【0040】次に請求項32の発明は、ICチップはシ
リコン基板上に回路パターンを設けた構成とし、保護層
を形成する樹脂には酸化ケイ素のフィラを混入させた請
求項30に記載の回路基板であって、樹脂に酸化ケイ素
のフィラを混入させることで、シリコン基板との熱膨張
係数が近くなり、よって基板への実装時や実装後に熱的
負荷が加わった際の突起電極とICチップの接続電極と
の接続部に対する損傷や、半導体ウェハからの保護層の
剥離を起きにくくすることができる。
A thirty-second aspect of the present invention is a circuit according to the thirty-third aspect, wherein the IC chip has a circuit pattern provided on a silicon substrate, and a filler of silicon oxide is mixed in the resin forming the protective layer. By mixing the filler of silicon oxide into the resin, the thermal expansion coefficient of the substrate becomes close to that of the silicon substrate, so that the protruding electrode and the IC chip when mounted on the substrate or when a thermal load is applied after mounting. It is possible to prevent the damage to the connection part with the connection electrode and the peeling of the protective layer from the semiconductor wafer.

【0041】次に請求項33の発明は、保護層の外周
の、シリコン基板の反対側部分は、シリコン基板側から
内方に向かう傾斜を設けた請求項32に記載の回路基板
であって、保護層の外周部が欠けにくくなり、よってI
Cチップを回路基板に実装する際に保護層の脱落欠けら
による実装不良が生じなくなる。
A thirty-third aspect of the present invention is the circuit board according to the thirty-second aspect, wherein a portion of the outer periphery of the protective layer on the opposite side of the silicon substrate is provided with an inward slope from the silicon substrate side. The outer peripheral portion of the protective layer is less likely to be chipped, and thus I
When the C chip is mounted on the circuit board, the mounting failure due to the chipping of the protective layer does not occur.

【0042】以下本発明の一実施形態を添付図面を用い
て説明する。
An embodiment of the present invention will be described below with reference to the accompanying drawings.

【0043】図1、図2に示す電子部品7は、板状で少
なくともその一面側に複数の接続電極8が設けられたI
Cチップ9と、このICチップ9の前記接続電極8にそ
れぞれ接続された金、またははんだ製の突起電極10と
を備え、前記ICチップ9の接続電極8形成面は突起電
極10の先端を露出させた状態で樹脂製の保護層11で
覆っている。
The electronic component 7 shown in FIGS. 1 and 2 is plate-shaped and is provided with a plurality of connection electrodes 8 on at least one side thereof.
The IC chip 9 is provided with a projection electrode 10 made of gold or solder, which is connected to the connection electrode 8 of the IC chip 9, and the connection electrode 8 formation surface of the IC chip 9 exposes the tip of the projection electrode 10. In this state, it is covered with a protective layer 11 made of resin.

【0044】そしてこの様にICチップ9の接続電極8
と突起電極10の接続部、および突起電極10の下部
(接続電極8側)を樹脂製の保護層11で覆えば、両部
分の強度が強くなる。
Then, in this way, the connection electrodes 8 of the IC chip 9 are
By covering the connecting portion of the protruding electrode 10 and the lower portion of the protruding electrode 10 (on the side of the connecting electrode 8) with the protective layer 11 made of resin, the strength of both portions becomes stronger.

【0045】一方基板12上には図2のごとく複数の実
装電極13が設けられており、この実装電極13上には
んだ14を介して電子部品7の突起電極10の露出部が
図3のごとく接続される。
On the other hand, a plurality of mounting electrodes 13 are provided on the substrate 12 as shown in FIG. 2, and the exposed portions of the protruding electrodes 10 of the electronic component 7 are exposed on the mounting electrodes 13 via the solder 14 as shown in FIG. Connected.

【0046】この様にして電子部品7は図4に示すよう
に基板12上に複数個実装され、他の電子部品15とと
もに機能回路を構成している。
In this way, a plurality of electronic components 7 are mounted on the substrate 12 as shown in FIG. 4, and form a functional circuit together with other electronic components 15.

【0047】この図4に示す各電子部品7は図1〜図3
のごとくあらかじめ突起電極10部等を保護する保護層
11が形成されているので、基板12への実装後に従来
の図12のごとく保護層6を形成することが不要で、生
産性がきわめて高くなる。
Each electronic component 7 shown in FIG. 4 is shown in FIGS.
Since the protective layer 11 for protecting the protruding electrodes 10 and the like is formed in advance, it is not necessary to form the protective layer 6 as shown in FIG. 12 of the related art after mounting on the substrate 12, resulting in extremely high productivity. .

【0048】以下電子部品7の製造方法について説明す
る。先ず図5に示すように、円板状の半導体ウェハ16
に設けた複数の接続電極(図2の8)にそれぞれ突起電
極10を接続し、次にこの半導体ウェハ16の接続電極
形成面に樹脂を図6のごとく突起電極10の先端より下
位まで供給し、その後この樹脂を硬化させて突起電極1
0の先端だけを突出させた保護層11を形成し、次に半
導体ウェハ16を図8の切断線17に沿って切断し、図
1に示す個々の電子部品7を製造する。
The method of manufacturing the electronic component 7 will be described below. First, as shown in FIG. 5, a disk-shaped semiconductor wafer 16
The protruding electrodes 10 are respectively connected to the plurality of connecting electrodes (8 in FIG. 2) provided on the semiconductor wafer 16, and then the resin is supplied to the connecting electrode forming surface of the semiconductor wafer 16 to a position lower than the tip of the protruding electrodes 10 as shown in FIG. Then, the resin is cured and the protruding electrode 1
A protective layer 11 is formed by protruding only the tip of 0, and then the semiconductor wafer 16 is cut along a cutting line 17 in FIG. 8 to manufacture the individual electronic components 7 shown in FIG.

【0049】この様にして、ICチップ9の接続電極8
と突起電極10および突起電極10の下部(接続電極8
側)が保護層11で覆われているので、これらの部分の
強度が強くなり、しかも各ICチップ9の保護層11は
半導体ウェハ16の状態で一度が形成できるので、その
生産性はきわめて高くなる。
In this way, the connection electrodes 8 of the IC chip 9 are
And the protruding electrode 10 and the lower part of the protruding electrode 10 (the connection electrode 8
Since the side) is covered with the protective layer 11, the strength of these portions is increased, and since the protective layer 11 of each IC chip 9 can be formed once in the state of the semiconductor wafer 16, its productivity is extremely high. Become.

【0050】また突起電極10の先端は樹脂供給時から
覆わず露出させているので、後で保護層11を削って突
起電極10の先端を露出させる工程が不要となり、生産
性が高くなる。
Further, since the tip of the bump electrode 10 is exposed without being covered since the resin is supplied, the step of exposing the tip of the bump electrode 10 by scraping the protective layer 11 later is not required, and the productivity is increased.

【0051】また図6のごとく突起電極10の先端を保
護層11から突出させているので、単に突起電極10の
先端が保護層11から露出しただけのものに比較すると
その表出面積が広くなることから、この電子部品7を基
板12に実装する時にはこの突起電極10と基板12の
実装電極13との接続強度を強くすることができる。
Further, as shown in FIG. 6, since the tip of the bump electrode 10 is projected from the protective layer 11, the exposed area is wider than that of the tip of the bump electrode 10 which is simply exposed from the protective layer 11. Therefore, when mounting the electronic component 7 on the substrate 12, the connection strength between the protruding electrode 10 and the mounting electrode 13 of the substrate 12 can be increased.

【0052】上記ICチップ9はシリコン基板上に回路
パターンを設けた構成とし、保護層11を形成する樹脂
には酸化ケイ素のフィラを混入させている。つまり、樹
脂に酸化ケイ素のフィラを混入させることで、シリコン
基板との熱膨張係数が近くなり、よって熱的負荷が加わ
った際の突起電極10とICチップ9の接続電極8との
接続部に対する損傷や、半導体ウェハ16からの保護層
11の剥離が起きにくくなる。
The IC chip 9 has a structure in which a circuit pattern is provided on a silicon substrate, and a filler of silicon oxide is mixed in the resin forming the protective layer 11. That is, by mixing the filler of silicon oxide into the resin, the thermal expansion coefficient of the resin becomes close to that of the silicon substrate, so that the connection between the protruding electrode 10 and the connection electrode 8 of the IC chip 9 when a thermal load is applied. Damage and peeling of the protective layer 11 from the semiconductor wafer 16 are less likely to occur.

【0053】次にこの樹脂を、突起電極10を接続済の
半導体ウェハ16上に供給する工程について詳述する。
Next, the step of supplying this resin onto the semiconductor wafer 16 to which the protruding electrodes 10 have been connected will be described in detail.

【0054】この場合先ず樹脂の供給前に半導体ウェハ
16の樹脂供給面(図5の上面側)をプラズマによりク
リーニングする。この様に樹脂供給面をクリーニングす
ることにより、上記フィラ混入をした樹脂の流れがスム
ーズになり、この結果として半導体ウェハ16上に略均
一な層厚の保護層11を形成することができるようにな
るからである。
In this case, first, the resin supply surface (upper surface side in FIG. 5) of the semiconductor wafer 16 is cleaned with plasma before the resin is supplied. By cleaning the resin supply surface in this way, the flow of the resin mixed with the filler becomes smooth, and as a result, the protective layer 11 having a substantially uniform layer thickness can be formed on the semiconductor wafer 16. Because it will be.

【0055】次にこの半導体ウェハ16への樹脂供給
後、加熱手段(図示せず)により樹脂を加熱する。この
様に樹脂を加熱することにより供給樹脂が軟化し半導体
ウェハ16上における樹脂の層厚が均一化しやすくな
る。
Next, after the resin is supplied to the semiconductor wafer 16, the resin is heated by a heating means (not shown). By heating the resin in this manner, the supplied resin is softened, and the layer thickness of the resin on the semiconductor wafer 16 is easily made uniform.

【0056】そしてこの状態で半導体ウェハ16を、そ
れを支持した基台(図示せず)とともに回転させる。半
導体ウェハ16を回転させることで、軟化した樹脂を広
げてその層厚を均一化しやすくする。
Then, in this state, the semiconductor wafer 16 is rotated together with a base (not shown) supporting the semiconductor wafer 16. By rotating the semiconductor wafer 16, the softened resin is spread to facilitate uniformization of the layer thickness.

【0057】なおこの回転に代えて樹脂の加熱後半導体
ウェハ16を振動させることで、軟化した樹脂を広げて
その層厚を均一化するようにしても良い。
Instead of this rotation, the semiconductor wafer 16 may be vibrated after heating the resin so that the softened resin is spread and the layer thickness is made uniform.

【0058】本実施形態においては樹脂はエポキシ系と
した。エポキシ系の樹脂は加熱により温度を上昇させれ
ば硬化するがそれまでの低温加熱時には先ず軟化するの
で、この状態で広げて均一な層厚とし、その後さらに温
度上昇させればこの均一層厚状態で硬化して保護層11
を形成することができ、生産性の良いものとなる。
In this embodiment, the resin is epoxy type. Epoxy resin cures when the temperature is raised by heating, but it softens first at low temperature heating until then, so spread it in this state to a uniform layer thickness, and then further raise the temperature to obtain this uniform layer thickness state. Curing with protective layer 11
Can be formed and the productivity can be improved.

【0059】以上のようにして保護層11が形成される
と次は図8に示す切断線17に沿っての切断を行う。
After the protective layer 11 is formed as described above, next, cutting is performed along the cutting line 17 shown in FIG.

【0060】本実施形態ではこの切断が容易に行えるよ
うに、保護層11を透明体とし、半導体ウェハ16上に
は図8の切断線17に対応する切断マーク(図7の1
8)を設けた。
In this embodiment, in order to facilitate this cutting, the protective layer 11 is made of a transparent material, and a cutting mark corresponding to the cutting line 17 in FIG. 8 (1 in FIG. 7) is formed on the semiconductor wafer 16.
8) is provided.

【0061】この様にすれば、保護層11が透明体なの
で半導体ウェハ16上の切断マークが透視でき、したが
ってICチップ9への切断が容易に行えるものとなる。
In this way, since the protective layer 11 is a transparent body, the cut mark on the semiconductor wafer 16 can be seen through, and the cutting into the IC chip 9 can be easily performed.

【0062】なおこの切断作業は、半導体ウェハ16
を、基台(図示せず)上に、この半導体ウェハ16を下
面側、保護層11を上面側として設置し、保護層11側
から行う。そしてこの様に、半導体ウェハ16を下面側
として基台上に設置すれば、切断時における平面度が維
持しやすくなり、よってICチップ9への切断が正確に
行いやすくなる。
The cutting operation is performed on the semiconductor wafer 16
The semiconductor wafer 16 is placed on the base (not shown) with the semiconductor wafer 16 as the lower surface side and the protective layer 11 as the upper surface side, and the protective layer 11 side is used. If the semiconductor wafer 16 is placed on the base as the lower surface side in this way, it is easy to maintain the flatness at the time of cutting, and thus the IC chip 9 is easily cut accurately.

【0063】またこの切断時において上方からの切断は
保護層11までとし、半導体ウェハ16の切断は反転さ
せ、切断刃を変えて行う。
At this time, the cutting from above is performed up to the protective layer 11, the cutting of the semiconductor wafer 16 is reversed, and the cutting blade is changed.

【0064】つまり、保護層11の切断と半導体ウェハ
16の切断はそれぞれ別方向から切断刃を変えて行うよ
うにしており、これは保護層11と半導体ウェハ16の
硬度が異なるからで、それぞれ別方向から切断刃を変え
て行う方がスムーズな切断、および各切断刃の損傷も起
きにくくなるのである。
That is, the cutting of the protective layer 11 and the cutting of the semiconductor wafer 16 are performed by changing the cutting blades from different directions. This is because the hardness of the protective layer 11 and the semiconductor wafer 16 are different. Changing the cutting blades from different directions will result in smoother cutting and less damage to the cutting blades.

【0065】またこの様に保護層11を先ず切断し、次
に反転させて半導体ウェハ16を切断する場合、前記保
護層11の切断時には半導体ウェハ16の外周部の余分
な部分に切欠マーク(図示せず)を形成しておく。
When the protective layer 11 is first cut and then the semiconductor wafer 16 is cut by reversing the protective layer 11 as described above, when the protective layer 11 is cut, a notch mark (Fig. (Not shown) is formed.

【0066】つまり、保護層11は透明なので半導体ウ
ェハ16上の切断マーク18を確認して保護層11を切
断することができるが、半導体ウェハ16は不透明なの
でそのままでは反転後の切断が困難となる。
That is, since the protective layer 11 is transparent, it is possible to cut the protective layer 11 by checking the cut marks 18 on the semiconductor wafer 16. However, since the semiconductor wafer 16 is opaque, it becomes difficult to cut after the inversion. .

【0067】そこで上述のごとく保護層11の切断時に
半導体ウェハ16に切欠マークを設けておくのであり、
この様にすれば反転しての半導体ウェハ16の切断も保
護層切断時に半導体ウェハ外周の不要部に設けていた切
欠マークを確認して適切に行えることとなるのである。
Therefore, as described above, the notch mark is provided on the semiconductor wafer 16 when the protective layer 11 is cut.
By doing so, it is possible to properly cut the semiconductor wafer 16 after reversing it by checking the notch mark provided in the unnecessary portion on the outer periphery of the semiconductor wafer when the protective layer is cut.

【0068】また上記保護層11の切断刃の幅は、半導
体ウェハ16の切断刃の幅よりも厚くしており、この様
に保護層11の切断刃の幅を厚くすることにより、保護
層11の外周には図2のごとく半導体ウェハ16側から
内方に向かう傾斜19が形成されることとなり、これに
より保護層11の外周部が欠けにくくなり、よってIC
チップ9を基板12に実装する際に保護層11の脱落欠
けらによる実装不良が生じなくなる。
The width of the cutting blade of the protective layer 11 is thicker than the width of the cutting blade of the semiconductor wafer 16. By increasing the width of the cutting blade of the protective layer 11 in this way, the protective layer 11 is made thicker. As shown in FIG. 2, an inclination 19 is formed on the outer periphery of the protective layer 11 from the side of the semiconductor wafer 16 toward the inner side.
When the chip 9 is mounted on the substrate 12, the mounting failure due to the chipping of the protective layer 11 does not occur.

【0069】図9、図10は本発明の他の実施形態を示
し、この実施形態では半導体ウェハ16に設けた複数の
接続電極8にそれぞれ突起電極10を接続し、次にこの
半導体ウェハ16の接続電極形成面に樹脂を突起電極の
先端より上位まで供給し、その後この樹脂を硬化させて
保護層11を形成し、次にこの保護層11を削って突起
電極10の先端を露出させ、その後前記半導体ウェハ1
6を切断してICチップ9を形成するものである。
FIGS. 9 and 10 show another embodiment of the present invention. In this embodiment, a plurality of connection electrodes 8 provided on the semiconductor wafer 16 are respectively connected to the protruding electrodes 10, and then the semiconductor wafer 16 is connected. A resin is supplied to the upper surface of the connection electrode formation surface above the tip of the bump electrode, and then the resin is cured to form a protective layer 11, and then the protective layer 11 is shaved to expose the tip of the bump electrode 10. The semiconductor wafer 1
6 is cut to form the IC chip 9.

【0070】なお保護層11は研磨機の研磨面に当接さ
せて削るようにしており、この様に半導体ウェハ16の
保護層11を研磨面に当接させて削ることとすれば、こ
の工程により露出した突起電極10の露出面には研磨に
もとづく凹凸面が形成され、これにより基板12の実装
電極13との接続強度を高めることができる。
The protective layer 11 is abraded by bringing it into contact with the polishing surface of the polishing machine. If the protective layer 11 of the semiconductor wafer 16 is brought into contact with the polishing surface and abraded in this way, this step is performed. As a result, a concavo-convex surface is formed on the exposed surface of the bump electrode 10 exposed by polishing, whereby the connection strength between the substrate 12 and the mounting electrode 13 can be increased.

【0071】[0071]

【発明の効果】以上のように本発明は、板状で少なくと
もその一面側に接続電極が設けられたICチップと、こ
のICチップの前記接続電極に接続された突起電極とを
備え、前記ICチップの接続電極形成面は突起電極の先
端を露出させて樹脂製の保護層で覆ったものであって、
ICチップの接続電極と突起電極の接続部、および突起
電極の下部を樹脂製の保護層で覆うので、両部分の強度
が強くなり、しかも各電子部品ごとにあらかじめ突起電
極部等を保護する保護層が形成されているので、基板実
装後の保護層形成が不要で、生産性がきわめて高くな
る。
As described above, the present invention is provided with an IC chip having a plate-like shape and provided with a connection electrode on at least one surface thereof, and a projecting electrode connected to the connection electrode of the IC chip. The connection electrode formation surface of the chip is one in which the tip of the protruding electrode is exposed and covered with a resin protective layer,
Since the connection part between the connection electrode of the IC chip and the protruding electrode and the lower part of the protruding electrode are covered with a resin protective layer, the strength of both parts is increased, and moreover, the protruding electrode part and the like are protected in advance for each electronic component. Since the layers are formed, it is not necessary to form a protective layer after mounting on the substrate, and the productivity is extremely high.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の電子部品の一実施形態の斜視図FIG. 1 is a perspective view of an embodiment of an electronic component of the present invention.

【図2】図1の電子部品を基板に実装する工程を示す断
面図
2 is a cross-sectional view showing a process of mounting the electronic component of FIG. 1 on a substrate.

【図3】図2の実装工程後の基板の断面図3 is a cross-sectional view of the board after the mounting process of FIG.

【図4】同基板の斜視図FIG. 4 is a perspective view of the board.

【図5】半導体ウェハの斜視図FIG. 5 is a perspective view of a semiconductor wafer.

【図6】その要部の拡大断面図FIG. 6 is an enlarged cross-sectional view of the main part.

【図7】同要部の斜視図FIG. 7 is a perspective view of the main part.

【図8】半導体ウェハの切断工程を示す斜視図FIG. 8 is a perspective view showing a semiconductor wafer cutting process.

【図9】本発明の他の実施形態を示す断面図FIG. 9 is a cross-sectional view showing another embodiment of the present invention.

【図10】同断面図FIG. 10 is a sectional view of the same.

【図11】従来の断面図FIG. 11 is a conventional sectional view.

【図12】同要部拡大断面図FIG. 12 is an enlarged sectional view of the same main part.

【符号の説明】[Explanation of symbols]

7 電子部品 8 接続電極 9 ICチップ 10 突起電極 11 保護層 12 基板 13 実装電極 7 electronic components 8 connection electrodes 9 IC chip 10 protruding electrode 11 Protective layer 12 substrates 13 Mounting electrode

Claims (33)

【特許請求の範囲】[Claims] 【請求項1】 板状で少なくともその一面側に接続電極
が設けられたICチップと、このICチップの前記接続
電極に接続された突起電極とを備え、前記ICチップの
接続電極形成面は突起電極の先端を露出させて樹脂製の
保護層で覆った電子部品。
1. A plate-shaped IC chip having a connection electrode provided on at least one surface side thereof, and a projection electrode connected to the connection electrode of the IC chip, wherein a connection electrode formation surface of the IC chip has a projection. An electronic component in which the tip of the electrode is exposed and covered with a protective layer made of resin.
【請求項2】 突起電極の先端を保護層から突出させた
請求項1に記載の電子部品。
2. The electronic component according to claim 1, wherein the tip of the protruding electrode is projected from the protective layer.
【請求項3】 ICチップはシリコン基板上に回路パタ
ーンを設けた構成とし、保護層を形成する樹脂には酸化
ケイ素のフィラを混入させた請求項1に記載の電子部
品。
3. The electronic component according to claim 1, wherein the IC chip has a structure in which a circuit pattern is provided on a silicon substrate, and a filler of silicon oxide is mixed in the resin forming the protective layer.
【請求項4】 保護層の外周の、シリコン基板の反対側
部分は、シリコン基板側から内方に向かう傾斜を設けた
請求項3に記載の電子部品。
4. The electronic component according to claim 3, wherein a portion of the outer periphery of the protective layer on the opposite side of the silicon substrate is provided with an inclination inward from the silicon substrate side.
【請求項5】 半導体ウェハに設けた複数の接続電極に
それぞれ突起電極を接続し、次にこの半導体ウェハの接
続電極形成面に樹脂を突起電極の先端より下位まで供給
し、その後この樹脂を硬化させて突起電極の先端だけを
突出させた保護層を形成し、次に半導体ウェハを切断し
てICチップを形成する電子部品の製造方法。
5. A projection electrode is connected to each of a plurality of connection electrodes provided on a semiconductor wafer, and then a resin is supplied to the connection electrode formation surface of the semiconductor wafer below the tip of the projection electrode, and then the resin is cured. A method of manufacturing an electronic component in which a protective layer is formed by protruding only the tips of the protruding electrodes, and then the semiconductor wafer is cut to form an IC chip.
【請求項6】 半導体ウェハはシリコン基板上に回路パ
ターンを設けた構成とし、保護層を形成する樹脂には酸
化ケイ素のフィラを混入させた請求項5に記載の電子部
品の製造方法。
6. The method of manufacturing an electronic component according to claim 5, wherein the semiconductor wafer has a circuit pattern provided on a silicon substrate, and a filler of silicon oxide is mixed in the resin forming the protective layer.
【請求項7】 樹脂の供給前に半導体ウェハの樹脂供給
面をプラズマによりクリーニングする請求項5に記載の
電子部品の製造方法。
7. The method of manufacturing an electronic component according to claim 5, wherein the resin supply surface of the semiconductor wafer is cleaned with plasma before the resin is supplied.
【請求項8】 半導体ウェハへの樹脂供給後樹脂を加熱
する請求項7に記載の電子部品の製造方法。
8. The method of manufacturing an electronic component according to claim 7, wherein the resin is heated after the resin is supplied to the semiconductor wafer.
【請求項9】 樹脂の加熱後半導体ウェハを回転させる
請求項8に記載の電子部品の製造方法。
9. The method of manufacturing an electronic component according to claim 8, wherein the semiconductor wafer is rotated after heating the resin.
【請求項10】 樹脂の加熱後半導体ウェハを振動させ
る請求項8に記載の電子部品の製造方法。
10. The method of manufacturing an electronic component according to claim 8, wherein the semiconductor wafer is vibrated after heating the resin.
【請求項11】 樹脂はエポキシ系とした請求項9、ま
たは10に記載の電子部品の製造方法。
11. The method for manufacturing an electronic component according to claim 9, wherein the resin is an epoxy resin.
【請求項12】 保護層を透明体とし、半導体ウェハ上
には切断マークを設けた請求項5に記載の電子部品の製
造方法。
12. The method of manufacturing an electronic component according to claim 5, wherein the protective layer is made of a transparent material and a cutting mark is provided on the semiconductor wafer.
【請求項13】 半導体ウェハを、基台上に、この半導
体ウェハを下面側、保護層を上面側として設置し、保護
層側から切断を行う請求項12に記載の電子部品の製造
方法。
13. The method of manufacturing an electronic component according to claim 12, wherein a semiconductor wafer is placed on a base with the semiconductor wafer as the lower surface side and the protective layer as the upper surface side, and the cutting is performed from the protective layer side.
【請求項14】 保護層の切断と半導体ウェハの切断は
それぞれ別方向から切断刃を変えて行う請求項13に記
載の電子部品の製造方法。
14. The method of manufacturing an electronic component according to claim 13, wherein cutting of the protective layer and cutting of the semiconductor wafer are performed by changing cutting blades from different directions.
【請求項15】 保護層を先ず切断し、次に反転させて
半導体ウェハを切断することとし、前記保護層の切断時
には半導体ウェハの外周部に切欠マークを形成する請求
項14に記載の電子部品の製造方法。
15. The electronic component according to claim 14, wherein the protective layer is first cut and then inverted to cut the semiconductor wafer, and a cut mark is formed on an outer peripheral portion of the semiconductor wafer when the protective layer is cut. Manufacturing method.
【請求項16】 保護層の切断刃の幅を、半導体ウェハ
の切断刃の幅よりも厚くした請求項12〜15のいずれ
か一つに記載の電子部品の製造方法。
16. The method of manufacturing an electronic component according to claim 12, wherein a width of the cutting blade of the protective layer is thicker than a width of the cutting blade of the semiconductor wafer.
【請求項17】 半導体ウェハに設けた複数の接続電極
にそれぞれ突起電極を接続し、次にこの半導体ウェハの
接続電極形成面に樹脂を突起電極の先端より上位まで供
給し、その後この樹脂を硬化させて保護層を形成し、次
にこの保護層を削って突起電極の先端を露出させ、その
後前記半導体ウェハを切断してICチップを形成する電
子部品の製造方法。
17. A projection electrode is connected to each of a plurality of connection electrodes provided on a semiconductor wafer, and then a resin is supplied to the connection electrode formation surface of this semiconductor wafer to a position higher than the tip of the projection electrode, and then the resin is cured. Then, a protective layer is formed, the protective layer is then shaved to expose the tips of the protruding electrodes, and then the semiconductor wafer is cut to form an IC chip.
【請求項18】 保護層を研磨面に当接させて削る請求
項17に記載の電子部品の製造方法。
18. The method of manufacturing an electronic component according to claim 17, wherein the protective layer is brought into contact with the polishing surface to be ground.
【請求項19】 半導体ウェハはシリコン基板上に回路
パターンを設けた構成とし、保護層を形成する樹脂には
酸化ケイ素のフィラを混入させた請求項18に記載の電
子部品の製造方法。
19. The method of manufacturing an electronic component according to claim 18, wherein the semiconductor wafer has a structure in which a circuit pattern is provided on a silicon substrate, and a filler of silicon oxide is mixed in the resin forming the protective layer.
【請求項20】 樹脂の供給前に半導体ウェハの樹脂供
給面をプラズマによりクリーニングする請求項17に記
載の電子部品の製造方法。
20. The method of manufacturing an electronic component according to claim 17, wherein the resin supply surface of the semiconductor wafer is cleaned with plasma before the resin is supplied.
【請求項21】 半導体ウェハへの樹脂供給後樹脂を加
熱する請求項20に記載の電子部品の製造方法。
21. The method of manufacturing an electronic component according to claim 20, wherein the resin is heated after the resin is supplied to the semiconductor wafer.
【請求項22】 樹脂の加熱後半導体ウェハを回転させ
る請求項21に記載の電子部品の製造方法。
22. The method of manufacturing an electronic component according to claim 21, wherein the semiconductor wafer is rotated after heating the resin.
【請求項23】 樹脂の加熱後半導体ウェハを振動させ
る請求項21に記載の電子部品の製造方法。
23. The method of manufacturing an electronic component according to claim 21, wherein the semiconductor wafer is vibrated after heating the resin.
【請求項24】 樹脂はエポキシ系とした請求項22、
または23に記載の電子部品の製造方法。
24. The resin according to claim 22, which is an epoxy resin.
23. A method for manufacturing an electronic component according to 23.
【請求項25】 保護層を透明体とし、半導体ウェハ上
には切断マークを設けた請求項17に記載の電子部品の
製造方法。
25. The method of manufacturing an electronic component according to claim 17, wherein the protective layer is made of a transparent material, and cutting marks are provided on the semiconductor wafer.
【請求項26】 半導体ウェハを、基台上に、この半導
体ウェハを下面側、保護層を上面側として設置し、保護
層側から切断を行う請求項25に記載の電子部品の製造
方法。
26. The method of manufacturing an electronic component according to claim 25, wherein a semiconductor wafer is placed on a base with the semiconductor wafer being the lower surface side and the protective layer being the upper surface side, and cutting is performed from the protective layer side.
【請求項27】 保護層の切断と半導体ウェハの切断は
それぞれ別方向から切断刃を変えて行う請求項26に記
載の電子部品の製造方法。
27. The method of manufacturing an electronic component according to claim 26, wherein the cutting of the protective layer and the cutting of the semiconductor wafer are performed by changing cutting blades from different directions.
【請求項28】 保護層を先ず切断し、次に反転させて
半導体ウェハを切断することとし、前記保護層の切断時
には半導体ウェハの外周部に切欠マークを形成する請求
項27に記載の電子部品の製造方法。
28. The electronic component according to claim 27, wherein the protective layer is first cut and then inverted to cut the semiconductor wafer, and a cut mark is formed on an outer peripheral portion of the semiconductor wafer when the protective layer is cut. Manufacturing method.
【請求項29】 保護層の切断刃の幅を、半導体ウェハ
の切断刃の幅よりも厚くした請求項25〜28のいずれ
か一つに記載の電子部品の製造方法。
29. The method of manufacturing an electronic component according to claim 25, wherein the width of the cutting blade of the protective layer is thicker than the width of the cutting blade of the semiconductor wafer.
【請求項30】 表面に実装電極が設けられた基板と、
この基板の実装電極上にその突起電極を接続した電子部
品とを備え、前記電子部品は、板状で少なくともその一
面側に接続電極が設けられたICチップと、このICチ
ップの前記接続電極に接続された突起電極とを備え、前
記ICチップの接続電極形成面は突起電極の先端を露出
させて樹脂製の保護層で覆った構成とした回路基板。
30. A substrate having a mounting electrode on the surface thereof,
An electronic component in which the protruding electrode is connected to a mounting electrode of the substrate is provided, and the electronic component is a plate-shaped IC chip provided with a connection electrode on at least one surface side thereof and the connection electrode of the IC chip. A circuit board having a connected protruding electrode, wherein the connection electrode forming surface of the IC chip is formed by exposing the tip of the protruding electrode and covering it with a protective layer made of resin.
【請求項31】 突起電極の先端を保護層から突出させ
た請求項30に記載の回路基板。
31. The circuit board according to claim 30, wherein the tip of the protruding electrode is projected from the protective layer.
【請求項32】 ICチップはシリコン基板上に回路パ
ターンを設けた構成とし、保護層を形成する樹脂には酸
化ケイ素のフィラを混入させた請求項30に記載の回路
基板。
32. The circuit board according to claim 30, wherein the IC chip has a configuration in which a circuit pattern is provided on a silicon substrate, and a filler of silicon oxide is mixed in the resin forming the protective layer.
【請求項33】 保護層の外周の、シリコン基板の反対
側部分は、シリコン基板側から内方に向かう傾斜を設け
た請求項32に記載の回路基板。
33. The circuit board according to claim 32, wherein a portion of the outer periphery of the protective layer on the opposite side of the silicon substrate is provided with a slope inward from the silicon substrate side.
JP2001296842A 2001-09-27 2001-09-27 Electronic component and manufacturing method thereof, and circuit board packaging the same Pending JP2003100808A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001296842A JP2003100808A (en) 2001-09-27 2001-09-27 Electronic component and manufacturing method thereof, and circuit board packaging the same

Publications (1)

Publication Number Publication Date
JP2003100808A true JP2003100808A (en) 2003-04-04

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001296842A Pending JP2003100808A (en) 2001-09-27 2001-09-27 Electronic component and manufacturing method thereof, and circuit board packaging the same

Country Status (1)

Country Link
JP (1) JP2003100808A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012505555A (en) * 2008-12-19 2012-03-01 インテル コーポレイション Bump stress relaxation layer of integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012505555A (en) * 2008-12-19 2012-03-01 インテル コーポレイション Bump stress relaxation layer of integrated circuit

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