JP2003092311A - Method of mounting ic chip having projecting electrode - Google Patents

Method of mounting ic chip having projecting electrode

Info

Publication number
JP2003092311A
JP2003092311A JP2001281309A JP2001281309A JP2003092311A JP 2003092311 A JP2003092311 A JP 2003092311A JP 2001281309 A JP2001281309 A JP 2001281309A JP 2001281309 A JP2001281309 A JP 2001281309A JP 2003092311 A JP2003092311 A JP 2003092311A
Authority
JP
Japan
Prior art keywords
chip
mounting
bonding
sealing resin
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001281309A
Other languages
Japanese (ja)
Inventor
Yoshihiro Ishida
芳弘 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nagase and Co Ltd
Original Assignee
Nagase and Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nagase and Co Ltd filed Critical Nagase and Co Ltd
Priority to JP2001281309A priority Critical patent/JP2003092311A/en
Publication of JP2003092311A publication Critical patent/JP2003092311A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body

Abstract

PROBLEM TO BE SOLVED: To solve problems of not being able to form a uniform fillet and requiring a long cycle time because of chip-by-chip treatment in FC (flip-chip) mounting with an NCF (non-conductive film) method in which an NCF film is attached on a circuit substrate, and bonding and resin curing are simultaneously made. SOLUTION: A uniform fillet can be formed by attaching the NCF film on the chip side, and the total cycle time can be reduced by bonding on an individual chip-by-chip basis while curing is made on batch basis. As a consequence, a cheap method of mounting an IC chip having projecting electrodes can be provided.

Description

【発明の詳細な説明】Detailed Description of the Invention

【発明の属する技術分野】本発明は突起電極付ICチッ
プの基板への実装方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting an IC chip with protruding electrodes on a substrate.

【従来の技術】近年、半導体パッケージの小型化及び半
導体チップをマザーボートに高密度化実装するため、半
導体チップを直接フェイスダウン方式で、基板上に実装
するフリップチップ実装が開発されている。なかでも、
金のスタッドバンプを使ったフリップチップ実装を安価
に製造する市場要求が本格化している。図4は、従来の
突起電極付ICチップの実装方法を示す。図4(a)に
示す基板は、突起電極付ICチップを接続する基板を示
す。基板9の上面には、ICチップと接続するボンディ
ングパット8が形成されており、ソルダーレジスト10
でカバーされている。基板9の上下面は、パターン11
が形成されており、ソルダーレジスト10でカバーして
いる。図4(b)に示す封止フィルム貼り付け工程は、
封止樹脂5上にカバーフィルム6の付いた封止フィルム
13を後工程の位置合わせ精度等を考慮し、ICチップ
よりも1ミリ程度の大きいサイズに切断し、実装される
基板9の上に貼り付ける。図4(c)に示す封止フィル
ム熱圧着工程は、封止フィルム13を基板9に熱圧着
し、封止フィルム13と基板9間の空隙を排除する。図
4(d)に示すカバーフィルム剥離工程は、次工程でI
Cチップをボンディングするため、封止フィルム13上
のカバーフィルム6を剥離する。図4(e)に示す実装
工程は、PV膜4で周りを保護されたパット3上に突起
電極2が形成されたICチップ1を基板9に位置合わせ
し、熱プレスすることで、突起電極2とボンディングパ
ット8を電気的に接合し、熱プレスを維持することで、
封止樹脂を硬化させ、硬化済封止樹脂7を形成する。例
えば、封止樹脂に、ナガセケムテックス社製速硬化性N
CFフィルムT693/R6003を使うと、ボンディ
ン条件を180℃10秒+240℃10秒で、ボンディ
ングと同時に封止樹脂を硬化させることができる。ボン
ディングと同時に封止樹脂の硬化を行うため、硬化時間
を含めたサイクルタイムが長くなる問題があった。ま
た、硬化済封止樹脂7は、ICチップ1の外周部にフィ
レット12を形成するが、封止フィルム13をICチッ
プ1に対し、均等に張り合わせることが難しいため、フ
ィレット12は、ICチップ1の外周部に均等に形成す
ることが、難しかった。そのため、信頼性が低下する問
題等があった。図4(f)に示す完成は、前述の図4
(a)から図4(e)により、実装完成品200が完成
する。
2. Description of the Related Art In recent years, flip chip mounting has been developed in which a semiconductor chip is directly mounted on a substrate by a face-down method in order to miniaturize the semiconductor package and mount the semiconductor chip on a mother board with high density. Above all,
The market demand for inexpensive manufacturing of flip chip mounting using gold stud bumps is in full swing. FIG. 4 shows a conventional mounting method of an IC chip with protruding electrodes. The substrate shown in FIG. 4A shows a substrate to which the IC chip with protruding electrodes is connected. A bonding pad 8 for connecting to an IC chip is formed on the upper surface of the substrate 9, and the solder resist 10
Is covered by. The pattern 9 is formed on the upper and lower surfaces of the substrate 9.
Are formed and are covered with the solder resist 10. The step of attaching the sealing film shown in FIG.
The sealing film 13 with the cover film 6 on the sealing resin 5 is cut into a size of about 1 mm larger than the IC chip in consideration of alignment accuracy in a later process and the like, and is cut on the substrate 9 to be mounted. paste. In the sealing film thermocompression bonding step shown in FIG. 4C, the sealing film 13 is thermocompression bonded to the substrate 9 to eliminate voids between the sealing film 13 and the substrate 9. The cover film peeling process shown in FIG.
In order to bond the C chip, the cover film 6 on the sealing film 13 is peeled off. In the mounting process shown in FIG. 4E, the IC chip 1 having the protruding electrode 2 formed on the pad 3 whose periphery is protected by the PV film 4 is aligned with the substrate 9 and hot pressed to form the protruding electrode. By electrically connecting 2 and the bonding pad 8 and maintaining the hot press,
The sealing resin is cured to form the cured sealing resin 7. For example, the encapsulating resin may be a fast-curing N made by Nagase Chemtex.
When the CF film T693 / R6003 is used, it is possible to cure the sealing resin at the same time as bonding under bonding conditions of 180 ° C. for 10 seconds and 240 ° C. for 10 seconds. Since the sealing resin is cured at the same time as the bonding, there is a problem that the cycle time including the curing time becomes long. Further, the cured encapsulation resin 7 forms the fillet 12 on the outer peripheral portion of the IC chip 1, but it is difficult to evenly attach the encapsulation film 13 to the IC chip 1. It was difficult to uniformly form the outer peripheral portion of No. 1. Therefore, there is a problem that reliability is lowered. The completion shown in FIG.
4A to 4E, the mounting completed product 200 is completed.

【発明が解決しようとする課題】しかしながら、前述し
た突起電極付ICチップの実装方法には次のような問題
点がある。即ち、封止フィルムを基板に貼り付けるた
め、封止フィルムをICチップよりも大きく切断する必
要があるため、コストが高くなる等の問題があった。ま
た、突起電極のボンディングと封止樹脂の硬化を同一プ
ロセスで行うため、サイクルタイムが長くなる等の問題
があった。さらに、封止樹脂フィルムを基板に貼り付け
た後ICチップを貼り付けるため、ボンディング時に位
置ずれが発生し、均等なフィレットが形成できず、信頼
性が低下する等の問題があった。本発明は、上記従来の
課題に鑑みなされたものであり、その目的は、突起電極
付ICチップの実装時、安価で信頼性のある実装方法を
提供するものである。
However, the above-mentioned mounting method of the IC chip with protruding electrodes has the following problems. That is, since the sealing film is attached to the substrate, it is necessary to cut the sealing film larger than the IC chip, which causes a problem such as an increase in cost. Further, since the bonding of the protruding electrodes and the curing of the sealing resin are performed in the same process, there is a problem that the cycle time becomes long. Furthermore, since the IC chip is attached after the encapsulating resin film is attached to the substrate, there is a problem in that misalignment occurs during bonding, uniform fillets cannot be formed, and reliability decreases. The present invention has been made in view of the above conventional problems, and an object thereof is to provide an inexpensive and reliable mounting method when mounting an IC chip with protruding electrodes.

【課題を解決するための手段】上記目的を達成するため
に、パット上に突起電極を有するICチップを回路基板
に接続する実装方法において、少なくとも前記ICチッ
プの実装面に封止樹脂を接着する接着工程と、封止樹脂
付ICチップと前記回路基板とを接合する実装工程とを
包含することを特徴とするものである。また、前記封止
樹脂は、少なくとも熱硬化性樹脂と熱可塑性樹脂とを包
含することを特徴とするものである。また、前記接着工
程の熱硬化性樹脂は、Aステージ樹脂であることを特徴
とするものである。また、前記実装工程は、前記封止樹
脂付ICチップと前記回路基板とを電気的に接合するボ
ンディング工程と、前記封止樹脂を硬化する硬化工程と
からなることを特徴とするものである。また、前記ボン
ディング工程は、前記封止樹脂付ICチップの突起電極
と前記回路基板とを位置合わせする位置決め工程と、前
記突起電極と前記回路基板とを電気的に接合する接合工
程とからなることを特徴とするものである。また、前記
位置決め工程の際の温度は、前記熱可塑性樹脂の軟化温
度よりも高く、前記熱硬化性樹脂の反応開始温度よりも
低いことを特徴とするものである。また、前記接合工程
は、熱プレス法を用いることを特徴とするものである。
また、前記接着工程は、前記封止樹脂を前記ICチップ
の実装面の面積とほぼ同じ大きさで、前記ICチップの
実装面に接着させる工程を包含することを特徴とするも
のである。また、前記突起電極は、金を主成分としてい
ることを特徴とするものである。また、前記突起電極
は、ワイヤーボンディング法により形成されていること
を特徴とするものである。また、前記回路基板上のボン
ディングパットは、予めハンダ処理がなされていること
を特徴とするものである。
In order to achieve the above object, in a mounting method for connecting an IC chip having protruding electrodes on a pad to a circuit board, a sealing resin is adhered to at least the mounting surface of the IC chip. It is characterized by including an adhering step and a mounting step of joining the IC chip with a sealing resin and the circuit board. Further, the sealing resin includes at least a thermosetting resin and a thermoplastic resin. Further, the thermosetting resin in the adhering step is an A stage resin. Further, the mounting step is characterized by including a bonding step of electrically bonding the IC chip with sealing resin and the circuit board, and a curing step of curing the sealing resin. Further, the bonding step includes a positioning step of aligning the protruding electrode of the IC chip with the sealing resin and the circuit board, and a bonding step of electrically bonding the protruding electrode and the circuit board. It is characterized by. The temperature in the positioning step is higher than the softening temperature of the thermoplastic resin and lower than the reaction start temperature of the thermosetting resin. Further, the joining step is characterized by using a hot pressing method.
Further, the bonding step includes a step of bonding the sealing resin to the mounting surface of the IC chip in a size substantially the same as the area of the mounting surface of the IC chip. Further, the protruding electrode is characterized by containing gold as a main component. Further, the protruding electrode is formed by a wire bonding method. Further, the bonding pad on the circuit board is characterized in that a soldering process is performed in advance.

【発明の実施の形態】以下図面に基づいて本発明におけ
る突起電極付ICチップの実装方法について説明する。
図1は本発明の実施の形態で突起電極付ICチップの実
装方法を説明する説明図である。図2は本発明の実施の
形態で実装工程を説明する説明図である。図3は本発明
の実施の形態でボンディング工程を説明する説明図であ
る。従来技術と同一部材は同一符号で示す。先ず、図1
(a)の突起電極付ICチップは、PV膜4で保護され
たICチップ1のパット3上に突起電極2が形成された
突起電極付ICチップである。突起電極2は、ワイヤー
ボンディング法、電解メッキ法等で作成することができ
るが、基板接合時に熱プレス法で電気接続するため、ワ
イヤーボンディング法で形成した突起電極が望ましい。
また、その材料は酸化しにくい金を主成分としたものが
望ましい。図1(b)に示す接着工程は、封止樹脂5を
ほぼICチップ1の大きさに接着する。そのため、封止
樹脂5を必要な部分のみに形成することができる。図1
(c)に示す実装工程は、基板9上のボンディングパッ
ト8とICチップ1の突起電極2を位置合わせし、熱プ
レス法で電気的に接続し、封止樹脂5を硬化させ、硬化
済封止樹脂7を形成する。封止樹脂5はほぼICチップ
1のサイズであるため、ICチップ1の外周面に均一な
フィレット12が形成できる。ボンディングパット8
は、周りをソルダーレジスト10で保護されており、基
板9の上下面はパターン11が形成されており、ソルダ
ーレジスト10がカバーしている。ボンディングパット
8の表面処理が金である場合、熱プレス法により熱硬化
性樹脂の硬化収縮と圧力により電気的に接続される。一
方、表面処理がハンダである場合、信頼性のある金とハ
ンダの金属間接合により接続される。図1(d)に示す
完成は、前述の図1(a)から図1(c)により、実装
完成品100が完成する。図2に本発明の図1(c)に
示した実装工程を説明する。図2(a)の封止樹脂付I
Cチップは、前述の図1(b)と同じであるため、説明
は省略する。図2(b)に示すボンディング工程は、周
りをソルダーレジスト10で保護された基板9上のボン
ディングパット8とICチップ1の突起電極を位置合わ
せし、熱プレス法で電気的に基板8とICチップ1を接
続する。図2(c)に示す硬化工程は、前述のボンディ
ング工程では、未硬化である封止樹脂5をバッチ式キュ
ア炉に入れて硬化済封止樹脂7を形成する。予め封止樹
脂5は、ICチップ1とほぼ同じサイズに接着してある
ため、ICチップ1の外周部にフィレット12が、均等
に形成され信頼性が向上した。図3に本発明の図2
(b)に示したボンディング工程を説明する。図3
(a)の封止樹脂付ICチップは、前述の図1(b)と
同じであるため、説明は省略する。図3(b)の位置決
め工程は、基板9上のボンディングパット8とICチッ
プ1の突起電極を位置合わせし仮接着する。例えば、熱
可塑性樹脂に軟化温度が約80℃のアクリル系樹脂を使
い、反応開始温度を約120℃に調整すると、100℃
で仮接着すると、粘度は充分下がっているため、ボイド
の発生を押さえながら、チップ1と基板9を仮接着でき
た。図3(c)に示す接合工程は、ICチップ1の突起
電極2と基板9のボンディングパット8を熱プレス法に
より電気的に接続する。次に、バッチ方式で封止樹脂を
硬化する。例えば、前記アクリル系樹脂で調整した封止
樹脂を使うと、240℃10秒で電気的接合が完了す
る。さらに、200℃10分で封止樹脂が熱硬化でき
た。これらのサイクルタイムを従来の方法と比べると、
50x100ミリの基板にICチップが20個乗り、こ
の基板をボンディング後20枚一括で封止樹脂をキュア
すると、従来の方法では、20ICチップを20基板分
実装完了するのに、8,000秒(=20ICチップx
20基板x20秒)である。一方、本発明の場合、3,
600秒(=20ICチップx20基板x10秒+10
分)となり、大幅にサイクルタイムを減少することがで
きる。
BEST MODE FOR CARRYING OUT THE INVENTION A method of mounting an IC chip with protruding electrodes according to the present invention will be described below with reference to the drawings.
FIG. 1 is an explanatory diagram for explaining a mounting method of an IC chip with a protruding electrode according to an embodiment of the present invention. FIG. 2 is an explanatory diagram illustrating a mounting process in the embodiment of the present invention. FIG. 3 is an explanatory diagram for explaining the bonding process in the embodiment of the present invention. The same members as those in the prior art are designated by the same reference numerals. First, Fig. 1
The IC chip with a protruding electrode of (a) is an IC chip with a protruding electrode in which the protruding electrode 2 is formed on the pad 3 of the IC chip 1 protected by the PV film 4. The bump electrode 2 can be formed by a wire bonding method, an electrolytic plating method, or the like, but a bump electrode formed by the wire bonding method is desirable because it is electrically connected by a hot pressing method when joining the substrates.
Further, it is desirable that the material is composed mainly of gold, which is difficult to oxidize. In the bonding step shown in FIG. 1B, the sealing resin 5 is bonded to approximately the size of the IC chip 1. Therefore, the sealing resin 5 can be formed only in a necessary portion. Figure 1
In the mounting step shown in (c), the bonding pad 8 on the substrate 9 and the protruding electrode 2 of the IC chip 1 are aligned and electrically connected by a hot press method, the sealing resin 5 is cured, and the cured sealing is performed. The stop resin 7 is formed. Since the encapsulating resin 5 has almost the size of the IC chip 1, the uniform fillet 12 can be formed on the outer peripheral surface of the IC chip 1. Bonding pad 8
Is protected by a solder resist 10, and a pattern 11 is formed on the upper and lower surfaces of the substrate 9 to cover the solder resist 10. When the surface treatment of the bonding pad 8 is gold, the thermosetting resin is electrically connected by the curing shrinkage and pressure of the thermosetting resin by the hot pressing method. On the other hand, when the surface treatment is solder, the connection is made by a reliable metal-metal joint between gold and solder. The completion shown in FIG. 1 (d) is completed by the above-described FIGS. 1 (a) to 1 (c). FIG. 2 illustrates the mounting process shown in FIG. 1C of the present invention. With sealing resin I of FIG. 2 (a)
The C chip is the same as that in FIG. In the bonding step shown in FIG. 2B, the bonding pad 8 on the substrate 9 whose periphery is protected by the solder resist 10 and the protruding electrode of the IC chip 1 are aligned with each other, and the substrate 8 and the IC are electrically connected by a hot press method. Connect chip 1. In the curing step shown in FIG. 2C, in the bonding step described above, the uncured sealing resin 5 is put into a batch type curing furnace to form the cured sealing resin 7. Since the sealing resin 5 is bonded to the IC chip 1 in substantially the same size in advance, the fillets 12 are evenly formed on the outer peripheral portion of the IC chip 1 and reliability is improved. 2 of the present invention in FIG.
The bonding process shown in (b) will be described. Figure 3
Since the IC chip with a sealing resin of (a) is the same as that of FIG. 1 (b) described above, the description thereof will be omitted. In the positioning step of FIG. 3B, the bonding pad 8 on the substrate 9 and the protruding electrode of the IC chip 1 are aligned and temporarily bonded. For example, if an acrylic resin with a softening temperature of about 80 ° C. is used as the thermoplastic resin and the reaction start temperature is adjusted to about 120 ° C., 100 ° C.
Since the viscosity was sufficiently reduced by temporarily bonding with, the chip 1 and the substrate 9 could be temporarily bonded while suppressing the generation of voids. In the bonding step shown in FIG. 3C, the protruding electrode 2 of the IC chip 1 and the bonding pad 8 of the substrate 9 are electrically connected by the hot pressing method. Next, the sealing resin is cured by a batch method. For example, when the sealing resin prepared with the acrylic resin is used, electrical joining is completed at 240 ° C. for 10 seconds. Furthermore, the sealing resin was able to be thermoset at 200 ° C. for 10 minutes. Comparing these cycle times with conventional methods,
If 20 IC chips are mounted on a 50 × 100 mm substrate and the sealing resin is cured in a batch after bonding the 20 IC chips, in the conventional method, 8,000 seconds ( = 20 IC chips x
20 substrates x 20 seconds). On the other hand, in the case of the present invention, 3,
600 seconds (= 20 IC chips x 20 substrates x 10 seconds + 10
Minutes), and the cycle time can be greatly reduced.

【発明の効果】以上説明したように、本発明の突起電極
付ICチップの実装方法によれば、ICチップに封止樹
脂を接着し実装するため、封止樹脂の無駄を無くし、安
価な実装方法を提供できる。また、封止樹脂が、少なく
とも熱硬化性樹脂と熱可塑性樹脂とを含有することで、
仮接着を容易に実現できる。また、熱硬化性樹脂がAス
テージ樹脂であることで、ボンディング時容易に、ボイ
ドの形成を防ぐことができる。また、ボンディング工程
と封止樹脂の硬化工程とを分離した工程にすることで、
サイクルタイムの短くした安価な実装方法を提供でき
る。また、ICチップを仮接着する工程と電気的接合す
る工程とを分離することで、工程のフレキシビリティを
向上させることができる。また、位置決め工程の際の温
度を、熱可塑性樹脂の軟化温度よりも高く、熱硬化性樹
脂の反応開始温度よりも低くすることで、ボイドがない
信頼性のある実装方法を提供できる。また、接合工程に
熱プレス法を採用することで、容易に突起電極を接合す
ることができる。また、封止樹脂の実装面とICチップ
の実装面とをほぼ同じ面積とすることで、均一なフィレ
ットを形成でき、信頼性の高い構造を提供できる。ま
た、突起電極が金を主成分とすることで、途中工程での
突起電極の酸化を防ぎ、容易にボンディングができる。
また、突起電極をワイヤーボンディング方式で形成する
ことで、容易に熱プレス法でボンディングすることがで
きる。また、基板上のボンディングは、予めハンダ処理
がなされていることで、金属間接合をした信頼性のある
接続方法を提供できる。
As described above, according to the mounting method of the IC chip with the protruding electrodes of the present invention, the sealing resin is bonded and mounted on the IC chip, so that the sealing resin is not wasted and the mounting is inexpensive. A method can be provided. Further, the sealing resin contains at least a thermosetting resin and a thermoplastic resin,
Temporary adhesion can be easily realized. Further, since the thermosetting resin is the A-stage resin, it is possible to easily prevent the formation of voids during bonding. In addition, by separating the bonding process and the sealing resin curing process,
An inexpensive mounting method with a short cycle time can be provided. Further, by separating the step of temporarily adhering the IC chip and the step of electrically connecting the IC chips, the flexibility of the steps can be improved. Further, by setting the temperature in the positioning step to be higher than the softening temperature of the thermoplastic resin and lower than the reaction start temperature of the thermosetting resin, it is possible to provide a reliable mounting method without voids. Further, by adopting the hot pressing method in the joining process, the protruding electrodes can be easily joined. Further, by making the mounting surface of the sealing resin and the mounting surface of the IC chip have substantially the same area, it is possible to form a uniform fillet and provide a highly reliable structure. In addition, since the protruding electrode contains gold as a main component, it is possible to prevent the protruding electrode from being oxidized in an intermediate step and easily perform bonding.
Further, by forming the protruding electrodes by the wire bonding method, the bonding can be easily performed by the hot pressing method. In addition, since the bonding on the substrate is performed by soldering in advance, it is possible to provide a reliable connection method in which metal-to-metal bonding is performed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施の形態に係わる突起電極付ICチ
ップの実装工程で、突起電極付ICチップ、接着工程、
実装工程、完成を示す説明図である。
FIG. 1 is a view showing a mounting process of an IC chip with protruding electrodes according to an embodiment of the present invention, an IC chip with protruding electrodes, an adhering process,
It is explanatory drawing which shows a mounting process and completion.

【図2】本発明の実施の形態に係わる実装工程で、封止
樹脂付ICチップ、ボンディング工程、硬化工程を示す
説明図である。
FIG. 2 is an explanatory diagram showing an IC chip with a sealing resin, a bonding process, and a curing process in the mounting process according to the embodiment of the present invention.

【図3】本発明の実施の形態に係わるボンディング工程
で、封止樹脂付ICチップ、位置決め工程、接合工程を
示す説明図である。
FIG. 3 is an explanatory diagram showing an IC chip with a sealing resin, a positioning process, and a bonding process in the bonding process according to the embodiment of the present invention.

【図4】従来の突起電極付ICチップの実装工程で、基
板、封止フィルム貼り付け工程、封止フィルム熱圧着工
程、カバーフィルム剥離工程、実装工程、完成を示す説
明図である。
FIG. 4 is an explanatory diagram showing a substrate, a sealing film attaching process, a sealing film thermocompression bonding process, a cover film peeling process, a mounting process, and a completion in a conventional mounting process of an IC chip with protruding electrodes.

【符号の説明】[Explanation of symbols]

1 ICチップ 2 突起電極 3 パット 4 PV膜 5 封止樹脂 6 カバーフィルム 7 硬化済封止樹脂 8 ボンディングパット 9 基板 10 ソルダーレジスト 11 パターン 12 フィレット 13 封止フィルム 100 実装完成品 200 実装完成品 1 IC chip 2 protruding electrodes 3 putts 4 PV film 5 Sealing resin 6 cover film 7 Cured sealing resin 8 bonding pads 9 substrates 10 Solder resist 11 patterns 12 fillets 13 Sealing film 100 finished products 200 finished product

Claims (11)

【特許請求の範囲】[Claims] 【請求項1】 パット上に突起電極を有するICチップ
を回路基板上に接続する実装方法であって、少なくとも
前記ICチップの実装面に封止樹脂を接着する接着工程
と、封止樹脂付ICチップと前記回路基板とを接合する
実装工程とを包含することを特徴とする突起電極付IC
チップの実装方法。
1. A mounting method for connecting an IC chip having a protruding electrode on a pad to a circuit board, the bonding step including bonding a sealing resin to at least a mounting surface of the IC chip, and an IC with a sealing resin. An IC with a bump electrode including a mounting step of joining a chip and the circuit board
Chip mounting method.
【請求項2】 前記封止樹脂は、少なくとも熱硬化性樹
脂と熱可塑性樹脂とを包含することを特徴とする請求項
1記載の突起電極付ICチップの実装方法。
2. The method of mounting an IC chip with protruding electrodes according to claim 1, wherein the sealing resin includes at least a thermosetting resin and a thermoplastic resin.
【請求項3】 前記接着工程の熱硬化性樹脂は、Aステ
ージ樹脂であることを特徴とする請求項2記載の突起電
極付ICチップの実装方法。
3. The mounting method of an IC chip with a protruding electrode according to claim 2, wherein the thermosetting resin in the bonding step is an A stage resin.
【請求項4】 前記実装工程は、前記封止樹脂付ICチ
ップと前記回路基板とを電気的に接合するボンディング
工程と、前記封止樹脂を硬化する硬化工程とからなるこ
とを特徴とする請求項1から3記載の突起電極付ICチ
ップの実装方法。
4. The mounting step comprises a bonding step of electrically joining the IC chip with sealing resin and the circuit board, and a curing step of curing the sealing resin. Item 4. A method for mounting an IC chip with a protruding electrode according to items 1 to 3.
【請求項5】 前記ボンディング工程は、前記封止樹脂
付ICチップの突起電極と前記回路基板とを位置合わせ
する位置決め工程と、前記突起電極と前記回路基板とを
電気的に接合する接合工程とからなることを特徴とする
請求項4記載の突起電極付ICチップの実装方法。
5. The bonding step includes a positioning step of aligning a protruding electrode of the IC chip with a sealing resin and the circuit board, and a bonding step of electrically bonding the protruding electrode and the circuit board. 5. The method for mounting an IC chip with protruding electrodes according to claim 4, comprising:
【請求項6】 前記位置決め工程の際の温度は、前記熱
可塑性樹脂の軟化温度よりも高く、前記熱硬化性樹脂の
反応開始温度よりも低いことを特徴とする請求項5記載
の突起電極付ICチップの実装方法。
6. The protrusion electrode according to claim 5, wherein the temperature in the positioning step is higher than the softening temperature of the thermoplastic resin and lower than the reaction start temperature of the thermosetting resin. IC chip mounting method.
【請求項7】 前記接合工程は、熱プレス法を用いるこ
とを特徴とする請求項5記載の突起電極付ICチップの
実装方法。
7. The method of mounting an IC chip with protruding electrodes according to claim 5, wherein the joining step uses a hot pressing method.
【請求項8】 前記接着工程は、前記封止樹脂を前記I
Cチップの実装面の面積とほぼ同じ大きさで、前記IC
チップの実装面に接着させる工程を包含することを特徴
とする請求項1から7記載の突起電極付ICチップの実
装方法。
8. The step of attaching the sealing resin to the I
The size of the IC is about the same as the area of the mounting surface of the C chip.
8. The method of mounting an IC chip with a protruding electrode according to claim 1, further comprising the step of adhering to the mounting surface of the chip.
【請求項9】 前記突起電極は、金を主成分としている
ことを特徴とする請求項1から8記載の突起電極付IC
チップの実装方法。
9. The IC with a bump electrode according to claim 1, wherein the bump electrode has gold as a main component.
Chip mounting method.
【請求項10】 前記突起電極は、ワイヤーボンディン
グ法により形成されていることを特徴とする請求項9記
載の突起電極付ICチップの実装方法。
10. The method of mounting an IC chip with a protruding electrode according to claim 9, wherein the protruding electrode is formed by a wire bonding method.
【請求項11】 前記回路基板上のボンディングパット
は、予めハンダ処理がなされていることを特徴とする請
求項1から10記載の突起電極付ICチップの実装方
法。
11. The mounting method of an IC chip with a bump electrode according to claim 1, wherein the bonding pad on the circuit board is soldered in advance.
JP2001281309A 2001-09-17 2001-09-17 Method of mounting ic chip having projecting electrode Pending JP2003092311A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001281309A JP2003092311A (en) 2001-09-17 2001-09-17 Method of mounting ic chip having projecting electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001281309A JP2003092311A (en) 2001-09-17 2001-09-17 Method of mounting ic chip having projecting electrode

Publications (1)

Publication Number Publication Date
JP2003092311A true JP2003092311A (en) 2003-03-28

Family

ID=19105155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001281309A Pending JP2003092311A (en) 2001-09-17 2001-09-17 Method of mounting ic chip having projecting electrode

Country Status (1)

Country Link
JP (1) JP2003092311A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009094353A (en) * 2007-10-10 2009-04-30 Furukawa Electric Co Ltd:The Semiconductor device and method of manufacturing the same
US10354985B2 (en) 2016-06-15 2019-07-16 Samsung Electronics Co., Ltd. Semiconductor device having stacked semiconductor chips and method for fabricating the same

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1197578A (en) * 1997-09-22 1999-04-09 Hitachi Ltd Semiconductor device and manufacture therefor
JPH11274241A (en) * 1998-03-26 1999-10-08 Matsushita Electron Corp Producing method for semiconductor device
JP2000124164A (en) * 1998-10-16 2000-04-28 Mitsubishi Electric Corp Manufacture of semiconductor device and mounting method thereof
JP2001093926A (en) * 1999-07-16 2001-04-06 Matsushita Electric Ind Co Ltd Semiconductor element package and manufacturing method
JP2002299378A (en) * 2001-03-30 2002-10-11 Lintec Corp Adhesive sheet with conductor, method for manufacturing semiconductor device and the semiconductor device
JP2003077944A (en) * 2001-06-22 2003-03-14 Nitto Denko Corp Method of manufacturing semiconductor wafer with adhesive film
JP2004512684A (en) * 2000-10-17 2004-04-22 スリーエム イノベイティブ プロパティズ カンパニー Solvent burnishing of pre-underfilled solder bump wafers for flip chip bonding

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1197578A (en) * 1997-09-22 1999-04-09 Hitachi Ltd Semiconductor device and manufacture therefor
JPH11274241A (en) * 1998-03-26 1999-10-08 Matsushita Electron Corp Producing method for semiconductor device
JP2000124164A (en) * 1998-10-16 2000-04-28 Mitsubishi Electric Corp Manufacture of semiconductor device and mounting method thereof
JP2001093926A (en) * 1999-07-16 2001-04-06 Matsushita Electric Ind Co Ltd Semiconductor element package and manufacturing method
JP2004512684A (en) * 2000-10-17 2004-04-22 スリーエム イノベイティブ プロパティズ カンパニー Solvent burnishing of pre-underfilled solder bump wafers for flip chip bonding
JP2002299378A (en) * 2001-03-30 2002-10-11 Lintec Corp Adhesive sheet with conductor, method for manufacturing semiconductor device and the semiconductor device
JP2003077944A (en) * 2001-06-22 2003-03-14 Nitto Denko Corp Method of manufacturing semiconductor wafer with adhesive film

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009094353A (en) * 2007-10-10 2009-04-30 Furukawa Electric Co Ltd:The Semiconductor device and method of manufacturing the same
US10354985B2 (en) 2016-06-15 2019-07-16 Samsung Electronics Co., Ltd. Semiconductor device having stacked semiconductor chips and method for fabricating the same
US10923465B2 (en) 2016-06-15 2021-02-16 Samsung Electronics Co., Ltd. Semiconductor device having stacked semiconductor chips and method for fabricating the same

Similar Documents

Publication Publication Date Title
TW501208B (en) Semiconductor device and manufacturing method of the same
JP3297254B2 (en) Semiconductor package and manufacturing method thereof
US6214642B1 (en) Area array stud bump flip chip device and assembly process
US7242433B2 (en) Small-sized image pickup device having a solid-state image pickup element and a lens holder mounted on opposite sides of a transparent substrate
US6515357B2 (en) Semiconductor package and semiconductor package fabrication method
US7598121B2 (en) Method of manufacturing a semiconductor device
KR100352865B1 (en) Semiconductor device and method for manufacturing the same
US6518649B1 (en) Tape carrier type semiconductor device with gold/gold bonding of leads to bumps
JP2003007902A (en) Electronic component mounting substrate and mounting structure
JP3836349B2 (en) Semiconductor device and manufacturing method thereof
JP4151136B2 (en) Substrate, semiconductor device and manufacturing method thereof
JP3705159B2 (en) Manufacturing method of semiconductor device
JP2000286302A (en) Method and device for assembling semiconductor chip
KR100379823B1 (en) Manufacturing method of semiconductor integrated circuit device
JP2003092311A (en) Method of mounting ic chip having projecting electrode
JP4035949B2 (en) Wiring board, semiconductor device using the same, and manufacturing method thereof
JPH0551179B2 (en)
JPH10125734A (en) Semiconductor unit and manufacturing method thereof
JP3419398B2 (en) Method for manufacturing semiconductor device
JP3721986B2 (en) Semiconductor device and manufacturing method thereof
JP2000277566A (en) Electronic part unit and its manufacture
JP3674550B2 (en) Semiconductor device
JP2002151643A (en) Semiconductor device
JP2003092310A (en) Ic chip having projected electrode with seal resin
JP2005038913A (en) Packaging method of electronic component

Legal Events

Date Code Title Description
A621 Written request for application examination

Effective date: 20080909

Free format text: JAPANESE INTERMEDIATE CODE: A621

A977 Report on retrieval

Effective date: 20101018

Free format text: JAPANESE INTERMEDIATE CODE: A971007

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101109

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20110308