JP2003087140A - Digital broadcast receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital broadcast receiver capable of reducing power while a TS null packet is reproduced or RS decoding processing does not have to be performed. SOLUTION: A TS packet reproducing means 13a outputs a null TS signal NTS showing a TS null (invalid) packet for time adjustment if a TS packet to be reproduced is the TS null packet, and is provided with a clock signal supply stop means 300 arranged on a supply path of a clock signal used in at least one circuit part on a stage subsequent to the TS packet reproducing means 13a in an error correction/decoding block 12 and for stopping the supply of a clock signal CLK 2 in the case of receiving the null TS signal NTS.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a terrestrial digital television broadcasting receiver and a terrestrial digital audio broadcasting receiver.

[0002]

2. Description of the Related Art Currently, digitization of television broadcasting and radio broadcasting is being promoted, and terrestrial digital television broadcasting and terrestrial digital audio broadcasting will be realized following the digitization of satellite broadcasting. .

Broadcasting systems of terrestrial digital television broadcasting and terrestrial digital audio broadcasting are described in "Technical conditions of terrestrial digital television broadcasting system" in the report of the Digital Broadcasting System Committee of the Telecommunications Technology Council, and electrical It is common to comply with the "technical conditions for terrestrial digital audio broadcasting systems" reported by the Communications Technology Council.

FIG. 18 is a diagram showing an example of a terrestrial digital television broadcast receiver of the above-mentioned general broadcasting system. In addition, this block diagram is described in, for example, Journal of the Institute of Image Information and Television Engineers Vol. 54, No. 6. p. 905 OFDM (Orthogonal Frequency)
This corresponds to a detailed configuration of the Division Multiplex (Receiver) receiver.

In FIG. 18, a tuner 1 for digital television broadcasting is a VHF band (about 90 MHz to about 20 MHz).
0 MHZ) or the UHF band (about 470 MHZ to about 770 MHZ), the band of the broadcast channel desired by the user is received. Then, the received wave is, for example, 57
IF (Intermedia) centered on MHz
te Frequency).

The output of the SAW filter 2 is IF
The IF conversion circuit 3 supplies the IF to the conversion circuit 3.
Is converted into a local frequency having a center frequency of 4.1 MHz, for example.

The low-pass filter 4 is the SAW filter 2
In subsequent processing steps, harmonic noise and the like mixed in the received signal are removed from the output signal of the IF conversion circuit 3.
Then, the output of the low-pass filter 4 is converted into a digital signal by the AD converter 6 and input to the time domain processing unit 8 in the OFDM demodulation unit 7.

The time domain processing unit 8 is a block that performs signal processing on the received wave expressed in the time domain, and performs timing detection and adjustment from the guard interval signal in the received wave, for example. Further, the time domain processing unit 8 uses the timing of the detected received wave to detect V
CXO (Voltage Controlled X)
Tally Oscillator 19 is controlled. The control signal to the VCXO 19 is the DA converter 1
At 8, the digital signal is converted into an analog signal. Further, the VCXO 19 is a compliant clock (512/63) MHZ = 8.12 of the terrestrial digital television broadcasting system.
It is possible to generate a clock signal of 32.5 MHZ, which is four times the MHZ.

Clock signal CL generated by VCXO 19
K1 is the time domain processing unit 8, FFT (Fast F
The input signal is input to the user Transform unit 9, the frequency domain processing unit 10, the deinterleave unit 11, and the error correction / decoding block 12, and serves as an operation clock for each unit.

The output of the time domain processing unit 8 is given to the FFT unit 9 and is subjected to a fast Fourier transform process for calculating the frequencies and signal intensities of a plurality of carriers (carrier waves) included in the output thereof and subjected to the frequency domain. It becomes the signal of.

The output of the FFT unit 9 is given to the frequency domain processing unit 10. In the frequency domain processing unit 10, a frequency shift of the carrier in the received wave converted into the frequency domain is detected and correction is performed using a PLL circuit or the like. Further, the frequency domain processing unit 10 also performs OFDM synchronous / differential demodulation processing.

The output of the frequency domain processing section 10 is given to the deinterleaving section 11 where deinterleaving processing is performed. Then, the output of the deinterleaving unit 11 is given to the error correction / decoding block 12, where
Error correction processing and decoding processing are performed. In addition,
According to the above regulations regarding digital television broadcasting, it is possible to set up to three layers as a transmission method, and the depth of deinterleaving processing, the convolutional coding rate in error processing, etc. should correspond to each layer. Can be converted.

In the error correction / decoding block 12, first, the TS packet reproducing unit 13 (TS packet reproducing means).
Playback of TS (Transport Stream) packets is performed. In reproducing the TS packet, the input signal is accumulated for each of the above layers until the data amount of one TS packet is accumulated, and when the accumulation of the signal for one TS packet is completed, the signal is output to the Viterbi composite unit 14 in the subsequent stage. 1
A null (invalid) TS packet is created and output until the data for the TS packet is accumulated. Usually T
An information bit indicating that the TS packet is a TS null packet is inserted in the S null packet, and meaningless data such as "0" is entered in the data area.

The Viterbi decoding unit 14 performs Viterbi decoding on the input signal and performs error correction. The Viterbi-decoded data is converted from symbols to bytes and output to the byte deinterleave unit 15 (byte deinterleave means).

The byte interleaving unit 15 independently performs convolutional byte deinterleaving on the input TS packet for each layer. T created by the TS packet reproducing unit 13
Deinterleaving is not performed on S null packets.

The output of the byte deinterleave unit 15 is given to the energy despreading unit 16 (energy despreading means). Similarly to the byte deinterleave unit 15, the energy despreading unit 16 also performs energy despreading independently on the input TS packet of each layer, and the energy despreading is performed on the TS null packet created by the TS packet reproducing unit 13. Do not process.

The T output from the energy despreading unit 16
The S packet is sent to the RS (Reed Solomon) decoding unit 17 (R
S decoding means). The RS decoding unit 17 can perform error correction up to 8 bytes on the input TS packet.

FIG. 19 is a diagram showing an internal circuit block of the RS decoding section 17 of FIG. The data of the input TS packet is stored in the memory 106 and the syndrome calculation circuit 100.
(Syndrome calculation means). Memory 106
Delays the data until the RS decoding process is completed and the packet data error can be corrected. The syndrome calculation circuit 100 calculates an error syndrome value from the data of the input TS packet.

The error syndrome calculated by the syndrome calculation circuit 100 is given to the error position polynomial calculation unit 101 and the error numerical value polynomial calculation unit 102 in the error calculation circuit 107 (error calculation means). Error locator polynomial calculator 1
In 01, a polynomial in which a value indicating an error position is a solution is calculated using the given error syndrome. On the other hand, the error numerical value polynomial calculation unit 102 calculates a polynomial whose error magnitude (numerical value) is a solution using the given error syndrome. The error locator polynomial calculated by the error locator polynomial calculator 101 is output to the error locator calculator 103.
The error value polynomial calculated by the error value polynomial calculation unit 102 is provided to the error value calculation unit 104.

The error position calculator 103 calculates the solution of the given error position polynomial and specifies the error position. The error position information, which is the solution of the error position polynomial, is given to the error value calculation unit 104.

From the error value polynomial given by the error value polynomial calculation unit 102 and the error value information given by the error position calculation unit 103, the error value calculation unit 104
Calculates the error magnitude for each of the plurality of error positions. Calculated error size (error value)
Then, the error position information is output to the error correction output circuit 105.

In the error correction output circuit 105, the memory 10
The data delayed from 6 is read, and the data in the TS packet indicated by the error position information calculated in the preceding stage is corrected according to the calculated error numerical value and output.

[0023]

The receiver of the terrestrial digital television broadcasting and the terrestrial digital audio broadcasting constructed as described above has an error correction / decoding block 1
It is necessary for the byte deinterleave unit 15 and the energy despreading unit 16 in No. 2 to independently process a plurality of transmission layers.

Further, since it is necessary to make the processing independent for each of a plurality of layers, a byte deinterleave unit and an energy despreading unit are individually provided for each layer, and in the terrestrial digital television broadcasting, a total is provided. In order to process three layers, as shown in FIG. 18, three sets of interleaving units and energy despreading units in parallel are required.

By the way, the TS packets output from the TS packet reproducing section 13 are time-multiplexed one TS packet at a time and output. FIG. 20 shows the TS packet reproducing unit 13.
It is a figure showing an example of a TS packet time-multiplexed and outputted from. As shown in FIG. 20, in the time-multiplexed output of TS packets, TS null packets 203 and 205 for time adjustment are multiplexed together with TS packets 201, 202 and 204 belonging to one of the layers.

Therefore, while the TS packet belonging to any of the layers is being output from the TS packet reproducing unit 13, the interleaving unit and the energy despreading unit for the TS packets belonging to the layers other than the corresponding layer are No need to do anything.

Further, during the period when the TS null packet is being output from the TS packet reproducing unit 13, all the circuit parts arranged in the subsequent stage of the TS packet reproducing unit 13, that is, the byte deinterleave unit 15 and the energy despreading unit. Part 16,
The RS decoding unit 17 does not need to perform processing.

For example, in the terrestrial digital broadcasting system, the period in which TS null packets are output from the TS packet reproducing unit 13 may correspond to about 7/8 of the total period if there are many periods.

Usually, an enable signal is used for stopping and executing such a process, and the process operation is stopped by the enable signal during a period when the process is not required. However, even if the processing operation is stopped by the enable signal, if the clock signal is supplied, the power is consumed in each circuit unit even during the period when the processing is not required, and each block / each unit is consumed. It does not mean that the electricity is effectively used in.

Even during the period in which the processing is not necessary, there is a problem that the power is wasted because the clock is supplied, and there is room for reducing the power.

Further, the syndrome calculating circuit 100 in the RS decoding unit 17 can judge whether or not the received TS packet includes error data, but it is judged that the TS packet does not include an error. In this case, the error number polynomial calculation unit 102, the error position polynomial calculation unit 101, the error number calculation unit 104, and the error position calculation unit 103 in the subsequent stage do not need to perform the processing. Since it is determined that there is no error in this way, there is a problem that power is wasted during the period when no processing is required, and there is room for power reduction.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to reduce the power consumption during the period in which the TS null packet is reproduced or the period in which the RS decoding process is unnecessary. To provide a broadcast receiver, and to provide a digital broadcast receiver capable of reducing power of a circuit unnecessary for processing other layers during a period when TS packets of different layers are being reproduced. It is an object.

[0033]

In order to achieve the above-mentioned object, a digital broadcast receiving apparatus of the present invention according to claim 1 is a clock for demodulating a received signal of a digital television broadcast or a digital audio broadcast. An error correction / decoding block that receives a signal and performs error correction and decoding processing is provided, and the error correction / decoding block is
A digital broadcast receiving apparatus having TS packet reproducing means for classifying and reproducing a plurality of hierarchical TS packets for each layer, wherein the TS packet reproducing means is a TS to be reproduced.
If the packet is a TS null packet for time adjustment, a null TS signal indicating the packet is output, and a clock used in at least one circuit unit subsequent to the TS packet reproducing means in the error correction / decoding block. It is characterized in that it is provided on a signal supply path and is provided with a clock signal supply stopping means for stopping the supply of the clock signal when the null TS signal is received.

Further, in the present invention described in claim 2, in the digital broadcast receiving apparatus according to claim 1, the error correction / decoding block has an RS decoding means for performing error correction of the reproduced TS packet data. However, the clock signal supply stopping means is installed on the supply path of the clock signal used in at least a part of the RS decoding means.

According to a third aspect of the present invention, in the digital broadcast receiving apparatus according to the second aspect, the RS decoding means has a syndrome calculating means for calculating an error syndrome, and the clock signal supply stopping means has a syndrome. It is characterized in that it is installed on the supply path of the clock signal used for the calculation means.

According to a fourth aspect of the present invention, in the digital broadcast receiving apparatus according to the second aspect, the RS decoding means includes an error calculating means for calculating an error position and an error value, and a clock signal supply stopping means. Is installed on the supply path of the clock signal used for the error calculating means.

The present invention according to claim 5 is the digital broadcast receiving apparatus according to claim 2, wherein the RS decoding means delays the reproduced TS packet data until an error value is calculated. A memory is provided, and the clock signal supply stopping means is installed on the supply path of the clock signal used for the memory.

According to the present invention of claim 6, in the digital broadcast receiving apparatus of claim 1, the error correction / decoding block performs byte deinterleaving on the reproduced TS packet data for each layer. It has a byte deinterleaving means, and the clock signal supply stopping means is installed on the supply path of the clock signal used in the byte deinterleaving means.

[0039] According to the present invention described in claim 7, in the digital broadcast receiver according to claim 1, the error correction / decoding block performs energy despreading on the reproduced TS packet data for each layer. The energy despreading means is provided, and the clock signal supply stopping means is installed on the supply path of the clock signal used in the energy despreading means.

Further, the digital broadcast receiving apparatus of the present invention according to claim 8 carries out error correction and decoding processing on the demodulated output of the received signal of the digital television broadcast or the digital audio broadcast by receiving the supply of the clock signal. A digital broadcast receiving apparatus having a TS packet reproducing means for reproducing a TS packet classified into a plurality of layers by classifying the error correction / decoding block. The reproducing means outputs a TS layer signal indicating the layer of the TS packet to be reproduced, and the error correction / decoding block has a byte deinterleave means for performing byte deinterleaving on the reproduced TS packet data for each layer. The byte deinterleaver is installed on the supply path of the clock signal used in each layer in the hierarchy, When receiving the layer signals, and supplies a clock signal only to the hierarchy specified by TS layer signals, for another layer, characterized in that it comprises a clock signal supply selecting means for stopping the supply.

Further, the digital broadcast receiving apparatus of the present invention according to claim 9 carries out error correction and decoding processing on the demodulated output of the received signal of the digital television broadcast or the digital audio broadcast by receiving the supply of the clock signal. A digital broadcast receiving apparatus having a TS packet reproducing means for reproducing a TS packet classified into a plurality of layers by classifying the error correction / decoding block. The reproducing unit outputs a TS layer signal indicating the layer of the TS packet to be reproduced, and the error correction / decoding block has an energy despreading unit that despreads the reproduced TS packet data for each layer. It is installed on the supply path of the clock signal used in each layer in the energy despreading means and receives the TS layer signal. If it, supplies a clock signal only to the hierarchy specified by TS layer signals, for another layer, characterized in that it comprises a clock signal supply selecting means for stopping the supply.

According to the tenth aspect of the present invention, the digital broadcast receiving apparatus performs error correction and decoding processing on the demodulated output of a received signal of digital television broadcast or digital audio broadcast by receiving a clock signal. Error correction / decoding block, and the error correction / decoding block includes a syndrome calculation means for calculating an error syndrome and an error position and an error value in an RS decoding means for performing error correction on the reproduced TS packet data. A digital broadcast receiving apparatus comprising error calculating means for calculating, wherein the syndrome calculating means outputs an error zero signal indicating that there is no error in the received packet data when the calculated syndrome value is zero error. Installed on the supply path of the clock signal used by the error calculation means, When receiving the items, characterized in that it comprises a clock signal supply stop means for stopping the supply of the clock signal.

[0043]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on the illustrated embodiments. Embodiment 1. In the digital broadcast receiving apparatus of this embodiment, when a TS null packet is output from the TS packet reproducing unit in the error correction / decoding block, the clock signal supplied to the syndrome calculating circuit in the RS decoding unit is stopped. As configured.

FIG. 1 is a block diagram showing the structure of an error correction / decoding block in the digital broadcast receiving apparatus according to the first embodiment of the present invention. In the following description based on FIG. 1, parts having the same functions as those of the error correction / decoding block in the conventional digital broadcast receiving apparatus shown in FIGS. Is omitted.

The error correction / decoding block 12 of FIG. 1 differs from the structure of the error correction / decoding block in the conventional digital broadcast receiving apparatus shown in FIG. 18 in that the TS packet reproducing unit 13a outputs a TS null packet. When a null TS signal is received, the clock signal CLK1 generated by the VCXO 19 is supplied to the syndrome calculation circuit 100 in the RS decoding unit 17 when the null TS signal is received. Of the clock signal CLK2 from the clock signal supply stopping unit 300 when the null TS signal is not received.
Is the point of supply. Other configurations are similar to those of the error correction / decoding block in the conventional digital broadcast receiving apparatus shown in FIG.

The configuration and operation of the TS packet reproducing unit 13a will be described in order to explain that the TS packet reproducing unit 13a outputs a null TS signal when outputting a TS null packet.

FIG. 2A shows the TS packet reproducing unit 13a.
2B shows a state in which the reproduced TS packet and TS null packet are output.

As shown in FIG. 2A, the TS packet reproducing unit 13a has a layer (1) TS buffer 401 and a layer (2) which store received data for each layer of layers (1) to (3). TS buffer 402, layer (3) TS buffer 4
03 and output as TS packets reproduced by switching the connection with each TS buffer 401 to 403, and not output from any TS buffer when the accumulated data in each TS buffer 401 to 403 is insufficient. And a switching means 404 for outputting a TS null packet.

As shown in FIG. 2B, each of the TS buffers 401 to 403 receives the input received data from the (1) th layer to the lower layer.
When the data is accumulated for each layer of the layer (3) and all the data of the TS packet of a certain layer is accumulated, a predetermined timing (for example, the interval T of 204 bytes of the TS packet shown in FIG. ...) reads all the data of the layer from the buffer and outputs it as a reproduced TS packet. Further, when all the data for the TS packet of the layer is not stored in any of the buffers, the TS packet reproducing unit 13a creates and outputs a TS null (invalid) packet during that period. The TS null packet is not a TS packet composed of received data, but an invalid packet inserted for time adjustment.

The TS packet output from the TS packet reproducing unit 13a is Viterbi decoded by the Viterbi decoding unit 14,
Byte deinterleave unit 1 provided independently for each layer
5 and the energy despreading unit 16, are subjected to byte deinterleaving and energy despreading processing, and are output to the RS decoding unit 17.

Next, in the present embodiment, when the null TS signal is received, the clock signal supply stopping unit 300 stops the clock supply to the syndrome calculating circuit 100 in the RS decoding unit 17, The reason why this is possible will be described.

First, in the RS decoding section 17, the input TS packet data is distributed and supplied to the memory 106 and the syndrome calculating circuit 100. In other words, the input data remains in the memory 106 even if the syndrome calculation circuit 100 disappears.

The syndrome calculating circuit 100 calculates an error syndrome from the input TS packet data. The syndrome value calculated by the syndrome calculation circuit 100 is an all-zero value, which is the syndrome value when there is no error in the input TS packet, and is an all-zero value when an error is included. The value other than the value is output to the error calculation circuit 107 in the next stage.

By the way, when a null TS signal is received,
That is, when the TS null packet created by the TS packet reproducing unit 13a is input to the RS decoding unit 17, since the TS null packet cannot contain error data, the syndrome calculation circuit 100
The syndrome calculated by is the value of all zeros, which is the syndrome value when there is no error. Therefore,
When the null TS signal is received, that is, when the TS null packet is input, it is not necessary to calculate the syndrome value by the syndrome calculation circuit 100, and it means that the syndrome value is all zero at any time.

Therefore, in the present embodiment, during the period in which the TS null packet is output, the TS reproducing unit 13a transmits the null TS signal NTS to the clock signal supply stopping unit 300, and the clock signal supply stopping unit 300 calculates the syndrome. The clock signal supplied to the circuit 100 is stopped.
By stopping the supply of this clock signal, in the syndrome calculation circuit 100, all processing operations are temporarily stopped (interrupted).

FIG. 3 is a flow chart showing the operation of stopping the clock signal supply in the first embodiment. The clock signal supply stopping unit 300 includes the TS packet reproducing unit 13a.
By determining whether or not the null TS signal NTS is received, it is determined whether or not the reproduced TS packet output from the TS packet reproducing unit 13a is a TS null packet (S1).

The clock signal supply stopping unit 300 outputs the TS packet output from the TS packet reproducing unit 13a to the TS packet.
When it is determined that the packet is a null packet (S1: YES), the clock signal CL to the syndrome calculation circuit 100 is output.
The supply of K2 is stopped (S2).

On the other hand, the clock signal supply stopping unit 300
When it is determined that the TS packet output from the TS packet reproduction unit 13a is not a TS null packet but a valid TS packet (S1: NO), the clock signal CLK2 is supplied to the syndrome calculation circuit 100 (S3). ).

As described above, in this embodiment, the null TS
By stopping the supply of the clock signal when the signal NTS is received, it is possible to stop all the processing operations of the syndrome calculation circuit 100 and suppress power consumption. Therefore, it is possible to reduce the power consumption of the syndrome calculation circuit 100 during the output period of the TS null packet, which is a maximum of 7/8 in the output period of the reproduced TS packet as described above, and thus the digital broadcast receiving apparatus. The overall power consumption can be greatly reduced.

Embodiment 2. In the above-described first embodiment, the clock signal supplied to the syndrome calculation circuit in the RS decoding unit is stopped when the TS null packet is output from the TS packet reproducing unit in the error correction / decoding block. In the second embodiment described below, the TS
When a TS null packet is output from the packet reproduction unit, the clock signal supplied to the error calculation circuit in the RS decoding unit is stopped.

FIG. 4 is a block diagram showing the structure of the error correction / decoding block in the digital broadcast receiving apparatus according to the second embodiment of the present invention. The error correction / decoding block 12 in FIG. 4 differs from the error correction / decoding block in the digital broadcast receiving apparatus according to the first embodiment shown in FIG. 1 in that the clock signal CLK generated by the VCXO 19 is used.
A clock signal supply stopping unit 301 (clock signal supply stopping means) for stopping the supply of the clock signal CLK3 when a null TS signal is received is provided in the middle of the route in which 1 is supplied to the error calculation circuit 107 in the RS decoding unit 17. Prepare, null TS
Clock signal supply stop unit 301 when no signal is received
Is the point at which the clock signal CLK3 is supplied from. Other configurations are similar to those of the error correction / decoding block in the digital broadcast receiving apparatus according to the first embodiment shown in FIG.

The error calculation circuit 107 is the error calculation circuit in the RS decoding unit 12 as described above with reference to FIG. 19, and is included in the input TS packet according to the syndrome value output from the syndrome calculation circuit 100. The error position and the error magnitude (numerical value) are calculated.

As in the first embodiment described above, also in the present embodiment, when the TS null packet created by the TS packet reproducing unit 13a is input to the RS decoding unit 17, the TS null packet contains error data. Is not included, the error position and the error numerical value calculated by the error calculating circuit 107 are all zero values which are the values when there is no error. Therefore, when the TS null packet is input, it is not necessary to calculate the error position and the error numerical value.

Therefore, in the present embodiment, during the period in which the TS null packet is output, the TS reproducing unit 13a transmits the null TS signal NTS to the clock signal supply stopping unit 301, and the clock signal supply stopping unit 301 calculates an error. The clock signal supplied to the circuit 107 is stopped. By stopping the supply of this clock signal, all the processing operations in the error calculation circuit 107 are temporarily stopped (interrupted).

FIG. 5 is a flow chart showing the operation of stopping the clock signal supply in the second embodiment. The clock signal supply stopping unit 301 includes the TS packet reproducing unit 13a.
By determining whether or not the null TS signal NTS is received, it is determined whether or not the reproduced TS packet output from the TS packet reproducing unit 13a is a TS null packet (S11).

The clock signal supply stopping unit 301 receives the TS packet output from the TS packet reproducing unit 13a as the TS packet.
When it is determined that the packet is a null packet (S11: YES)
First, the supply of the clock signal CLK3 to the error calculation circuit 107 is stopped (S12).

On the other hand, the clock signal supply stopping unit 301
When it is determined that the TS packet output from the TS packet reproduction unit 13a is not a TS null packet but a valid TS packet (S11: NO), the error calculation circuit 1
Clock signal CLK3 is supplied to 07 (S1
3).

As described above, in this embodiment, the null TS
By stopping the supply of the clock signal when the signal NTS is received, it is possible to stop all the processing operations of the error calculation circuit 107 and suppress power consumption. Therefore, it is possible to reduce the power consumption of the error calculation circuit 107 in the output period of the TS null packet, which is a maximum of 7/8 in the output period of the reproduced TS packet as described above. The overall power consumption can be greatly reduced.

Third Embodiment In the first embodiment described above, when the TS null packet is output from the TS packet reproducing unit in the error correction / decoding block, the clock signal supplied to the syndrome calculating circuit in the RS decoding unit is stopped, In 2, the clock signal supplied to the error calculation circuit in the RS decoding unit is stopped, but in the third embodiment described below, the TS packet reproduction unit outputs T
When the S null packet is output, the clock signal supplied to the memory in the RS decoding unit is stopped.

FIG. 6 is a block diagram showing the structure of an error correction / decoding block in the digital broadcast receiving apparatus according to the third embodiment of the present invention. The error correction / decoding block 12 in FIG. 6 differs from the error correction / decoding block in the digital broadcast receiving apparatus according to the first embodiment shown in FIG. 1 in that the clock signal CLK generated by the VCXO 19 is used.
1 is supplied to the memory 106 in the RS decoding unit 17, the clock signal C is received when a null TS signal is received.
Clock signal supply stopping unit 302 for stopping the supply of LK4
The point is that (clock signal supply stopping means) is provided and the clock signal CLK4 is supplied from the clock signal supply stopping unit 302 when the null TS signal is not received. Other configurations are similar to those of the error correction / decoding block in the digital broadcast receiving apparatus according to the first embodiment shown in FIG.

Further, the memory 106 of this embodiment is
In the S decoding unit 17, the TS reproduced from the received data
This is for delaying and outputting the packet, and when the supply of the clock signal CLK4 is stopped, the TS packet is allowed to pass without being delayed (writing / accumulation / reading is not executed).

In the first and second embodiments described above, TS
When the TS null packet created by the packet reproducing unit 13a is input to the RS decoding unit 17, the TS null packet does not include error data.
The error position and the error numerical value calculated by the error calculation circuit 107 have been used that they are all zero values which are values in the case of no error. However, in the present embodiment, the TS null packet is known data. The fact that the TS null packet can be reproduced by the RS decoding unit 17 does not need to be stored in the memory 106 and delayed, which is utilized.

Therefore, in the present embodiment, during the period in which the TS null packet is output, the TS reproducing unit 13a transmits the null TS signal NTS to the clock signal supply stopping unit 302, and the clock signal supply stopping unit 302 causes the memory 106.
Stop the clock signal supplied to. By stopping the supply of this clock signal, in the memory 106,
All processing operations are temporarily stopped (suspended)
The TS null packet is reproduced by the error correction output circuit 105.

FIG. 7 is a flow chart showing the operation of stopping the clock signal supply in the third embodiment. The clock signal supply stopping unit 302 includes the TS packet reproducing unit 13a.
By determining whether or not the null TS signal NTS is received, it is determined whether or not the reproduced TS packet output from the TS packet reproducing unit 13a is a TS null packet (S21).

The clock signal supply stopping unit 302 outputs the TS packet output from the TS packet reproducing unit 13a to the TS packet.
When it is determined that the packet is a null packet (S21: YES)
First, the supply of the clock signal CLK4 to the memory 106 is stopped (S22).

On the other hand, the clock signal supply stopping unit 302
When it is determined that the TS packet output from the TS packet reproducing unit 13a is not a TS null packet but a valid TS packet (S21: NO), the clock signal CLK4 is supplied to the memory 106 (S23).

As described above, in this embodiment, the null TS
By stopping the supply of the clock signal when the signal NTS is received, the delay (writing / accumulating / reading) processing operation in the memory 106 can be stopped and power consumption can be suppressed. Therefore, as described above, the memory 106 in the output period of the TS null packets, which has a maximum ratio of 7/8 in the output period of the reproduced TS packets,
Since the power consumption of the digital broadcast receiving apparatus can be reduced, the power consumption of the entire digital broadcast receiving apparatus can be greatly reduced.

Fourth Embodiment Embodiments 1 to 3 described above
Then, when the TS null packet is output from the TS packet reproducing unit in the error correction / decoding block, the clock signal supplied to a part of the circuit in the RS decoding unit is stopped. In the form 4, the clock signal supplied to the byte deinterleave unit in the error correction / decoding block is stopped when the TS null packet is output from the TS packet reproducing unit.

FIG. 8 is a block diagram showing the structure of an error correction / decoding block in the digital broadcast receiving apparatus according to the fourth embodiment of the present invention. The error correction / decoding block 12 in FIG. 8 differs from the error correction / decoding block in the digital broadcast receiving apparatus according to the first embodiment shown in FIG. 1 in that the clock signal CLK generated by the VCXO 19 is used.
When a null TS signal is received on the way of 1 being supplied to the byte deinterleave unit 15, the clock signal CL
Clock signal supply stopping unit 303 for stopping the supply of K5
(Clock signal supply stopping means) is provided, and the clock signal CLK5 is supplied from the clock signal supply stopping unit 303 when the null TS signal is not received. Other configurations are similar to those of the error correction / decoding block in the digital broadcast receiving apparatus according to the first embodiment shown in FIG.

Further, for example, in the terrestrial digital broadcasting system, since up to 3 layers can be used, the convolutional coding rate, the interleave length, etc. can be independently set for each layer, so that the byte deinterleave is possible. The unit 15 also needs to be provided with a plurality (three sets) of processing blocks for each layer. Therefore, the byte deinterleave unit 15 of this embodiment also has the first layer: (1) to the third layer shown in FIG.
Although it is composed of a plurality of layers as in (3), for the clock signal CLK5, the clock signal supply stopping unit 3
The case where the data is supplied to each layer from 03 at once is shown.

The TS packets output from the TS packet reproducing unit 13a are time-multiplexed for each TS packet, and TS packets belonging to a plurality of layers are not output at the same time. Therefore, the byte deinterleave unit 15
It is possible to control the supply of the clock signal for each of the layers, but that point will be described in a sixth embodiment to be described later.

As in the first and second embodiments described above,
When the TS null packet created by the TS packet reproducing unit 13a is input to the byte deinterleave unit 15, since the TS null packet does not include error data, the byte deinterleave unit 15 performs deinterleaving. You don't have to.

Therefore, in the present embodiment, during the period in which the TS null packet is output, the TS reproducing unit 13a transmits the null TS signal NTS to the clock signal supply stopping unit 303, and the clock signal supply stopping unit 303 causes the byte data to stop. The clock signal CLK5 supplied to the interleave unit 15 is stopped. By stopping the supply of the clock signal CLK5, all processing operations are temporarily stopped (interrupted) in the byte deinterleave unit 15, and the TS packet is deinterleaved in the byte deinterleave unit 15. It is passed through without being processed, and is input to the energy despreading unit 16.

FIG. 9 is a flow chart showing the operation of stopping the clock signal supply in the fourth embodiment. The clock signal supply stopping unit 303 uses the TS packet reproducing unit 13a.
By determining whether or not the null TS signal NTS is received, it is determined whether or not the reproduced TS packet output from the TS packet reproducing unit 13a is a TS null packet (S31).

The clock signal supply stopping unit 303 receives the TS packet output from the TS packet reproducing unit 13a as TS.
When it is determined that the packet is a null packet (S31: YES)
Then, the supply of the clock signal CLK5 to the byte deinterleave unit 15 is stopped (S32).

On the other hand, the clock signal supply stopping unit 303
When it is determined that the TS packet output from the TS packet reproducing unit 13a is not a TS null packet but a valid TS packet (S31: NO), the clock signal CLK5 is supplied to the byte deinterleave unit 15 ( S33).

As described above, in this embodiment, the null TS
By stopping the supply of the clock signal when the signal NTS is received, it is possible to stop the deinterleaving processing operation in the byte deinterleaving unit 15 and allow the data to pass as it is, thus suppressing power consumption. Therefore, as described above, it is possible to reduce the power consumption of the byte deinterleave unit 15 during the output period of the TS null packet, which is a maximum of 7/8 in the output period of the reproduced TS packet, and thus the digital broadcast reception The power consumption of the entire device can be greatly reduced.

Embodiment 5. In the fourth embodiment described above, when the TS null packet is output from the TS packet reproducing unit in the error correction / decoding block, the clock signal supplied to the byte deinterleave unit in the error correction / decoding block is stopped. However, in the fifth embodiment described below, the clock signal supplied to the energy despreading unit in the error correction / decoding block is configured to be stopped.

FIG. 10 is a block diagram showing the structure of an error correction / decoding block in the digital broadcast receiving apparatus according to the fifth embodiment of the present invention. The error correction / decoding block 12 in FIG. 10 differs from the error correction / decoding block in the digital broadcast receiving apparatus according to the fourth embodiment shown in FIG. 8 in that the clock signal C generated by the VCXO 19 is different.
When a null TS signal is received on the way of the LK1 being supplied to the energy despreading unit 16, the clock signal CLK is received.
6 is provided with a clock signal supply stopping unit 304 (clock signal supply stopping means), and the clock signal CLK6 is supplied from the clock signal supply stopping unit 304 when the null TS signal is not received. The other configuration is the same as the configuration of the error correction / decoding block in the digital broadcast receiving apparatus according to the fourth embodiment shown in FIG.

Further, for example, in the terrestrial digital broadcasting system, up to 3 layers can be used, and the convolutional coding rate, the interleave length, etc. can be independently set for each layer in the byte deinterleave section 15 in the preceding stage. Therefore, the energy despreading unit 16 also needs to be provided with a plurality of (3 sets) processing blocks for each hierarchy. Therefore, the energy despreading unit 16 of the present embodiment is also composed of a plurality of layers such as the first layer: (1) to the third layer: (3) shown in FIG. , A case where the clock signal supply stopping unit 304 collectively supplies the respective layers.

The TS packets output from the TS packet reproducing unit 13a are time-multiplexed for each TS packet, and TS packets belonging to a plurality of layers are not output at the same time. It is possible to control the supply of the clock signal for each layer, which will be described in a seventh embodiment to be described later.

Similar to the first and second embodiments described above,
When the TS null packet created by the TS packet reproducing unit 13a is input to the energy despreading unit 16, since the TS null packet does not include error data, the energy despreading unit 16 performs energy despreading. It need not be implemented.

Therefore, in this embodiment, during the period in which the TS null packet is output, the TS reproducing unit 13a transmits the null TS signal NTS to the clock signal supply stopping unit 304, and the clock signal supply stopping unit 304 reverses the energy. The clock signal CLK6 supplied to the diffusion unit 16 is stopped. By stopping the supply of the clock signal CLK6, all the processing operations are temporarily stopped (interrupted) in the energy despreading unit 16, and the TS packet causes the energy despreading unit 16 to reverse the energy. The data is passed through without being spread and is input to the RS decoding unit 17.

FIG. 11 is a flow chart showing the operation of stopping the clock signal supply in the fifth embodiment. The clock signal supply stopping unit 304 uses the TS packet reproducing unit 13
By determining whether or not the null TS signal NTS is received from a, it is determined whether or not the reproduced TS packet output from the TS packet reproducing unit 13a is a TS null packet (S41).

The clock signal supply stopping unit 304 outputs the TS packet output from the TS packet reproducing unit 13a to the TS packet.
When it is determined that the packet is a null packet (S41: YES)
Is the clock signal CLK to the energy despreader 16.
The supply of 6 is stopped (S42).

On the other hand, the clock signal supply stopping unit 304
When it is determined that the TS packet output from the TS packet reproducing unit 13a is not a TS null packet but a valid TS packet (S41: NO), the clock signal CLK6 is supplied to the energy despreading unit 16 ( S
43).

As described above, in this embodiment, the null TS
By stopping the supply of the clock signal when the signal NTS is received, it is possible to stop the energy despreading processing operation in the energy despreading unit 16 and allow the data to pass therethrough, thus suppressing power consumption. Therefore,
As described above, it is possible to reduce the power consumption of the energy despreading unit 16 during the output period of the TS null packet, which is a maximum ratio of 7/8 in the output period of the reproduced TS packet. It is possible to greatly reduce the power consumption.

Sixth Embodiment Embodiments 1 to 4 described above
Then, when the TS null packet is output from the TS packet reproducing unit in the error correction / decoding block, the clock signal supplied to a part of the circuits in the error correction / decoding block is stopped. In the sixth embodiment to be described,
For example, during a period in which a TS packet belonging to any one of a plurality of layers transmitted according to the terrestrial digital broadcasting system is being output from the TS packet reproducing unit, a clock signal is supplied only to the byte deinterleave unit of the layer to which the TS packet belongs. Is supplied to stop the clock signal supplied to the byte deinterleave units of the remaining layers.

FIG. 12 is a block diagram showing the structure of an error correction / decoding block in the digital broadcast receiving apparatus according to the sixth embodiment of the present invention. The error correction / decoding block 12 of FIG. 12 is different from the error correction / decoding block of the digital broadcast receiving apparatus of the fourth embodiment shown in FIG.
Unlike the S packet reproducing unit 13a, it does not send a null TS signal but outputs a TS layer signal indicating which layer the TS packet to be reproduced and output is, and the clock signal CLK1 generated by the VCXO 19 is byte deinterleaved. When a TS layer signal is received in the middle of the route supplied to the unit 15, the clock signals CLK7 to
A clock signal supply selection unit 305 that supplies one clock signal from 9 and stops the supply of the remaining clock signals.
(Clock signal supply selecting means) is provided, and a clock signal supply path from the clock signal supply selecting unit 305 to the byte deinterleave units 15a to 15c for each layer is individually set. The other configuration is the same as the configuration of the error correction / decoding block in the digital broadcast receiving apparatus according to the fourth embodiment shown in FIG.

In the present embodiment, the clock signals to the respective layers of the byte deinterleave section 15 which are collectively supplied in the fourth embodiment are supplied to the byte deinterleave section 15a of the first layer: (1), the first layer. The case where the byte deinterleave unit 15b of the second layer: (2) and the byte deinterleave unit 15c of the third layer: (3) are individually supplied to only one of them is shown.

As described above, the TS packet reproducing unit 13
The TS packets output from b are time-multiplexed for each TS packet, and since TS packets belonging to a plurality of layers are not output at the same time, they are individually output to the byte deinterleave units 15a to 15c for each layer. It is possible to further reduce power consumption by supplying the clock signal only to the hierarchy required for the above.

For example, when the data of the TS packet of the first layer: (1) created by the TS packet reproducing unit 13b is input to the byte deinterleave unit 15a, the second layer: the byte deinterleave unit 15b of (2). Alternatively, since the data of the TS packet is not input to the byte deinterleave unit 15c in the third layer (3), it is not necessary to perform the deinterleave at the byte deinterleave unit 15b or 15c.

Therefore, in the present embodiment, for example, the first
Hierarchy: The period during which the TS packet of (1) is output is TS
TS from the reproducing unit 13b to the clock signal supply stopping unit 305
The clock signal supply stopping unit 30 that transmits the hierarchical signal TSS
5, only the clock signal CLK7 supplied to the byte deinterleave unit 15a is output, and the clock signal CLK8 supplied to the remaining byte deinterleave unit 15b.
The output of the clock signal CLK9 supplied to the byte deinterleave unit 15c is stopped.

Only this clock signal CLK7 is supplied to the other clock signals CLK8 and CL.
By stopping K9, the byte deinterleave unit 15a performs deinterleaving processing on the data of the TS packet of the first layer: (1), while the byte deinterleave units 15b and 15c. Then, all processing operations are temporary (first layer:
It is stopped (interrupted) while the TS packet of (1) is output.

Similarly, during the period in which the TS packet of the second layer (2) is output, the byte deinterleave unit 1
The clock signal CLK8 is supplied only to 5b, the supply of the clock signal to the other byte deinterleave units 15a and 15c is stopped, and the byte deinterleave unit 15c is provided during the period in which the TS packet of the third layer (3) is output. Only the clock signal CLK9 is supplied to the other byte deinterleaving units 15a and 15b, and the supply of the clock signal is stopped.

FIG. 13 is a flow chart showing the operation of stopping the clock signal supply in the sixth embodiment. The clock signal supply suspending unit 305 is provided in the TS packet reproducing unit 13
By determining the layer indicated by the TS layer signal TSS from b, the reproduced TS packet output from the TS packet reproducing unit 13b is the first layer (1) TS packet or the second layer: It is determined whether it is the TS packet of (2) or the TS packet of the third layer: (3) (S51).

The clock signal supply stopping unit 305 outputs the first TS packet output from the TS packet reproducing unit 13b.
Layer: When it is determined that the TS packet is (1) (S
51: N = 1), the byte deinterleave unit 15a
The clock signal CLK7 is supplied only to the clock signal CLK7 and the clock signals CLK8 and CLK9 are stopped (S52).

The clock signal supply stopping unit 305 outputs the second TS packet output from the TS packet reproducing unit 13b.
When it is determined that the layer is a TS packet of (2) (S
51: N = 2), the byte deinterleave unit 15b
The clock signal CLK8 is supplied only to the clock signal CLK7 and the clock signals CLK7 and CLK9 are stopped (S53).

The clock signal supply stopping unit 305 outputs the third TS packet output from the TS packet reproducing unit 13b.
When it is determined that the layer is a TS packet of (3) (S
51: N = 3), the byte deinterleave unit 15c
Clock signal CLK9 to CLK8 and CLK8 and CLK8 are stopped (S54).

That is, in the present embodiment, only one TS packet is processed at a certain time, and the byte deinterleave unit used for the processing is the byte deinterleave unit 15 corresponding to the hierarchy of the TS packet.
Since only one of a to c is provided, the clock signal is supplied only to the byte deinterleave section of the layer on which the processing is performed, and the clock signal is not supplied to the byte deinterleave section of the other layers. Is configured as follows.

As described above, in the present embodiment, the byte deinterleave unit of the layer (N) (N is a positive integer: 1, 2, 3, ...) Required for receiving the TS layer signal TSS. The clock signal is supplied only to the byte deinterleave unit of other layers, and the clock signal to the byte deinterleave units of other layers is stopped, so that the processing operations such as deinterleave in the byte deinterleave units of unnecessary layers are stopped, and power consumption is suppressed. can do. From this, the power consumption during the output period of the reproduced TS packet as described above can be reduced to 1/3 in the case of three layers such as terrestrial digital television broadcasting. In addition, in the case of two layers such as terrestrial digital audio broadcasting, the ratio can be reduced to 1/2. Therefore, in this embodiment, it is possible to greatly reduce the power consumption of the entire digital broadcast receiving apparatus.

Seventh Embodiment In the sixth embodiment described above, for example, a TS packet belonging to any one of a plurality of layers transmitted according to the terrestrial digital broadcasting system is T
While the TS packet is being output, the TS
The clock signal is supplied only to the byte deinterleave unit of the layer to which the packet belongs, and the clock signal supplied to the byte deinterleave units of the remaining layers is stopped. This is the same as in the fourth embodiment. It can also be applied to the energy despreading unit as in the form 5. In the following seventh embodiment, during a period in which a TS packet belonging to any one layer is being output from the TS packet reproducing unit, the clock signal is supplied only to the energy despreading unit of the layer to which the TS packet belongs, and the remaining A configuration for stopping the clock signal supplied to the energy despreading unit of the hierarchy will be described.

FIG. 14 is a block diagram showing the structure of an error correction / decoding block in the digital broadcast receiving apparatus according to the seventh embodiment of the present invention. The error correction / decoding block 12 in FIG. 14 differs from the error correction / decoding block in the digital broadcast receiving apparatus in the fifth embodiment shown in FIG. 10 in that the TS packet reproducing unit 13b
Unlike the TS packet reproducing unit 13a, it does not send a null TS signal but outputs a TS layer signal indicating which layer the TS packet to be reproduced and output is, and the clock signal CLK1 generated by the VCXO 19 causes energy despreading. Part 16
When a TS layer signal is received on the way to the clock signals supplied to the clock signals CLK10 to CLK1 according to the instruction content.
A clock signal supply selection unit 306 that supplies one clock signal from among 2 and stops the supply of the remaining clock signals.
(Clock signal supply selecting means) is provided, and a clock signal supply path from the clock signal supply selecting unit 306 to the energy despreading units 16a to 16c for each layer is individually set. Other configurations are similar to those of the error correction / decoding block in the digital broadcast receiving apparatus in the fifth embodiment shown in FIG.

In this embodiment, the clock signals to the respective layers of the energy despreading unit 16 which are collectively supplied in the fifth embodiment are supplied to the energy despreading unit 16a of the first layer: (1), Second layer: (2) energy despreading unit 16
b, 3rd hierarchy: The case where each of the energy despreaders 16c of (3) is individually supplied to only one is shown.

As described above, the TS packet reproducing unit 13
The TS packets output from b are time-multiplexed for each TS packet, and the TS packets belonging to a plurality of layers are not output at the same time. Therefore, the energy despreading units 16a to 16c for each layer individually. It is possible to further reduce power consumption by supplying the clock signal only to the hierarchy required for the above.

For example, when the data of the TS packet of the first layer: (1) created by the TS packet reproducing unit 13b is input to the energy despreading unit 16a, the second layer: the energy despreading unit 16b of (2). Alternatively, since the TS packet data is not input to the energy despreading unit 16c in the third layer (3), it is not necessary to perform the energy despreading in the energy despreading unit 16b or 16c.

Therefore, in the present embodiment, for example, the first
Hierarchy: The period during which the TS packet of (1) is output is TS
TS from the reproduction unit 13b to the clock signal supply stop unit 306
The clock signal supply stopping unit 30 that transmits the hierarchical signal TSS
6 outputs only the clock signal CLK10 supplied to the energy despreading unit 16a, and supplies the clock signal CLK11 supplied to the remaining energy despreading unit 16b and the clock signal CLK supplied to the energy despreading unit 16c.
For 12, the output is stopped.

Only this clock signal CLK10 is supplied, and the other clock signals CLK11 and C
By stopping the LK12, the energy despreading unit 16a performs the energy despreading process on the TS packet data of the first layer: (1), while the energy despreading units 16b and 16c. Then, all the processing operations are temporary (first layer: (1) TS
It is stopped (suspended) during the packet output period.

Similarly, during the period when the TS packet of the second layer: (2) is output, the clock signal CLK11 is supplied only to the energy despreading unit 16b and the clock signals for the other energy despreading units 16a and 16c are supplied. Is stopped, and the clock signal CLK12 is supplied only to the energy despreading unit 16c and the clock signals to the other energy despreading units 16a and 16b are supplied during the period in which the TS packet of the third layer: (3) is output. Supply is stopped.

FIG. 15 is a flow chart showing the operation of stopping the clock signal supply in the seventh embodiment. The clock signal supply stopping unit 306 controls the TS packet reproducing unit 13
By determining the layer indicated by the TS layer signal TSS from b, the reproduced TS packet output from the TS packet reproducing unit 13b is the first layer (1) TS packet or the second layer: It is determined whether the packet is the TS packet of (2) or the TS packet of the third layer: (3) (S61).

The clock signal supply stopping unit 306 receives the first TS packet output from the TS packet reproducing unit 13b.
Layer: When it is determined that the TS packet is (1) (S
61: N = 1), only the clock signal CLK10 to the energy despreader 16a is supplied, and the clock signal CL
K11 and CLK12 are stopped (S62).

The clock signal supply stopping unit 306 outputs the second TS packet output from the TS packet reproducing unit 13b.
When it is determined that the layer is a TS packet of (2) (S
61: N = 2), only the clock signal CLK11 to the energy despreader 16b is supplied, and the clock signal CL
K10 and CLK12 are stopped (S63).

The clock signal supply stopping unit 305 determines that the TS packet output from the TS packet reproducing unit 13b is the third TS packet.
When it is determined that the layer is a TS packet of (3) (S
61: N = 3), only the clock signal CLK12 is supplied to the energy despreader 16c, and the clock signal CL
K10 and CLK11 are stopped (S64).

That is, in the present embodiment, only one TS packet is processed at a certain time, and the energy despreading unit used for the processing is the energy despreading unit 16a corresponding to the hierarchy of the TS packet. Since there is only one of the above-mentioned to c, the clock signal is supplied only to the energy despreading unit of the layer in which the processing is performed, and the clock signal is not supplied to the energy despreading unit of the other layers. Is configured.

As described above, in the present embodiment, the energy despreader of the layer (N) (N is a positive integer: 1, 2, 3, ...) Necessary for receiving the TS layer signal TSS. By supplying the clock signal only to the other layers and stopping the clock signals to the energy despreading units of the other layers, the despreading processing operation in the energy despreading units of the unnecessary layers is stopped and the power consumption is suppressed. be able to. From this, the power consumption during the output period of the reproduced TS packet as described above can be reduced to 1/3 in the case of three layers such as terrestrial digital television broadcasting. In addition, in the case of two layers such as terrestrial digital audio broadcasting, the ratio can be reduced to 1/2. Therefore, in this embodiment, it is possible to greatly reduce the power consumption of the entire digital broadcast receiving apparatus.

Eighth Embodiment In the second embodiment described above, when a TS null packet is output from the TS packet reproducing unit in the error correction / decoding block, it is supplied to the error calculation circuit 107 of the RS decoding unit 17 in the error correction / decoding block. Although the clock signal is stopped, it is possible to detect that an error-free TS packet is output, for example, by the output of the syndrome calculation circuit arranged in the preceding stage of the error calculation circuit 107.

This is because, for example, in the terrestrial digital broadcasting system, the error correction processing is performed by Viterbi decoding and RS decoding, but the TS packet data having an error is In some cases, all the errors contained in the received data can be corrected only by the processing of the Viterbi decoding circuit in stages, and in that case, the processing of the RS decoding unit becomes unnecessary. In such a case, since the TS null packet is not output from the TS packet reproducing unit,
It is important to detect a TS packet having no error by the output of the syndrome calculation circuit.

Therefore, in the eighth embodiment described below, the clock signal supplied to the error calculating circuit 107 is stopped while the TS null packet is detected by the syndrome calculating circuit.

FIG. 16 is a block diagram showing the structure of the error correction / decoding block in the digital broadcast receiving apparatus in the eighth embodiment of the present invention. The error correction / decoding block 12 in FIG. 16 differs from the error correction / decoding block in the digital broadcast receiving apparatus according to the second embodiment shown in FIG. 4 in that the TS packet reproducing unit 13 first determines that the null TS signal is received. The point that the syndrome calculating circuit 100a outputs the error syndrome value calculated from the input TS packet to the clock signal supply stopping unit 307 instead. Clock signal CL generated by VCXO19
The clock signal CL is received when an error syndrome value that can determine that error data is not included is received in the middle of the route in which K1 is supplied to the error calculation circuit 107 in the RS decoding unit 17.
Clock signal supply stopping unit 307 for stopping the supply of K13
(Clock signal supply stopping means) is provided, and the clock signal CLK13 is supplied from the clock signal supply stopping unit 307 when an error syndrome value (error zero syndrome value EZS) that can be determined not to include error data is not received. is there. The other configuration is the same as that of the second embodiment shown in FIG.
This is the same as the configuration of the error correction / decoding block in the digital broadcast receiving apparatus.

Similar to the second embodiment described above, also in the present embodiment, when the error zero syndrome value EZS is output to the TS packet input from the syndrome calculation circuit 100a, the TS packet contains the error data. Therefore, the error position and the error numerical value calculated by the error calculating circuit 107 are all zero values which are the values when there is no error. Therefore, the syndrome calculation circuit 100a
When the TS packet having the error zero syndrome value EZS is input in, it is not necessary to calculate the error position and the error numerical value.

Therefore, in the present embodiment, during the period in which the TS packet having the error zero syndrome value EZS is output from the syndrome calculating circuit 100a, the syndrome calculating circuit 100a transmits the error zero syndrome value EZS to the clock signal supply stopping unit 307. Then, the clock signal supply stopping unit 307 stops the clock signal supplied to the error calculating circuit 107. By stopping the supply of this clock signal, all the processing operations in the error calculation circuit 107 are temporarily stopped (interrupted).

FIG. 17 is a flow chart showing the operation of stopping the clock signal supply in the eighth embodiment. The clock signal supply stopping unit 307 is used in the syndrome calculation circuit 1
By determining whether or not the error zero syndrome value EZS is received from 00a, the syndrome calculation circuit 10
It is determined whether the reproduced TS packet output from 0a is a TS packet having an error zero syndrome value EZS (S71).

When the clock signal supply stopping unit 307 determines that the TS packet output from the syndrome calculating circuit 100a is the TS packet having the error zero syndrome value EZS (S71: YES), it sends the error calculating circuit 107. The supply of the clock signal CLK13 is stopped (S72).

On the other hand, the clock signal supply stopping unit 307
When it is determined that the TS packet output from the syndrome calculation circuit 100a is not the TS packet having the error zero syndrome value EZS but the TS packet including an error (S71: NO), the clock signal CLK13 to the error calculation circuit 107 is output. Is supplied (S73).

As described above, in this embodiment, the TS packet output from the syndrome calculation circuit 100a is
By stopping the supply of the clock signal in the case of the TS packet having the error zero syndrome value EZS, it is possible to stop all the processing operations of the error calculation circuit 107 and suppress the power consumption. Therefore, for example, even when all the errors included in the received data can be corrected only by Viterbi decoding, the processing of the error calculation circuit of the RS decoding unit can be stopped, and the error calculation circuit of the TS packet processing period Since the power consumption can be reduced, the power consumption of the entire digital broadcast receiving apparatus can be greatly reduced.

In each of the above embodiments, the method of stopping or selecting the clock supply to each individual circuit to reduce the power consumption is described. However, each individual circuit described in each embodiment is described. It is also possible to carry out any combination of the above methods.

[0137]

Since the present invention is configured as described above, it has the following effects.

According to the digital broadcast receiving apparatus of the first aspect, the clock signal supplied to at least one circuit of the error correction / decoding block is supplied while the TS null packet is being output from the TS packet reproducing unit. Since the processing is stopped, all the processing operation of the circuit is stopped during the input period of the TS null packet which does not need to be processed.
The power consumption can be suppressed, and the power consumption of the entire digital broadcast receiving device can be reduced.

According to the digital broadcast receiving apparatus of the second aspect, the clock signal supplied to the RS decoding section is stopped while the TS null packet is being output from the TS packet reproducing section. During the input period of the TS null packet that does not need to be processed, all the processing operations of the RS decoding unit are stopped, power consumption can be suppressed, and the power consumption of the entire digital broadcast receiving apparatus can be reduced.

According to the digital broadcast receiving apparatus of the third aspect, the clock signal supplied to the syndrome calculating circuit is stopped while the TS null packet is being output from the TS packet reproducing section. During the input period of the TS null packet that does not need to be processed, all the processing operations of the syndrome calculation circuit are stopped, power consumption can be suppressed, and the power consumption of the entire digital broadcast receiving apparatus can be reduced.

According to the digital broadcast receiving apparatus of the fourth aspect, the clock signal supplied to the error calculating circuit is stopped while the TS null packet is being output from the TS packet reproducing section. During the input period of the TS null packet that does not need to be processed, all the processing operations of the error calculation circuit are stopped, power consumption can be suppressed, and the power consumption of the entire digital broadcast receiving apparatus can be reduced.

According to the digital broadcast receiving apparatus of the fifth aspect, the clock signal supplied to the memory is stopped while the TS null packet is being output from the TS packet reproducing unit. There is no need to do T
During the input period of the S null packet, all the processing operations of the memory are stopped, power consumption can be suppressed, and the power consumption of the entire digital broadcast receiving apparatus can be reduced.

According to the digital broadcast receiving apparatus of the sixth aspect, the clock signal supplied to the byte deinterleave unit is stopped while the TS null packet is being output from the TS packet reproducing unit. Therefore, during the input period of the TS null packet that does not need to be processed, all the processing operations of the byte deinterleave unit are stopped, power consumption can be suppressed, and the power consumption of the entire digital broadcast receiving apparatus can be reduced. You can

According to the digital broadcast receiving apparatus of the seventh aspect, the clock signal supplied to the energy despreading unit is stopped during the period in which the TS packet reproducing unit outputs the TS null packet. Therefore, all processing operations of the energy despreading unit are stopped during the input period of the TS null packet that does not need to be processed, power consumption can be suppressed, and the power consumption of the entire digital broadcast receiving apparatus can be reduced. You can

According to the digital broadcast receiving apparatus of the eighth aspect, the TS of the layer output from the TS packet reproducing unit
Only the clock signal supplied to the byte deinterleave unit for byte deinterleaving the packet is supplied, and the clock signal supplied to the byte deinterleave unit for byte deinterleaving the TS packets of other layers is stopped. , Only the byte deinterleave unit of the layer that needs to be processed operates, and all processing operations stop at the byte deinterleave unit that receives the TS packet of the layer that does not need to be processed, and power consumption is suppressed. Therefore, the power consumption of the entire digital broadcast receiving apparatus can be reduced.

According to the digital broadcast receiving apparatus of the ninth aspect, the TS of the layer output from the TS packet reproducing unit
Only the clock signal supplied to the energy despreading unit that despreads the energy of the packet is supplied, and the clock signal supplied to the energy despreading unit that despreads the energy of TS packets of other layers is stopped. , Only the energy despreading unit of the layer that needs to perform processing operates, and all the processing operations stop at the energy despreading unit that receives the TS packet of the layer that does not need to perform processing, thus suppressing power consumption. Therefore, the power consumption of the entire digital broadcast receiving apparatus can be reduced.

According to the digital broadcast receiving apparatus of the tenth aspect, when the syndrome value output from the syndrome calculating circuit of the RS decoding unit is a value indicating that the input TS packet does not include an error. Since the clock signal supplied to the error calculating circuit is stopped, all the processing operations of the error calculating circuit are stopped during the period in which error-free TS packets that do not need to be processed are input. The power consumption can be suppressed, and the power consumption of the entire digital broadcast receiving device can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an error correction / decoding block in a digital broadcast receiving apparatus according to a first embodiment of the present invention.

FIG. 2A is a diagram showing a configuration of a TS packet reproducing unit, and FIG. 2B is a diagram showing how reproduced TS packets and TS null packets are output.

FIG. 3 is a flowchart showing the operation of stopping the supply of the clock signal in the first embodiment.

FIG. 4 is a block diagram showing a configuration of an error correction / decoding block in the digital broadcast receiving apparatus in the second embodiment of the present invention.

FIG. 5 is a flowchart showing the operation of stopping the supply of the clock signal in the second embodiment.

FIG. 6 is a block diagram showing a configuration of an error correction / decoding block in a digital broadcast receiving apparatus according to a third embodiment of the present invention.

FIG. 7 is a flowchart showing an operation of stopping supply of a clock signal in the third embodiment.

[Fig. 8] Fig. 8 is a block diagram showing a configuration of an error correction / decoding block in a digital broadcast receiving device according to a fourth embodiment of the present invention.

FIG. 9 is a flowchart showing the operation of stopping the clock signal supply according to the fourth embodiment.

FIG. 10 is a block diagram showing a configuration of an error correction / decoding block in the digital broadcast receiving apparatus in the fifth embodiment of the present invention.

FIG. 11 is a flowchart showing an operation of stopping clock signal supply in the fifth embodiment.

FIG. 12 is a block diagram showing a configuration of an error correction / decoding block in a digital broadcast receiving apparatus according to a sixth embodiment of the present invention.

FIG. 13 is a flowchart showing the operation of stopping the clock signal supply in the sixth embodiment.

FIG. 14 is a block diagram showing a configuration of an error correction / decoding block in the digital broadcast receiving apparatus in the seventh embodiment of the present invention.

FIG. 15 is a flowchart showing the operation of stopping the clock signal supply in the seventh embodiment.

FIG. 16 is a block diagram showing a configuration of an error correction / decoding block in a digital broadcast receiving device according to an eighth embodiment of the present invention.

FIG. 17 is a flowchart showing the operation of stopping the clock signal supply in the eighth embodiment.

FIG. 18 is a diagram showing an example of a terrestrial digital television broadcast receiver of a general broadcast system.

FIG. 19 is a diagram showing internal circuit blocks of the RS decoding unit in FIG. 18.

FIG. 20 is a diagram showing an example of TS packets that are time-multiplexed and output from the TS packet reproducing unit.

[Explanation of symbols]

1 tuner, 2 SAW filter, 3 IF conversion circuit, 4 low pass filter, 6 AD converter,
7 OFDM demodulator, 8 time domain processor, 9
FFT, 10 frequency domain processing unit, 11 deinterleave unit, 12 error correction block, 13
TS packet reproducing unit, 14 Viterbi decoding unit, 15
Byte deinterleave unit, 16 energy despreading unit, 17RS decoding unit, 18 DA converter, 19
VCXO (clock signal supply unit), 100 syndrome calculation circuit, 101 error locator polynomial calculation unit, 1
02 error value polynomial calculation unit, 103 error position calculation unit, 104 error value calculation unit, 105 error correction output circuit, 106 memory, 107 error calculation circuit,
CLK1 clock signal, NTS null TS signal,
TSS TS layer signal.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H04N 5/44 H04N 5/44 Z 5K061 7/24 7/13 AF term (reference) 5C025 AA28 BA08 BA25 BA27 BA30 DA01 5C059 KK49 RA04 RA06 RB10 RC07 RD03 RF05 SS02 TA00 TB17 TC00 TC22 UA05 UA32 5J065 AB03 AC02 AD03 AD11 AG02 AG04 AG06 5K014 AA01 BA08 BA11 EA07 FA08 FA16 HA05 HA10 5K028 AA06 BB04 CC05 DD01 DD02 KK 02 DD01 DD02

Claims (10)

[Claims] 1. An error correction / decoding block for performing error correction and decoding processing by receiving a clock signal for demodulated output of a received signal of digital television broadcasting or digital audio broadcasting, said error correction / decoding block. Is a multi-layered TS (Transport S
stream) T that classifies and reproduces packets for each layer
A digital broadcast receiving apparatus having an S packet reproducing means, wherein the TS packet reproducing means, when the TS packet to be reproduced is a TS null (invalid) packet for time adjustment, outputs a null TS signal indicating the packet. The null T is provided on the supply path of the clock signal which is output and is used in at least one circuit section subsequent to the TS packet reproducing means in the error correction / decoding block.
A digital broadcast receiving apparatus comprising a clock signal supply stopping means for stopping the supply of a clock signal when an S signal is received. 2. The error correction / decoding block has RS (Reed Solomon) decoding means for performing error correction on the data of the reproduced TS packet, and the clock signal supply stopping means is at least the RS decoding means. The digital broadcast receiving apparatus according to claim 1, wherein the digital broadcast receiving apparatus is installed on a supply path of a clock signal used in part. 3. The RS decoding means includes a syndrome calculating means for calculating an error syndrome, and the clock signal supply stopping means is installed on a supply path of a clock signal used in the syndrome calculating means. The digital broadcast receiving apparatus according to claim 2, characterized in that: 4. The RS decoding means includes an error calculating means for calculating an error position and an error value, and the clock signal supply stopping means is installed on a supply path of a clock signal used for the error calculating means. The digital broadcast receiving apparatus according to claim 2, wherein: 5. The RS decoding means includes a memory for delaying the data of the reproduced TS packet until an error value is calculated, and the clock signal supply stopping means includes a clock signal used for the memory. The digital broadcast receiving apparatus according to claim 2, wherein the digital broadcast receiving apparatus is installed on the supply path of the. 6. The error correction / decoding block has a byte deinterleave means for performing byte deinterleave on the reproduced TS packet data for each layer, and the clock signal supply stopping means for the byte deinterleave. The digital broadcast receiving apparatus according to claim 1, wherein the digital broadcast receiving apparatus is installed on a supply path of a clock signal used in the means. 7. The error correction / decoding block has an energy despreading means for despreading energy of the reproduced TS packet data for each layer, and the clock signal supply stopping means has the energy despreading means. The digital broadcast receiving apparatus according to claim 1, wherein the digital broadcast receiving apparatus is installed on a supply path of a clock signal used in the means. 8. An error correction / decoding block for performing error correction and decoding processing by receiving a clock signal for demodulated output of a reception signal of digital television broadcasting or digital audio broadcasting, and the error correction / decoding block. Is a digital broadcast receiving apparatus having TS packet reproducing means for reproducing TS packets having a plurality of layers classified for each layer, wherein the TS packet reproducing means is a TS layer indicating a layer of TS packets to be reproduced. A signal is output, and the error correction / decoding block has a byte deinterleaving unit that performs byte deinterleaving on the reproduced TS packet data for each layer, and is used in each layer in the byte deinterleave unit. When the TS layer signal is received and installed on the clock signal supply path, the TS layer A digital broadcast receiving apparatus comprising: a clock signal supply selection unit that supplies a clock signal only to a layer designated by a signal and stops the supply to other layers. 9. An error correction / decoding block for performing error correction and decoding processing by receiving a clock signal for demodulated output of a received signal of digital television broadcasting or digital audio broadcasting, said error correction / decoding block. Is a digital broadcast receiving apparatus having TS packet reproducing means for reproducing TS packets having a plurality of layers classified for each layer, wherein the TS packet reproducing means is a TS layer indicating a layer of TS packets to be reproduced. A signal is output, and the error correction / decoding block has energy despreading means for despreading energy of the reproduced TS packet data for each layer, and is used in each layer in the energy despreading means. When the TS layer signal is installed on the clock signal supply path, the TS layer signal specifies the TS layer signal. A digital broadcast receiving apparatus comprising: a clock signal supply selecting unit that supplies a clock signal only to a selected layer and stops the supply to other layers. 10. An error correction / decoding block for performing error correction and decoding processing by receiving a clock signal for demodulated output of a received signal of digital television broadcasting or digital audio broadcasting, said error correction / decoding block. Is a digital broadcast receiving apparatus including an RS decoding means for performing error correction of reproduced TS packet data, and a syndrome calculating means for calculating an error syndrome and an error calculating means for calculating an error position and an error value. When the calculated syndrome value is zero error, the syndrome calculating means outputs an error zero signal indicating that there is no error in the data of the received packet, and the clock signal used by the error calculating means. When the error zero signal is received, it is installed on the supply path of the clock signal supply Digital broadcast receiving apparatus characterized by comprising a clock signal supply stop means for stopping.