JPH118601A - Receiver for digital broadcast - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce useless power consumption of a digital broadcast receiver. SOLUTION: The receiver is provided with a detection circuit 23 that detects whether or not a received digital signal is synchronous and provided with a circuit 25 that is controlled with a detection signal from the detection circuit 23 and supplies a clock signal to a decoder circuit 16 and its succeeding circuits 17, 18 only when the receiver is synchronous and that stops the supply of the clock signal to the decoder circuit 16 and its succeeding circuits 17, 18 to cause the clock operation of the circuits 16-18 to be stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital broadcast receiver suitable for use in a digital audio broadcast receiver.

[0002]

2. Description of the Related Art In Europe, DAB (Digital Audio Broadcasting) according to the Eureka 147 standard is implemented. The signal processing on the transmitting side is as follows. (1) Digital audio data of a maximum of 64 channels is data-compressed by MPEG audio layer II for each channel. (2) Encode processing for error correction is performed on the data of each channel resulting from the term (1) by convolutional coding and interleaving on the time axis. (3) The result of item (2) is multiplexed into one channel. At this time, auxiliary data such as PAD is also added. (4) Interleave the result of item (3) on the frequency axis and add a symbol for synchronization. (5) The result of (4) is subjected to OFDM processing (orthogonal frequency division multiplexing processing) and further D / A converted. (6) The carrier signal is subjected to QPSK modulation (quadrature modulation) according to the result of the item (5), and this QPSK signal is transmitted.

[0003]

SUMMARY OF THE INVENTION An object of the present invention is to suppress wasteful power consumption in a receiver for receiving a digital broadcast as described above.

[0004]

Therefore, according to the present invention, a detection circuit for detecting whether or not a received digital signal is synchronized is controlled by the detection signal of the detection circuit. And a circuit for supplying a clock to circuits subsequent to the decoder circuit only when the
When the synchronization is not established, the digital broadcast receiver is designed to stop the operation of the circuits subsequent to the decoder circuit by the clock. Therefore,
The circuits after the decoder circuit operate normally only when synchronization is established, and stop operation when synchronization is not established.

[0005]

In FIG. 1, a broadcast wave signal of DAB is received by an antenna 11, and the received signal is supplied to a front end circuit 12 configured in a superheterodyne format and converted into an intermediate frequency signal. This intermediate frequency signal is supplied to the A / D converter circuit 13 and converted into a digital signal.

The digital intermediate frequency signal is supplied to a quadrature demodulation circuit 14 to demodulate baseband data. The data is sequentially written to a buffer RAM 21 and the data written to the RAM 21 is written to an FFT circuit. The demodulated data is taken into the memory 15 and OFDM demodulation is performed. The demodulated data is sequentially written into the RAM 21.

Next, the data written in the RAM 21 is taken into the Viterbi decoder circuit 16 and deinterleaving and error correction are performed. At this time,
A predetermined selection signal is supplied from the system control microcomputer 40 to the decoder circuit 16 to perform channel selection (program selection), select data of a target channel, and sequentially write the data to the RAM 21.

The data written in the RAM 21 is taken into the data decompression circuit 17 and the digital audio data of the target channel is decompressed to the original data. The signal is supplied to the converter circuit 18 and D / A converted into an analog audio signal.
It is taken out to 9.

The Viterbi decoder circuit 16 generates RA
The data written in M21 is taken into the RDI circuit 22 to be data of a predetermined transfer format, and this data is output to the terminal 29 and supplied to the microcomputer 40.

Further, for example, a reproduction synchronizing circuit 23 is constituted by a DSP, AFC of the front end circuit 12 is performed, and processing such as time synchronization in the FFT circuit 15 is executed. Are synchronized. At this time, R
The AM 21 is used for a buffer and a work area of the reproduction synchronization circuit 23.

The clock forming circuit 24 forms a clock CK having a frequency of, for example, 24 MHz.
CK is supplied to the circuits 13 to 15 and 23, respectively, and is supplied to the circuits 16 to 18 and 22 through the AND circuit 25, respectively.

Further, in this case, the reproduction synchronization circuit 23 detects the magnitude of the frequency offset of the carrier synchronization and the magnitude of the time axis offset of the symbol synchronization. When the magnitude of both the offsets is within a predetermined value, it becomes "H". On the other hand, if it exceeds the predetermined value, a detection signal S23 which becomes "L" is extracted. That is, the detection signal S23
Is a signal which becomes "H" when the synchronization circuit 23 is locked, and becomes "L" when it is not locked. Then, the detection signal S23 is supplied to the AND circuit 25.

According to such a configuration, when the synchronization circuit 23 is locked to the received data, S23 =
Since it is "H", the clock CK is also supplied to the circuits 16 to 18 and 22 through the AND circuit 25. Therefore, the circuits 16 to 18 and 22 operate normally as described above, and the terminal 1
Desired output signals can be obtained at 9, 29.

However, when the synchronization circuit 23 is not locked to the received data, the clock CK is blocked by the AND circuit 25 since S23 = "L", and the circuits 16-1
8 and 22 are not supplied. Therefore, the circuits 16-1
Since the circuits 8 and 22 stop operating, these circuits 16 to 1
8, 22, the power consumption is reduced, that is, power saving is performed.

In this case, an output signal cannot be obtained at the terminals 19 and 29, but in this case, since the synchronization circuit 23 is not originally locked, the circuits 16 to 18
Even if the clock CK is supplied to the terminal 22, an output signal cannot be obtained at the terminals 19 and 29, so that there is no problem even if the circuits 16 to 18 and 22 are stopped.

Rather, if the circuits 16 to 18 are operated while the synchronization circuit 23 is not locked, error detection and error correction will malfunction, and as a result, an audio signal to be reproduced as abnormal noise at the terminal 19 will be output. However, in the above-described receiver, when the synchronization circuit 23 is not locked, the circuits 16 to 18 stop operating, so that no abnormal signal is output.

In the receiver shown in FIG.
In this case, the frequency of the clock supplied to 18, 22, and 23 is the lowest frequency required in those circuits.

That is, in FIG. 2, a broadcast wave signal of DAB is received by an antenna 11, and this received signal is supplied to a front end circuit 12 and converted into an intermediate frequency signal, and this intermediate frequency signal is converted into an A / D converter circuit. 13 to be converted into a digital signal. The digital signal is supplied to a quadrature demodulation circuit 14 to demodulate baseband data. The data is supplied to an FFT circuit 15 for OFDM demodulation. The OFDM demodulated data is supplied to a Viterbi decoder circuit 16. Deinterleaving and error correction are performed.

At this time, a predetermined selection signal is supplied from the system control microcomputer 40 to the decoder circuit 16 to perform channel selection (program selection) to select digital audio data of a target channel.
MPE is supplied to the selected data decompression circuit 17 and
G data decompression is performed.

In this way, the digital audio data of the target channel is expanded from the data expansion circuit 17 to the original data and extracted. Then, the extracted digital audio data is supplied to a D / A converter circuit 18 and D / A converted into an analog audio signal.

Further, a part of the data is supplied from the Viterbi decoder circuit 16 to the RDI circuit 22 to be converted into data of a predetermined transfer format. The data is output to the terminal 29 and is also supplied to the microcomputer 40. Further, for example, the reproduction synchronization circuit 23 is configured by the DSP, AFC of the front end circuit 12 is performed, and processing such as synchronization in the FFT circuit 15 is executed.

In the above processing, the circuits 14 to 1
7, 22, and 23 have a RAM 34 instead of the RAM 21.
To 37, 32, and 33 are respectively connected to these RAMs.
Like the RAM 21, the buffers 34 to 37, 32, and 33 are used as buffers or work areas for data processing of the connected circuits, and are used as buffers for transferring data to the next stage.

In the clock forming circuit 24, the clocks CK13 to CK18, CK2 of the circuits 13 to 18, 22, and 23 are output.
2. CK23 is formed, clocks CK13 to CK15 and CK23 are supplied to the circuits 13 to 15 and 23, respectively, and clocks CK16 to CK18 and CK22 are supplied to the circuit 1 through the AND circuit 25.
6 to 18 and 22 (actually, the AND circuit 25 is four AND circuits to which clocks CK16 to CK18 and CK22 are respectively supplied.
Due to space limitations, it is represented by an AND circuit 25).

In this case, the clocks CK13 to CK18,
The frequencies of CK22 and CK23 are the lowest frequencies necessary for the circuits 13 to 18 and 22 to which these clocks are supplied. For example, CK14 = 4 MHz, CK15 = 24 MHz, CK16 = 12 MHz, CK17 = 3
MHz CK22 = 3 MHz, CK23 = 12 MHz.

Further, the lock detection signal S23 is extracted from the reproduction synchronization circuit 23 and supplied to the AND circuit 25.
Further, for example, circuits 14 to 17, 22 to 2 enclosed by chain lines
5, 32 to 37 are integrated into one chip IC in the LSI 10.

According to such a configuration, when the synchronization circuit 23 is locked to the received data, S23 =
Since it is "H", the clocks CK16 to CK18 and CK22 are also supplied to the circuits 16 to 18 and 22 through the AND circuit 25. Therefore, the circuits 16 to 18 and 22 operate normally as described above, and desired output signals can be obtained at the terminals 19 and 29.

However, when the synchronous circuit 23 is not locked to the received data, the clocks CK16 to CK18 and CK22 are blocked by the AND circuit 25 and are not supplied to the circuits 16 to 18 and 22, since S23 = "L". . Therefore, since the circuits 16 to 18 and 22 stop operating, the power consumption of these circuits 16 to 18 and 22 is reduced, and power is saved.

Further, according to the LSI 10 shown in FIG. 2, if the circuits 14 to 17, 22, and 23 are formed as LSIs, the clocks CK14 to CK17, CK22, and CK23 will pass through the LSI 10. , These clocks CK14 ~ CK
The frequency of 23, as described above, except for clock CK15,
The frequency is set to 1/8 to 1/2 of the frequency 24 MHz of the clock CK in FIG. Therefore, these clocks CK14 to CK23 are low.
Even if the signal passes through the SI 10, the loss is small, and the power consumed by the clocks CK14 to CK23 is small.

A high frequency clock is supplied to the LSI 10
, The trouble caused by the clock jump can be reduced.

In the above description, the magnitudes of the frequency offset and the time axis offset are determined by the reproduction synchronization circuit 23.
However, the detection signal S23 can be obtained by using the detection circuit separately from the reproduction synchronization circuit 23. In the above description, the present invention is applied to a receiving circuit of a DAB receiver. However, the present invention can be applied to a digital broadcasting receiver.

[0031]

According to the present invention, useless power consumption can be suppressed in a digital broadcast receiver. Further, when the synchronization is not locked, no abnormal signal is output.

[Brief description of the drawings]

FIG. 1 is a system diagram illustrating one embodiment of the present invention.

FIG. 2 is a system diagram showing another embodiment of the present invention.

[Explanation of symbols]

10: LSI, 12: front-end circuit, 13: A /
D converter circuit, 14: orthogonal demodulation circuit, 15: FFT
Circuit, 16 Viterbi decoder circuit, 17 data expansion circuit, 18 D / A converter circuit, 22 RDI circuit,
23: reproduction synchronization circuit, 24: clock formation circuit, 25:
AND circuit, 40 ... microcomputer, CK, CK13 ~
CK18, CK22 and CK23… Clock

Claims (2)

[Claims] 1. A detection circuit for detecting whether or not a received digital signal is synchronized. A detection circuit controlled by a detection signal of the detection circuit, and a clock is supplied to circuits subsequent to a decoder circuit only when the synchronization is obtained. And a circuit for supplying, when the synchronization is not achieved, the operation of the circuits subsequent to the decoder circuit by the clock is stopped. 2. The digital broadcast receiver according to claim 1, wherein the received digital signal is sequentially supplied to a demodulation circuit, an error correction circuit, and a data decompression circuit to obtain original digital data. A digital broadcast receiver in which carrier synchronization on the frequency axis and symbol synchronization on the time axis of the digital signal are detected by a reproduction synchronization circuit.