JP4179954B2 - Digital broadcast receiver - Google Patents

Description

This invention relates to a digital receiving device, in particular, it relates to a digital receiver comprising a Viterbi decoder including a path memory for storing information for specifying a survivor path.

  In the field of broadcasting and communication, when digital data is transmitted, errors occur in received data due to noise on the transmission path. Therefore, in order to correct this error, it is generally performed to correct the error by adding an error correction code to the transmission data and decoding it in the receiving apparatus.

  Viterbi decoding is known as an error correction method having a strong error correction capability even in a system with a particularly poor transmission path such as terrestrial digital broadcasting and mobile communication. Viterbi decoding is an error correction method that efficiently realizes maximum likelihood decoding of a convolutional code, and is a maximum likelihood decoding method that estimates the transmission sequence closest to the received reception sequence and decodes the original information sequence. One (see Non-Patent Document 1).

  FIG. 9 is a functional block diagram schematically showing a configuration of a conventional digital broadcast receiving apparatus including a Viterbi decoder. FIG. 9 mainly shows a part related to error correction in the digital broadcast receiving apparatus.

  Referring to FIG. 9, digital broadcast receiving apparatus 100 includes antenna 102, demodulator 104, multiplex frame configuration unit 106, Viterbi decoder 108, and Reed-Solomon (hereinafter also referred to as “RS”) decoder. 110. The antenna 102 receives a digitally modulated radio frequency signal (hereinafter also referred to as “RF (Radio Frequency) signal”) and outputs it to the demodulator 104. The demodulator 104 demodulates the RF signal received from the antenna 102 into encoded data by various demodulation processes.

  Multiplex frame configuration section 106 converts the encoded data received from demodulation section 104 into transport stream data (hereinafter also referred to as “TS data”), and outputs the TS data in units of transmission packets (hereinafter TS data). The transmission packet that constitutes the above is referred to as “TSP (Transport Stream Packet)”).

  The Viterbi decoder 108 receives TS data from the multiplex frame construction unit 106 in units of TSP, and performs Viterbi decoding on the TS data that has been convolutionally encoded on the transmission device side to perform error correction.

  The RS decoding unit 110 receives the Viterbi-decoded TS data from the Viterbi decoder 108, and RS-decodes the TS data that has been RS-encoded on the transmission device side. Then, the RS decoding unit 110 outputs the decoded data subjected to error correction to a decoder (not shown), and the decoded data is displayed on a display device or the like.

  FIG. 10 is a functional block diagram schematically showing the configuration of the multiplex frame configuration unit 106 shown in FIG.

  Referring to FIG. 10, multiplex frame configuration unit 106 includes a layer division / layer combination unit 112, a TS buffer 114, a null packet generation unit 116, a select switch 118, and a TS reproduction unit 120.

  Hierarchical division / hierarchical synthesis unit 112 converts encoded data demodulated by demodulation unit 104 (not shown) into TS data through a series of processes such as hierarchical division, depunctured, and hierarchical synthesis, and the converted TS data Is output to the TS buffer 114.

  The TS buffer 114 accumulates TS data received from the layer division / layer combination unit 112. The TS playback unit 120 checks the amount of TS data stored in the TS buffer 114 at regular intervals. If TS data of 1 TSP or more is stored in the TS buffer 114, the TS playback unit 120 switches the select switch 118 to the TS buffer 114 side. . Then, the TS reproducing unit 120 outputs the data packet DTP output from the TS buffer 114 to the Viterbi decoder 108 (not shown).

  On the other hand, when the amount of data stored in the TS buffer 114 is less than 1 TSP, the TS playback unit 120 switches the select switch 118 to the null packet generation unit 116 side. Then, the TS reproduction unit 120 outputs the null packet NLP generated by the null packet generation unit 116 to the Viterbi decoder 108.

  As described above, when the data for 1 TSP is not accumulated in the TS buffer 114, the null packet NLP is output because TS data needs to be supplied to a decoding unit (not shown) at a constant rate because of decoding processing. Because there is.

  FIG. 11 is a functional block diagram schematically showing the configuration of the Viterbi decoder 108 shown in FIG.

  Referring to FIG. 11, Viterbi decoder 108 includes branch metric calculation circuit 52, ACS (addition comparison selection) circuit 54, path metric memory 56, path memory 122, traceback circuit 124, and path metric minimum. And a value & state search circuit 126.

  When the branch metric calculation circuit 52 receives the TS data from the multi-frame configuration unit 106 (not shown), the branch metric calculation circuit 52 calculates the difference between the received TS data and the received data assumed in the state for each possible state of the convolutional encoder. The branch metric shown is calculated, and the branch metric is output to the ACS circuit 54.

  The ACS circuit 54 receives a branch metric corresponding to each state from the branch metric calculation circuit 52, and receives a path metric of each state from the path metric memory 56. Here, each state has two paths that transition with respect to the state, and the ACS circuit 54 adds a branch metric corresponding to each of the two path metrics associated with the two paths. Is added.

  Then, for each state, the ACS circuit 54 compares the addition results for the two paths transitioning to the state, and selects the path with the smaller addition result, that is, the path with the higher likelihood. . When the path is selected, the ACS circuit 54 outputs the path metric of each state corresponding to the path selected for each state to the path metric memory 56, and outputs the selected path to the path memory 122. The selected path is generally referred to as a “surviving path”, while the other path that has not been selected is discarded.

  When the path metric memory 56 receives the path metric of each state from the ACS circuit 54, the path metric memory 56 updates the path metric stored therein with the received path metric. The path metric minimum value & state search circuit 126 searches the path metric of each state for the minimum value because the path metric is monotonically non-decreasing, and for example, finds the minimum value from the path metric of each state. By subtracting, the path metric stored in the path metric memory 56 is normalized. Further, the path metric minimum value & state search circuit 126 searches the current state corresponding to the searched minimum path metric, and outputs the searched state to the traceback circuit 124.

  The path memory 122 stores path information for identifying each surviving path for each state selected by the ACS circuit 54 for the length of the path memory. Here, the surviving paths in each state converge to one as time elapses, and the time required for this convergence varies depending on the performance of the system. The path memory length is appropriate for each system. Determined by length.

  The traceback circuit 124 receives a state corresponding to the minimum path metric from the path metric minimum value & state search circuit 126, and traces the path information stored in the path memory 122 from the state in the reverse direction in time. Read. Then, the traceback circuit 124 outputs the read path information as decoded data.

  The above Viterbi decoding is called a traceback method. For Viterbi decoding, there are known a register method in which the path memory is configured by a hard register and the above-described traceback method in which the path memory is configured by a RAM (Random Access Memory) or the like. For digital broadcast receivers and the like in which the path memory length and the number of states are large in consideration, the traceback method is considered advantageous from the viewpoint of circuit scale and power consumption.

  As a digital modulation method in the digital broadcast receiving apparatus as described above, an orthogonal frequency division multiplexing (hereinafter also referred to as “OFDM”) method is known as a method excellent in high-quality transmission and frequency utilization efficiency. It has been. The OFDM method is a multiplexing method in which each carrier wave is orthogonal to each other and digitally modulated for each carrier wave. A modulation method in which a large number of subcarriers are provided in one channel band and is excellent in anti-multipath interference. is there. This OFDM method is also employed as a modulation method for terrestrial digital broadcasting, which will start broadcasting in the future.

  The modulation data according to the OFDM scheme is composed of units called “frames”, and each frame includes 204 data units called “symbols”. Each symbol consists of valid data and invalid data including a guard interval and a null carrier.

  FIG. 12 is a diagram showing a configuration of effective data in the OFDM symbol.

  Referring to FIG. 12, valid data is composed of 13 data units called “segments” in which pilot signals are added to data grouped in predetermined units.

  FIG. 13 is a diagram showing a configuration of each segment shown in FIG.

Referring to FIG. 13, each segment is composed of 108 × 2 ^(M−1) (M represents a mode and is composed of one of 1, 2, and 3). In FIG. 13, the case of mode 1 is shown, and each segment is composed of 108 carriers 0 to 107.

In this OFDM system, in addition to the case where the receiving apparatus receives all 13 segments of segments 0 to 12 (hereinafter, such reception is also referred to as “13-segment reception”), only a part of the segments is partially received. "Partial reception" to receive is possible. Such a reception form is defined as a standard for a digital broadcast receiver (see Non-Patent Documents 2 and 3).
Yoshihiro Iwabuchi, “Introduction to Coding Theory”, Shosodo Co., Ltd., December 1992, p. 135-159 Japan Radio Industry Association, “Transmission Standard for Digital Terrestrial Television Broadcasting”, ARIB STD-B31 1.1 version, Japan Radio Industry Association, November 2001 The Japan Radio Industry Association, “Technical Data for Digital Terrestrial Television Broadcasting Operation Regulations”, ARIB TR-B14 version 1.1, The Japan Radio Industry Association, July 2002

  In the conventional Viterbi decoder, it is assumed that data packets DLP including valid data are continuously received from the preceding multiple frame configuration unit. When the Viterbi decoder may continuously receive the data packet DLP, in order to perform parallel processing of writing data to the path memory by the ACS circuit and reading data from the path memory by the traceback unit It is necessary to have two memory areas operating alternately in the path memory.

  FIG. 14 is a diagram for explaining a memory operation in the conventional Viterbi decoder shown in FIG.

  Referring to FIG. 14, Viterbi decoder 108 receives TS data in units of TSP from multi-frame configuration unit 106 at the previous stage. As described above, the TSP is composed of a data packet DTP or a null packet NLP.

  At time T1, the Viterbi decoder 108 receives the data packet DTP from the multiplex frame configuration unit 106, the path information corresponding to the data packet DTP is written into the area 1 of the path memory 122, and the path information in the area 1 is Updated.

  At time T2, when a data packet DTP is input following time T1, path information corresponding to the data packet DTP is written to area 2 of path memory 122, and the path information in area 2 is updated. While the path information is being written in the area 2, the traceback unit 124 traces back the path information in the area 1, and the traceback result is read from the area 1 and written in the surviving path memory area 1. Is included.

  At time T3, when a data packet DTP is input subsequent to time T2, path information corresponding to the data packet DTP is written into area 1 of path memory 122, and the path information in area 1 is updated. While the path information is being written in area 1, the traceback unit 124 traces back the path information in area 2, and the traceback result is read from area 2 and written to the surviving path memory area 2. Is included.

  In this way, when data packets DTP are continuously input, two memory areas for storing path information are provided in the path memory, and data writing and reading are performed in parallel by alternately using them. Need to be processed.

  On the other hand, when the data packets DTP are not continuously input, the reading process from the path memory and the writing process to the path memory are not performed at the same time, and the memory configuration as described above is not necessary. However, since the conventional Viterbi decoder is based on the premise that the data packet DTP is continuously received without considering the characteristics of the input data, it is known in advance that the data packet DTP is not continuously input. In contrast, the conventional memory configuration is used.

  In the above traceback method, the current state corresponding to the minimum path metric is searched by the path metric minimum value & state search circuit 126, and traceback is performed from that state as a starting point. Here, when it is known in advance that known data is included in a part of the data, the state when the part corresponding to the known data is received can be determined in advance. Therefore, by performing the traceback using such known data, it is possible to eliminate the search process for the state corresponding to the minimum path metric.

  Therefore, the present invention has been made to solve such a problem, and an object of the present invention is to provide a Viterbi decoder that reduces the amount of necessary memory by utilizing the characteristics of input data.

  Another object of the present invention is to provide a digital receiver that reduces the amount of required memory by utilizing the characteristics of input data.

  Another object of the present invention is to provide a Viterbi decoder that performs a traceback process using characteristics of input data.

  Another object of the present invention is to provide a digital receiver that performs a traceback process using the characteristics of input data.

  According to the present invention, the Viterbi decoder is a Viterbi decoder that receives a predetermined unit of data subjected to convolutional coding at an interval corresponding to at least a predetermined unit, and is calculated based on the predetermined unit of data. A path memory that stores path information corresponding to the surviving path for each internal state, and after the path information is written to the path memory, the path information stored in the path memory is traced back to obtain the maximum likelihood path metric. A traceback unit for reading out and outputting the path information.

  Preferably, the path memory stores path information for at least a predetermined unit of data for each internal state, and the traceback unit starts from a state determined by known data included in the predetermined unit of data in the path memory. Trace back the stored path information.

  Preferably, the predetermined unit is a transport stream packet unit based on a predetermined standard.

  According to the present invention, the digital receiving device is a digital receiving device that receives a transmission signal including encoded data that has been subjected to convolutional coding, and converts the received signal into a predetermined unit of data for output. And a Viterbi decoder that receives data of a predetermined unit from the data converter and decodes the convolutionally encoded data by a maximum likelihood decoding method. At least at intervals corresponding to a predetermined unit, and the Viterbi decoder stores path information corresponding to a surviving path calculated based on data of the predetermined unit for each internal state, and a path memory After the path information is written, trace back the path information stored in the path memory, and read and output the path information having the maximum likelihood path metric. Tsu and a click portion.

  Preferably, the path memory stores path information for at least a predetermined unit of data for each internal state, and the traceback unit starts from a state determined by known data included in the predetermined unit of data in the path memory. Trace back the stored path information.

  Preferably, the reception signal is a partial reception signal modulated by an orthogonal frequency division multiplexing method.

  Preferably, the predetermined unit is a transport stream packet unit based on a predetermined standard.

  According to the present invention, in the Viterbi decoder, data writing to the path memory and data reading from the path memory are not performed at the same time in consideration of the characteristics of the input data. The amount of memory required can be halved. Therefore, the circuit area can be reduced and the power consumption can be reduced.

  Further, according to the present invention, in the Viterbi decoder, the traceback is started from the state determined by the known data included in the predetermined unit of data, and therefore the circuit for searching for the state corresponding to the minimum path metric is provided. The most likely survival path can be determined without providing it. Therefore, it is possible to further reduce the circuit area and power consumption.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  FIG. 1 is a functional block diagram schematically showing a configuration of a front end unit in a digital broadcast receiving apparatus according to the present invention.

  Referring to FIG. 1, a digital broadcast receiver 1 includes a tuner 2, an A / D converter 4, a Hilbert converter 6, a delay circuit 8, a narrow band automatic frequency tuning (AFC), A processing unit 10 that performs clock recovery and symbol synchronization processing, a fast Fourier transform unit (hereinafter also referred to as “FFT unit”) 12, a wideband AFC unit 14, a frame synchronization / TMCC decoding unit 16, a differential Detection / synchronous detection unit 18, frequency deinterleaving unit 20, time deinterleaving unit 22, demapping unit 24, bit deinterleaving unit 26, multiplex frame configuration unit 28, Viterbi decoder 30, byte demultiplexer An interleaving unit 32, an energy spreading unit 34, and an RS decoder 36 are provided.

  The tuner 2 receives an RF signal received by an antenna (not shown), down-converts the RF signal to an intermediate frequency (IF frequency), extracts a desired frequency with an IF filter, further performs frequency conversion, and performs IF frequency Are converted into baseband signals.

  The A / D converter 4 receives a baseband signal from the tuner 2 and converts the baseband signal, which is an analog signal, into a digital signal.

  The Hilbert conversion unit 6 receives the output from the A / D conversion unit 4 and performs Hilbert conversion. The delay circuit 8 delays the output from the A / D conversion unit 4 for a predetermined time and outputs it to the processing unit 10. The processing unit 10 receives outputs from the Hilbert transform unit 6 and the delay circuit 8 and performs narrow band AFC, clock recovery, and symbol synchronization processes. Then, the processing unit 10 performs a real-axis (hereinafter also referred to as “I-axis”) component signal (in-phase detection axis signal) and an imaginary-axis (hereinafter also referred to as “Q-axis”) component signal (orthogonal detection). Axis signal) is output to the FFT unit 12.

  The FFT unit 12 performs fast Fourier transform on the input signal to convert time axis data into frequency axis data. The broadband AFC unit 14 receives the output from the FFT unit 12 and performs pattern matching of a large number of pilot signals arranged at predetermined arrangement positions in the data, thereby providing a carrier in each broadcasting form. Adjust the frequency deviation in intervals.

  The frame synchronization / TMCC decoding unit 16 receives the output from the wideband AFC unit 14 and decodes a TMCC (Transmission and Multiplexing Configuration Control) signal by one bit per symbol. The TMCC signal includes a synchronization word and various transmission parameters. When the TMCC signal for one frame is decoded, the frame synchronization / TMCC decoding unit 16 determines the frame head position by detecting the synchronization word, thereby achieving frame synchronization. Thereafter, the frame synchronization / TMCC decoding unit 16 performs error correction on the TMCC signal.

  The differential detection / synchronous detection unit 18 modulates each of DQPSK (Differential Quadrature Phase Shift Keying), 16 QAM (Quadrature Amplitude Modulation), 64 QAM, and QPSK (Quadrature Phase Shift Keying) based on various transmission parameters included in the TMCC signal. The system is determined, and demodulation processing is performed based on the determination result.

  The frequency deinterleaving unit 20 receives the output from the differential detection / synchronous detection unit 18 and performs processing to restore the frequency interleaving performed to compensate for the loss of a signal of a specific frequency due to radio wave reflection or the like. The time deinterleaving unit 544 performs processing for restoring the time interleaving performed for pair fading and the like.

  The demapping unit 24 converts the I-axis component signal and Q-axis component signal subjected to time deinterleaving into a signal of 6 bits (in the case of QPSK), 12 bits (in the case of 16 QAM) or 18 bits (in the case of 64 QAM). Convert. The bit deinterleaving unit 26 performs processing for canceling bit interleaving performed for the purpose of increasing error resilience.

  The multiplex frame configuration unit 28 receives the output from the bit deinterleave unit 26, converts the received data into TS data, and outputs the TS data in units of TSP. The configuration of the multiplex frame configuration unit 28 is the same as the configuration of the multiplex frame configuration unit 106 described in the background art.

  The Viterbi decoder 30 receives TS data from the multiplex frame configuration unit 28 in units of TSP, and performs Viterbi decoding on the TS data that has been convolutionally encoded on the transmission device side to perform error correction. The configuration of the Viterbi decoder 30 will be described in detail later.

  The byte deinterleaving unit 32 cancels byte interleaving performed for the purpose of increasing error resilience, similarly to bit interleaving. The energy spreader 34 receives the output from the byte deinterleaver 32 and performs energy spread processing. The RS decoder 36 receives the output from the energy spreading unit 34 and RS-decodes TS data that has been RS-encoded on the transmission device side.

  Then, the RS-decoded TS data is decompressed by a compressed signal in an MPEG decoding unit (not shown) and converted into analog video or analog audio via a digital / analog conversion unit (not shown).

  The multiple frame configuration unit 28 configures a “data conversion unit”.

  FIG. 2 is a diagram for explaining the structure of TS data received by the Viterbi decoder 30 shown in FIG.

  Referring to FIG. 2, TS data generated by multiple frame configuration unit 28 and input to Viterbi decoder 30 is made up of TSP units, and TSP is made up of data packet DTP or null packet NLP as described above. The enable signal is generated by the multiplex frame configuration unit 30 and becomes H (logic high) level in accordance with the output of the data packet DTP.

  Here, the digital receiving apparatus 1 uses the OFDM method as a digital modulation method, and further performs partial reception for receiving only one segment out of 13 segments constituting the symbol. Then, according to the standards shown in Non-Patent Documents 2 and 3 described above, when receiving 13 segments, the data packet DTP continues when receiving data as described in the background art, whereas when receiving partially, According to the above standard, data packets DTP do not continue even when the carrier modulation scheme and the coding rate are assumed to be 16 QAM and 1/2 maximum transmission capacities, respectively.

  Therefore, as shown in FIG. 2, data packets DTP do not continue in TS data, and in this digital broadcast receiving apparatus 1 in which partial reception is performed, the TSP next to the data packet DTP is always a null packet NLP. It becomes. As described above, the enable signal becomes H level according to the data packet DTP.

  Furthermore, predetermined known data is added to the last part of all TSPs.

  FIG. 3 is a diagram showing a TSP configuration received by the Viterbi decoder 30 shown in FIG.

  Referring to FIG. 3, “47” (hereinafter referred to as “47Hex”) expressed in hexadecimal is always added as the known data to the last part of each TSP. That is, the TS data necessarily includes 47 Hex at regular intervals. Therefore, by using this known data, the optimum path can be uniquely determined when the Viterbi decoder 30 traces back the path memory, as will be described later.

  FIG. 4 is a functional block diagram schematically showing the configuration of the Viterbi decoder 30 shown in FIG.

  Referring to FIG. 4, the Viterbi decoder 30 includes a branch metric calculation circuit 52, an ACS circuit 54, a path metric memory 56, a path metric minimum value search circuit 58, a path memory 60, and a traceback circuit 62. including. Since branch metric calculation circuit 52, ACS circuit 54, and path metric memory 56 are the same as the circuits in Viterbi decoder 108 described in the background art, description thereof will not be repeated.

  The path metric minimum value search circuit 58 searches for the minimum value among the path metrics in each state, and performs processing for normalizing the path metric stored in the path metric memory 56.

  The path memory 60 stores path information for identifying each surviving path for each state selected by the ACS circuit 54 for the length of the path memory. Here, the path memory 60 does not include two memory areas that operate alternately as described in the background art. The reason for this is that, as described above, in the digital reception device 1, when partial reception is performed, the Viterbi decoder 30 does not continuously receive the data packets DTP as shown in FIG. This is because the path memory 60 can serially process the data writing by the ACS circuit 54 and the data reading by the traceback circuit 62 described later.

  The traceback circuit 62 traces and reads the path information stored in the path memory 60 in the reverse direction with respect to time. Here, the traceback circuit 62 traces the path information using 47Hex of known data included in the path information for 1 TSP stored in the path memory 60. That is, since 47 Hex, which is known data, is added to the last part of the TSP, the traceback circuit 62 traces path information for 1 TSP starting from the state determined by this known data.

  Therefore, in this Viterbi decoder 30, the path metric minimum value search circuit 58 corresponds to the minimum path metric provided in the path metric minimum value & state search circuit 126 in the Viterbi decoder 108 described in the background art. There is no processing to retrieve the status.

  Although not particularly illustrated, each circuit included in the Viterbi decoder 30 receives an enable signal from the multiple frame configuration unit 28, and when the enable signal is at L (logical low) level, the branch metric calculation circuit 52, ACS The circuit 54 and the path metric minimum value search circuit 58 stop operating, and the path metric memory 56 and the path memory 60 hold stored data.

  FIG. 5 is a functional block diagram showing the configuration of the path memory 60 shown in FIG.

  Referring to FIG. 5, the path memory 60 includes a memory area 602 and a memory control unit 604. The memory area 602 stores path information for identifying the surviving path for each state selected by the ACS circuit 54 for 1 TSP. The memory control unit 604 serially controls data writing to and data reading from the memory area 602. Here, since the path memory 60 does not include two memory areas that operate alternately, the required memory amount is ½ compared to the case where the path memory 60 includes two memory areas that operate alternately.

  FIG. 6 is a functional block diagram showing a configuration example of a path memory assuming that the Viterbi decoder continuously receives data packets DTP. Note that this path memory is an example shown for comparing the configuration with the path memory 60 shown in FIG. 5, and is not actually included in the Viterbi decoder 30.

  Referring to FIG. 6, path memory 60A includes first and second memory areas 602A and 602B, a memory control unit 604A, and select switches 606A and 606B. The first and second memory areas 602A and 602B alternately store path information for identifying the surviving path for each state selected by the ACS circuit 54 for 1 TSP.

  The memory control unit 604A switches the select switches 606A and 606B every time TSP is received. When the path information is written in the first memory area 602A, the memory control unit 604A controls the select switches 606A and 606B so that the path information is read from the second memory area 602B. When the path information is written in the second memory area 602B, the select switches 606A and 606B are controlled so that the path information is read from the first memory area 602A.

  Thus, the path memory 60 shown in FIG. 5 can halve the required memory amount as compared with the path memory 60A shown in FIG.

  FIG. 7 is a diagram for explaining a memory operation in the Viterbi decoder 30 shown in FIG.

  Referring to FIG. 7, the Viterbi decoder 30 receives TS data in units of TSP from the multiple frame configuration unit 28 in the previous stage. The TSP includes a data packet DTP or a null packet NLP. As described above, the data packet DTP is not continuously input to the Viterbi decoder 30.

  At time T1, the Viterbi decoder 30 receives the data packet DTP from the multiplex frame configuration unit 28, and the path information corresponding to the data packet DTP is written into the memory area 602 of the path memory 60, and the path in the memory area 602 Information is updated.

  At time T <b> 2, the Viterbi decoder 30 receives a null packet NLP from the multiple frame configuration unit 28. Therefore, the Viterbi decoder 30 does not write data to the memory area 602 of the path memory 60. On the other hand, the traceback circuit 62 traces back the path information of the memory area 602, and the traceback result is read from the memory area 602 and written into the surviving path memory area.

  Also at time T3, the Viterbi decoder 30 receives the null packet NLP from the multiple frame configuration unit 28. Therefore, the Viterbi decoder 30 does not write data to the memory area 602 of the path memory 60. On the other hand, the traceback circuit 62 reads the traceback result from the surviving path memory area and outputs the read result as a decoding result.

  FIG. 8 is a diagram for explaining the operation of each unit of the Viterbi decoder 30 shown in FIG.

  Referring to FIG. 8, at times T <b> 1 to T <b> 2, Viterbi decoder 30 receives null packet NLP and an enable signal that becomes L level accordingly from multiplex frame configuration unit 28. Then, branch metric calculation circuit 52, ACS circuit 54, and path metric minimum value search circuit 58 each stop operating, and path metric memory 56 and path memory 60 hold the stored path metric and path information, respectively. To do. Note that the state of the traceback circuit 62 depends on the state before time T1.

  At times T <b> 2 to T <b> 3, the Viterbi decoder 30 receives the data packet DTP and an enable signal that becomes H level in response thereto from the multiplex frame configuration unit 28. Then, each of branch metric calculation circuit 52, ACS circuit 54, and path metric minimum value search circuit 58 performs the predetermined processing described above. Then, the contents of the stored path metric are updated in the path metric memory 56, and the path information corresponding to the received data packet DTP is written in the path memory 60.

  During this period, since the path information is written in the path memory 60, the traceback circuit 62 stops operating. Further, during the period of receiving 47 Hex known data added to the last part of the data packet DTP, as shown in the figure, the branch metric calculation circuit 52 outputs the branch metric corresponding to the known data. Termination processing may be performed, and the path metric memory 56 may perform internal termination processing (for example, set to a minimum value) for initializing the path metric.

  At times T <b> 3 to T <b> 4, the Viterbi decoder 30 receives the null packet NLP and the enable signal that becomes L level accordingly from the multiplex frame configuration unit 28. Therefore, as in the case of times T1 to T2, each of branch metric calculation circuit 52, ACS circuit 54, and path metric minimum value search circuit 58 stops its operation. On the other hand, the traceback circuit 62 traces back the path information written in the path memory 60 at times T2 to T3, and writes the maximum likelihood survivor path to the survivor path memory.

  At times T4 to T5, the Viterbi decoder 30 receives the null packet NLP and the enable signal that becomes L level in response thereto from the multiplex frame configuration unit 28. Therefore, following time T3 to T4, each of branch metric calculation circuit 52, ACS circuit 54, and path metric minimum value search circuit 58 stops its operation. On the other hand, the traceback circuit 62 reads the maximum likelihood survivor path written in the survivor path memory from time T3 to T4, and outputs the read maximum likelihood survivor path as a decoding result.

  The processing of each circuit at times T5 to T6 is the same as the processing of each circuit at times T2 to T3.

  As described above, according to the digital receiver 1 according to this embodiment, in consideration of the characteristics of the received signal at the time of partial reception, data writing to the path memory and data from the path memory in the Viterbi decoder 30 are performed. Since reading is not performed at the same time, the required memory capacity of the path memory in the Viterbi decoder 30 can be halved. Therefore, the circuit area can be reduced and the power consumption can be reduced.

  Also, according to the digital receiver 1 according to this embodiment, the Viterbi decoder 30 traces back the known data included in the last part of the TSP as a starting point, so that a state corresponding to the minimum path metric is searched. The most likely survival path can be determined without providing a circuit. Therefore, it is possible to further reduce the circuit area and power consumption.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiment but by the scope of claims for patent, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims for patent.

  The Viterbi decoder and the digital receiver according to the present invention can be used in digital partial reception broadcasting and communication. The Viterbi decoder according to the present invention is not limited to digital partial reception, and can be applied to a system in which input data input to the Viterbi decoder is intermittent.

It is a functional block diagram which shows roughly the structure of the front end part in the digital broadcast receiver by this invention. It is a figure for demonstrating the structure of TS data which the Viterbi decoder shown in FIG. 1 receives. It is a figure which shows the structure of TSP which the Viterbi decoder shown in FIG. 1 receives. FIG. 2 is a functional block diagram schematically showing a configuration of a Viterbi decoder shown in FIG. 1. FIG. 5 is a functional block diagram illustrating a configuration of a path memory illustrated in FIG. 4. It is a functional block diagram which shows the structural example of the path memory which assumes that the Viterbi decoder receives the data packet DTP continuously. FIG. 5 is a diagram for explaining a memory operation in the Viterbi decoder shown in FIG. 4. FIG. 5 is a diagram for explaining the operation of each unit of the Viterbi decoder shown in FIG. 4. It is a functional block diagram which shows roughly the structure of the conventional digital broadcast receiver provided with a Viterbi decoder. FIG. 10 is a functional block diagram schematically showing a configuration of a multiplex frame configuration unit shown in FIG. 9. FIG. 10 is a functional block diagram schematically showing a configuration of a Viterbi decoder shown in FIG. 9. It is a figure which shows the structure of the effective data in an OFDM symbol. It is a figure which shows the structure of each segment shown in FIG. It is a figure for demonstrating the memory operation | movement in the conventional Viterbi decoder shown in FIG.

Explanation of symbols

  1,100 Digital broadcast receiver 2 Tuner 4 A / D converter 6 Hilbert converter 8 Delay circuit 10 Processing unit 12 FFT unit 14 Wideband AFC unit 16 Frame synchronization / TMCC decoding unit 18 Difference Dynamic detection / synchronous detection unit, 20 frequency deinterleaving unit, 22 time deinterleaving unit, 24 demapping unit, 26 bit deinterleaving unit, 28,106 multiple frame configuration unit, 30,108 Viterbi decoder, 32 byte deinterleaving unit , 34 Energy spreading unit, 36, 110 RS decoder, 52 branch metric calculation circuit, 54 ACS circuit, 56 path metric memory, 58 path metric minimum value search circuit, 60, 60A, 122 path memory, 62, 124 Traceback circuit , 102 antenna, 104 demodulator, 1 2 Hierarchy division / Hierarchy synthesis unit, 114 TS buffer, 116 Null packet generation unit, 118, 606A, 606B Select switch, 120 TS playback unit, 126 Path metric minimum value & state search circuit, 602 Memory area, 602A First memory Area, 602B Second memory area, 604, 604A Memory control unit.

Claims (2)

A digital receiver that partially receives terrestrial digital broadcast data,
A data conversion unit that outputs a received signal for each data of a transport stream unit based on the ARIB standard ;
A Viterbi decoder for decoding the data output from the data converter by a maximum likelihood decoding method,
The Viterbi decoder is
A path memory for storing path information corresponding to the surviving path calculated based on the data of the transport stream unit at least for the data of the transport stream unit ;
After the path information is written to the path memory, the path information stored in the path memory is traced starting from a state determined by known data included in the last part of the transport stream unit data. by back, and a traceback unit for outputting path information with the highest likelihood path metric is read, digital receiver.   2. The digital receiving apparatus according to claim 1, wherein only one segment is partially received out of 13 segments constituting a symbol of digital terrestrial broadcasting data modulated by OFDM.

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