JP2002530996A - Signal processing at different data rates - Google Patents

Abstract

(57) [Summary] A wireless communication system is described. In one embodiment, a set of demodulation resources demodulates a set of signals that can be transmitted at a set of rates. For signals transmitted at low data rates, all signals are demodulated with one demodulation resource. For signals transmitted at a high data rate, two or more demodulation resources share the signal and each partially demodulates. Advantageously, the first and second parts of the high rate signal are substantially different.

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION FIELD OF THE INVENTION The present invention relates to wireless communications. In particular, the invention relates to data transmitted at various rates in a wireless communication system. II. 2. Description of the Related Art Mobile digital wireless communications have been used initially to provide voice communications. With the advent of the World Wide Web, e-mail and computer networking, the need for data-based wireless communication has been increasing.

[0002] Data communications typically require higher data rates and more diverse data rates than voice-based wireless communications. This increased variety in communication rates typically increases the complexity and circuit size of the systems used to process and generate the data to be transmitted. Increasing complexity and circuit size typically increase costs.

The present invention seeks to reduce the complexity and size of systems that process data at various rates, and consequently the cost.

SUMMARY OF THE INVENTION A wireless communication system will be described. In one embodiment of the invention, the set of demodulation resources demodulates a set of signals that can transmit data at a set of rates. For signal transmission at lower data rates, a single demodulation resource demodulates all signals. For signal transmission at higher data rates, two or more demodulation resources each demodulate a portion of the signal. Advantageously, the first part of the higher rate signal is substantially different than the second part.

[0005] The features, objects and advantages of the present invention will become more apparent from the detailed description set forth below, together with the drawings, in which like reference numerals identify corresponding parts throughout.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A wireless communication system will be described. An exemplary embodiment is described with reference to the reverse link of a cellular telephone system. Different embodiments of the present invention may be incorporated in different environments and configurations, while use in such a relationship is advantageous. In general, the various systems described herein are software controlled processors, integrated circuits, or discrete logic.
) Can be formed. Newer implementations are also consistent with the use of the present invention, including the use of biological or chemical computing systems.

In addition, data, commands, instructions, information, signals, codes and chips, which can be referenced throughout the application, are conveniently voltages, currents, electromagnetic waves, magnetic fields or particles, light fields (chips). optical field) or fine particles,
Alternatively, it is expressed by a combination of these. Further, the blocks shown in each block diagram may represent hardware or method steps.

FIG. 1 is a block diagram of a wireless communication system configured according to one embodiment of the present invention. Subscriber units 10A and 10B interface with base station 12 using digitally modulated radio frequency signals. The reverse link is the signal transmitted from subscriber units 10A and 10B to base station 12, and the forward link is the signal transmitted from base station 12 to subscriber unit 10.
The base station controller (BSC) 14 and the mobile switching center (MSC) have call and data routing functions as well as call mobility management.

[0009] Both the reverse and forward links carry different types of data at different rates. For example, a telephone call based on voice is 10 kilobits per second (Kbi
ts / sec). 64Kbits
/ Sec data rate is in web browsing
sing), and used for data communication for applications such as video conferencing. By way of illustration, subscriber unit 10A is shown as a cellular telephone and subscriber unit 10B is shown as a laptop computer.

FIG. 2 shows a block diagram of a reverse link transmission system configured according to one embodiment of the present invention. As illustrated by FIG. 1, the system typically comprises
(Shown as a cellular telephone and a computer) at any given time, including a complex transmission system similar to that transmitted to base station 12. In one embodiment of the present invention, some subscriber units 10 may transmit to base station 12 in a different cooperative manner than that shown in FIG. For example, some subscriber units 10 may transmit according to the IS-95 standard, or one of its derivatives, while other subscriber units 10 transmit according to those shown in FIG. I do. A system and method of processing RF signals essentially according to the use of the IS-95 standard is described in US Pat. No. 5,103,459 entitled "System and Method for Generating Signal Waveforms in CDMA Cellular Telephone Systems." Described in
Assigned to the assignee of the present invention and incorporated herein by reference (the '459 patent).

Still referring to FIG. 2, each data frame is a data frame that includes one of four possible data volumes, and during the “low data rate mode”, the data frame is received at input A1. Is done. Different amounts of data correspond to different data rates, with a set of different data rates referred to as a “rate set”. The four data rates have four different amounts of voice activity (amount of vo
The low data rate mode typically corresponds to voice-based communication, corresponding to the activity. The CRC generator 100.1 adds CRC checksum bits to some frames depending on the rate and the rate set. In addition, a known value of tail bits (preferably all logic zeros) is added to each frame by tail bit generator 102.1. The number of tail bits is preferably equal to k-1, where k is the encoder depth. In one embodiment of the invention, eight tail bits are added.

In one embodiment of the present invention, two different rate sets may be utilized. Different rate sets correspond to two different levels of voice quality, with the rate set having the highest data rate with the highest voice quality. The different rate sets are identified by the highest rate (or "rate 1") in each set, each set being 9.6K bits per second for the first rate set (8K rate set) and the second Rate set (13K rate set) is 14.4K bits per second. The three additional rates in the rate set are referred to as a half (1/2) rate, a 1/4 rate, and a 1/8 rate based on a fraction that approximates that rate compared to rate 1. Such low data rates are over-the-a for IS-95 and IS-95B wireless communications.
ir) As found in interface standards.

In order to perform “medium” rate transmissions (ie, higher rate transmissions than those utilized in the low data rate mode) using the system shown in FIG. Input to A8. In one embodiment of the invention, the total number of inputs A1-A8 used must be an integer power of two. This is an intermediate rate approximately equal to twice (Rate 2), 4 (Rate 4) and 8 (Rate 8) of Rate 1 of one of the two rate sets (8K and 13K). Provide transmission.

This modulation provides a total of six additional intermediate transmission rates, and a total of 14 possible rates. The 14 rates can be split into two sets, one related to 13K and the other related to 8K. The 14 data rates, taken together, are 8K, Rate 8, Rate 4, Rate 2, Rate 1, Half rate, 1
４ rate and ８ rate, and rate 8, rate 4, rate 2, rate 1, half rate, ４ rate and ８ rate for 13K. In one embodiment of the present invention, subscriber unit 10 operates in either a lower data rate mode or an intermediate data rate mode. However, in other embodiments of the invention, the subscriber units can operate at any available data rate.

The data received at inputs A1-A8 during the "intermediate data rate mode" is a single data that is convolutionally encoded by convolutional encoder 106 at a rate that depends on the data rate as described below. Multiplexer 104 to stream
Are time multiplexed. The repeater 108 provides a rate R (either rate 1 to 1/8 rate, referred to herein as "low rate") for either an 8K or 13K rate set, for rate 1 or lower transmission rates. It performs symbol repetition, and Walsh cover also modulates the low rate transmission with a low rate Walsh code WL depending on the data rate.

The puncture circuit 110 punctures a data stream for data transmission related to a 13K frame according to a puncture factor P. A puncture factor P of 1/3 means that one out of a total of three code symbols is removed from the data stream. This effectively reduces the rate coding performed on the data, but allows more data to be transmitted, thereby increasing the data rate. For example, if the encoder 106 performs encoding with R = 1/4 and the puncture factor P is 1/3, the effective encoding rate RE is RE = 3/8.

Interleaver 112 performs block interleaving of 20 ms blocks of transmitted data, whatever the data rate. Thus, at any time of interleaving, the amount of data or the number of code symbols depends on the data transmission rate.

The intermediate rate repeater circuit 114 relays intermediate rates according to the intermediate rate relay factor RM. Furthermore, for intermediate rate data transmission (rates 2, 4 and 8), the intermediate rate Walsh cover circuit 116 modulates the symbols with an intermediate rate Walsh code WM depending on the high data rate used. .

In one embodiment of the present invention, various parameters used for the system of FIG. 2 are listed in Table 1.

[Table 1]

Where Walsh code entries are left empty, no Walsh code modulation is performed. The subscript for each rate (8 or 13) indicates whether the particular data rate is associated with the 8K or 13K rate. As is evident, the repetition rates RL and RM are adjusted to keep the effective symbols constant. Keeping the effective symbol rate constant simplifies the processing of various rates of data at the end of both transmission and reception. Performing low and medium rate Walsh code modulation at different stages during processing facilitates distinguishing low rate transmissions from intermediate rate transmissions. For both low and medium data rates, Walsh code modulation also facilitates determining the rate at which data is being sent.

In one embodiment of the present invention, the gate circuit 118 uses one to prevent power consumption.
Open / close the gate for the / 8 rate frame. This gating involves transmitting only the last half of the frame, or 10 ms. Further, the gate circuit 1
18 also gates half rate and quarter rate frames when the subscriber unit 10 is in "search mode". Gating for these frames is preferably performed in the same way as for 1/8 rate frames. That is, the first half of the frame, or 10 ms, is blocked. During the gating of any frame, the subscriber unit 10 can search for another forward link in a frequency band that is not currently being processed. this is,
It facilitates performing a hard handoff, which occurs when the subscriber unit switches frequency bands operating in that frequency band (as in the other examples).

The resulting chip stream from gate circuit 118 is repeated by 2 × circuit 120, and the output of 2 × circuit 120 is coupled to Walsh traffic channel using XOR gate 122.
nel) code Wc, t and is then gain adjusted by a traffic channel gain adjustment Gt using a multiplier or amplifier 124. Further, pilot data is multiplexed with control data and 2
X is repeated by circuit 120 and covered with control channel Walsh code Wc, c using XOR gate 122. Pilot channels may also be gain adjusted in some embodiments of the present invention.

The control data is typically a power control command, which is generated in response to the forward link signal and which is the transmission power of the channel in the forward link signal allocated to communicate with the terminal. Should be increased, decreased or kept constant.

The resulting traffic channel data and control channel data are combined using an in-phase PN code and a quadrature PN code using a composite multiplier 126 to produce an in-phase term XI and a quadrature term XQ. It is. The in-phase term XI and the quadrature-phase term XQ are filtered by a low-pass filter 128 and upconverted by the mixer 130 with the in-phase and quadrature-phase carriers respectively.
t), summed by summer 132, gain adjusted by amplifier 134, and transmitted.

FIG. 3A illustrates a data frame structure for medium rate data transmission used in one embodiment of the present invention. As noted earlier, in one embodiment of the present invention, each frame corresponds to a duration of 20 ms.

In rate 1 frame 150, the frame consists of data field 160, CRC
A checksum field 162 and a tail data field 164 are included. Tail data field 164 is used to clear the convolutional encoder during encoding and assist in decoding. Tail data field 164 can be any known data sequence. In order to completely clear the decoder, the length of the data sequence is less than the depth K of the convolutional coding. In one embodiment of the invention, the encoding depth K is 9 and the tail data field 164 contains eight logic zeros. CRC checksum field 162
And the use of the tail data field 164 is preferred, but other embodiments of the invention may use a different "control" field.

In rate 2 frame 152, the frame includes data fields 160.2 and 160.3, CRC fields 162.2 and 162.3, and tail data fields 164.2 and 164.3. In one embodiment of the present invention, the format and size of data fields 160.2 and 160.3 correspond to data field 160.1. Similarly, CRC fields 162.2 and 1
The format and size of 62.3 is the same as that of CRC field 162.1, and the format and size of tail data fields 164.2 and 164.3 are the same as tail data field 164.1.

In rate 4 frame 154, the frames are data fields 160.4, 1
60.5, 160.6 and 160.7, CRC fields 162.4, 162.
5, 162.6 and 162.7 and tail data fields 164.4, 16
4.5, 164.6 and 164.7. In one embodiment of the present invention, the format and size of data fields 160.4, 160.5, 160.6, and 160.7 are data fields 160.1 (and therefore data fields 160.2 and 160.3). ). Similarly, CRC field 162
. 4, 162.5, 162.6 and 162.7 have the format and size C
It is the same as that of the RC field 162.1, and the format and size of the tail data fields 164.4, 164.5, 164.6 and 164.7 are the same as the tail data field 164.1.

For a rate 8 frame, the frame consists of data fields 160.8-160.
15, a CRC field 162.8-162.15 and a tail data field 164.8-164.15. In one embodiment of the present invention, the format and size of data fields 160.8-160.15 are data fields 160.1 (and therefore data fields 160.2 and 160.7).
Is equivalent to Similarly, the format and size of CRC field 162.8-162.15 is the same as that of CRC field 162.1, and the format and size of tail data field 164.8-164.15 are tail data field 164. Same as 1.

Having the format and size of the various fields that are the same as the corresponding fields of the different rate frames facilitates processing of different rate frames. In particular, the circuitry used to generate one-rate frames can be used to easily generate high-rate frames by increasing the rate at which these circuits operate. Allowing the same circuitry to be used for different rate frames reduces the amount of total circuitry required to perform the necessary transmission and reception processing, and therefore some embodiments of the present invention The size and cost of any integrated circuits or systems that operate in conjunction with the above are also reduced. The processing rate is also increased because less alternation to the processing path is required.

Increasing the rate of operation of the circuit can take many forms, including reducing the time division of the circuit during each frame or increasing the duration of operation of the circuit. Also, while the preferred embodiment of the present invention has equivalent fields of different rate frames that are identical in both format and size to maximize circuit reuse, other embodiments of the present invention have the same Or just need to have some attributes of a similar corresponding field.

For example, the size of the corresponding fields can be the same, but the format is not the same. Or, the format may be the same for some of the data for some fields, but different rate frames may have additional data in these fields. In other embodiments,
The size and format of the fields can be different, but the order of the fields repeats in the same order with respect to the order of the other rate frames. In either case, the field, size, formatting, or similarity between the various rate frames facilitates both the data reception and transmission processes.

In one embodiment of the present invention, for a data frame processed essentially according to the IS-95 standard, the data field size decreases as the transmission rate decreases, and the number of transmitted bits is Reduced by transmission gating. A system and method for formatting lower rate frames is disclosed in US Pat. No. 5,504, entitled "Method and Apparatus for Formatting Data for Transmission."
No. 773, assigned to the assignee of the present invention and incorporated herein by reference.

The frame format used in one embodiment of the present invention, as another low rate frame, such as some rate frames listed in Table 1, is shown in FIG. 3B. Each frame includes user data 170, CRC data 172, and tail bit data 174. The number of bits for some types of data varies from rate to rate as shown. In one embodiment of the present invention, as high data frames, a rate 1 frame format is used for each set of user, CRC and tail data fields.

FIG. 4 is a block diagram of a base station configured according to one embodiment of the present invention.
RF unit 362 receives the RF signal via the antenna and filters, downconverts, and digitizes the RF signal, which produces a baseband sample. In one embodiment of the present invention, each antenna and RF unit is used to provide telephone service to a coverage area of the base station. Each sector typically also has more than one antenna for additional diversity.

Baseband samples are received by a cell site modem (CSM) 366 controlled by a control unit 364. A CSM is typically an integrated circuit.
In one embodiment of the invention, control unit 364 is a microprocessor, typically controlled by software instructions stored in memory. CSM3
66 demodulates a set of signals included in the baseband received samples that generate data to be transferred to a data formatter 368. Data formatter 368 places the data into packets containing address information and forwards the packets to the base station controller.

In one embodiment of the invention, individual systems or integrated circuits perform the modulation and demodulation functions performed by CSM 366.

FIG. 5 is a block diagram of a demodulation unit of CSM 366 when configured according to one embodiment of the present invention. During the exemplary operation of the exemplary embodiment of the invention provided herein, the signal processing circuit receives the reverse link signal generated by a transmission system similar to that shown in FIG. And process. The circuits preferably operate on a single integrated circuit, with control functionality provided either on the same integrated circuit or externally. Control functionality is typically performed by software stored in memory running on a microprocessor. In general, tasks are divided between a microprocessor and a DSPS as described herein. However, alternative embodiments of the present invention may assign tasks differently.

In an exemplary process, the down-converted baseband received samples (RX_IQ) are:
An external RF of FIG. 4 is provided by an interpolator 300.
Received from unit. The interpolator 300 includes the searcher subsystem 30
2 and generate the interpolated samples received by channel element 312. The searcher subsystem 302 periodically searches for a reverse link signal,
The results of these searches are provided to the SP controller 304 and an external control system (not shown). An external controller (microprocessor) can respond by deciding which signals are to be processed and assigning channel elements 312 to process the signals. The assignment is typically made by providing a time offset of the signal to be processed to a particular channel element 312. In the described embodiment of the invention, each channel element is associated with a respective finger (
Multiple instances of the signal can be handled, where the fingers are referred to as fingers requiring different time offsets. Thus, an external controller can provide multiple time offsets to the channel element 312.

In one embodiment of the present invention, the received samples are received at one of two rates: a 2 × spread chip rate (Chip × 2) or an 8 × spread chip rate (Chip × 8). Can be done. When the received samples RX_IQ are received at Chip × 2, interpolator 300 interpolates the samples to a rate of eight times the spreading rate (Chip × 8). When a sample is received at Chip × 8, interpolator 30
0 is bypassed. This allows the system to operate in differently configured systems, such as providing samples in either Chip × 8 or Chip × 2.

Digital signal processor (DSP) 304.0 includes channel elements 312.
Interfaces 0-312.5, and DSP 304.1 interfaces to channel element 312.6-312.11. Viterbi decoder 31
6.0 is an intermediate rate Walsh (Wm) recover 3
Deinterleaver via 23.0-323.3
) Interface to 322.0-322.3. Viterbi decoder 316.1
Interfaces to the deinterleaver 322.4-322.7 via an intermediate rate Walsh decover 323.4-323.7. Viterbi decoder 3
16.3 interfaces to the deinterleaver 322.8-322.11 via an intermediate rate Walsh decover 323.8-323.11. The channel element 312 is a multiply-accumulate.
) (MAC) to the deinterleaver 322. In an alternative embodiment of the invention, a different number of DSPSs may be used, including one DSP.

In one embodiment of the present invention, channel element 312 includes de-spreading and medium-rate Walsh dec for medium-rate transmission.
perform a variety of functions, including overriding. Further, the channel element 31
2 is a symbol drop on part of the data processed for intermediate rate transmission
(Symbol drop). Preferably, the specific amount and the specific part of the dropped data are the transmission rate of the data being processed and the corresponding DSP3
04 depends on the control input.

During exemplary processing by the demodulation system of FIG. 4, DSP 304 receives instructions to process incoming signals transmitted at either an intermediate data rate or a lower data rate, and if the signal is a particular Allocate one channel element 312 to process the signal if lower than the rate, and two or more to process the signal if the signal is being transmitted at a data rate above a particular rate. Assign more channel elements. In one embodiment of the present invention, if the signal is being transmitted at a low data rate or a data rate intermediate between Rate 1 or Rate 2, the microprocessor may use one channel element 31 to process the signal.
Assign 2.

If the signal is being transmitted at an intermediate data rate between rate 4 or rate 8, DSP 304 allocates more than one channel element 312 to process the signal. In particular, if the signal is being transmitted at a data rate intermediate to rate 4, DSP 304 allocates two channel elements 312 to process the signal, and if the signal is at a data rate intermediate to rate 8, If so, the microprocessor allocates four channel elements 312 to process the signal. Where multiple channel elements are assigned, each channel element processes only a portion of the incoming signal. For example, 2
If one channel element has been assigned, each channel element processes one half of the signal. With four channel elements, each channel element processes one quarter of the signal.

Further, in one embodiment of the present invention, the DSP or microprocessor may include a channel element assigned to process higher rate signals (in one embodiment of the present invention, rate 4 and rate 8). To channel element type (CE_TYPE)
Is assigned. The particular part of the signal processed by a particular channel is determined by the type of channel element, one example of which will be described in greater detail below.

After the signal has been processed by channel element 312, the resulting despread chip data is accumulated by MAC 320 for the duration of the symbol,
The MAC then performs the accumulation for each channel element, preferably in a time-sharing manner. In addition, the MAC calculates the vector product of the pilot traffic channel and sums the results over the set of fingers being processed by a particular channel element. The resulting resulting symbol data is forwarded to a deinterleaver 322, which performs time division deinterleaving and demodulation for the channel elements. The deinterleaver 322 is
Each 20 ms frame of received data is deinterleaved, and the data received for different rates corresponds to different amounts of data. For higher data rates, the symbol drop performed by channel element 312 reduces the amount of data processed by each deinterleaver 322. This reduces the required size of the memory of the deinterleaver 322, and the memory of the deinterleaver 322 essentially reduces the overall circuit area of the demodulation system.

The intermediate rate Walsh decoverer performs low rate Walsh decovering and forwards the recovered soft decision data to the Viterbi decoder 316.
For intermediate rate transmission, Viterbi decoder 322 decodes the soft decision data at the specified transmission rate. For low rate transmission, the Viterbi decoder 316
Decode at all four data rates, with the actual used data rate determined by the error and the probability value generated thereby. Determine the rate 1
One method is described in U.S. Pat. No. 5,566,206 entitled "Method and Apparatus for Determining Data Rates of Various Rates of Data Transmitted in a Communication Receiver".
And assigned to the assignee of the present invention and incorporated herein by reference. The output data is then made available for additional processing, which in an exemplary embodiment of the present invention includes forwarding to the base station controller 14 of FIG. .

As should be apparent in the described embodiment, channel element 312, deinterleaver 322, medium rate Walsh decover 323 and time division MAC 32
0 forms a channel resource. As described throughout that application, the channel resources may be used to process some intermediate and lower rate signals, or in combination with other channel resources, other intermediate rate signals (highest rate intermediate rate signals). Signal) can be used alone.

FIG. 6 illustrates a channel element 312 when configured according to one embodiment of the present invention.
It is a block diagram of. RX_IQ samples are received by four finger processors 570. Each finger processor processes one example of a particular signal assigned to the associated channel element at a time offset provided by the control system (connection from the control system, not shown). The demodulated symbols from finger processor 570 are transferred to the MAC of FIG.

FIG. 7 shows a finger processor 5 when configured according to one embodiment of the present invention.
70 is a block diagram of FIG. Antenna select 500 selects one set of RX samples from the supplied set of received samples. According to the base station described previously, six sets of RX samples are provided, corresponding to two antennas for each sector. The antenna to be selected is determined by the searcher 302, working with the controller, searching for each set of RX samples for the incoming multipath, and each set of RX samples is provided to the antenna select 500. Generate a select signal.

The selected RX samples are forwarded to a decimator 502, which reduces the RX samples by 10 × chip × 2. The phase rotator 504 is RX
An initial phase adjustment of the sample is made, and the despreader 505
The signal is demodulated using the pseudo noise (PN) spreading code from 06. A particular PN generator 506 generates the code, and a particular time offset is determined by the timing and control unit 507 and its timing and control unit 5
07 are sequentially controlled by the DSP unit 304.0 based on the search results received from the searcher 302 by the DSP unit 304.0.

The despreading-decovering 505 provides three signals for the signal being processed by despreading using PNI and PNQ codes and control and traffic channel Walsh codes (WC, T and WC, C). Generate a set of outputs. Each set of outputs includes in-phase and quadrature components. The set of three outputs corresponds to on-time despreading, pre-on-time despreading, and post-on-time despreading. On-time despreading is the best estimate of the signal time offset, and in one embodiment of the invention, the on-time despreading is offset by the duration of the spreading chip before the on-time despreading, and Spreading is offset by the duration of the spreading tip after the scheduled despreading.

The 2 × accumulator 510 accumulates data despread by the two spreading chips,
Then, the data accumulated on time is supplied to an iterative decovering circuit 512 of an intermediate rate. The data that has been despread and stored before and after the time period is directly transferred to the DSP 304. The DSP 304 receives the timing and control circuit 5 through the control input.
07 advances or delays processing of the signal in response to the despread data before and after the periodicity.

The DSP 304 also supplies phase rotation information to a phase accumulator 511 that supplies phase rotation data to the rotator 504.

The data stored on time is received by the intermediate rate iterative decovering circuit 512. An intermediate rate iterative decovering circuit 512 accumulates data despread by a number of symbols depending on the rate at which the data is being transmitted. In particular, the despread data is stored on RM symbols as described in Table 1, depending on the rate at which the data is transmitted. Further, if the despread data is being transmitted at rate 2, rate 4 and rate 8, the intermediate rate iterative decoupling circuit 512 converts the intermediate rate Walsh code WM as described in Table 1 to Decover the corresponding despread data. The resulting symbol is transferred to a symbol dropper 516.

In one embodiment of the present invention, symbol dropper 516 drops or “gates” a portion of the received recovered symbols. In particular, symbol dropper 516 drops some of the received symbols for higher data rate transmissions and passes all received signals for lower rate transmissions. The amount of symbols dropped by the symbol dropper 516 depends on the data rate of the signal being processed. The portion of the dropped symbol depends on the channel element type CE_TYPE assigned to the channel element 312 where the finger processor 570 is located.

In an exemplary embodiment of the invention, the symbol dropper drops の of the symbols received for rate 4 transmission and ／ of the symbols received for rate 8 transmission. I do. That is, 1/2 of the symbols are passed for rate 4 transmission, and 1/4 of the symbols are passed for rate 8 transmission.

The particular symbol passed and dropped by the symbol dropper 516 is the channel element type CE_ assigned to the corresponding channel element 312.
Determined by TYPE. For example, for a rate 4 transmission, the channel element type CE_TYPE could indicate whether the finger should process even or odd symbols. For rate 8 transmission, the channel element type CE_TYPE could indicate which of a total of four symbols (eg, first, second, third or fourth) should be passed. .

Thus, to process an intermediate rate signal of rate 4 or rate 8, DS
P304 includes a different channel element type CE_ for a set of channel elements 312.
Assign a TYPE, and then assign that set of channel elements to process the same intermediate rate signal. As a result, each channel element 312 processes a different portion of the same signal, and the set of channel elements 312 together process the entire signal. Different parts of the resulting data may be later combined during processing to yield the entire signal.

As will be described in greater detail below, by dropping a portion of the signal before the signal is interleaved, the size of the interleaver for each channel element can be reduced. Deinterleavers typically require a substantial amount of memory, and memory occupies a significant amount of circuit area in an integrated circuit. Thus, the circuit area required to perform the operation of the integrated circuit is reduced.

The despread symbols are transferred to data buffer 514. Data buffer 514 stores 128-bit symbol values for the in-phase and quadrature phases of the signal being processed. The despread symbols are delayed in a data buffer to eliminate time skew between various fingers of the signal being processed in the channel element. The MAC unit receives the deskewed symbols and sums the data from the four fingers that produce the combined despread symbols.

FIG. 8 illustrates a deinterleaver (d) when configured according to one embodiment of the present invention.
FIG. 6 is a block diagram of an interleaver 322 (FIG. 5) and an intermediate rate Walsh code decover 323. The combined despread symbols are received by a deinterleaver RAM 600. In one embodiment of the invention, the deinterleaver RAM is 1536 x 4 bits, which is enough to store 1536 4 bit symbols. The 1536 symbols represent ４ of the symbols received in a 20 ms frame transmitted at rate 8, or の of the symbols received in a 20 ms frame transmitted at rate 4. In addition, 15
The 36 symbols are rate 2 given a medium rate symbol repetition RM.
Or less than the total number of symbols in a 20 ms frame. In another embodiment of the invention, the interleaver uses 1536x to allow double buffering.
8

Under the control of the deinterleaver address control 601, the symbols stored in the deinterleaver are transferred to the XOR gate 60 in a deinterleaved manner.
2 is read. XOR gate 602 is decovered with four lower rate Walsh codes (W1 / 8, W1 / 4, W1 / 2 and WFULL). The decovered resulting symbols are accumulated by accumulator 604 beyond the number of Walsh chips in the corresponding lower rate Walsh code. The recovered symbols, along with additional copies of the deinterleaved symbols, are forwarded to a corresponding Viterbi decoder 316. In another embodiment of the invention, a single XOR gate and accumulator are used in a time division manner. For lower rate transmissions, Viterbi decoder 316 decodes at all four data rates and determines a corrected data rate based on any errors detected during decoding.

Modulation with a low rate Walsh code facilitates determination of the transmitted rate. This is because different rates are modulated with mutually orthogonal codes. Thus, decovering with a low-rate Walsh code does not correspond to the actual transmission rate of the frame to produce a lower energy value compared to the energy level of the corrected decovered symbol.

For intermediate rate transmission, the uncovered symbols are decoded by Viterbi decoder 316 at a corresponding data rate as configured by a microprocessor.

FIG. 9 (2-13) is a block diagram of the iterative decovering and symbol drop circuit 516 when configured according to one embodiment of the present invention. The data being processed is latched by the in-phase input DATA_I and the quadrature-phase input DATA_Q.
0 (multi-bit latch) is received. The output of latch 710 is applied to the B input of adder / subtractor 705, and also forms the output of intermediate rate iterative decovering circuit 512. The A input of adder / subtractor 705 receives the on-time despread chip data from 2 × accumulator 510. Adder / subtractor 705 adds and subtracts inputs A and B based on signals applied to control inputs +/-.

The Walsh code generator 700 generates an intermediate rate Walsh code WM according to the transmission rate of the data being processed. The resulting Walsh code is applied to a control input of adder / subtractor 705 that specifies whether an add operation or a subtract operation is to be performed.

[0068] adder / subtracter 705 and the latch 710 plays the cooperation with the accumulator function, or input on the basis of the logic level of the Walsh code W _M of the intermediate rate is added to the accumulated value, the accumulated Is subtracted from the calculated value. The effect is that the despread data is demodulated with a medium rate Walsh code, and the data thus demodulated is accumulated to the length of the medium rate Walsh code. Accumulator Clear generator 712 resets the value of the latch 710 for each repetition value R _M of the intermediate rate. The intermediate rate decovered symbols thus obtained are sent to the symbol dropper 516. Various methods other than the above are known as a method for adding a Walsh code.

FIG. 10 shows a symbol drop block (symbol d) according to an embodiment of the present invention.
FIG. Decover symbol (DSYMBOL_I &
DSYMBOL_Q) is received by the latch 810 from the intermediate rate repetitive decover circuit 512. A symbol selection permission generator 800 receives the channel element type CE_TYPE, generates a symbol permission signal, and applies it to the permission input of latch 810.

The symbol selection permission generator 800 provides an exemplary circuit and method for generating a symbol permission signal based on the channel element type CE_TYPE. An increasing 2-bit count value at each new symbol (CNT (0: 1)) is applied to one input of comparator 802. An AND gate can be used instead of the comparator. A hardware binary number is input to the other input of the comparator 802 as shown. The output of the comparator 802 is applied to a multiplexer 804 controlled by CE_TYPE. The output of the multiplexer 804 is supplied to one input of an OR gate 805. The other input of OR gate 805 receives a logic high when CE_TYPE = 6 or 7.

In one embodiment of the present invention, the channel element type CE_TYPE may be any value from 0 to 7. Values 0-3 correspond to the type of channel element used for rate 8 transmission. Values 4 and 5 correspond to the type of channel element used for rate 4 transmission. Values 6 and 7 correspond to the type of channel element used for rate 2 and lower transmissions.

As described above, a signal transmitted at a rate of 8 is processed using four types of channel elements. In four CE_TYPEs 0 to 3, the symbol permission signal appears once every four symbol periods. The specific symbol period in which the signal appears is CE_TYPE0-CE_TYPE0.
Every three are different. For example, in CE_TYPE0, a symbol permission signal appears every time the first four symbol periods are reached. In CE_TYPE1, the second 4
A symbol permission signal appears each time a symbol period is reached.

Similarly, in CE_TYPEs 4 and 5, a symbol permission signal appears once every other symbol period, but a specific symbol period appears in CE_TYPE.
Different for each PE. In CE_TYPEs 6 and 7, the symbol permission signal appears in each symbol period.

Thus, when processing a signal transmitted at a high transmission rate, the microprocessor allocates a set of channel elements for processing the signal and assigns a different channel element type CE_TYPE to each channel element. Each channel element processes a different part of the signal accordingly. The sum of the partial signals processed in this way is equal to the whole of the signal.

Since each channel element only needs to process a part of the signal, both channel elements may have low capability and low resources. Therefore, the total circuit area of the integrated circuit required for the configuration of the demodulator can be small. Therefore, efficiency is increased and costs are reduced. In contrast, a system in which every channel element is configured to have the processing capability of high-rate transmission creates wasted resources that are not used during low-rate transmission. Providing channel resources that can be used in concert for the same transmission increases overall usage and efficiency.

Since the total communication capability of many CDMA systems is limited, as the number of high rate communications increases, the number of low rate communications decreases. Therefore, with a demodulation system that can combine the number of low rate demodulation resources with the demodulation of high rate transmission,
The capacity and allocation of demodulation resources can be better adapted to the transmission capacity of the CDMA system. Efficiency is further improved by adapting resources to capacity.

[Brief description of the drawings]

FIG. 1 is a block diagram of a wireless communication system configured according to one embodiment of the present invention.

FIG. 2 shows a block diagram of a reverse link transmission system configured according to one embodiment of the present invention.

FIG. 3A is a diagram illustrating a data frame structure for intermediate rate data transmission used in one embodiment of the present invention.

FIG. 3B illustrates a frame format used in one embodiment of the present invention for another lower rate frame.

FIG. 4 is a block diagram of a base station configured according to one embodiment of the present invention.

FIG. 5 is a block diagram of a demodulation unit of CSM 366 when configured according to one embodiment of the present invention.

FIG. 6 is a block diagram of a channel element 312 when configured according to one embodiment of the present invention.

FIG. 7 is a block diagram of a finger processor 570 when configured according to one embodiment of the present invention.

FIG. 8 illustrates a deinterleaver demodulator 322 when configured according to one embodiment of the present invention.
FIG. 6 is a block diagram of FIG.

FIG. 9 is a block diagram of an iterative decovering and symbol dropping circuit 516 when configured according to one embodiment of the present invention.

FIG. 10 is a block diagram of a symbol drop block when configured according to one embodiment of the present invention.

[Explanation of symbols]

10A, 10B ... subscriber unit 12 ... base station 14 ... base station controller 16 ... public telephone communication network 18 ... mobile switching center 100 ... CRC generator 10
2 ... tail bit generator 104 ... multiplexer 106 ... encoder 108 ...
Repeater 110 puncture circuit 112 interleaver 114 repeater circuit 116 Walsh cover circuit 118 gate circuit 120 circuit 12
2 XOR gate 124 Amplifier 126 Composite multiplier 128 Low-pass filter 130 Mixer 132 Totalizer 134 Amplifier 150, 152
Frame 160 Data field 162 CRC check sum field 164 Tail data field 170 User data 172 CRC data 174 Tail bit data 300 Interpolator 302 Searcher subsystem 304 DSP controller 312 Channel element 31
6 Viterbi decoder 322 Deinterleaver 323 Walsh decover
362 RF unit 364 Control unit 366 Cell site modem 3
68 ... data formatter 500 ... antenna select 502 ... decimator
504 phase rotator 505 despreader 506 PN generator 507
Control circuit 510 accumulator 511 phase accumulator 512 iterative decovering circuit 514 data buffer 516 symbol dropper 570
... finger processor 600 ... deinterleaver RAM 601 ... deinterleaver address control 602 ... XOR gate 604 ... accumulator 700
... Walsh code generator 705 ... Adder / subtractor 710 ... Latch 712 ...
Accumulator clear generator 800 ... symbol selection permission generator 802 ... comparator 80
4: Multiplexer 805: OR gate 810: Latch

──────────────────────────────────────────────────続 き Continuation of front page (81) Designated country EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE ), OA (BF, BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, KE, LS, MW, SD, SL, SZ, TZ, UG, ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, CA, CH, CN, CR, CU, CZ, DE, DK, DM, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID , IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, NO, (72) Invention NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, TZ, UA, UG, UZ, VN, YU, ZA, ZW Vendor, Paul E. United States 92122, California California, Angel Avenue 2879 (72) Inventor Butler, Brian K. United States, California 92037 La Jolla, Glenwick Lane 8736 (72) Inventor Hans Quin, David W. 92122, California, USA Diego Charmant Drive 7510 F-term (reference) 5J065 AC02 AD04 AD10 AG06 AH04 5K 004 AA08 JG01 JH00 5K014 AA01 BA06 BA10 EA01 FA16 HA05 HA10 5K022 EE01 EE32 5K067 CC10 CC24 EE02 EE10 EE16 EE71 HH21 HH23

Claims (27)

[Claims] 1. A demodulator for demodulating a high rate signal and a low rate signal, comprising: a first channel resource for demodulating substantially all of the low rate signal and a first portion of the high rate signal; A demodulator comprising a second channel resource for demodulating a second portion of the rate signal, wherein the first portion and the second portion are substantially different. 2. The demodulator of claim 1, wherein the first channel resource comprises a first symbol dropper for selecting a first portion of the high rate signal. 3. The demodulator according to claim 2, wherein the second channel resource comprises a second symbol dropper for selecting a second portion of the high rate signal. 4. The demodulator according to claim 2, further comprising a first deinterleaver memory sized sufficiently to store the entire frame of the low rate signal and the first portion of the high rate signal. 5. The demodulator of claim 4, further comprising a second deinterleaver memory sized sufficiently to store a second portion of the high rate frame. 6. The demodulator of claim 5, wherein the second deinterleaver memory is of a size sufficient to store all frames of the low rate signal. 7. The demodulator according to claim 1, wherein the first part and the second part have substantially the same format. 8. The first portion includes first user data and first control data in a first order, and the second portion includes second user data and second control data in a second order. 8. The demodulator of claim 7, wherein the demodulator includes a first order and the first order and the second order are substantially the same. 9. The demodulator according to claim 8, wherein the first user data is substantially similar in format to the first part and the second part. 10. A circuit for demodulating a first portion of a low rate signal and a second portion of a high rate signal, and a second circuit for demodulating a third portion of the high rate signal. A demodulator wherein the first part is larger than the second part and the third part, and wherein the second part and the third part are substantially different. 11. The demodulator of claim 10, wherein the first portion is the entire low rate signal and the second portion is a portion of the high rate signal. 12. A method for demodulating a high rate signal and a low rate signal, comprising: (a) demodulating substantially all of the low rate signal; and (b) demodulating a first portion of the high rate signal. And c) demodulating a second portion of the high rate signal, wherein the first portion and the second portion are substantially different. 13. The method of claim 12, wherein step (b) includes dropping a second portion of the high rate signal. 14. The method of claim 13, wherein step (c) includes dropping a first portion of the high rate signal. 15. Storing all frames of the low-rate signal; deinterleaving all frames of the low-rate signal; storing a first portion of the high-rate signal; 14. The method of claim 13, further comprising: deinterleaving a portion of 16. The method of claim 15, further comprising: storing a second portion of the high rate signal; and deinterleaving the second portion of the high rate signal. 17. The method of claim 12, wherein the first and second parts are in substantially the same format. 18. The first part includes first user data and first control data in a first order, and the second part includes second user data and second control data in a second order. 20. The method of claim 17, comprising order, wherein the first order and the second order are substantially the same. 19. The method of claim 18, wherein the first part is in substantially the same format as the first part and the second part. 20. A first reception processing system for processing a low rate signal in a first mode and processing a first portion of a high rate signal in a second mode; A second reception processing system for processing and processing a second portion of the high rate signal in a second mode. 21. The receiving system of claim 20, wherein the first receiving processing system comprises a first symbol dropper for selecting a first portion of the high rate signal. 22. The receiving system of claim 21, wherein the second receiving processing system comprises a second symbol dropper for selecting a second portion of the high rate signal. 23. A first interleaver memory that is smaller in size than a first reception processing system needs to store a first portion of the high rate signal and a second portion of the high rate signal. 22. The receiving system according to claim 21, comprising: 24. A second interleaver memory having a size smaller than that required by the second reception processing system to store the first portion of the high rate signal and the second portion of the high rate signal. 24. The receiving system according to claim 23, comprising: 25. The receiving system of claim 21, wherein the second deinterleaver memory is of a size sufficient to store all frames of the low rate signal. 26. The receiving system according to claim 21, wherein the first part and the second part have substantially the same format. 27. A first part comprising first user data and first control data in a first order, and a second part comprising second user data and second control data in a second order. 22. The method of claim 21, comprising the order, wherein the first order and the second order are substantially the same.