CN1333957A - Processing signals of different data rates - Google Patents
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- CN1333957A CN1333957A CN99815760A CN99815760A CN1333957A CN 1333957 A CN1333957 A CN 1333957A CN 99815760 A CN99815760 A CN 99815760A CN 99815760 A CN99815760 A CN 99815760A CN 1333957 A CN1333957 A CN 1333957A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7097—Interference-related aspects
- H04B1/711—Interference-related aspects the interference being multi-path interference
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
- H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
- H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
- H04B2201/70703—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation using multiple or variable rates
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Abstract
A wireless communications system is described. In one embodiment of the invention, a set of demodulation resources demodulates a set of signals that can transmit data at a set of rates. For signals transmitting at lower data rates, a single demodulation resource demodulates an entire signal. For signals transmitting at higher data rates, two or more demodulation resources each demodulate a portion of the signal. Advantageously, the first portion of the higher rate signal is substantially different than the second portion.
Description
Invention field
The present invention is directed to radio communication.Especially, the present invention is directed to the data that in wireless communication system, send with various speed.
Background technology
Made the mobile digital radio communication be mainly used in the transmission Speech Communication.Along with the appearance of World Wide Web (WWW), Email and computer network, increase for demand based on the radio communication of data exponentially.
General data communication is than the data rate of having relatively high expectations based on the radio communication of speech and the data rate of more kind.The increase of this traffic rate kind has generally increased the size of the circuit of complexity or system, and upward system is to be used to handle and to produce the data that send.Generally, increase complexity or circuit size and just increase cost.
The present invention is directed to and reduce complexity and size, therefore reduced cost with the system of multiple rate processing data.
Summary of the invention
A kind of wireless communication system is described.In one embodiment of the invention, a group demodulation resource is to carrying out demodulation with one group of signal of one group of rate sending data.For the signal that sends at lower data speed place, single demodulation resource is carried out demodulation to whole signal.For the signal that sends at the higher data rate place, each of two or more demodulation resources is carried out demodulation to a part of signal.Advantageously, the first of higher rate signal is different from second portion basically.
The accompanying drawing summary
From below in conjunction with the detailed description of accompanying drawing to embodiments of the invention, will be more clear to characteristic of the present invention, purpose and advantage, in all accompanying drawings, do corresponding identification with identical mark, wherein:
Fig. 1 is the block diagram of the wireless communication system that disposes according to one embodiment of present invention;
Fig. 2 illustrates the block diagram of the rl transmission system of configuration according to one embodiment of present invention;
Fig. 3 A illustrates the data frame structure of the middle speed transfer of data of using in one embodiment of the invention;
Fig. 3 B is illustrated in one of the present invention and is used for the frame format that other uses than the embodiment of low rate frame;
Fig. 4 is the block diagram of the base station that disposes according to one embodiment of present invention;
Fig. 5 is the block diagram of the demodulation part of CSM 366 when disposing according to one embodiment of present invention;
Fig. 6 is the block diagram of element in channel 312 when disposing according to one embodiment of present invention;
Fig. 7 is the block diagram of finger processor 370 when disposing according to one embodiment of present invention; And
Fig. 8 is the block diagram of deinterleaver-demodulator 322 (Fig. 5) when disposing according to one embodiment of present invention;
Fig. 9 repeats to cover the block diagram that abandons circuit 516 with each when disposing according to one embodiment of present invention;
Figure 10 is the block diagram that code element abandons piece when disposing according to one embodiment of present invention.
The preferred mode that carries out an invention
Wireless communication system is described.The ins and outs according to the reverse link of cell phone system are described example embodiment.And use in this scope is favourable, can be combined in different embodiments of the invention in varying environment or the configuration.Generally, can use and be subjected to software-controlled processor.Integrated circuit or discreet logic form various system described herein.The also symbol application of the present invention of enforcement that pattern is more peculiar comprises the use of biological or chemical computing system.
In addition, advantageously represent all in should be with the data of quoting, instruction, order, information, signal, code element and chip by voltage, electric current, electromagnetic wave, magnetic field or particle, light field or particle or their combination.In addition, can represent hardware or method step at the piece shown in each block diagram.
Fig. 1 is the block diagram of the wireless communication system that disposes according to one embodiment of present invention.Use the digital modulation radiofrequency signal that subscriber unit 10a and 10b are docked with base station 14.Reverse link is that signal is sent to base station 14 from subscriber unit 10a and 10b, and forward link is 14 signal to be sent to subscriber unit 10 from the base station.Base station controller (BSC) 16 and mobile switching centre (MSC) 18 provide calls out and data routing function and calling mobile management.
Reverse link and forward link both send various types of data of various data rates.For example, the usage quantity level is that the data rate of per second 10 kilobits (Kbits/sec) carries out the call based on speech.The usage quantity level is that the data rate of 64Kbits/sec carries out data communication, is used for the application such as web page browsing and video conference.Schematically, subscriber unit 10a is shown, and subscriber unit 10b is shown as laptop computer as cell phone.
Fig. 2 illustrates the block diagram of the reverse link transmitting system of configuration according to one embodiment of present invention.As shown in Figure 1, system generally comprises and resembles shown in figure 2 (being depicted as cell phone and computer) a plurality of transmitting systems 10, sends to the base station at any time.In one embodiment of the invention, certain user unit 10 can send to base station 14 according to being different from technology shown in Figure 2.For example, certain user unit 10 can be according to IS one 95 standards, or one of its derivation standard sends, and other subscriber unit 10 can be according to transmission shown in Figure 2.At the United States Patent (USP) the 5th that is entitled as " system and method that in the cdma cellular telephone system, produces signal waveform ", 103, system and method according to the use processing RF signals of IS-95 standard has been described in No. 459 basically, this patent has transferred assignee of the present invention, and is incorporated herein by reference (' 459 patents).
Still with reference to figure 2, during " low data rate mode ", receiving data frames on input A1, but each Frame comprises a kind of in four kinds of energy of data.The difference amount of data calls the group of different pieces of information speed " speed group " corresponding to different data rates.Generally, the lower data rate mode is corresponding to the communication based on speech, and four data speed are measured corresponding to four differences of voice activity.CRC generator 100.1 is added to the CRC check position on some frame according to speed and speed group.In addition, by tail position generator 102.1 the tail position of given value (preferably all logical zeros) are added to each frame.The number of tail position preferably equals k-1, and wherein k is the length of encoder.In one embodiment of the invention, add 8 tail positions.
In one embodiment of the invention, can obtain two different speed groups.The different rates group is corresponding to two varying levels of speech quality, and the speed group with peak data rate is a highest speed group of speech quality.Distinguish different speed groups by the flank speed (or " speed one ") in each group, the described flank speed of first rate group (8K speed group) is 9.6Kbits/sec, and the described flank speed of the second speed group (13K speed group) is 14.4Kbits/sec.According to the comparison of the approximate fraction and the speed one of speed, other three (3) the individual speed in the speed group are called half (1/2) speed, 1/4th (1/4) speed and 1/8th (1/8) speed.This lower data speed is similar in appearance to those data rates that can find in IS-95 and IS-95B aerogram long-range (over-the air) interface standard.
All shown in figure 2 system carry out " in " speed rates (that is, with than the higher speed rates of those data rates that can in low data rate mode, obtain), in the other data of input A2-A8 input.In one embodiment of the invention, the sum of employed input A1-A8 must be 2 integer power.Like this, the middle speed rates that each provided of two speed groups (8K and 13K) is approximately equal to two (2) and takes advantage of speed one speed (speed two), four (4) to take advantage of speed one speed (speed four) and eight (8) to take advantage of speed one speed (speed eight).
This modulation provides other six (6) individual middle transmission rates, may speed and always have 14.Can be divided into two groups to 14 speed: one group is associated with 13K, and another group is associated with 8K.14 speed be together for 8K speed 8, speed 4, speed 2, speed 1, half rate, 1/4 speed and 1/8 speed and for speed 8, speed 4, speed 2, speed 1, half rate, 1/4 speed and 1/8 speed of 13K.In one embodiment of the invention, subscriber unit 10 works in lower data rate mode or middle data rate mode.Yet in another embodiment of the present invention, subscriber unit can work in any available data rate.
During " middle data rate mode ", 104 pairs of data that receive at input A1-A8 of multiplexer are carried out time multiplexing becomes individual traffic, and described individual traffic carries out convolutional encoding at the speed place according to data rate as described below by convolution coder 106.For 8K or 13K set of data rates, 108 pairs of repeaters are in the speed 1 at speed R place or carry out code element than low transmission rate (speed 1 to 1/8 speed being called " than low rate " here) and repeat, and Walsh covers with also being that low rate walsh code WL according to data rate is to modulating than lower rate transmissions.
Perforation (puncture) circuit 110 is bored a hole by the data flow of the perforation FACTOR P pair transfer of data that is associated with the 13K frame.The perforation FACTOR P is 1/3 to mean that per 3 code symbols remove a code symbols from data flow.This has reduced the code rate of carrying out effectively on data, but allows to send more data, thereby has increased data rate.For example, if encoder 106 is carried out the R=1/4 coding, and the perforation FACTOR P is 1/3, then efficient coding speed RE=3/8.
Interleaver 112 execution block on the 20ms of the data that sending piece is staggered, no matter data rate.Data volume of therefore, interlocking at any given time or code symbols number depend on message transmission rate.
Speed repeated during speed repeat factor RM carried out in middle speed repeat circuit 114 bases.In addition, for middle speed transfer of data ( speed 2,4 and 8), middle speed Walsh covers speed walsh code WM modulated symbol in circuit 116 usefulness, and described middle speed walsh code WM is relevant with the higher data rate of using.
In Table I, stipulate the various parameters of system's use of Fig. 2 in one embodiment of the invention.
| R L | R M | Code rate | P | Low rate walsh code W L | Middle speed walsh code W M | |
| / 8th speed 8(1/8) | ?16 | ?8 | ?1/4 | +??+??+??+??+??+??+ +?-?-?-?-?-?-?-?- | ||
| / 4th speed x (1/4) | ?8 | ?8 | ?1/4 | +?+?+?+?-?-?-?- | ||
| Half rate 8(1/2) | ?4 | ?8 | ?1/4 | +?+?-?- | ||
| Speed- 8(1) | ?2 | ?8 | ?1/4 | +?- | ||
| / 8th speed 13(1/8) | ?16 | ?8 | ?1/4 | ?1 ?/ ?3 | +?+?+?+?+?+?+ +?-?-?-?-?-?-?-?- | |
| / 4th speed 13(1/4) | ?8 | ?8 | ?1/4 | ?1 ?/ ?3 | +?+?+?+?-?-?-?- | |
| Half rate 13(1/2) | ?4 | ?8 | ?1/4 | ?1 ?/ ?3 | +?+?-?- | |
| Speed one 13(1) | ?2 | ?8 | ?1/4 | ?1 ?/ ?3 | +?- | |
| Speed two 8 | ?1 | ?4 | ?1/4 | +?+?+?+?-?-?-?- | ||
| Speed four 8 | ?1 | ?2 | ?1/4 | +?+?-?- | ||
| Speed eight 8 | ?1 | ?1 | ?1/4 | +?- | ||
| Speed two 13 | ?1 | ?4 | ?1/4 | ?1 ?/ ?3 | +?+?+?+?-?-?-?- | |
| Speed four 13 | ?1 | ?2 | ?1/4 | ?1 ?/ ?3 | +?+?-?- |
| Speed eight 13 | ?1 | ?1 | ?1/4 | ?1 ?/ ?3 | +- |
Table I
At the walsh code inlet is blank space, does not carry out walsh code modulation.The subscript of each speed (8 or 13) indication specific data rate is to be associated with 8K or to be associated with 13K.Should be clear, regulate repetition rate RL and RM, so that effective code element speed keeps constant.The constant processing simplification that makes at the variable-speed data at transmitting terminal and receiving terminal two places of the chip rate of remaining valid.For low and middle data rate, walsh code modulation further promotes to determine sending the speed at data place.
In one embodiment of the invention, gating circuit 118 is carried out the gating of 1/8th rate frame, so that save power.This gating comprises and only sends last half frame, or the 10ms of frame.In addition, when subscriber unit 10 was in " search pattern ", gating circuit 118 also can gating half rate and 1/4th rate frame.Best, resemble the gating of carrying out these frames the gating of carrying out 1/8th rate frame.That is, the blocking-up frame first half, or 10ms.In gating any image duration, subscriber unit 10 can not searched for other forward link signal at the frequency band place that handles current.This has promoted the execution that hard handoff switches, and described hard handoff switching took place when (with other example) frequency band that switches its operation when subscriber unit.
Repeat from the stream of chips of gating circuit 118 generations by 2 * circuit 120, and use XOR gate 122 by Walsh traffic channels sign indicating number Wc, t covers the output of 2 * circuit 120, uses multiplier or amplifier 124 to regulate gain by traffic channel gain-adjusted Gt then.In addition, with control data pilot data is carried out multiplexedly, repeat by 2 * circuit 120, and use XOR gate 122 usefulness control channel walsh code Wc, c covers.In certain embodiments of the present invention, also can carry out gain-adjusted to pilot channel.
Control data generally is a power control command, and these orders produce according to forward link signal, and whether expression should make channel emission power in the forward link signal that is distributed with terminal communication increase, reduce or keep stable.
The traffic channel data of using complex multiplier 126 to make to be produced and control channel data and homophase PN sign indicating number and quadrature be PN sign indicating number complex multiplication mutually, produces homophase item XI and quadrature item XQ mutually.By 128 pairs of homophase items of low pass filter XI and quadrature mutually an XQ carry out filtering, use frequency mixer 130 respectively with homophase carrier wave and quadrature mutually carrier wave carry out up-conversion, always add by summation instrument, carry out gain-adjusted by amplifier, then transmission.
Fig. 3 A illustrates the data frame structure that is used for the speed transfer of data that uses in one embodiment of the invention.As mentioned above, in one embodiment of the invention, each frame is corresponding to the duration of 20ms.
For speed one frame 150, by data field 160, CRC check field 162 and tail bit data field 164 configuration frames.During encoding, use tail bit data field 164 to remove convolution coder and to help to decode.In order to remove decoder fully, the length of data sequence is littler by 1 than the length K of convolutional encoding.In one embodiment of the invention, code length K is nine (9), and tail bit data field 164 comprises eight (8) individual logical zeros.Best, use CRC check field 162 and tail bit data field 164, other embodiments of the invention may be used different " control " fields.
For speed two frames 152, by data field 160.2 and 160.3, crc field 162.2 and 162.3 and tail bit field 164.2 and 164.3 configuration frames.In one embodiment of the invention, data field 160.2 and 160.3 form and size are corresponding to data field 160.1.Similarly, crc field 162.2 is identical with crc field 162.1 with size with 162.3 form, and tail bit field 164.2 and 164.3 form are with big or small identical with tail bit field 164.1.
For speed four frames 152, by data field 160.4,160.5,160.6 and 160.7, crc field 162.4,162.5,162.6 and 162.7 and tail bit field 164.4,164.5,164.6 and 164.7 configuration frames.In one embodiment of the invention, data field 160.4,160.5,160.6 and 160.7 form and size are corresponding to data field 160.1 (therefore corresponding to data field 160.2 and 160.3).Similarly, crc field 162.4,162.5,162.6 is identical with crc field 162.1 with size with 162.7 form, and tail bit field 164.4,164.5,164.6 is identical with tail bit field 164.1 with size with 164.7 form.
For speed eight frames, by data field 160.8-160.15, crc field 162.8-162.15 and tail bit field 164.8-164.15 configuration frame.In one embodiment of the invention, the form of data field 160.8-160.15 and size are corresponding to data field 160.1 (therefore corresponding to data field 160.2 and 160.7).Similarly, the form of crc field 162.8-162.15 is identical with crc field 162.1 with size, and the form of 164.8-164.15 is identical with tail bit field 164.1 with size.
The form of each field and size and the corresponding identical processing that promotes the different rates frame of field in the different rates frame.Especially, can use the circuit of the frame that is used to produce a kind of speed to produce the frame of higher rate, as long as increase the operating rate of these circuit simply.Permission is used identical circuit to reduce to different frame rates and is carried out necessary transmission and receive the necessary circuit total amount of processing, therefore reduced according to any integrated circuit of some embodiment operation of the present invention or the size and the cost of system.Also have, increased processing speed, because only need less processing path change.
Can increase the operating rate of circuit by many forms, be included in reduce each image duration circuit the time-minute or increase work duration of circuit.Also have, when the field of the different rates frame of one embodiment of the present of invention has identical form and size so that circuit is when re-using maximum, other embodiments of the invention may be only corresponding to some attribute of same or similar field.
For example, the size of respective field can be identical, but form is inequality.Or the form of a part of data of some field can be identical, but the different rates frame may have other data in these fields.In other embodiments, field size can be different with form, but the order that the order of field repeats with respect to other rate frame is identical order.In each case, the size between the field of various rate frame, form or both similitudes have promoted the reception processing and the transmission of data to handle both.
In one embodiment of the invention, according to IS-95 standard process frames of data, data field size reduces when transmission rate reduces basically, and by sending gating the figure place that is sent is reduced.Described in No. the 5th, 504,773, the United States Patent (USP) that is entitled as " method and apparatus that is used to make the transmission data formatting " and be used to make the formative system and method for low rate frame, this patent has transferred assignee of the present invention, and is incorporated herein by reference.
In other frame format of using in one embodiment of the invention shown in Fig. 3 B than low rate frame (such as some frame of in Table I, listing).Each frame comprises user data 170, CRC data 172 and tail bit data 174.As shown in the figure, the figure place of some categorical data changes with speed.In one embodiment of the invention, use speed one frame format of high data rate for every group of user, CRC and tail bit data field.
Fig. 4 is the block diagram of the base station that disposes according to one embodiment of present invention.RF unit 362 receives the RF signal by antenna, and the RF signal that produces the base band sampling is carried out filtering, down-conversion and digitlization.In one embodiment of the invention, use each antenna and RF unit telephone service to be offered the sector of base station range.Generally, there is more than one antenna each sector, the diversity that is used to add.
The on-the-spot modulator-demodulator in sub-district (CSM) 366 that is controlled unit 364 controls receives the base band sampling.Generally, CSM is an integrated circuit.In one embodiment of the invention, control unit 364 generally is the microprocessor that is subjected to being stored in the software instruction control in the memory.CMS366 carries out demodulation to the one group of signal that is included in the base band reception sampling, produces the data that are delivered to data formatter 368.Data formatter 368 is placed on data in the grouping that comprises address information, and packet delivery is arrived base station controller.
In other embodiments of the invention, discrete part or integrated circuit are carried out the modulation and demodulation function that CMS366 carries out.
Fig. 5 is the block diagram of the demodulation part of CMS366 when disposing according to one embodiment of present invention.During the typical operation of the example embodiment of the present invention that here provides, signal processing circuit receives and handles reverse link signal, shown in reverse link signal be to produce by the system that resembles the emission system shown in Figure 2.Best, on single integrated circuit, implement described circuit, can provide controlled function on the same integrated circuit or on the other integrated circuit.Generally the microprocessor that is stored in the software in the memory by operation comes execution control function.Generally, as described here, allocating task between microprocessor and DSP, however an alternative embodiment of the invention is allocating task differently.
In the processing of an example, by the down-conversion base band reception sampling (RX_IQ) of interpolater 300 receptions from the external RF unit of Fig. 4.Interpolater 300 produces the sampling through interpolation that receives by search subsystem 302 and element in channel 312.The search of 302 pairs of reverse link signal execution cycle property of search subsystem, and the result of these search offered dsp controller 304 and external control system (not shown).Peripheral control unit (microprocessor) can be by determining that handle which signal responds, and distribute the element in channel 312 of a processing signals.Generally, offer particular channel element 312 and carry out distribution by the time of pending signal is departed from.In described embodiments of the invention, a plurality of multipath examples that each element in channel can processing signals are referred to as to refer to, and each refers to that the different time of requirement departs from.Therefore, peripheral control unit can provide a plurality of times to depart to element in channel 312.
In one embodiment of the invention, can receive sampling in a speed place in two speed: the octuple (Chip * 8) of the twice (Chip * 2) of expansion spreading rate or expansion spreading rate.When receiving sampling RX_IQ at Chip * 2 places, interpolater 300 is the speed of sample interpolation to octuple spreading rate (Chip * 8).When receiving sampling at Chip * 8 places, bypass interpolater 300.This permission system operates in the system of the difference configuration of the sampling that Chip * 8 or Chip * 2 are provided.
Digital signal processor (DSP) 304.1 is connected with element in channel 312.0-312.5, and DSP304.2 is connected to element in channel 312.6-312.11.Viterbi decoder 316.0 is connected with deinterleaver 322.0-322.3 with 323.2 by middle speed Walsh (WM) decoder 323.0.Viterbi decoder 316.1 is connected with deinterleaver 322.8-322.11 with 323.7 by middle speed walsh-decoded device 323.4.Make element in channel 312 be coupled to deinterleaver 322 by taking advantage of (MAC) 320 that add up.In another embodiment of the present invention, can use the DSP of different numbers, comprise a DSP.
In one embodiment of the invention, element in channel 312 is carried out various functions, comprises that the go expansion and the middle speed Walsh of centering speed rates goes to cover.In addition, element in channel 312 is used for speed rates and carries out code element on the data handled and abandon in a part.Best, abandon specified quantitative and partial data according to the transmission rate of the data of handling with from the control input of corresponding DSP304.
Time durations at an example of demodulator system handles that passes through Fig. 4, DSP304 receives instruction, processing if the speed of signal transmitted is lower than special speed, then distributes an element in channel 312 that is used for processing signals with the input signal that middle data rate or low data rate send; If the data rate of signal transmitted, then distributes two or more element in channel that are used for processing signals greater than special speed.In one embodiment of the invention, if send signal at the low data rate or the middle data rate place of speed one or speed two, then microprocessor distributes an element in channel to come processing signals.
In addition, in one embodiment of the invention, DSP304 or microprocessor are distributed to the element in channel that each appointment is used to handle higher rate signal (being speed four and speed eight in one embodiment of the invention) to element in channel type (CE_TYPE).Determine to be described in greater detail below one of them example by the element in channel type by the specific part of the signal of particular channel processing.
By after element in channel 312 processing signals, MAC320 code element add up on the duration produced go to expand the chip data, best, the time carried out adding up in the mode in one minute to each element in channel.In addition, MAC calculates the vector product of pilot tone traffic channel, and refers to the result is always added at one group that handles by the particular channel element.The symbol data that adds up that is produced is delivered to deinterleaver 322, and its carries out time one fen deinterleave and the demodulation of element in channel.Each 20ms frame of 322 pairs of data that receive of deinterleaver carries out deinterleave, and its different rates is corresponding to different data volumes.For higher data rate, the code element that element in channel 312 is carried out abandons and reduces the data volume of handling by each deinterleaver 322.This has reduced the needed size of deinterleaver 322 memories, has reduced total circuit region of demodulator system basically.
Middle speed Walsh removes to cover execution low rate Walsh and goes to cover, and arrives Viterbi decoder 316 going to cover the soft decision data passes.For middle speed rates, 322 pairs of soft decision data at the specified transmission rate place of Viterbi decoder are decoded.For than lower rate transmissions, Viterbi decoder 316 uses the actual data rate of determining by sum of errors probable value there to decode at all four data speed places.At the United States Patent (USP) the 5th that is entitled as " in communication control processor, being used for definite method and apparatus that sends the data rate of variable-speed data ", 566, described a kind of method that speed is determined of carrying out in No. 206, this patent has transferred assignee of the present invention, and is incorporated herein by reference.Can be used for other processing to dateout then, this comprises the base station controller 14 that is delivered to Fig. 1 in one embodiment of the invention.
In described embodiment, should understand, element in channel 312, deinterleaver 322, middle speed Walsh go to cover device 323 and the time one fen MAC320 form channel resource.Described in all application, can use channel resource to handle in some speed and separately than low-rate signal, or with other channel resource combination to handle rate signal in other (rate signal in the flank speed).
Fig. 6 is the block diagram of the element in channel 312 when disposing according to one embodiment of present invention.Receive the RX_IQ sampling by four finger processors 570.Depart from the time that provides from control system (not shown connection from control system), each finger processor processes is distributed to an example of the signal specific of associated channel element.Produce from finger processor 570 be delivered to the MAC320 of Fig. 5 through demodulation code element.
Fig. 7 is the block diagram of the finger processor 400 when disposing according to one embodiment of present invention.The one group of Rx sampling of reception sampling group selection of it line options 500 from being provided.According to above-mentioned base station, 6 groups of Rx samplings are provided, it is corresponding to two antennas of each sector.Determine selected antennas by searcher 306, described searcher 306 is searched for each input group of the Rx sampling of multi-path signal with controller, and described controller produces the selection signal that offers day line options 500.
Selected Rx sampling is delivered to withdrawal device 502, and it extracts the Rx sampling and makes it to drop to chip x 2.Phase rotation device 504 is carried out the initial phase of Rx sampling and is regulated, and despreader 505 uses and from pseudo noise (PN) extended code of PN generator 506 signal carried out demodulation.Timing and control unit 508 determine that the generation and the special time of special code PN generators 506 depart from, and then, according to the Search Results that DSP unit 304.2 receives from searcher 306, it is subjected to the control of DSP unit 304.1.
Despreader one removes to cover device 505, and (going C) expanded 3 output groups of the signal that generation handling for WC, T and WC by using PNI and PNQ sign indicating number and control and traffic channel walsh code.Each output group comprises in-phase component and quadrature phase component.3 output groups corresponding to going expansion, going expansion and hysteresis to go expansion ahead of time on time.Go to expand is the best estimate that departs from time of signal on time, in one embodiment of the invention, going ahead of time to expand is the duration of departing from _ expanding chip before on time going to expand, and to go to expand be the duration of departing from _ expanding chip after on time going to expand and lag behind.
510 pairs in 2 * accumulator is subjected to growth data at two expansion chips and adds up, and the speed during data offer on time through adding up is repeated to cover circuit 512.Through add up ahead of time and hysteresis go growth data to be directly delivered to DSP304.According to be input to by control timing and control circuits 507 ahead of time and hysteresis remove growth data, DSP304 pushes away Signal Processing preceding or postpones.
DSP304 also offers phase accumulator 511 to the phase place rotation information, and it offers circulator 504 to the phase place spin data.
In speed repeat to cover the approximate end of circuit 512 through data accumulated on time.In speed repeat to cover circuit 512 on the code element number relevant with the speed of the data that sending to going growth data to add up.Especially, according to the speed of transmission data, in Table I on the RM code element of defined to going growth data to add up.In addition, remove growth data if sending with speed two, speed four or speed eight, then middle speed repeats to cover circuit 512 usefulness and goes to cover to removing growth data as the corresponding middle speed walsh code WM that stipulates in Table I.Going of being produced covered code element be delivered to code element Dropper 516.
In one embodiment of the invention, the part that code element Dropper 516 abandons or " gating " receives goes to cover code element.Especially, code element Dropper 516 abandons a part of code element that receives that is used for the higher data rate transmission, and transmits all code elements that receive that are used for than lower rate transmissions.The code element amount that code element Dropper 516 abandons is relevant with the data rate of the signal of handling.The code element that abandons of part is relevant with element in channel Type C E_TYPE, and described element in channel Type C E_TYPE distributes to the element in channel 312 that is placed with finger processor 570.
In example embodiment of the present invention, for speed four transmission, the code element Dropper abandons half (1/2) of the code element that receives, and for speed eight transmission, and the code element Dropper abandons 3/4ths (3/4) of the code element that receives.That is,, transmit the code element of half (1/2), and, transmit 1/4th (1/4) code element for speed eight transmission for speed four transmission.
Determine transmission of code element Dropper and the specific code element that abandons by the element in channel Type C E_TYPE that distributes to corresponding element in channel 312.For example, for speed four transmission, whether element in channel Type C E_YTPE can should handle even number or odd symbol to indication.For speed eight transmission, element in channel Type C E_TYPE can indicate, and should transmit which (that is the, the first, second, third or the 4) in per four code elements.
Therefore, for rate signal in processing speed four or the speed eight, DSP304 distributes to one group of element in channel to different element in channel Type C E_TYPE to handle identical middle rate signal.The result is the different piece that each element in channel 312 is handled same signals, and one group of element in channel 312 signal of processes complete together.The different piece of the data that produced can produce afterwards in the processing of complete signal and make up.
As described in more detail below, by before signal is carried out deinterleave, abandoning a part of signal, can reduce the size of the deinterleaver of each element in channel.Deinterleaver generally needs the base quantity of memory, and memory will account for circuit area amount bigger on the integrated circuit.Therefore, reduced enforcement integrated circuit circuitry needed area.
Be delivered to data buffer 514 going to expand code element.The homophase of the data that data buffer 514 storage is being handled and quadrature be partly 128 eight (8) bit symbols values mutually.In data buffer 514, make and expand symbol delay, with the time skew between the various fingers of eliminating the signal of in element in channel, handling.MAC unit 402 receives and goes the skew code element, and the data from 4 fingers are always added, and produces to go to expand code element through combination.
Fig. 8 is the block diagram that deinterleaver 322 (Fig. 5) when disposing according to one embodiment of present invention and middle speed walsh code remove to cover device 323.Deinterleaver RAM 600 receives and goes to expand code element through combination.In one embodiment of the invention, deinterleaver RAM is 1536 * 4, and it enough stores 1536 4 bit symbols.1536 code element tables are shown in 1/4th of the code element that receives in the 20ms frame that speed eight places send, or half of the code element that receives in the 20ms frame that speed sends everywhere.In addition, 1536 code elements are represented the code element sum in speed two or the following 20ms frame, if middle speed code element repeats RM.In another embodiment of the present invention, interleaver is 1536 * 8, to allow double buffering.
Under the control of deinterleaver address control 601, the code element that is stored in the deinterleaver reads into XOR gate 602 with the form of deinterleave.4 of XOR gate 602 usefulness go to cover to code element than low rate walsh code (W1/8, W1/4, W1/2 and W are complete).On the Walsh chip number of accumulator 604 in corresponding low rate walsh code going of being produced being covered code element adds up.Be delivered to corresponding Viterbi decoder 316 removing to cover the other duplicate of code element with the deinterleave code element.In another embodiment of the present invention, with the time-minute form use single XOR gate and accumulator.For than lower rate transmissions, Viterbi decoder 316 is decoded at all 4 data speed places, and determines correct data rate according to detected any mistake during decoding.
Promote to the determining of institute's transmission rate, because modulate different speed with the modulation of low rate walsh code with orthogonal sign indicating number.Therefore, go to cover the actual transmission rate that is not equivalent to frame with the low rate walsh code, comparing with the energy level that correctly goes to cover code element to produce a low energy value.
For middle speed rates, Viterbi decoder 316 is not decoded to covering code element at the corresponding data rate place of microprocessor configuration.
Fig. 9 (2-13) is that repeating when disposing according to one embodiment of present invention covers the block diagram that abandons circuit 516 with code element.DATA_I imports the data that reception is being handled in latch 710 (multibit latch) on the DATA_Q mutually with quadrature in the homophase input.The B that the output of latch 710 is applied to adder/subtracter 705 imports, and the output that speed repeats to cover circuit 512 in forming.The A of adder/subtracter 705 input receives goes to expand the chip data from 2 * accumulator 510 on time.According to the control that applied input+/-signal, adder/subtracter 705 pairs of inputs A and input B add deduct.
Walsh code generator 700 is according to speed walsh code WM in the transmission rate generation of the data of handling.The control that the walsh code that is produced is applied to adder/subtracter 705 is imported, to specify whether should carry out the operation that adds deduct.
Adder/subtracter 705 and latch 710 are together as accumulator, and it is imported the logic level of speed walsh code WM in the basis and the value addition through adding up or subtracts each other.Its effect is to carry out demodulation by middle speed walsh code to removing growth data, and the demodulating data that is produced is added up on the length of middle speed walsh code.Accumulator is removed generator 712 resets the value of latch 710 during speed repetition values RM in each.The middle speed that is produced is gone to cover code element be delivered to code element Dropper 516.Should understand and be used to carry out the various other method that applies walsh code.
Figure 10 is the block diagram that the code element when disposing according to one embodiment of present invention abandons piece.Latch 810 receives from what middle speed repeated to cover circuit 512 and goes to cover code element (DSYMBOL_I and DSYMBOL_Q).Code element is selected to enable generator 800 receive channel component type CE_TYPE and is produced the code element enable signal that enables to import that is applied to latch 810.
Code element is selected to enable generator 800 exemplary circuit and method is provided, and is used for producing the code element enable signal according to element in channel Type C E_TYPE.Two bit counter value that increase with each new code element are applied to an input of comparator 802.Also can use with door and replace comparator.Another input of comparator 802 receives the binary number that hard lead connects, as shown in the figure.The output of comparator 802 is applied to the multiplexer 804 that is subjected to CE_TYPE control.Or the output of an input reception multiplexer 804 of door 805, and when CE_TYPE=6 or 7, or another input receive logic high level of door 805.
In one embodiment of the invention, element in channel Type C E_TYPE can be any value of from 0 to 7.The value 0-3 element in channel type that eight transmission are used corresponding to speed.The value 4 and 5 element in channel type that four transmission are used corresponding to speed.The element in channel type that value 6 and 7 is used corresponding to speed two or following transmission.
As mentioned above, use 4 element in channel to handle the signal that sends at speed eight places.For the CE_TYPE of 4 0-3, per 4 symbol times require a code element enable signal, and for each CE_TYPE 0-3, the distinct symbols time at requirement signal place is different.For example, for CE_TYPE0, during first symbol time of per 4 symbol times, require the code element enable signal.For CE_TYPE1, during second symbol time of per 4 symbol times, require the code element enable signal.
Similarly, for two CE_TYPE4 and 5, require a code element enable signal every a symbol time, wherein, the distinct symbols time is different for each CE_TYPE.For CE_TYPE6 and 7, each symbol time requires the code element enable signal.
Therefore, in order to handle the signal that sends at the higher transmission rates place, microprocessor distributes one group of element in channel so that signal is handled, and then different element in channel Type C E_TYPE is distributed to each element in channel.Each element in channel responds by the different piece of processing signals, and the summation of all parts of the signal of handling equals complete signal.
Each element in channel is the part of processing signals only, has reduced the ability of each element in channel and the resource of each element in channel.This has just reduced the circuit gross area of the integrated circuit that is used to implement demodulator, has therefore increased efficient and has reduced cost.Under the contrast, each channel resource is configured to have the system that handles the high rate data transmission ability then during than lower rate transmissions, resource will not be utilized.By the channel resource that can operate together is provided, full use and efficient have been improved on identical traffic.
Also have,, when the number of higher rate communication is carried out in increase, carry out just having reduced than the number of low rate communication because in many cdma systems, total communication capacity is limited.Therefore, by having a kind of demodulating system, in this system, can make up many than the low rate demodulation resource so that demodulation is carried out in higher rate transmission, make the capacity of demodulation resource and distribute the transmittability that closer cooperates cdma system.Coordination resource with ability has further increased efficient.
Claims (26)
1. one kind is used for higher rate signal and the demodulator that carries out demodulation than low-rate signal are comprised:
First channel resource is used for all described firsts than low-rate signal and described higher rate signal are basically carried out demodulation;
The second channel resource is used for the second portion of described higher rate signal is carried out demodulation, and wherein, described first is different with described second portion basically.
2. demodulator as claimed in claim 1 is characterized in that, described first channel resource comprises the first code element Dropper, is used to select the described first of described higher rate signal.
3. demodulator as claimed in claim 2 is characterized in that, described second channel resource comprises the second code element Dropper, is used to select the described second portion of described higher rate signal.
4. demodulator as claimed in claim 2 is characterized in that, further comprises the first deinterleaver memory, and the size that it has is enough to store described full frame than low-rate signal, and the described first of described higher rate signal.
5. demodulator as claimed in claim 4 is characterized in that, further comprises the second deinterleaver memory, and the size that it has is enough to store the described second portion of described higher rate frame.
6. demodulator as claimed in claim 5 is characterized in that, described second deinterleaver also has the size that is enough to store described full frame than low-rate signal.
7. demodulator as claimed in claim 1 is characterized in that, described first and described second portion have substantially the same form.
8. demodulator as claimed in claim 7, it is characterized in that, described first comprises by first user data of first order and first control data, and described second portion comprises second user data and second control data by second order, wherein, described first order and described second order are substantially the same.
9. demodulator as claimed in claim 8 is characterized in that, the form that described first user data has is basically similar in appearance to described first and described second portion.
10. demodulator comprises:
First circuit is used for carrying out demodulation than the first of low-rate signal and the second portion of higher rate signal; And
Second circuit is used for the third part of described higher rate signal is carried out demodulation, and wherein, described first is greater than described second portion and described third part; And
Described second portion is different basically with described third part.
11. demodulator as claimed in claim 10 is characterized in that, described first is described whole than low-rate signal, and described second portion is the part of described higher rate signal.
12. one kind is used for the higher rate signal and the method for carrying out demodulation than low-rate signal are comprised the following steps:
A) all carry out demodulation to described basically than low-rate signal;
B) first to described higher rate signal carries out demodulation;
C) second portion to described higher rate signal carries out demodulation, and wherein, described first is different with described second portion basically.
13. method as claimed in claim 12 is characterized in that, step b) comprises the step of the described second portion that abandons described higher rate signal.
14. method as claimed in claim 13 is characterized in that, step c) comprises the step of the described first that abandons described higher rate signal.
15. method as claimed in claim 13 is characterized in that, further comprises the following steps:
Store described full frame than low-rate signal;
Described full frame than low-rate signal is carried out deinterleave;
Store the first of described higher rate signal; And
Described first to described higher rate signal carries out deinterleave.
16. method as claimed in claim 15 is characterized in that, further comprises the following steps:
Store the described second portion of described higher rate signal; And
Described second portion to described higher rate signal carries out deinterleave.
17. method as claimed in claim 12 is characterized in that, described first and described second portion have substantially the same data format.
18. method as claimed in claim 17, it is characterized in that, described first comprises by first user data of first order and first control data, and described second portion comprises second user data and second control data by second order, wherein, described first order and described second order are substantially the same.
19. method as claimed in claim 18 is characterized in that, the form that described first has is basically similar in appearance to described first and described second portion.
20. a receiving processing system comprises:
First receiving processing system is used for handling in first pattern one than low-rate signal, and is used for handling the first at the higher rate signal of second pattern;
Second receiving processing system is used for handling in described first pattern one than low-rate signal, and is used for handling the second portion at the described higher rate signal of second pattern.
21. receiving system as claimed in claim 20 is characterized in that, described first receiving processing system comprises the first code element Dropper, is used to select the described first of described higher rate signal.
22. receiving system as claimed in claim 21 is characterized in that, described second receiving processing system comprises the second code element Dropper, is used to select the described second portion of described higher rate signal.
23. receiving system as claimed in claim 21, it is characterized in that, described first receiving processing system comprises: the first deinterleaver memory, its size is less than the described first of the described higher rate signal of storage and the needed size of described second portion of described higher rate signal.
24. receiving system as claimed in claim 23, it is characterized in that, described second receiving processing system comprises: the second deinterleaver memory, its size is less than the described first of the described higher rate signal of storage and the needed size of described second portion of described higher rate signal.
25. receiving system as claimed in claim 21 is characterized in that, the size that the described second deinterleaver memory has is enough to store described full frame than low-rate signal.
26. receiving system as claimed in claim 21 is characterized in that, described first and described second portion have substantially the same form.
27. receiving system as claimed in claim 21, it is characterized in that, described first comprises by first user data of first order and first control data, and described second portion comprises second user data and second control data by second order, wherein, described first order and described second order are substantially the same.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US19808098A | 1998-11-23 | 1998-11-23 | |
| US09/198,080 | 1998-11-23 |
Publications (1)
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|---|---|
| CN1333957A true CN1333957A (en) | 2002-01-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN99815760A Pending CN1333957A (en) | 1998-11-23 | 1999-11-18 | Processing signals of different data rates |
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| EP (1) | EP1133835A1 (en) |
| JP (1) | JP2002530996A (en) |
| KR (1) | KR20010080528A (en) |
| CN (1) | CN1333957A (en) |
| AU (1) | AU3102200A (en) |
| CA (1) | CA2351317A1 (en) |
| HK (1) | HK1042172A1 (en) |
| IL (1) | IL143147A0 (en) |
| NO (1) | NO20012501L (en) |
| WO (1) | WO2000031889A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7082174B1 (en) * | 2000-07-24 | 2006-07-25 | Qualcomm, Incorporated | Method and apparatus for processing a modulated signal using an equalizer and a rake receiver |
| JP3730842B2 (en) * | 2000-08-02 | 2006-01-05 | 日本電気株式会社 | CDMA receiver and method thereof |
| US7590164B2 (en) | 2001-01-19 | 2009-09-15 | Qualcomm Incorporated | Method and apparatus for efficient use of communication resources in a communication system |
| KR100786400B1 (en) * | 2005-12-09 | 2007-12-17 | 주식회사 팬택 | Receiving apparatus for Digital Multimedia Broadcasting shorten channel changing time |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3385299B2 (en) * | 1996-05-20 | 2003-03-10 | 三菱電機株式会社 | Spread spectrum communication equipment |
| US6064663A (en) * | 1996-09-10 | 2000-05-16 | Nokia Mobile Phones Limited | Cellular CDMA data link utilizing multiplexed channels for data rate increase |
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1999
- 1999-11-18 EP EP99965015A patent/EP1133835A1/en not_active Withdrawn
- 1999-11-18 IL IL14314799A patent/IL143147A0/en unknown
- 1999-11-18 CN CN99815760A patent/CN1333957A/en active Pending
- 1999-11-18 JP JP2000584611A patent/JP2002530996A/en active Pending
- 1999-11-18 CA CA002351317A patent/CA2351317A1/en not_active Abandoned
- 1999-11-18 KR KR1020017006432A patent/KR20010080528A/en not_active Application Discontinuation
- 1999-11-18 AU AU31022/00A patent/AU3102200A/en not_active Abandoned
- 1999-11-18 WO PCT/US1999/027593 patent/WO2000031889A1/en not_active Application Discontinuation
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2001
- 2001-05-22 NO NO20012501A patent/NO20012501L/en not_active Application Discontinuation
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2002
- 2002-04-02 HK HK02102439.3A patent/HK1042172A1/en unknown
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| CA2351317A1 (en) | 2000-06-02 |
| KR20010080528A (en) | 2001-08-22 |
| IL143147A0 (en) | 2002-04-21 |
| HK1042172A1 (en) | 2002-08-02 |
| JP2002530996A (en) | 2002-09-17 |
| EP1133835A1 (en) | 2001-09-19 |
| AU3102200A (en) | 2000-06-13 |
| NO20012501D0 (en) | 2001-05-22 |
| WO2000031889A1 (en) | 2000-06-02 |
| NO20012501L (en) | 2001-07-23 |
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