JP4593529B2 - DIGITAL DEMODULATION DEVICE, ITS CONTROL METHOD, DIGITAL DEMODULATION DEVICE PROGRAM, RECORDING MEDIUM CONTAINING THE PROGRAM, AND DIGITAL RECEPTION DEVICE - Google Patents

Description

  The present invention relates to a digital demodulator, a control method thereof, a program for a digital demodulator, a recording medium recording the program, and a digital receiver.

  In a digital demodulator that demodulates a received signal, an error may occur in the received signal, for example, by controlling a part of a group of circuit parts constituting the tuner. In order to suppress such an error from affecting the effective portion of the received signal, it is conceivable to perform control during a guard interval period that is not an effective portion of the received signal as in Patent Document 1.

JP 2001-251275 A

  However, according to Patent Document 1, the control of the circuit component group can be performed only during the guard interval period. On the other hand, when the control is performed outside the guard interval period, if the error that is included in the effective portion of the received signal exceeds the correctable range by the control, the information acquired from the received signal is incorrect. Become. Even if the control of the circuit component group is performed so that it falls within the guard interval period, the influence of the received signal by the control may exceed the guard interval and reach the effective portion. Therefore, in order to obtain accurate information from the demodulated received signal, control is performed so that an error included in the received signal is within a correctable range regardless of whether it is during the guard interval. There must be.

  An object of the present invention is to provide a digital demodulator that performs control so that an error that occurs in a received signal due to control of a circuit component group is within a correctable range, a control method thereof, a program for the digital demodulator, and a program thereof Is to provide a recording medium on which is recorded.

Means for Solving the Problems and Effects of the Invention

  A digital demodulator according to the present invention includes a plurality of circuit component groups, a reception unit that receives a reception signal including a plurality of blocks, and a circuit control unit that controls at least one of the plurality of circuit component groups. And the circuit control means controls the circuit component group so that errors received in the respective ranges of the plurality of blocks in the received signal from the receiving means are distributed within the range of the blocks. The first error correction means for correcting the error while the circuit control means controls the circuit component group, and whether the first error correction means can correct an error included in the block range or not. First correctability determination means for determining whether or not the first error correction means cannot correct an error included in the block range. Main control means for causing the circuit control means to start controlling the circuit component group at a timing subsequent to the leading edge of the next block connected to the trailing edge of the block that is determined to be uncorrectable when the possibility determining means determines I have.

  According to another aspect of the present invention, there is provided a control method for a digital demodulator comprising: a plurality of circuit component groups; a receiving unit that receives a reception signal in which a plurality of blocks are connected; and at least one of the plurality of circuit component groups. Circuit control means for controlling, and errors that are included in the respective ranges of the plurality of blocks in the received signal from the receiving means by the circuit control means controlling the circuit component group. A method of controlling a digital demodulator having error correction means for correcting while dispersing within a range, wherein the circuit control means is included in the block range by controlling the circuit component group A correction propriety determination step for determining whether or not the error correction means can correct the error, and an error included in the block range When it is determined in the correctability determination step that the error correction means cannot be corrected, the circuit control means is connected to the circuit control means at a timing after the leading edge of the next block connected to the trailing edge of the block determined to be uncorrectable. And a main control step for starting control of the component group.

  The program for a digital demodulator according to the present invention controls at least one of a plurality of circuit component groups, a receiving means for receiving a reception signal in which a plurality of blocks are connected, and the plurality of circuit component groups. Circuit control means for controlling the circuit component group, and errors received in the respective ranges of the plurality of blocks in the received signal from the receiving means by the circuit control means controlling the circuit component group. A program for a digital demodulator comprising error correction means for correcting while being dispersed within the block, and the circuit control means is included in the block range by controlling the circuit component group. Correction error determination means for determining whether or not the error correction means can correct the error, and included in the range of the block When the correction correctability determining means determines that the error correction means cannot correct the error, the circuit control means is notified to the circuit control means at a timing after the leading edge of the next block connected to the trailing edge of the block determined to be uncorrectable. The digital demodulator is made to function as main control means for starting control of the circuit component group.

  According to the digital demodulating device, the digital demodulating device control method, or the digital demodulating device program of the present invention, if the error included in the received signal by the control is not correctable, the block determined to be uncorrectable Control is performed after the next block. Therefore, control is performed so that errors that occur in the received signal due to control fall within a correctable range, and accurate information is acquired from the received signal.

  Further, in the present invention, when the first correction correctability determining means determines that the first error correcting means can correct an error that will be included in the range of the block, the main control means It is preferable that the circuit control unit starts to control the circuit component group at a timing within the range of the block. According to this configuration, when it is determined that correction is possible, control is performed within the range of the block, so that it is necessary to suppress errors that occur in the received signal by control within a correctable range. Control can be ensured.

  Further, in the present invention, the main control unit assigns the circuit component group to the circuit control unit so that the period during which the circuit control unit controls the circuit component group straddles the boundary between two adjacent blocks. It may be controlled. According to this configuration, an error to be included in a signal by one control is divided into two blocks, and further corrected while being distributed within the range of each block. Therefore, compared with the case where control is performed so as to be within the range of one block, an error generated in the signal is easily corrected by the control.

  Also, in the present invention, the data included in the block range is distributed so that the first error correction means averagely distributes the error included in the block range within the block range. It is preferable to include a rearranging unit for rearranging within the range of the block, and a post-sorting correcting unit for correcting an error included in the block range rearranged by the rearranging unit. According to this configuration, since the error is corrected after the error is averagely distributed within the block range, the error is corrected after the error is reliably distributed.

  In the present invention, the first correction correction determining unit determines that the first error correction unit cannot correct an error included in the range of the block, and then at the rear end of the block. The first error correction means can correct an error that is included in the range of the block in the received signal from the reception means by the circuit control means controlling the circuit component group until the first error correction means. Second correction propriety determining means for re-determining whether or not the error is included in the range of the block. If the first error correcting means can correct the second correction propriety If the determination means determines that the error that will be included in the block range can be corrected by the first error correction means, the second correction possibility determination means determines that the block is It is preferable that the main control unit at any timing up to the rear end of the click begins to control the circuit part group to the circuit control means. According to this configuration, once it is determined that correction is not possible, it is determined whether correction is possible again. Therefore, in the second determination after the first determination, a more accurate determination can be made in consideration of more information necessary for determining whether or not correction is possible than in the first determination. If it is determined that correction is possible in the second determination, necessary control is ensured.

  In the present invention, a part of the block is a correction block including error correction data for correcting an error included in the received signal, and the first error correction means is included in the correction block. An error included in the received signal may be corrected based on the error correction data. According to this configuration, the error included in the received signal can be reliably corrected based on the error correction data included in the correction block.

  Moreover, in this invention, when the said block contains the said correction block, it is preferable to have the following structures. That is, the block is composed of a sequence of a plurality of sub-blocks, and is included in each of a plurality of sub-block groups including two or more sub-blocks that are temporally separated from each other among the plurality of sub-blocks included in the block. Each of the data for correcting an error of the data to be corrected is included in the error correction data of the correction block in the block, and when the sub block group includes an error, Preferably, the first error correction unit corrects an error included in the sub-block group based on data corresponding to the sub-block group. According to this configuration, error correction is performed by collecting data included in sub-blocks separated in time, so even if errors occur in the received signal due to time concentration, the influence of the error is dispersed. Error correction is done above. Therefore, it is easier to correct an error when correcting the same error than when error correction is performed on a group of continuous sub-blocks without being separated in time.

  In the present invention, it is preferable that the rear end of the block coincides with the rear end of the correction block in the block. According to this configuration, the position of the correction block in the block is determined, and control using the position of the correction block is easy to be performed.

  In the present invention, the error existence determination means for determining whether or not the block contains an error in the received signal immediately before the first error correction means corrects the error using the error correction data. And when the error existence determination means determines that the block does not contain an error in the received signal immediately before correcting the error, the circuit control is within the range of the correction block in the block. It is preferable that the main control unit causes the circuit control unit to control the circuit component group so that a period during which the unit controls the circuit component group falls. According to this configuration, when it is not necessary to use a correction block, control is performed so that it is within the range of the correction block. For this reason, the area other than the correction block in the block is not affected by the error due to the control.

  In the present invention, the check data for checking whether or not the block includes an error in the received signal immediately before the first error correction means corrects the error using the error correction data. Is included in the received signal, and the error existence determining means determines whether the block contains an error in the received signal immediately before the first error correcting means corrects the error using the error correction data. It is preferable to determine whether or not based on the check data. According to this configuration, it can be reliably determined whether an error is included based on the check data.

  In the present invention, the first error correction means may further include a second error correction means for correcting an error included in the received signal before the error correction data is used to correct the error of the received signal. It is preferable to provide. According to this configuration, an error can be corrected more reliably than in the case where error correction is performed only by the first error correction means.

  Further, in the present invention, the error existence determination unit is configured to correct the error after the second error correction unit corrects the error based on the determination result of whether or not the second error correction unit can correct the error. It may be determined whether an error is included in the received signal. According to this configuration, when the amount of error corrected by the second error correction unit is below the limit of the amount that can be corrected by the second error correction unit, substantially all errors are corrected. To be judged. Further, when the amount of error corrected by the second error correction means reaches the limit of the amount that can be corrected by the second error correction means, all errors are not corrected and errors remain. It is judged. Thus, it can be easily determined whether or not an error is included in the received signal before correction by the first error correction means.

  Further, in the present invention, an error that is included in a range other than the correction block in the block by the circuit control unit controlling the circuit component group is the first and second error correction units. And a third correctability determination unit that determines whether or not the error can be corrected by both, wherein an error that is included in a range other than the correction block in the block is the first and second errors. When the third correction possibility determination unit determines that correction can be performed by both of the correction units, the main control unit sends the circuit component group to the circuit control unit within the range other than the correction block in the block. It is preferable to start to control. According to this configuration, when it is determined that error correction is possible by both error correction means, the error can be corrected even if control is performed in a range other than the correction block. Therefore, the control is appropriately secured while taking into consideration the influence of errors that are included in the received signal by the control.

  Further, in the present invention, the received signal is divided into a plurality of channel regions including at least one channel region in which the plurality of blocks are connected, and each of the plurality of channel regions is temporally related to each other in the received signal. The circuit control means controls the circuit component group in time before a rear end of a received signal occupying the sub-channel area in the channel area where the plurality of blocks are connected to each other. Preferably, the main control means causes the circuit control means to control the circuit component group so as to end. According to this configuration, the effect of controlling the circuit component group can be obtained more quickly than when the control is finished after the rear end of the sub-channel region.

  In the present invention, the receiving unit includes a tuner including a plurality of circuit component groups that perform channel selection processing on a received signal, and the plurality of circuit component groups that perform demodulation processing on the received signal from the tuner. It is preferable to further comprise a demodulator consisting of According to this configuration, when controlling the circuit component group included in the tuner or the demodulator, an apparatus configuration that performs control so that an error included in the received signal is within a correctable range is realized.

  In the present invention, it is preferable that the main control unit controls the circuit control unit to control the circuit component group constituting the tuner or the demodulator so that power consumption of the tuner or the demodulator is reduced. . According to this configuration, it is possible to realize a device configuration that performs control such that errors included in the received signal fall within a correctable range while reducing the power consumption of the tuner and the demodulator.

  Further, in the present invention, the tuner includes an RF amplifier, a mixer, a filter, an IF amplifier, and a VCO / PLL composed of the circuit component group, and the main control means controls the circuit control means. The component group is preferably the circuit component group constituting at least one of an RF amplifier, a mixer, a filter, an IF amplifier, and a VCO / PLL. According to this configuration, detailed control of each circuit component group included in the tuner is possible.

  The digital demodulator of the present invention can be employed in various digital receivers such as mobile phones and digital TVs that perform at least one reproduction process of data such as characters, images, programs, and sounds. Such a digital receiving apparatus acquires information on data such as characters, images, programs, voices, etc. from the received signal whose error has been corrected by the digital demodulating apparatus of the present invention, and performs reproduction processing of these characters. By adopting the digital demodulator of the present invention in the digital receiver as described above, errors included in the received signal due to control of the circuit component group are not concentrated in time. For this reason, compared with a digital receiver that does not perform control, such as the digital demodulator of the present invention, desired information related to characters and the like is easily obtained from the received signal.

  The program for a digital demodulator according to the present invention is a removable recording medium such as a CD-ROM (Compact Disc Read Only Memory) disk, a flexible disk (FD), or an MO (Magneto Optical) disk, or a fixed recording such as a hard disk. In addition to being able to be recorded on a recording medium such as a medium and distributed, it can be distributed via a communication network such as the Internet by wired or wireless telecommunication means. In addition, this program does not have to be dedicated to the digital demodulator, and is a program that causes a general-purpose processor to function as a digital demodulator by being used in combination with other programs related to channel selection processing and digital demodulation processing. It may be.

  Further, in this specification, “circuit parts” are circuit parts constituting at least a part of the digital demodulator, and “circuit parts group” is a set of a plurality of circuit parts. Specifically, for example, a circuit configuring each unit included in the tuner 110 illustrated in FIG. 3, a circuit configuring each unit included in the demodulator 120 illustrated in FIG. 4, and these circuits are configured. All units of components such as components equivalent to one transistor can correspond to circuit components. For example, if the circuit component is a single circuit equivalent to a transistor constituting the RF amplifier, the RF amplifier is composed of a circuit component group in which a plurality of these circuit components are collected.

  The following is a description of a digital processing apparatus which is an example of a preferred embodiment of the present invention. FIG. 1 is a diagram illustrating a configuration of the digital processing device 180.

<Digital processing equipment>
The digital processing device 180 (digital receiving device) is a device that demodulates a signal received from a transmission source, and reproduces data representing images, characters, sounds, programs, and the like based on information acquired from the demodulated signal. . The digital processing device 180 includes a demodulation device 100 (digital demodulation device) and an image processing unit 181. Among these, the demodulator 100 includes a tuner 110 and a demodulator 120. The tuner 110 performs a channel selection process on the received signal S to generate an IF (Intermediate Frequency) signal. The demodulator 120 demodulates the IF signal from the tuner 110 to generate a TS (Transport Stream) signal. The TS signal generated by the demodulator 100 is sent to the image processing unit 181, and the image processing unit 181 reproduces images, sounds, data, and the like. Further, the demodulator 100 has a control unit 130, and the control unit 130 controls the tuner 110 and the demodulator 120. Examples of such a digital processing device 180 include a digital TV, a mobile phone, and a PC equipped with a wireless LAN device that performs the above demodulation processing.

  It should be noted that the present invention is applied to an apparatus such as the digital processing apparatus 180 that has both the demodulation device 100 and the image processing unit 181 and has a configuration other than the configuration that performs both the demodulation processing and the image processing. May be. For example, a reproduction processing device 190 that performs image reproduction processing such as the image processing unit 181 and a demodulation device 100 that performs demodulation processing are configured separately and connected to each other by a cable or the like. A configuration in which the reproduction processing device 190 performs reproduction processing based on the transmitted TS signal may be employed.

  The digital processing device 180 is composed of a plurality of circuit component groups. Each circuit component group may be a set of a plurality of circuit components having circuits specialized to perform independent functions, or a general-purpose CPU, RAM, etc. and a CPU that performs the following functions. It may be composed of a program that functions. In the latter case, the tuner 110, the demodulator 120, and the like are constructed by combining hardware such as a CPU and a program.

<Signal>
The following is a description of signals received by the digital processing device 180. In the following description, as an example according to the present embodiment, it is assumed that digital terrestrial broadcasting employing an OFDM (Orthogonal Frequency Division Multiplexing) scheme is received. The OFDM system is a multi-carrier system in which a plurality of carrier waves having different frequencies are used to carry data. The carriers used in the OFDM system have waveforms that are orthogonal to each other. Here, “the two waveforms are orthogonal” means that the function (inner product) obtained by multiplying each function representing the amplitude of the wave with respect to time and performing time integration in an integration range corresponding to one period becomes zero. Say. Various transmission schemes such as a transmission scheme employing a single carrier wave and a CDMA (Code Division Multiple Access) scheme may be applied to the present embodiment instead of a multicarrier scheme such as the OFDM scheme.

  When data is transmitted from the transmission source, a signal in which a plurality of carrier waves modulated according to each value of the transmitted data are superimposed is formed. That is, each data value is distributed to a different carrier according to the arrangement order of a plurality of data values included in the transmitted data. Then, the carrier wave is modulated according to the distributed data value, and an OFDM signal is formed by superimposing the plurality of modulated carrier waves. Forming an OFDM signal in this way in the OFDM scheme is equivalent to performing an inverse Fourier transform.

  Next, in order to reduce the influence of delayed waves other than the direct wave, a guard interval is further inserted into a signal in which a plurality of carrier waves modulated as described above are superimposed. The guard interval is used by the AFC / symbol synchronization unit 122 described later to remove a delayed wave from the signal. A delayed wave in a signal is a wave that arrives after being delayed with respect to the direct wave of the signal that reaches the receiving side in the shortest time, due to various conditions on the transmission path until the signal is received. In the signal formed by superimposing a plurality of carrier waves as described above, a part of one end of this signal is copied and inserted into the other end for each signal of a predetermined length. This copy portion is a guard interval. One symbol is formed by combining such a guard interval and the signal having the predetermined length. Among these, the signal having the predetermined length is called an effective symbol, and the length thereof is called an effective symbol length. A signal with the guard interval inserted in this way is transmitted from the transmission source.

  By the way, the data transmitted by the OFDM signal as described above is encoded for correcting errors generated by noise and interference waves generated in the transmission path. For example, there are Reed-Solomon codes (RS codes) and Viterbi codes for encoding used in digital terrestrial broadcasting in Japan and Europe. Of these, in the RS code used as an outer code in terrestrial digital broadcasting, the last 16 bytes of the transmitted 204 bytes of data are check bits, and an error of up to 8 bytes out of 204 bytes can be corrected. In addition, in a Viterbi code used as an inner code in Japanese terrestrial digital broadcasting, the encoding rate when the data before encoding is k bits is set to k / n with respect to n bits transmitted after encoding. 1/2 to 7/8 is standardized.

  In order to restore the RS-encoded and Viterbi-encoded data, RS decoding and Viterbi decoding are performed on the receiving side. In the present embodiment, “error correction is possible” refers to a case where the bit error rate after decoding is a predetermined value or less.

  On the other hand, depending on the state of the transmission path, there may occur a burst error in which errors are continuously concentrated on a transmission signal in terms of time or frequency. When an error occurring in a signal of a certain length is corrected by error correction of RS coding as described above, the number of errors that can be corrected per signal of this length is limited. If an error occurs, it may be impossible to correct the error. In Viterbi coding, if there are concentrated errors such as burst errors, erroneous coding correction is performed, and errors may increase.

  Thus, interleaving processing is performed on data transmitted by the OFDM signal so that error correction is possible even when a burst error occurs in the transmission signal. In interleaving, data to be transmitted is rearranged in terms of time and frequency and randomized, and errors are spread on average. Interleaving is roughly classified into convolutional interleaving and block interleaving. Convolutional interleaving is used for time interleaving in Japanese digital TV, but it rearranges symbols by delaying data in a fixed pattern with different delay amounts. In the present embodiment, unlike such convolutional interleaving, it is assumed that the signal is subjected to block interleaving in which the signal is divided into blocks and symbols are rearranged in the blocks for each block. Note that both convolutional interleaving and block interleaving may be applied to the signal of this embodiment.

  FIG. 2 shows an example of interleaving and deinterleaving when OFDM symbols are used as data and block interleaving is used for temporal rearrangement of the symbols. The signal Sα is a signal received by the digital processing device 180. As shown in FIG. 2, the signal Sα is composed of a series of a plurality of symbols Sb. In block interleaving, the signal Sα is divided into a plurality of blocks having the length of the interleaving length Li, and rearrangement is performed as shown in FIG. 2 within the range of each block. When the signal Sα is received, block deinterleaving is performed on the receiving side, and the order is returned to the order before block interleaving.

  By such block interleaving and block deinterleaving, burst errors generated in the transmission signal are distributed on the average in a block range having the length of the interleave length Li. For example, as shown in FIG. 2, it is assumed that a burst error 201 occurs when the signal Sα after block interleaving is transmitted. However, the burst error 201 is distributed to each symbol 202 by block deinterleaving on the receiving side. Even when burst errors that concentrate in time occur in this way, errors do not concentrate in the signal after block deinterleaving. That is, the amount of errors per unit length is reduced, and errors are easily corrected.

<Tuner>
The following is a more detailed description of the tuner 110. FIG. 3 is a diagram illustrating a configuration of the tuner 110.

  The tuner 110 includes an RF amplifier unit 111, a mixer unit 112, a VCO / PLL unit 113, a filter unit 114, and an IF amplifier unit 115. The signal Sα received by the tuner 110 is amplified by the RF amplifier unit 111 and sent to the mixer unit 112. On the other hand, the VCO / PLL unit 113 forms a mixing signal based on a frequency corresponding to a specific channel in accordance with the channel control signal sent from the control unit 130. The mixing signal formed by the VCO / PLL unit 113 is sent to the mixer unit 112. The mixer unit 112 then mixes the signal Sα sent from the RF amplifier unit 111 and the mixing signal sent from the VCO / PLL unit 113 to form an IF signal corresponding to the IF frequency.

  The IF signal formed by the mixer unit 112 is sent to the filter unit 114. The filter unit 114 removes unnecessary signal components from the IF signal sent from the mixer unit 112. The IF signal Si from which unnecessary signal components have been removed is sent to the IF amplifier unit 115, amplified by the IF amplifier unit 115, and transmitted to the demodulator 120.

<Demodulator>
The following is a description of the demodulator 120. FIG. 4 is a block diagram showing the configuration of the demodulator 120.

  The demodulator 120 includes an ADC unit 121, an AFC / symbol synchronization unit 122, an FFT unit 123, a frame synchronization unit 124, a waveform equalization unit 125, and an error correction unit 126.

  The IF signal Si transmitted from the tuner 110 is input to the ADC unit 121. The ADC unit 121 converts the input signal Si, which is an analog signal, into a digital signal, and sends the converted digital signal to the AFC / symbol synchronization unit 122. The AFC / symbol synchronization unit 122 performs correction processing such as filter processing on the digital signal sent from the ADC unit. Then, the AFC / symbol synchronization unit 122 determines the starting point of the Fourier transform by the FFT unit 123, that is, the symbol synchronization point. Then, the synchronized digital signal is sent to the FFT unit 123.

  In the determination of the symbol synchronization point, a point at which optimum reception with the least influence of delayed waves and the like that arrive after delay is possible is set as the synchronization point. As a method of determining such a synchronization point, a method of referring to signal correlation, a method of correcting a phase shift using a pilot signal, or the like is used.

  As described above, one guard interval is inserted in one symbol. That is, the same signal is included in the vicinity of the front end and the rear end of one symbol at positions separated by the effective symbol length. Therefore, for example, when the correlation between signals at positions separated by the effective symbol length is calculated, the correlation value related to the signal at the position of the guard interval is relatively large in the calculation result. On the other hand, since the correlation value related to signals at positions other than the guard interval is the correlation between signals included in different symbols, the correlation value is relatively small. Accordingly, the position of the guard interval, that is, the position of the leading end or the trailing end of the symbol is accurately grasped.

  On the other hand, when a delayed wave is included in the signal, the calculated correlation value is smaller than the original correlation value. The range in which a smaller correlation value is calculated in the signal differs depending on the delay time of the delayed wave included in the signal. Based on the delay time or the like ascertained from such a difference in correlation value, the point at which optimum reception with the least influence of the delayed wave is possible is set as the synchronization point.

  An FFT (Fast Fourier Transform) unit 123 performs Fourier (time-frequency) conversion on the digital signal transmitted from the AFC / symbol synchronization unit 122. For example, so-called fast Fourier transform (FFT) is generally used in terrestrial digital broadcasting. Signal Si from tuner 110 has a waveform obtained by inverse Fourier transform at the transmission source, that is, a waveform in which a plurality of carrier waves modulated in accordance with data values are superimposed. The FFT unit 123 extracts a plurality of carrier waves modulated according to the data value from the superimposed waveforms by Fourier transform. Then, a digital signal corresponding to the data before the OFDM signal is formed at the transmission source is re-formed. Then, the FFT unit 123 sends this digital signal to the frame synchronization unit 124.

  The frame synchronization unit 124 synchronizes the digital signal sent from the FFT unit 123 in units of frames. One frame corresponds to a signal having a predetermined length, and includes a predetermined amount of data. The block interleaving period is composed of one or more frames. Frame synchronization is performed by detecting synchronization information included in one frame. The digital signal synchronized by the frame synchronization unit 124 is sent to the waveform equalization unit 125. Further, the frame synchronization unit 124 extracts a block interleave boundary from the frame synchronization (boundary) information based on the block interleave length information.

  The waveform equalization unit 125 performs signal correction by waveform equalization on the digital signal synchronized by the frame synchronization unit 124 based on a pilot signal or the like included in the digital signal. Thereafter, the digital signal is demodulated into a demodulated signal corresponding to the data value, and the demodulated signal is sent to the error correction unit 126. Note that, when the amount of error included in the signal is evaluated by the CN ratio in the determination of whether correction is possible, which will be described later, the waveform equalizer 125 extracts information necessary for calculating the CN ratio from the signal. For example, when calculating the CN ratio, there may be a case where a modulation scheme applied at the transmission source is required. In such a case, the waveform equalizer 125 extracts information relating to the modulation method from the digital signal. Alternatively, a difference between the constellation of each carrier wave subjected to waveform equalization based on a pilot signal included in the digital signal and the specified value is derived. The waveform equalization unit 125 sends information necessary for calculating the CN ratio, such as the difference between the constellation and the specified value and the modulation method, to the control unit 130.

  The error correction unit 126 performs deinterleaving processing and error correction processing on the demodulated signal from the waveform equalization unit 125 (corresponding to the function of the first error correction means in this embodiment). As described above, the signal Si from the tuner is subjected to various interleaving processes and encoding processes at the transmission source. The error correction unit 126 performs deinterleaving processing and decoding processing for returning to signals before these processing according to interleaving processing such as byte interleaving performed at the transmission source and encoding processing such as RS encoding.

  The error correction unit 126 calculates the bit error rate of the demodulated signal based on the number of corrected errors. The calculated bit error rate is sent to the control unit 130. This bit error rate is the ratio of the number of bits corrected by decoding to the number of bits of the signal immediately after the deinterleaving process. The bit error rate may be calculated for each of a plurality of decodings performed by the error correction unit 126, or may be calculated based on the number of errors corrected in all decodings. .

  The interleaving process assumed in this embodiment includes a block interleaving process. For this reason, the deinterleave processing performed by the error correction unit 126 includes block deinterleave processing (corresponding to the function of the rearranging means). Then, after the block interleaving process is performed, the error included in the signal is corrected by a decoding process such as RS decoding (corresponding to the function of the correcting means after rearrangement).

  These various deinterleaving processes and decoding processes are performed in the order corresponding to the various interleaving and encoding processes performed at the transmission source. An error is corrected by such deinterleaving processing and decoding processing, and the digital signal subjected to the interleaving processing and encoding processing is returned to the digital signal before encoding.

  The demodulator 120 generates a TS signal from the demodulated signal that has been subjected to error correction processing by the error correction unit 126 as described above. Then, the generated TS signal is sent to the image processing unit 181.

<Control based on block deinterleaving>
The following is a description of the control of the control unit 130 performed based on block deinterleaving by the error correction unit 126. The control unit 130 controls the tuner 110 and the demodulator 120 as described above. Specifically, a circuit component group constituting the RF amplifier unit 111 and the like included in the tuner 110 is controlled (corresponding to the function of the circuit control means). Such control includes, for example, control of power supplied to each unit in the tuner 110, control of changing the gain of the RF amplifier unit 111 and the like, and control of changing the power consumption of the demodulator 120. On the other hand, a signal to which errors due to various factors on the transmission path to reach the tuner 110 are added to the tuner 110. Therefore, in the signal Si handled by the demodulating apparatus 100, errors generated by the control by the control unit 130 are overlapped in addition to errors generated on the transmission path until reaching the tuner 110.

  A curve 91a in FIG. 5A indicates the amount of errors that are included in the signal Si. For example, when control for changing the power supplied to the tuner 110 is performed, the amount of errors included in the signal Si increases. If control is performed at times T1 and T2 corresponding to the symbols Sb1 and Sb2 in the signal Si, errors that are included in the signal Si increase. A curve 91a shows a state in which error peaks 81 and 82 are generated by two times of control at times T1 and T2. In FIG. 5, it is assumed that the effect of errors falls within one symbol.

  Such errors included in the signal Si are dispersed by deinterleaving of the error correction unit 126. A curve 92a indicates an error amount of a signal included in the signal Sd dispersed by block deinterleaving, for example. The errors corresponding to the error peaks 81 and 82 are distributed over the range of the block B1 having the length of the interleave length Li.

  Here, it is assumed that further control is performed at time T3 after time T2. At this time, as shown in the figure, the time T3 is within the same range of the block B1 as the symbols Sb1 and Sb2. Therefore, the range in which the error peak 83 'generated by the control performed at time T3 is dispersed in the signal Sd after block deinterleaving overlaps the range in which the error peaks 81 and 82 are dispersed.

  In this way, block deinterleaving is performed within the range of the interleave length Li. For this reason, when the next control is performed within the range of the same block where the previous control was performed, the distributed errors overlap within the range of the same block. If errors due to a plurality of controls overlap in this way, the error correction unit 126 may not be able to completely correct the error included in the signal. For example, when only error peaks 81 and 82 exist within the range of the block B1, as shown in the curve 92a, the error reference value that can be corrected in the signal Sd after block deinterleaving is set to the error amount. Is below.

  On the other hand, if an error peak 83 ′ appears in the signal Si due to the following control at time T <b> 3, the amount of error in the signal Sd may exceed the reference value. Curve 92a 'shows the amount of error in signal Sd after error peak 83' and error peaks 81 and 82 have been dispersed by block deinterleaving. As shown in the curve 92a ′, the influence of the error peak 83 ′ in addition to the error peaks 81 and 82 appears in the signal Sd, so that the total amount of errors included in the signal Sd is a reference. It is above the value. In such a case, the error included in the signal Sd is not corrected. And the reliability of the information contained in the signal after error correction becomes low.

  In order to avoid a situation in which the error correction unit 126 cannot correct the error included in the signal, the control unit 130 has a configuration for performing the following control.

<Correctability>
The control unit 130 determines whether or not the error included in the signal Si can be corrected by performing the control as follows. First, the control unit 130 calculates the CN ratio between the carrier power and the noise power in the signal. The signal includes noise generated by various factors in addition to noise that causes an error in the signal Si under the control of the control unit 130. For example, it is the total noise including the noise included in the signal Sα from the beginning when the tuner 110 receives the signal Sα and the noise generated until the tuner 110 receives the signal Sα and converts it to the IF signal Si. In the following, it is assumed that the power of noise generated by the control of the control unit 130 is Ni, and the power of noise caused by factors other than the control of the control unit 130 is No. First, the carrier power Cd and the noise power No are calculated from information relating to the CN ratio sent from the demodulator 120.

  Next, the noise power Ni is estimated from the magnitude of the virtual noise that is generated in the signal Si when it is assumed that the control by the control unit 130 is performed. The control by the control unit 130 is predetermined, and it can be estimated to some extent in advance how much noise is generated according to the amount of change in the operation parameter in the control. Therefore, the control unit 130 has a configuration in which the relationship between the control target, the amount of change in the operation parameter in the control, and the like and the power of the noise are held as a table or function, and the noise Ni is estimated based on the table or function. May have. For example, when the power supply is controlled in each part of the tuner 110, the change amount of the operation parameter in the control means the change amount of the supply power.

  Then, from the carrier and noise powers Cd, Ni, and No derived as described above, the CN ratio is calculated as in Equation 1 below. In the following description, unless otherwise specified, it is assumed that there is no temporal change in the noise generated until the demodulator 100 receives a signal and the reception state is stable.

  On the other hand, since the signal Si is subjected to block deinterleave processing, the influence of the noise Ni is dispersed in the signal Sd. In order to evaluate the noise Ni dispersed in the signal Sd in this way, an equivalent CN ratio expressed by Equation 2 is introduced. Here, n represents the number of symbols included in the range of the time interleave length Li.

  Here, the average value of the power per interleave length may be used as the carrier power Cd and the noise power No. This is because, when each of the carrier power Cd and the noise power No is relatively stable as described above, even if the average value is used to determine whether or not the error can be corrected, the determination does not greatly deviate. This is because a determination using an accurate measurement value is made by using the average of the measurement values measured over a considerable period. On the other hand, when the power of the carrier or noise is not stable, an average value for a period shorter than the interleave length may be used. In this case, the determination is made in response to the change in the reception situation more than when the average value of the interleave length is used.

  Next, the control unit 130 derives a reference value to be compared with the equivalent CN ratio calculated based on Equation 2 above. This reference value corresponds to the limit amount of errors that the error correction unit 126 can correct. When the noise generated in the signal increases, the above-mentioned equivalent CN ratio decreases, and when the noise becomes less than a certain value, the error correction unit 126 cannot correct the error. The reference value of the equivalent CN ratio corresponds to such a lower limit of the equivalent CN ratio. When it is determined whether correction is possible based on the error amount, such a reference value indicates the upper limit of the error amount. That is, it corresponds to the reference value itself shown in FIG.

  Then, the control unit 130 compares the equivalent CN ratio with the reference value and determines that the error can be corrected when the equivalent CN ratio is equal to or higher than the reference value. When the equivalent CN ratio is lower than the reference value, It is determined that the error cannot be corrected (corresponding to the function of the first correction availability determination unit).

  The correctable value varies depending on the signal system such as the carrier modulation system and the encoding system. For this reason, the control unit 130 holds a table indicating the correspondence relationship between the carrier modulation method and the reference value, and derives an appropriate reference value from the information related to the signal method extracted from the signal and the above table. . The demodulator 100 may have a configuration in which information related to the signal system is extracted by the waveform equalization unit 125 of the demodulator 120 and sent from the demodulator 120 to the control unit 130.

  Different reference values may be set according to the stability of the reception status of the signal Si. That is, a small reference value may be set when the reception status is stable, and a large reference value may be set when the reception status is unstable. When the reference value is set large, the reliability of the determination when it is determined that correction is possible is improved. Therefore, even when the carrier or noise power changes greatly in a short period of time, a judgment is made based on a sufficient standard, and control suitable for a case where the signal is unstable is ensured. When the reception state of the signal Si is stable, it is considered that the power of the carrier or noise does not change in a short time, and therefore, it may be set to a value close to the minimum value that can be corrected. As a result, useless control of the control unit 130 due to the fact that it can be corrected but cannot be corrected is omitted.

  Whether or not correction is possible may be determined based on information on the bit error rate from the demodulator 120. In this case, the control unit 130 estimates the amount of error included in the signal by controlling the circuit component group as the bit error rate, and calculates the reference value as the bit error rate. Then, whether or not correction is possible is determined based on the information related to the bit error rate from the demodulator 120, the estimated amount of error, and the calculated reference value.

  Specific examples of the determination based on whether or not correction is possible and the control based on the judgment on whether or not correction is possible (corresponding to the function of the main control means) are as follows. In FIG. 5A, it is assumed that the next control of the circuit component group by the control unit 130 is scheduled at time T3 included in the block B1. On the other hand, error peaks 81 and 82 due to the previous control appear in the range of the block B1 including the time T3. Alternatively, in some cases, the signal Si includes errors that occur accidentally on the transmission line other than errors that occur in the signal Si due to control.

  First, the control unit 130 calculates the amount of errors that will be included in the range of the block B1 at the present time based on information from the demodulator 120. Specifically, the amount of error is calculated as the power of noise that is included in the signal Si as described above. For example, immediately before time T3 in FIG. 5A, it is assumed that the power of noise corresponding to the total number of errors included in the block B1 at that time is N1. The noise power N1 includes the effects of noise corresponding to error peaks 81 and 82 and various noises generated on the transmission line.

  Next, the control unit 130 estimates the amount of errors to be included in the signal Si by performing the following control within the range of the block B1. For example, it is assumed that the power of noise generated when the next control is performed at time T3 in FIG. The noise power N2 corresponds to the error peak 83 '. The influence of the noise powers N1 and N2 overlaps in the signal Sd after block deinterleaving. Therefore, the equivalent CN ratio R when the influence of two noises overlaps is calculated as R = 10 log [nCd / (nNo + N1 + N2)] from Equation 2. When k noises of power N1 to Nk (k: natural number of 2 or more) are generated in one block, the equivalent CN ratio is expressed as 10 log [nCd / (nNo + N1 +... + Nk)].

  Furthermore, the control unit 130 derives a lower limit value of the CN ratio that can be corrected by the error correction unit 126. For example, it is assumed that the reference value R0, which is the lower limit value of the CN ratio that can be corrected by the error correction unit 126, is derived as R0 = 10 log [nCd / (nNo + Nb)].

  Here, assuming that N1 + N2 ≦ Nb, the relationship of equivalent CN ratio is R0 ≦ R. That is, the equivalent CN ratio R estimated even when the next control is performed at time T3 is equal to or greater than the reference value R0, which is a correctable lower limit value. Therefore, control unit 130 determines that correction is possible even when the next control is performed at time T3. In this case, control by the control unit 130 is performed at time T3 within the range of the block B1.

  On the other hand, when Nb <N1 + N2, the relationship of equivalent CN ratio is R <R0, and the equivalent CN ratio R when the next control is performed at time T3 is lower than the reference value R0. Therefore, control unit 130 determines that correction is not possible when the next control is performed at time T3. A curve 92a 'in FIG. 5A represents such a case. R <R0 means that the error distributed in the signal Sd is no longer correctable. Therefore, the situation where R <R0 corresponds to the situation where the curve 92a ′ indicating the amount of error in the signal Sd exceeds the reference value due to the influence of the error peak 83 ′ in addition to the error peaks 81 and 82. To do.

  When it is determined that the error is no longer correctable when the next control is performed at time T3, the control unit 130 waits until just before time T4 to reach the symbol located at the rear end of the block B1. When the time just before time T4 is reached, the control unit 130 calculates the total noise power up to the present within the range of the block B1 based on the information sent from the demodulator 120. Then, it is determined again whether or not the error included in the signal Sd is correctable by performing the following control on the symbol at the rear end of the block B1 (in the function of the second correction possibility determination means). Corresponding). If it is determined that the error included in the signal Sd is still not correctable, the control unit 130 determines the time after the leading edge of the block B2 next to the block B1 (for example, the time in FIG. 5A). In T5), it is determined again whether or not to perform the next control. If correction is possible even if the next control is performed in block B2, the next control is performed in block B2. The error peak 83 indicates the amount of error that will be included in the signal Si when the next control is performed at time T5 of the block B2.

  As described above, when it is finally determined that the error included in the signal Sd is not correctable by the control based on the determination as to whether correction is possible or not, the block subsequent to the current block Control is made. Therefore, since control is performed within a range where the error can be corrected, accurate information can be acquired from the demodulated signal.

  Here, the waveform equalization unit 125 of the demodulation unit 120 measures the CN ratio, and the control unit 130 performs control based on the measured value, but until the CN ratio is calculated from the signal Si that has entered the demodulation unit 120. Takes a delay time of several symbols. For example, since the FFT unit 123 performs Fourier transform, the input signal Si is buffered by one symbol, so that the FFT unit 123 requires a delay time of at least one symbol.

  Therefore, as described above, when it is determined that the error cannot be corrected when the next control is performed at time T3, control unit 130 determines the time to reach the symbol located at the rear end of block B1. While waiting until just before T4, it is necessary to set the waiting time in consideration of the delay time from when the signal is input until the processing is completed. In the following, for the sake of simplicity, the description is not made in consideration of the above delay time, but it is assumed that the standby time is actually set in consideration of the delay time.

  On the other hand, even if it is determined that correction is not possible when the next control is performed at time T3, the equivalent CN ratio is calculated based on information actually measured by demodulator 120 immediately before time T4. Then, the following control may be performed with the symbol located at the rear end of the block B1. FIG. 5B shows such a case. A curve 91b indicates an error that is included in the signal Si before block deinterleaving, and a curve 92b indicates an error that is included in the signal Sd after block deinterleaving. Curves 91b and 92b indicate the amount of error derived by the control unit 130 immediately before time T4, and are different from the curves 92a and 92a 'derived at the timing immediately before time T3. A curve 91b shows an error peak 84 appearing in the signal Si when the next control is performed on the rear end symbol of the block B1.

  That is, unlike the curves 92a and 92a ', the curve 92b is derived after taking into account changes in the reception status after time T3. Therefore, the actual situation at the time T4 is more accurately reflected in the curve 92b than in the curves 92a and 92a '. For example, in the curve 92a ′, even if it is determined that the amount of error included in the signal Sd exceeds the reference value by performing the next control at time T3, the reception situation improves after time T3. As a result, the amount of errors that are actually included in the signal Sd may differ from the prediction.

  Therefore, the control unit 130 performs the next control with the symbol at the rear end of the block B1 immediately before the time T4 (note that the timing immediately before this time is the timing after considering the delay time). If it is determined that the error included in the signal Sd is correctable (corresponding to the function of the second correctability determination means), the next symbol in the rear end of the block B1 Start control.

  Thus, even if it is once determined that the error included in the signal Sd cannot be corrected by the control within the range of the block, the demodulator 120 is actually used at the time until the symbol located at the rear end of the block. The noise is measured and a final decision is made as to whether correction is possible. If it is determined that the error can be corrected even if the control is performed with the symbol located at the rear end of the block, the next control is performed with the symbol located at the rear end of the block. Therefore, the determination as to whether or not correction is possible is made twice, and the information necessary for the determination is sufficiently secured, so that the determination as to whether or not correction is possible becomes more reliable. Even if it is determined that correction is not possible in the first determination, it is determined in the second determination that correction is possible based on more accurate information than in the first determination. Can be secured.

  The above is the description of the control by the control unit 130 in the case where the peak of the amount of error appearing in the signal Si by one control falls within one symbol. On the other hand, the following description is a description of the control by the control unit 130 when the peak of the amount of error appearing in the signal Si appears across a plurality of symbols by one control.

  6 and 7 show the amount of errors included in a signal when continuous control is performed so that the influence of errors appears across a plurality of symbols. Among these, FIG. 6 shows a case where the control may be divided, and FIG. 7 shows a case where the control is not divided and needs to be performed integrally and continuously.

  A curve 93 in FIG. 6 indicates the amount of errors that are included in the signal Si under the control of the control unit 130. Curve 94 shows the amount of error that will be included in signal Sd. For example, it is assumed that control is scheduled to start at time T10 and end at time T12. When the control is started from time T10, the control unit 130 determines the equivalent CN at that time corresponding to the amount of error to be included in the signal Sd within the range of the block B3 based on the information from the demodulator 120. Start calculating the ratio.

  And the control part 130 calculates the equivalent CN ratio in the time as control is continued. As the control continues, the total number of errors in the block B3 increases, so the equivalent CN ratio calculated by the control unit 130 decreases. Here, the control unit 130 calculates the equivalent CN ratio and whether or not the calculated equivalent CN ratio is below a correctable reference value, that is, whether or not an error included in the signal Sd can be corrected. Determine whether. For example, when it is determined that the equivalent CN ratio is lower than the correctable reference value at time T11, that is, the amount of errors included in the signal Sd exceeds the correctable reference value, the control unit 130 Stop control once.

  The curve 93 shows an error peak 85 that appears in the signal Si when the control is started at the time T10 and stopped once at the time T11. On the other hand, since the control is originally scheduled to be continued until time T12, the control once stopped at time T11 must be resumed after time T11. Note that the error peak 85 'indicates the amount of error appearing in the signal Si when the control is continued until time T12.

  The control unit 130 resumes the control corresponding to the originally scheduled control from the time T11 to the time T12 after the symbol located at the front end of the block B4 next to the block B3. Curve 93 shows a peak 86 of errors appearing in signal Si due to the control resumed in block B4. In block B4 as well, the control unit 130 calculates an equivalent CN ratio that changes every moment, and determines whether or not the equivalent CN ratio is maintained within a correctable range at that time. If it is determined that the correction is impossible, the control is temporarily stopped, and further resumed in the next block. The error peak 86 indicates the amount of error that is included in the signal Si when the control is performed in the block B4.

  By the above control, it is avoided that an error exceeding a correctable reference value is included in each block, and necessary control is ensured within a correctable range after each block.

  Note that the control unit 130 may continue to calculate the equivalent CN ratio based on information from the demodulator 120 from when control is temporarily stopped in each block until the end of the block. Then, based on the calculated equivalent CN ratio, if it is determined that the amount of errors that will be included in the block even if control is resumed from a certain point in the block is below the correctable reference value, The control unit 130 may resume control from that point. For example, in FIG. 6, even after the control is temporarily stopped at time T11, the control unit 130 continues to calculate the equivalent CN ratio of the block B3. If it is determined immediately before time T13 that the equivalent CN ratio of block B3 does not fall below the reference value even when control is resumed from time T13, that is, the error of block B3 falls within the correctable range, The control unit 130 resumes control from time T13. The error peak 86 'indicates the amount of error included in the signal Si when the control is resumed from time T13.

  Unlike the control shown in FIG. 6, when the control cannot be divided, the control shown in FIG. 7 is performed.

  It is assumed that continuous control over a plurality of symbols is scheduled in block B5. When such control cannot be performed in a divided manner, the control unit 130 is included in the signal Sd when the control is continuously performed over a plurality of symbols in the block B5. Predict the amount of errors that will be. A curve 95a in FIG. 7A indicates the amount of errors that are included in the signal Si when, for example, control is continuously performed in the period of time T20 to T21 in the block B5. A curve 96a indicates the amount of error that will be included in the signal Sd. Further, the control unit 130 determines whether or not the predicted error amount exceeds a correctable reference value. If it is determined that the predicted error amount does not exceed the reference value even if the control is continued over the period T20 to T21, the control unit 130 executes the control over the period T20 to T21.

  On the other hand, as shown in the curve 96a, when it is predicted that the amount of errors included in the signal Sd exceeds the correctable reference value, the control unit 130 determines whether the block B5 and the block B5 Next, control is performed across the boundary with the next block B6. The curve 95b in FIG. 7B shows the amount of error that is included in the signal Si by such control, and the curve 96b shows the amount of error that is included in the signal Sd. As shown by the curve 95b, the control is started at time T22 in the block B5, and the control is ended at time T23 in the block B6. A curve 95b shows error peaks 88a and 88b that are included in the signal Si by the control performed in the respective ranges of the blocks B5 and B6. Further, curve 96b shows how error peaks 88a and 88b are distributed in blocks B5 and B6, respectively, in signal Sd. Times T22 and T23 are determined by the control unit 130 so that the amount of error to be included in the signal Sd does not exceed the correctable reference value in each of the blocks B5 and B6. If it is determined that there are no times T22 and T23 that are below the correctable reference value in any of the blocks B5 and B6, the control is started in a block subsequent to the block B6.

<Flow 1>
The following is a description of a series of steps in which the control unit 130 controls the circuit component group in the present embodiment. 8 to 11 are flowcharts showing an example of the control by the control unit 130. Note that the flowcharts of FIGS. 8 to 11 show a series of steps when one control is performed. In the following, description will be made for each of the flowcharts of FIGS.

  First, the control unit 130 estimates the power of noise that causes an error to be included in the range of the block in the signal Si under control. Based on the estimated power, information on the CN ratio from the demodulator 120, and the like, the equivalent CN ratio in the signal Sd after the block interleaving process is predicted (S1).

  Next, based on the comparison between the equivalent CN ratio predicted in S1 and the reference value of the CN ratio derived in advance, the control unit 130 detects an error that will be included in the range of the block in the signal Sd by control. The correction unit 126 determines whether correction is possible (S2). When it is determined that an error within the block range can be corrected (S2, YES), the control unit 130 performs control within the block range (S3). Then, a series of steps is completed.

  On the other hand, when it is determined that if the control is performed within the range of the block, the error included in the block range is not correctable (S2, NO), the control unit 130 will execute the control. It is determined whether or not the control to be within the range of one symbol (S4). When it is determined that it falls within the range of one symbol (S4, YES), the control unit 130 executes the processing from S6 of FIG. On the other hand, when it is determined that it does not fall within the range of one symbol (S4, NO), the control unit 130 determines whether or not the control to be executed can be divided and executed (S5). . When it is determined that it can be divided and executed (S5, YES), the control unit 130 executes the processing from S10 of FIG. If it is determined that it cannot be divided and executed (S5, NO), the processing from S16 in FIG. 11 is executed.

  The series of steps shown in FIG. 9 shows a case where an error that is included in the signal Si by control can be contained in one symbol. In S6 of FIG. 9, the control unit 130 waits until just before the symbol located at the rear end of the block (S6, NO). If it is determined that the symbol is located immediately before the symbol located at the rear end of the block (S6, YES), the control unit 130 determines whether the symbol located at the rear end of the block is based on the information from the demodulator 120. It is determined again whether or not an error that is included in the range of the block when the control is performed is correctable (S7). If it is determined that an error within the block range can be corrected even if control is performed on the symbol located at the rear end of the block (S7, YES), the control unit 130 Control is performed on the symbol located at the end (S8). On the other hand, when it is determined that the error in the block range exceeds the correctable range when the control is performed on the symbol located at the rear end of the block (S7, NO), the control unit 130 Wait until the next block is reached (S9, NO). When the next block is reached (S9, YES), the steps from S1 in FIG. 8 are executed in the next block. That is, the scheduled control is performed after the block next to the block.

  A series of steps shown in FIG. 10 shows a case where an error that is included in the signal Si by control extends over a plurality of symbols, and control can be divided and executed. In S10 of FIG. 10, the control unit 130 starts control within the range of the block and starts calculating the equivalent CN ratio (S11). Then, the control unit 130 compares the calculated equivalent CN ratio with a correctable reference value, and determines whether or not the equivalent CN ratio is below the reference value (S12). When it is determined that the equivalent CN ratio is not lower than the reference value (S12, NO), the control unit 130 determines whether or not the control is performed for a predetermined time (S15). If it is determined that the scheduled time has been reached (S15, YES), all necessary control has been performed while keeping the error included in the block range within the correctable range. Control by the unit 130 is completed. When it is determined that the scheduled time has not yet been reached (S15, NO), the control unit 130 executes the steps from S11 while continuing the control.

  On the other hand, when it is determined in S12 that the equivalent CN ratio has fallen below the reference value, the control unit 130 temporarily stops the control (S13). And it waits until it reaches the next block of the said block (S14, NO). When the next block is reached (S14, YES), the control unit 130 executes the steps from S1 in FIG. That is, control for the remaining time excluding the time made in the block in the time to be controlled is performed after the next block.

  A series of steps shown in FIG. 11 shows a case where an error that is included in the signal Si by control straddles a plurality of symbols and the control cannot be divided and executed. In S16 of FIG. 11, the control unit 130 determines whether or not the control start time and end time can be determined (S16). That is, when the control is performed across the boundary between the two blocks as shown in FIG. 7B, the start time T22 and the end time are set so that both of the errors included in the two blocks can be corrected. It is determined whether or not time T23 can be determined. If it is determined that the start time and end time can be determined (S16, YES), the control unit 130 determines the control start time and end time (S17), as shown in FIG. 7B. Then, control is performed so as to straddle the block and the block next to the block (S18). Then, a series of steps is completed. On the other hand, when it is determined in S16 that the start time and end time cannot be determined (S19), the control unit 130 waits until the next block is reached (S19, NO). If it is determined that the next block has been reached (S19, YES), the steps from S1 in FIG. 8 are executed in the next block. That is, the scheduled control is performed after the block next to the block.

<Other embodiments>
The following is a description of another embodiment relating to the control of the circuit component group by the control unit 130. In addition, this embodiment and the above-mentioned embodiment contain many common structures. The following description will mainly focus on the differences between them, and description of the common configuration will be omitted as appropriate.

  There is a difference in the error correction method performed by the error correction unit 126 between the present embodiment and the above-described embodiment. FIG. 12 shows the signal Sβ received by the demodulator 100 according to this embodiment. The signal Sβ is divided into a plurality of blocks having a length Lb. Each block is further divided into a plurality of areas. That is, each block is composed of a series of sub-blocks corresponding to each area.

  Data included in the correction block 311 located at the rear end in each block is correction data used when error correction is performed by the error correction unit 126. Based on the data included in the correction block 311, error correction processing is performed on data included in a portion other than the correction block 311 in each block. At this time, the error correction processing is performed as a group of data included in a sub-block group composed of a plurality of sub-blocks separated from each other in time. That is, the correction data included in the correction block 311 is included in each of the group of data A, B, and C included in each of the sub-block groups 312a, 312b, and 312c including a plurality of sub-blocks separated in time. Based on this, an error correction process is performed.

  By performing error correction on each of the sub-block groups composed of a plurality of sub-blocks separated from each other in this way, even when a burst error 301 occurs in the signal Sβ, the error is substantially dispersed and the error is Corrections are made. Therefore, as in the case of the above-described embodiment, the error correction is performed after the error is averagely distributed within the block, as in the case where the error correction is performed after the error is distributed by block deinterleaving. That is, when error correction is performed after the symbols in the block are actually rearranged as in the above-described embodiment, and each of a plurality of sub-block groups including a plurality of sub-blocks spaced apart from each other as in this embodiment. The case where error correction is performed is equivalent in the sense that error correction is performed while distributing errors within the block range.

  Similar to the above-described embodiment, also in this embodiment, the control unit 130 controls the circuit component group so that the control is not started twice or more within the range of one block. Therefore, errors that are included in the signal by control are easily corrected. Further, as in the above-described embodiment, the above-described control is performed based on the determination as to whether correction is possible. That is, when it is determined that an error included in the block range cannot be corrected, the control timing is adjusted so that the control is started after the next block. On the other hand, when it is determined that the error included in the block range can be corrected, the control unit 130 controls the circuit components within the block range.

  In such error correction, subblocks included in each subblock group may be randomly extracted from a plurality of subblocks included in one block. Alternatively, each sub-block at a position separated from the reference position by one, two, three,... From the reference position in one block may be extracted.

  As a signal system as in this embodiment, specifically, there is DVB-H (Digital Video Broadcasting-Handheld) which is a standard for digital terrestrial broadcasting received by a mobile phone in Europe. The following is a description of signals related to the DVB-H system. In the DVB-H system, the signal Sβ is composed of a plurality of channel regions 310, 320, 330, etc. as shown in FIG. That is, the signal Sβ is composed of a plurality of channel regions divided in time. Each channel region is composed of a plurality of subchannel regions that are separated in time. For example, the channel region 310 includes subchannel regions 310a and 310b that are separated in time. As shown in FIG. 13B, each sub-channel region is further composed of a series of blocks having a structure as shown in FIG.

  Further, in the DVB-H system, a Viterbi code is adopted as an inner code, and an RS code is adopted as an outer code. Bit interleaving and frequency interleaving are adopted as the interleaving for the inner code, and byte interleaving is adopted as the interleaving for the outer code. Furthermore, the DVB-H system signal includes CRC (Cyclic Redundancy Check) -32 check data. This check data is data for determining whether or not an error has occurred in the valid area 312 including valid data with respect to a signal subjected to RS decoding corresponding to RS coding which is an outer code. is there. The correction block 311 includes data related to RS encoding. This RS encoding is different from RS encoding that is an outer code (hereinafter referred to as “second RS encoding”, and the corresponding decoding is referred to as “second RS decoding” (in this embodiment, Corresponding to the function of one error correction means), and is performed before RS encoding which is an outer code at the transmission source.

  When the DVB-H system as described above is employed in the digital processing apparatus 180 of the present embodiment, the following control is further performed. First, Viterbi decoding and RS decoding are performed on the DVB-H signal Sβ in accordance with the inner code and the outer code. At the same time, bit deinterleaving, frequency deinterleaving, and byte deinterleaving are performed according to the interleaving for the inner code and the outer code.

  Next, the control unit 130 determines whether each block of the signal Sβ subjected to RS decoding corresponding to the outer code (corresponding to the function of the second error correction means in the present embodiment) includes an error. Is determined based on the CRC-32 check data included in the signal Sβ (corresponding to the function of the error existence determination means). Here, when the control unit 130 determines that no error is included in the range of a certain block, the second RS decoding is not performed. This is because if it is determined that no error is included, error correction by the second RS decoding is not effective. That is, if no error is included, the data included in the correction block 311 is not used.

  Note that it may be determined whether or not an error is included in the signal Sβ after RS decoding without being based on the CRC-32 check data. For example, when RS decoding corresponding to the outer code is performed by the error correction unit 126, there is an upper limit on the amount of error that can be corrected per predetermined amount of data. The error correction unit 126 determines whether or not the amount of errors included in the signal Sβ is equal to or less than an upper limit that can be corrected. If it is determined that the amount of error included in the signal Sβ is equal to or less than the upper limit, the error correction unit 126 corrects the error after grasping which one includes the error. However, when it is determined that an error exceeding the upper limit is included, error correction by RS decoding is impossible, and thus the error is not corrected.

  Therefore, the error correction unit 126 may transmit the determination result when determining whether or not the error included in the signal is equal to or lower than the upper limit that can be corrected before performing RS decoding corresponding to the outer code to the control unit 130. . As a result, the control unit 130 can determine whether or not there is an error in the signal after error correction by the error correction unit 126. That is, if the error correction unit 126 determines that the correction is not more than the upper limit correctable by RS decoding, the control unit 130 determines that no error is included in the decoded signal Sβ. On the other hand, when the error correction unit 126 determines that the error included in the signal exceeds the upper limit that can be corrected, the control unit 130 does not perform error correction by RS decoding corresponding to the outer code, but after decoding. It is determined that an error is included in the signal Sβ. As described above, the control unit 130 determines whether or not an error is included based on the determination result of the correction by the error correction unit 126.

  As described above, after determining whether or not an error is included in the signal Sβ after RS decoding corresponding to the outer code based on CRC-32 check data or the like, the control unit 130 performs the following according to the determination result. The power source of the tuner 110 is controlled. That is, when determining that the signal Sβ does not include an error, the control unit 130 controls the circuit component group so that the control period falls within the range of the correction block 311 included in the block. This is because if no error is included, the correction block 311 is not used, and therefore no problem occurs even if an error occurs in the correction block 311 by control.

  For example, the following power control of the tuner 110 is performed. As described above, the DVB-H system signal is divided into a plurality of channel regions composed of a plurality of subchannel regions separated in time. For example, when one broadcast assigned to one channel area is continuously received, only the sub-channel area belonging to the channel area needs to be received. Therefore, it is possible to reduce the power consumption of the tuner 110 by performing control such that the tuner 110 is turned on only during a period of receiving the sub-channel area belonging to the channel area and is turned off in other channel areas. Become.

  Assume that the channel region to be received is the channel region 310 shown in FIG. At this time, as indicated by a curve 391 in FIG. 13B, the power source of the tuner 110 is kept off until just before receiving the sub-channel region 310a belonging to the channel region 310. Then, the control unit 130 turns on the tuner 110 immediately before the timing at which the sub-channel region 310a is to be received.

  Next, the control unit 130 stands by until reaching the rear end of the effective area 312 containing valid data in the block located at the front end of the sub-channel area 310a. Then, when reaching the rear end of the effective area 312, whether or not an error is included in the effective area 312 of the block after RS decoding corresponding to the outer code by the error correction unit 126 is indicated in CRC-32 check data or the like. Judgment based on. If it is determined that no error is included, as indicated by a curve 391, the power source of the tuner 110 is supplied for a certain period within the range of the correction block 311 in the block (for example, the period from time T7 to T8). Set to OFF. If it is determined that an error is included, the control proceeds to the next block while the power is kept on. And the control part 130 repeats such control for every block contained in the subchannel area | region 310a.

  Thus, the control unit 130 performs the above-described control also for the block Lb located at the rear end of the sub-channel region 310a. That is, first, it is determined whether or not an error is included in the effective area 312 of the block after RS decoding corresponding to the outer code. When it is determined that no error is included, the tuner 110 is turned off at a timing within the range of the block (for example, time T9). Since this block is a block located at the rear end of the sub-channel area 310a, it waits until the next sub-channel area 310 is received without turning the power back on. On the other hand, if it is determined that an error is included, the control unit 130 turns off the power of the tuner 110 at a timing after the time T10 that is the rear end of the correction block 311 (for example, time T10). And it waits until the next subchannel area | region 310 is received.

  A curve 392 shows the amount of error that will be included in the signal Sβ when the power supply of the tuner 110 is controlled as described above. As indicated by the curve 392, errors increase during the period of time T7 to T8 by turning off the power. However, the period during which errors are increasing is within the range of the correction block 311. Therefore, it is possible to prevent an increase in errors from directly affecting the effective area 312 including valid data.

  In addition, when the second RS decoding using the correction block 311 is performed, if power control is performed in the correction block 311, errors that are included in the correction block increase, so that error correction is accurate. Not made. In other words, the effect of increased errors reaches the effective area 312 after correction. However, in the present embodiment, the power is turned off within the range of the correction block 311 only when an error included in the valid area 312 is corrected by RS decoding corresponding to the outer code. In such a case, since the second RS decoding using the correction block 311 is not performed, even if errors increase in the correction block 311, the effect does not reach the effective area 312.

  As described above, according to the power supply control of the present embodiment, the influence of the power supply control is prevented from affecting the range of the effective region 312 that is the signal effective region 312 in the sub-channel region 310a. In addition, the power consumption of the tuner 110 can be further reduced as compared with the case where the power is turned off after time T7, which is the rear end of the sub-channel region 310a.

  In the above control, power control is performed in each block. However, the power supply may be kept ON from the front end of the subchannel region 310a to the block located at the rear end of the subchannel region 310a. Then, in the block located at the rear end of the sub-channel area 310a, control may be performed so that the power is turned off within the range of the correction block 311 if no error is included in the effective area 312.

Further, the power of only a part of the components constituting the tuner 110 may be reduced instead of turning off the entire power supply of the tuner 110. Furthermore, not only the power supply of the tuner 110 is turned off, but also the power supply of the entire demodulator 120 or a part of the components such as the ADC unit 121 may be turned off. As a result, the power consumption can be further reduced.
<Flow 2>
The following is a description of a series of steps in which the control unit 130 controls the circuit component group when the DVB-H system signal is employed in the present embodiment. 14 and 15 are flowcharts showing an example of control by the control unit 130. FIG. Note that the flowcharts of FIGS. 14 and 15 show a series of steps when control is performed in one subchannel region.

  The control unit 130 turns on the tuner 110 at a timing immediately before the start of the sub-channel region to be received (S31). Until then, the power supply of the tuner 110 is kept off.

  Next, the control unit 130 determines whether or not control other than power supply control is performed on the circuit component group constituting the tuner 110 or the demodulator 120 in the block (S32). If it is determined that control other than power control is not performed (S32, NO), the control unit 130 executes processing from S21 of FIG. The control other than the power control refers to various controls other than the control for turning off the power of the tuner 110. On the other hand, when it is determined in S32 that control other than the power supply control is performed (S32, YES), the control unit 130 causes noise that causes an error to be included in the range of the block by such control. Estimate power. Then, based on the estimated power, information on the CN ratio from the demodulator 120, and the like, the equivalent CN ratio in the signal Sβ after the block interleaving process is calculated (S33).

  Next, based on the comparison between the equivalent CN ratio calculated in S33 and the reference value of the CN ratio derived in advance, the control unit 130 corrects errors that are included in the effective area 312 of the block by control. The error correction unit 126 determines whether or not correction is possible (S34). When it is determined in S34 that the error included in the effective area 312 by the control is uncorrectable (S34, NO), the control unit 130 executes the processing from S36 in FIG. On the other hand, when the control unit 130 determines that an error within the effective area 312 can be corrected (S34, YES), the control unit 130 performs control within the effective area 312 of the block. . And the process from S36 of FIG. 15 is performed. Note that the determination of whether correction is possible in S34 is an error due to all of Viterbi decoding and RS decoding corresponding to the inner code and outer code, and second RS decoding performed after RS decoding corresponding to the outer code. Is determined to be correctable (corresponding to the function of the third correctability determination means).

  In S36 of FIG. 15, the control unit 130 waits until it reaches the rear end of the effective area 312 of the block (S36, NO). When it is determined that the rear end of the effective area 312 of the block has been reached (S36, YES), the control unit 130 determines whether the block is a block located at the rear end of the sub-channel area (S37). If it is determined that the block is not a block located at the rear end of the sub-channel area (S37, NO), the control unit 130 includes an error in the effective area 312 based on CRC-32 check data or the like. It is determined whether or not it is (S38). If it is determined that an error is included in the effective area 312 (S38, YES), the process of S40 is executed. On the other hand, when it is determined that no error is included in the effective area 312 (S38, NO), the control unit 130 performs a certain period in the correction block 311 (time T7 to T8 in FIG. 13B). After turning off the power of the tuner 110 (S39), the process of S40 is executed. In S40, the control unit 130 waits until it reaches the rear end of the block (S40, NO), and when it reaches the rear end of the block (S40, YES), the processing from S32 in FIG. Execute.

  If it is determined in S37 that the block is a block located at the rear end of the sub-channel area (S37, YES), the control unit 130 enters the valid area 312 based on CRC-32 check data or the like. It is determined whether an error is included (S41). If it is determined that an error is included in the effective area 312 (S41, YES), the tuner 110 is turned on at the timing after the rear end of the sub-channel area (time T10 in FIG. 13B). It is turned off (S43). And the control part 130 complete | finishes a series of steps. On the other hand, when it is determined that no error is included in the effective area 312 (S41, NO), the control unit 130 at any timing in the correction block 311 (time T9 in FIG. 13B). The power of the tuner 110 is turned off (S42). Then, a series of steps is completed.

  As described above, in this embodiment, the power supply of the tuner 110 is controlled by the correction block 311 located at the rear end of each block, and control other than the power supply control is performed in the effective area 312 in the block. Note that power control may be performed in the effective area 312. In this case, it is determined whether or not an error included in the effective area 312 can be corrected by the power control, and the power control is performed in the effective area 312 only when the error can be corrected.

  Control other than power supply control may be performed in the correction block 311. In this case, when it is determined at the rear end of the effective area 312 that the effective area 312 does not include an error based on CRC-32 check data or the like, the correction block 311 performs control other than power control. . For example, in the present embodiment, as described above, the control is performed in the effective area 312 only when the error included in the effective area 312 in the block can be corrected by the control. That is, if it is determined that the correction is not possible, the effective area 312 is not controlled.

  However, even if it is determined that correction is not possible, it is determined on the basis of CRC-32 check data or the like whether or not an error has been corrected by RS decoding corresponding to the outer code when the end of the effective area 312 is reached. May be. When it is determined that the error has been corrected, control may be performed in the correction block 311. Thus, even if it is once predicted that correction is not possible, whether or not an error is actually included at the rear end of the effective area 312 is measured to ensure necessary control other than power control. obtain.

  Further, in the present embodiment, the number of times control is performed within the range of the correction block 311 is not particularly limited. For example, power control and control other than power control may be performed once within the range of one correction block 311, or each may be performed multiple times. Alternatively, either one may be performed a plurality of times. If the correction block 311 is not used for error correction, no matter how many errors occur within the range of the correction block 311, the effective area 312 of the signal is not affected. Therefore, what kind of control is performed and how much is performed are not limited.

<Modification>
The above is a description of a preferred embodiment of the present invention. However, the present invention is not limited to the above-described embodiment, and various modifications can be made as long as the contents are described in the means for solving the problem. It can be changed.

  For example, in the above-described embodiment, it is assumed that the signal received by the digital processing device 180 adopts the OFDM method. However, unlike the OFDM system, the present invention can be applied to a transmission system in which a data value is transmitted by a single carrier wave. Further, the present invention may be applied to a signal in which a guard interval is further inserted in the OFDM system. For example, the digital processing apparatus may have a configuration in which block interleaving or the like is performed after an effective signal region from which a delayed wave is removed by the guard interval is extracted.

It is a block diagram which shows schematic structure of the digital processing apparatus which is one Embodiment of this invention. It is a figure explaining the interleaving and deinterleaving which are performed to the received signal which the digital processing apparatus of FIG. 1 receives. FIG. 2 is a block diagram illustrating a configuration of a tuner in FIG. 1. FIG. 2 is a block diagram illustrating a configuration of a demodulator in FIG. 1. It is a figure which shows the error contained in a received signal by control which the control part of FIG. 1 performs. It is a figure which shows the error which will be contained in a received signal by control different from FIG. 5 which the control part of FIG. 1 performs. It is a figure which shows the error which will be contained in a received signal by control different from FIG.5 and FIG.6 which the control part of FIG. 1 performs. It is a part of flowchart which shows a series of steps in control which the control part of FIG. 1 performs. It is a flowchart which shows a part of part other than FIG. 8 among a series of steps in control which the control part of FIG. 1 performs. 10 is a flowchart showing a part of a part other than FIGS. 8 and 9 in a series of steps in control performed by the control unit of FIG. 1. It is a flowchart which shows parts other than FIGS. 8-10 among a series of steps in control which the control part of FIG. 1 performs. It is a figure which shows the received signal which concerns on embodiment different from the received signal of FIG. It is a figure which shows the error which will be contained in a received signal by control of the control part which concerns on embodiment different from control of FIGS. 12 is a part of a flowchart showing a series of steps in control performed by a control unit according to an embodiment different from the control in FIGS. It is a flowchart which shows a part other than FIG. 14 among the series of steps in the control which the control part which concerns on embodiment different from control of FIGS.

100 demodulator 110 tuner 120 demodulator 126 error correction unit 130 control unit 180 digital processor 310 channel region 310a, 310b, 310c subchannel region 311 correction block

Claims (21)

A plurality of circuit component groups;
Receiving means for receiving a reception signal in which a plurality of blocks are connected;
Circuit control means for controlling at least one of the plurality of circuit component groups;
The circuit control means controls the circuit component group and corrects errors that are included in the respective ranges of the plurality of blocks in the received signal from the receiving means while being distributed within the range of the blocks. First error correction means to:
First correction enable / disable determining means for determining whether or not the first error correcting means can correct an error that is included in the block range by controlling the circuit component group by the circuit control means. When,
When the first correction correction determining unit determines that the first error correction unit cannot correct an error that will be included in the range of the block, at the rear end of the block determined to be uncorrectable. A digital demodulator comprising: main control means for causing the circuit control means to start controlling the circuit component group at a timing after the leading end of the next block.   When the first correction correction determination unit determines that the first error correction unit can correct an error included in the block range, the main control unit sends the circuit control unit to the circuit control unit. 2. The digital demodulator according to claim 1, wherein the component group starts to be controlled at a timing within the range of the block.   The main control unit causes the circuit control unit to control the circuit component group such that a period during which the circuit control unit controls the circuit component group straddles the boundary between two adjacent blocks. The digital demodulator according to claim 1 or 2. The first error correction means comprises:
Reordering means for reordering data included in the block range within the block range so that errors included in the block range are averagely distributed within the block range;
4. The digital according to claim 1, further comprising a post-sorting correction unit that corrects an error included in the range of the blocks rearranged by the rearranging unit. 5. Demodulator. During the period from the time when the first error correction means determines that the first error correction means cannot correct an error that will be included in the range of the block to the end of the block, It is determined again whether or not the first error correction means can correct an error that is included in the range of the block in the received signal from the reception means by the circuit control means controlling the circuit component group. And further comprising a second correction propriety determination means.
An error to be included in the block range when the second error correction determining unit determines that the first error correction unit can correct an error included in the block range. Can be corrected by the first error correction means, and the main control means sends the circuit control means to the circuit control means at any timing from when the second correction enable / disable determination means determines to the rear end of the block. 5. The digital demodulator according to claim 1, wherein control of the circuit component group is started. A part of the block is a correction block including error correction data for correcting an error included in the received signal;
2. The digital demodulator according to claim 1, wherein the first error correction unit corrects an error included in the received signal based on error correction data included in the correction block. The block consists of a series of sub-blocks,
Each data for correcting an error of data included in each of a plurality of sub-block groups composed of two or more sub-blocks separated from each other in time among the plurality of sub-blocks included in the block, Included in the error correction data of the correction block in a block,
In the case where an error is included in the sub-block group, the error included in the sub-block group based on the data corresponding to the sub-block group in the error correction data is changed to the first error correcting means. 7. The digital demodulator according to claim 6, wherein:   8. The digital demodulator according to claim 7, wherein a rear end of the block coincides with a rear end of the correction block in the block. The first error correction means further comprises an error presence / absence determination means for determining whether or not the block contains an error in the received signal immediately before correcting the error using the error correction data;
When the error existence determination means determines that the block does not contain an error in the received signal immediately before correcting the error, the circuit control means includes the circuit component group within the range of the correction block in the block. 9. The digital demodulator according to claim 6, wherein the main control unit causes the circuit control unit to control the circuit component group so that a period for controlling the circuit is controlled. The received signal includes check data for checking whether or not the block includes an error in the received signal immediately before the first error correcting unit corrects the error using the error correction data. And
Based on the check data, the error existence determination means determines whether the block contains an error in a received signal immediately before the first error correction means corrects an error using the error correction data. The digital demodulator according to claim 9, wherein the determination is made.   The first error correction means further comprises second error correction means for correcting an error contained in the received signal before correcting the error of the received signal using the error correction data. The digital demodulator according to claim 9.   An error is included in the received signal after the second error correction unit corrects the error based on a result of determination by the second error correction unit whether the error existence determination unit can correct the error. The digital demodulator according to claim 11, wherein it is determined whether or not there is any. Whether or not an error that is included in a range other than the correction block in the block by the circuit control unit controlling the circuit component group can be corrected by both the first and second error correction units. A third correction propriety judging means for judging whether or not
When the third correction availability determination unit determines that an error that is included in a range other than the correction block in the block can be corrected by both of the first and second error correction units, 13. The digital demodulator according to claim 12, wherein the main control means starts to cause the circuit control means to control the circuit component group at a timing within a range other than the correction block in the block. The received signal is divided into a plurality of channel regions including at least one channel region in which the plurality of blocks are continuous.
Each of the plurality of channel regions comprises a plurality of subchannel regions that are temporally separated from each other in the received signal,
The main control means controls the circuit component group so that the circuit control means finishes controlling the circuit component group in time before the rear end of the received signal occupying the sub-channel area in the channel area where the plurality of blocks are connected. The digital demodulator according to claim 1, wherein a control unit controls the circuit component group. The receiving means includes a tuner composed of a plurality of circuit component groups that perform channel selection processing on a received signal,
The digital demodulator according to any one of claims 1 to 14, further comprising a demodulator including a plurality of circuit component groups for performing demodulation processing on a reception signal from the tuner.   16. The main control unit controls the circuit control unit to control the group of circuit components constituting the tuner or the demodulator so that power consumption of the tuner or the demodulator is reduced. Digital demodulator. The tuner includes an RF amplifier, a mixer, a filter, an IF amplifier, and a VCO / PLL that are composed of the circuit component group.
The circuit component group controlled by the circuit control unit by the main control unit is the circuit component group constituting at least one of an RF amplifier, a mixer, a filter, an IF amplifier, and a VCO / PLL. The digital demodulator according to claim 15 or 16. A digital demodulator according to any one of claims 1 to 17, comprising:
A digital reception device that performs reproduction processing of at least one of characters, images, sounds, and data based on a reception signal demodulated by the digital demodulation device. A plurality of circuit component groups, receiving means for receiving a reception signal in which a plurality of blocks are connected, circuit control means for controlling at least one of the plurality of circuit component groups, and the circuit control means Error correction means for correcting errors that are included in the respective ranges of the plurality of blocks in the received signal from the receiving means by controlling the circuit component group while being distributed within the range of the blocks; A method for controlling a digital demodulator comprising:
A correction propriety determining step for determining whether or not the error correcting unit can correct an error that is included in the range of the block by the circuit control unit controlling the circuit component group;
The next block connected to the rear end of the block determined to be uncorrectable when it is determined in the correctability determination step that the error correction means cannot correct the error included in the block range And a main control step for causing the circuit control means to start controlling the circuit component group at a timing after the tip of the digital demodulator. A plurality of circuit component groups, receiving means for receiving a reception signal in which a plurality of blocks are connected, circuit control means for controlling at least one of the plurality of circuit component groups, and the circuit control means Error correction means for correcting errors that are included in the respective ranges of the plurality of blocks in the received signal from the receiving means by controlling the circuit component group while being distributed within the range of the blocks; A program for a digital demodulator comprising:
A correction propriety judging means for judging whether or not the error correcting means can correct an error that is included in the range of the block by the circuit control means controlling the circuit component group; and
When the error correction means determines that the error correction means cannot correct an error that is included in the range of the block, the next block connected to the rear end of the block determined to be uncorrectable is determined. A program for a digital demodulator, which causes the digital demodulator to function as a main controller that starts to cause the circuit controller to control the circuit component group at a timing after the leading edge.   A computer-readable recording medium on which the program for a digital demodulator according to claim 20 is recorded.

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