JP4541311B2 - Digital demodulator, digital receiver, digital demodulator control method, digital demodulator control program, and recording medium recording the control program - Google Patents

Description

  The present invention relates to a digital demodulation technique for demodulating a modulation signal transmitted from a digital transmission device.

  In recent years, as a digital demodulator that demodulates a modulation signal transmitted from a digital transmitter, one capable of realizing low power consumption has been proposed. For example, Patent Document 1 discloses a digital demodulator that demodulates a signal in which an invalid period (guard interval) is provided between symbol valid periods. The digital demodulator disclosed in Patent Document 1 is configured to be able to reduce the overall power consumption by turning on and off the power of each part constituting the tuner and demodulator during the invalid period. Yes.

JP 2001-251275 A

  However, in the digital demodulator of Patent Document 1, since power control is performed only during the invalid period, it is difficult to say that power consumption can be effectively reduced. On the other hand, even when power control is performed during the invalid period, such control may affect the signal beyond the invalid period, and an error may occur in the signal. In this case, there may arise a problem that information such as an image and sound cannot be accurately obtained from the demodulated signal.

  An object of the present invention is to provide a digital demodulation technique capable of acquiring more accurate data by reducing errors that occur when the operation of a tuner or a demodulator is controlled.

Means for Solving the Problems and Effects of the Invention

The digital demodulator of the present invention has a plurality of symbols including a guard interval added to be connected to the other end of the main signal, which is the same signal as the sub guard interval formed from one end of the main signal, and A digital demodulator that demodulates a received signal that has undergone interleave processing for rearranging these symbols, a tuner that performs channel selection processing on the received signal, and demodulation that performs demodulation processing on the signal from the tuner And deinterleaving means for performing deinterleaving processing on the received signal that has been subjected to the interleaving process to distribute errors contained in the received signal, and correcting errors distributed by the deinterleaving means Error correction means and at least one of a plurality of circuit components constituting the tuner and the demodulator An operation control means for controlling the operation; and a start timing determining means for determining a timing at which the operation control means starts the operation control of the circuit component, wherein the start timing determining means is the circuit component by the operation control means. The operation control start timing is determined within a period including the guard interval of a certain symbol and the sub-guard interval of another symbol connected to the guard interval, and the operation control means is included in the plurality of circuit components. Configured to control the operation of the first circuit component and the second circuit component respectively,
The start timing determining means includes a start timing of the operation control of the first circuit component and a start timing of the operation control of the second circuit component, which are occupied by errors that are generated by the operation control, respectively. Are determined so as not to overlap each other after the deinterleaving process .

  The guard interval is made up of the same signal as the sub-guard interval made up of one end of the main signal of the symbol, and is added to the other end of the main signal. That is, the guard interval and the sub guard interval, which are the same signal, are located at both ends of the symbol. Therefore, since there are a guard interval and a sub guard interval composed of the same signal at the boundary between two adjacent symbols, even if a delayed wave (multipath) occurs, the symbols before and after are less likely to overlap, and more accurately. It becomes possible to acquire data. On the other hand, an invalid period that is not used for data acquisition exists within a period composed of a guard interval and a subguard interval of one symbol.

Therefore, in the digital demodulator of the present invention, the operation control of the circuit components by the operation control means is started within a period composed of a guard interval of a certain symbol and a sub-guard interval of another symbol connected to this guard interval. In other words, since the operation control of the circuit component is started within or near the invalid period that is not used for data acquisition, the received signal (corrected by the error correction unit is corrected by the operation control of the circuit component by the operation control unit. Errors contained in the previous signal) are reduced. Further, since this error is distributed by the deinterleave means, the error correction means can easily correct the error. Accordingly, it is possible to obtain more accurate data by minimizing errors caused by the operation control of the circuit components constituting the tuner and the demodulator. In the following description, the “circuit component” is not limited to the circuit constituting each part of the tuner or the demodulator, but any unit component such as a component equivalent to one transistor constituting the circuit. It can correspond to a circuit component.
The operation control means is configured to control the operations of the first circuit component and the second circuit component included in the plurality of circuit components, respectively, and the start timing determination means is configured to control the first timing component. The start timing of the operation control of the circuit component and the start timing of the operation control of the second circuit component are not overlapped with each other after the deinterleaving process in the range occupied by the errors caused by the operation control. To be determined. According to this configuration, after the deinterleaving process, an error range that occurs due to the operation control of the first circuit component and an error range that occurs due to the operation control of the second circuit component Since they do not overlap, it becomes difficult for errors to concentrate on a part of the signal, and it becomes easier to correct errors in the error correction means.

  In addition, the start timing determining means determines the start timing of the operation control of the circuit component by the operation control means as a time between the guard interval of a certain symbol and the sub guard interval of another symbol connected to the guard interval. And the operation control means is configured to straddle the boundary between the guard interval and the sub guard interval from the start timing determined by the start timing determination means. It may be one that controls the operation of a component. According to this configuration, it is possible to lengthen the control time of the operation control of the circuit components and reduce the influence of the operation control on the acquired data.

  In addition, the demodulator includes a valid period determining unit that determines a valid period in which data is acquired from the symbol, the time length of which is equal to the time length of the main signal, Preferably, the start timing determining means determines the start timing within an invalid period that does not overlap with the valid period. According to this configuration, the influence of the operation control of the circuit component is less likely to affect the finally acquired data, so that more accurate data can be acquired.

  Further, the deinterleaving process is a time deinterleaving process for returning the arrangement of the plurality of symbols rearranged in time by the time interleaving process, and the start timing determining means includes the first circuit component of the first circuit component. The start timing of the operation control and the start timing of the operation control of the second circuit component may be determined so that the time interval between these two start timings is not less than the time interleave length. According to this configuration, the range of errors that are generated by the operation control of the first circuit component and the range of errors that are generated by the operation control of the first circuit component are after the time deinterleave processing. Therefore, the errors are less likely to concentrate in time, and the error correction means can more easily correct the errors.

  Here, the digital demodulator is configured to perform error control of the circuit component by the operation control unit, so that an error estimation unit that estimates an amount of virtual error that occurs in the received signal, and the error estimation unit From the amount of the virtual error estimated in step (1), it is determined whether or not the error correction means can correct an error that is included in the received signal by the operation control of the circuit component being performed by the operation control means. And a correction possibility determination unit. According to this configuration, it is possible to determine whether or not the error correction unit can correct an error that is included in the received signal by the operation control of the circuit component being performed by the operation control unit.

  The digital receiver of the present invention comprises pre-control error deriving means for deriving an amount of pre-control error included in a received signal before operation control of the circuit component is performed by the operation control means, and the correction propriety determination means Deriving the amount of error that will be included in the received signal from the amount of virtual error estimated by the error estimation unit and the amount of pre-control error derived by the pre-control error deriving unit It is characterized by. According to this configuration, it is possible to accurately derive the total amount of errors that are included in the received signal by controlling the operation of the circuit components from the amount of virtual errors and the amount of pre-control errors. .

  In addition, the correctability determination means includes threshold value derivation means for deriving a threshold value of the amount of error that will be included in the received signal when operation control of the circuit component is performed, and is included in the received signal. It is preferable that when the amount of error to be detected is equal to or less than the threshold value derived by the threshold value deriving unit, it is determined that the error correcting unit can correct the error. According to this configuration, it is possible to easily determine whether or not an error that is included in the received signal can be corrected.

  The threshold deriving unit may be configured to derive the threshold based on at least one of a received signal modulation scheme and a coding rate. In this configuration, an appropriate threshold value is derived according to the method adopted for the received signal.

  Here, the pre-control error deriving unit may include an error rate deriving unit for deriving an error rate of the received signal before the operation control of the circuit component is performed by the operation control unit. In this configuration, whether or not error correction is possible is determined based on the error rate of the received signal before the operation control of the circuit components is performed.

  Alternatively, the pre-control error deriving unit may include a deviation deriving unit for deriving a deviation from a specified value of the constellation of the received signal before the operation control unit performs the operation control of the circuit component. Good. In this configuration, whether error correction is possible or not is determined based on a deviation from the constellation value of the received signal before the operation control of the circuit components is performed.

  Alternatively, the pre-control error deriving unit may include a CN ratio deriving unit for deriving a CN ratio of a reception signal before the operation control of the circuit component is performed by the operation control unit. In this configuration, whether error correction is possible is determined based on the CN ratio of the received signal before the operation control of the circuit components is performed.

  The operation control means is configured to control operations of a third circuit component and a fourth circuit component included in the plurality of circuit components, respectively, and further, the operation control means includes the first circuit component. The operation of the fourth circuit component may be controlled so that the amount of errors included in the received signal is reduced by controlling the operation of the third circuit component. According to this configuration, the error that is included in the received signal by performing the operation control of the third circuit component is reduced by performing the operation control of the fourth circuit component. This makes it easier to correct errors.

  Further, the operation control means may perform operation control of the fourth circuit component prior to operation control of the third circuit component. According to this configuration, the operation control of the fourth circuit component is performed prior to the operation control of the third circuit component, so that the third circuit is reduced in a state where the amount of errors included in the received signal is reduced. Operation control of parts is performed.

  Further, when it is determined by the correctability determination means that the error correction means cannot correct an error included in the received signal by controlling the operation of the third circuit component by the operation control means. The operation control means may be configured to control the operation of the third circuit component and to control the operation of the fourth circuit component. According to this configuration, the operation control of the fourth circuit component is performed even when the error correction means cannot correct the error included in the received signal by the operation control of the third circuit component. Therefore, errors can be reduced by error correction means.

  In addition, the digital demodulator may detect an error that is included in the received signal when the correction control unit determines that the operation control of the circuit component by the operation control unit is performed for a certain amount of control. After it is determined whether or not the correction means can correct, control change means for changing at least one of the control amount and the control time of the operation control based on the determination result may be provided. According to this configuration, the control amount of the operation control is set as large as possible, or the control time is set as long as possible within the range in which an error included in the received signal can be corrected by the operation control of the circuit component. Is possible.

  In addition, the performance of the digital demodulator may be reduced when processing a symbol that causes an error due to the operation control of at least one of a plurality of circuit components constituting the demodulator. There may be provided demodulation control means for controlling the above. When one or more symbols are almost completely crushed, such as when the control time of the operation control of the circuit component is longer than the effective symbol length, correct data cannot be extracted from such symbols. In such a case, it is wasteful that the demodulator performs the same demodulation processing as a symbol having a normal signal state on a symbol that has been completely crushed. Therefore, in such a case, the power consumption of the demodulator can be reduced by controlling the operation of the circuit components constituting the demodulator so that the performance thereof is lowered by the demodulation control means.

  The start timing determination means preferably includes delay means for delaying the received signal to generate a delayed signal, and correlation derivation means for deriving a correlation between the received signal and the delayed signal. According to this configuration, since the start timing of the operation control of the circuit component is determined based on the correlation between the received signal and the delay signal, the operation control suitable for the signal state is possible.

  Here, the operation control means may control power supplied to the circuit component at a timing determined by the start timing determination means. According to this structure, the power consumption of a circuit component can be reduced effectively.

  Further, the operation control means may make the power supplied to the circuit component zero at the timing determined by the start timing determination means. According to this configuration, the power consumption of the circuit components can be further effectively reduced.

  The tuner includes an RF amplifier, a mixer, a filter, an IF amplifier, and a VCO / PLL, and the operation control means includes at least one of an RF amplifier, a mixer, a filter, an IF amplifier, and a VCO / PLL. It is also possible to control the power supplied to the circuit components constituting one. According to this configuration, it is possible to effectively reduce the power consumption of at least one of the RF amplifier, mixer, filter, IF amplifier, and VCO / PLL of the tuner.

  The demodulator includes an ADC that converts an analog signal from the tuner into a digital signal, and the operation control means controls power supplied to circuit components constituting the ADC. Also good. According to this configuration, the power consumption of the ADC of the demodulator can be effectively reduced.

According to the control method of the digital demodulator of the present invention, a plurality of symbols including a guard interval added to be connected to the other end of the main signal, which is the same signal as the sub guard interval formed from one end of the main signal. A digital demodulator comprising: a tuner that performs channel selection processing on a received signal that has undergone interleave processing for rearranging these symbols; and a demodulator that performs demodulation processing on the signal from the tuner. An apparatus control method, wherein the received signal subjected to the interleaving process is subjected to a deinterleaving process to disperse an error included in the received signal, and an error correcting step for correcting the dispersed error; An operation control step for controlling the operation of at least one of a plurality of circuit components constituting the tuner and the demodulator. Flop and, a start timing determining step of determining a timing for starting the operation control of the circuit components in the motion control step, in the start timing determining step, the start timing of the operation control of the circuit components in the motion control step Is determined within a period consisting of the guard interval of a certain symbol and the sub-guard interval of another symbol connected to the guard interval, and in the operation control step, a first circuit component included in the plurality of circuit components And in the start timing determination step, the start timing of the operation control of the first circuit component and the start timing of the operation control of the second circuit component are It will be generated by motion control respectively. Range occupied by Ri is characterized in that to determine so as not to overlap each other after the de-interleaving processing.

According to the control method of the digital demodulator, the operation control of the circuit component is started within a period including a guard interval of a symbol and a sub-guard interval of another symbol that is connected to the guard interval. By performing the operation control, errors that occur in the received signal are reduced. Further, since this error is distributed by the deinterleave process, it becomes easier to correct the error in the error correction step. Accordingly, it is possible to obtain more accurate data by minimizing errors caused by the operation control of the circuit components constituting the tuner and the demodulator.
In the operation control step, the operations of the first circuit component and the second circuit component included in the plurality of circuit components are respectively controlled. In the start timing determination step, the operation control of the first circuit component is performed. And the start timing of the operation control of the second circuit component are determined so that the ranges occupied by errors caused by the operation control do not overlap each other after the deinterleaving process. According to this, the error range that occurs due to the operation control of the first circuit component and the error range that occurs due to the operation control of the second circuit component overlap after the deinterleaving process. Therefore, it is difficult for errors to concentrate on a part of the signal, and it becomes easier to correct errors in the error correction step.

According to the control program of the digital demodulator of the present invention, a plurality of symbols including a guard interval added to be connected to the other end of the main signal are the same signal as the sub guard interval formed from one end of the main signal. A digital demodulator comprising: a tuner that performs channel selection processing on a received signal that has undergone interleave processing for rearranging these symbols; and a demodulator that performs demodulation processing on the signal from the tuner. An apparatus control program, which performs a deinterleaving process on the received signal subjected to the interleaving process to disperse errors contained in the received signal and corrects the dispersed errors, Control operation of at least one of a plurality of circuit components constituting the tuner and the demodulator. A work control step, and a start timing determining step of determining a timing for starting the operation control of the circuit components in the motion control step, in the start timing determining step, the operation control of the circuit components in the motion control step A start timing is determined within a period including the guard interval of a symbol and the sub-guard interval of another symbol connected to the guard interval. In the operation control step, a first timing included in the plurality of circuit components is determined. Controlling the operation of each of the circuit component and the second circuit component, and in the start timing determining step, the start timing of the operation control of the first circuit component and the start timing of the operation control of the second circuit component, Generated by their motion control Range occupied by become erroneous it is characterized in that to determine so as not to overlap each other after the de-interleaving processing.

According to the control program of this digital demodulator, since the operation control of the circuit component is started within a period including a guard interval of a certain symbol and a sub-guard interval of another symbol connected to the guard interval, By performing the operation control, errors that occur in the received signal are reduced. Further, since this error is distributed by the deinterleave process, it becomes easier to correct the error in the error correction step. Accordingly, it is possible to obtain more accurate data by minimizing errors caused by the operation control of the circuit components constituting the tuner and the demodulator.
In the operation control step, the operations of the first circuit component and the second circuit component included in the plurality of circuit components are respectively controlled. In the start timing determination step, the operation control of the first circuit component is performed. And the start timing of the operation control of the second circuit component are determined so that the ranges occupied by errors caused by the operation control do not overlap each other after the deinterleaving process. According to this, the error range that occurs due to the operation control of the first circuit component and the error range that occurs due to the operation control of the second circuit component overlap after the deinterleaving process. Therefore, it is difficult for errors to concentrate on a part of the signal, and it becomes easier to correct errors in the error correction step.

  The recording medium of the present invention is characterized in that the control program for the digital demodulator described above is recorded. According to the recording medium in which the control program is recorded, it is possible to obtain more accurate data by minimizing errors caused by controlling the operation of the circuit components constituting the tuner and the demodulator.

  Embodiments of the present invention will be described with reference to the drawings. The digital demodulator 1 according to the present embodiment is provided in, for example, a mobile phone 201 (digital receiver) as shown in FIG. Then, the signal Sr received from the antenna by the mobile phone 201 is demodulated by the digital demodulator 1, and data such as characters, images, sounds, or programs is reproduced from the demodulated signal, and these information are stored in the mobile phone. It is provided to the user through a display or speaker (not shown) provided in 201. In this embodiment, the digital demodulator 1 for a mobile phone will be described as an example, but a digital receiver other than a mobile phone, for example, a digital TV, a wireless LAN device, a PC equipped with a wireless LAN, or the like It may be used for.

  Next, the signal Sr (received signal) received by the antenna of the mobile phone 201 and demodulated by the digital demodulator 1 will be described briefly. Here, a case where a system related to terrestrial digital broadcasting in Japan, that is, an ISDB-T (Integrated Services Digital Broadcasting-Terrestrial) system is adopted will be described as an example.

  First, character, image, and sound data to be transmitted is digitized based on a predetermined method. Furthermore, the digitized data is encoded so that errors generated by noise and interference waves generated in the transmission path can be corrected on the receiving side. As such a code, a Reed-Solomon code (RS code) and a convolutional code (Viterbi code) are used. In the RS code used in terrestrial digital broadcasting, the last 16 bytes of the transmitted 204 bytes of data are check bits, and an error of up to 8 bytes in 204 bytes can be corrected. In the Viterbi code, with respect to n bits to be transmitted after encoding, the encoding rate when the data before encoding is k bits is k / n, and 1/2 to 7/8 is standardized. Has been. Then, in the digital demodulator 1 on the receiving side, RS decoding and Viterbi decoding are performed to restore the RS encoded and Viterbi encoded data, respectively, thereby correcting errors generated during transmission.

  By the way, depending on the state of the transmission path, there may occur a burst error in which errors are continuously concentrated on a transmission signal in terms of time or frequency. Then, when correcting an error generated in a signal of a certain length by error correction of RS encoding as described above, there is a limit to the number of errors that can be corrected per signal of this length. If a burst error occurs, the error may not be corrected. In Viterbi coding, if there are concentrated errors, erroneous coding correction is performed, and errors may increase. Therefore, in the ISDB-T system, various kinds of data transmitted on the transmission side are rearranged in time or frequency so that error correction is possible even when a burst error occurs in the transmission signal. Interleave processing is performed. Then, by performing deinterleaving processing for restoring the data sequence on the receiving side, burst errors generated during transmission are discretely distributed (see FIG. 7). Such interleaving processing and deinterleaving processing will be described in detail later.

  Furthermore, energy diffusion is also performed in order to prevent energy deviation of the transmission signal due to data deviation. This energy diffusion is performed by randomizing data by taking a bitwise exclusive OR of pseudo-random data and data related to a transmission signal.

  Data is transmitted after the various processes as described above are performed. As an ISDB-T transmission method, an OFDM (Orthogonal Frequency Division Multiplexing) method is adopted. This OFDM method is one type of multi-carrier method in which a plurality of carrier waves having different frequencies are used for carrying data.

  First, according to the arrangement order of a plurality of data values included in transmission data, each data value is distributed to a carrier wave having a different frequency. Next, an inverse Fourier transform is performed on the data value sequence distributed to a plurality of carriers having different frequencies, so that the plurality of carriers are overlapped to form an OFDM signal. Here, the waveforms of the carrier waves used in the OFDM method are orthogonal to each other so that the carrier waves do not interfere with each other. “Two waveforms are orthogonal” means that a function (inner product) obtained by multiplying each function representing the amplitude of a wave with respect to time and performing time integration in an integration range corresponding to one period becomes zero. .

  Furthermore, in order to reduce the influence of delay waves other than the direct wave, a guard interval is further inserted in the OFDM signal in which a plurality of modulated carriers are superimposed. This guard interval is a signal (main signal) obtained by performing inverse Fourier transform on a data value sequence distributed to a plurality of carrier waves having different frequencies, and the same signal portion as one end portion (sub guard interval) of this main signal. It is added so as to be connected to the other end of the main signal. The effective symbol length is the time length of one symbol in which one data is carried on a carrier wave, and corresponds to the reciprocal of the frequency interval of the carrier wave used in the OFDM system. The symbol length is a length obtained by adding the effective symbol length and the guard interval section, and one symbol is composed of an effective symbol and a guard interval. An OFDM signal is composed of a plurality of such symbols in time.

  As shown in FIG. 2, among one symbol Sb (symbol length Ts) of the OFDM signal 50, the signal portion (sub-guard interval 54) at one end (rear end) of the main signal having the effective symbol length Te and the other The signal portion (guard interval 53) at the end portion (front end portion) is a signal having a length Tg having the same waveform. That is, the guard interval 53 and the sub guard interval 54 made of the same signal are located at both ends of the symbol Sb.

  As will be described later, when data is acquired from the symbol Sb in the digital demodulator 1, an effective period (an FFT window described later) of an effective symbol length Te is set within the period of the symbol Sb, and a signal in this period is set. Is subjected to Fourier transform. However, the Fourier transform may use a fast Fourier transform (FFT) for speeding up. At that time, even in a state where a delayed wave (multipath) is generated, an FFT window whose time length is Te is set to one symbol (symbol length Ts) according to the signal state so that the preceding and following symbols do not overlap. ), The data can be accurately acquired. Contrary to the above configuration, the signal portion at the front end portion of the main signal may be added as a guard interval continuous to the rear end of the main signal. Then, the OFDM signal with the guard interval added in this way is transmitted to the transmission path.

  The case where the received signal Sr is a signal transmitted by the ISDB-T method has been described above. However, if the received signal Sr is a signal to which the guard interval as described above is added, the signal is transmitted by another method. Also good. Therefore, in addition to this ISDB-T system, for example, European DAB (Digital Audio Broadcasting), DVB-T (Digital Video Broadcasting-Terrestrial), DVB-H (-Handheld) system, DMB (Digital Multimedia Broadcasting) system, wireless It may be a signal transmitted by the IEEE802.11a / b / g / n method used for the LAN.

  Next, the digital demodulator 1 that demodulates the received signal Sr received by the antenna will be described in detail. As shown in FIG. 3, the digital demodulator 1 includes a tuner 2, a demodulator 3, and a control unit 4. The tuner 2 receives the received signal Sr from the antenna of the mobile phone 201 (see FIG. 1), amplifies the signal Sr, and converts the signal Sr into an IF (Intermediate Frequency) signal Si to demodulate the demodulator. Send to 3. The demodulator 3 receives the IF signal Si transmitted from the tuner 2, and generates a demodulated signal, for example, a TS (Transport Stream) signal from the IF signal Si. The control unit 4 controls the operations of the tuner 2 and the demodulator 3.

  First, the tuner 2 will be described. As shown in FIG. 4, the tuner 2 includes an RF amplifier unit 21, a mixer unit 22, a VCO / PLL unit 23, a filter unit 24, an IF amplifier unit 25, and a tuner control unit 26. The signal Sr input to the tuner 2 is amplified by the RF amplifier unit 21 and sent to the mixer unit 22. The VCO / PLL unit 23 generates a mixing signal based on a frequency corresponding to a specific channel in accordance with the channel control signal sent from the control unit 4.

  The mixing signal is sent to the mixer unit 22 where the signal Sr and the mixing signal are mixed. Further, in the filter unit 24, signal components having unnecessary frequencies are removed from the mixed signal, and an IF signal Si corresponding to the selected channel is generated (channel selection process). Further, the IF signal Si is amplified by the IF amplifier unit 25 and sent to the demodulator 3.

  As shown in FIG. 4, the tuner 2 further includes a tuner control unit 26. The tuner control unit 26 (operation control unit) receives the command from the control unit 4 and configures the RF amplifier unit 21, the mixer unit 22, the VCO / PLL unit 23, the filter unit 24, and the IF amplifier unit 25 described above. The operations of the plurality of circuit components are controlled. Here, the tuner control unit 26 may be a component made up of a circuit specialized to perform its control function, or may include a general-purpose CPU, ROM, RAM, etc., and a program recorded in the ROM. May be configured to perform its control function by being executed by the CPU.

  Next, the demodulator 3 will be described. As shown in FIG. 5, the demodulator 3 includes a demodulation unit 40 that performs demodulation processing on the IF signal Si from the tuner 2, and a demodulation control unit 41 that controls each unit of the demodulation unit 40.

  First, the demodulator 40 will be described. As shown in FIG. 6, the demodulation unit 40 includes an ADC unit 31, an AFC / symbol synchronization unit 32, an FFT unit 33, a frame synchronization unit 34, a detection unit 35, a waveform equalization unit 37, and an error correction unit 36. The demodulator 40 performs demodulation processing and error correction processing on the IF signal Si sent from the tuner 2.

  The IF signal Si transmitted from the tuner 2 is first input to the ADC unit 31. The ADC unit 31 converts the IF signal Si, which is an analog signal, into a digital signal, and sends the converted digital signal to the AFC / symbol synchronization unit 32. The AFC / symbol synchronization unit 32 performs correction processing such as filtering on the digital signal sent from the ADC unit 31. Further, the AFC / symbol synchronization unit 32 determines a starting point of Fourier transform by the FFT unit 33 described later, that is, a symbol synchronization point. Then, the AFC / symbol synchronization unit 32 sends the synchronized digital signal to the FFT unit 33. Furthermore, information related to the mode indicating the effective symbol length is derived, and information related to this mode is sent to the control unit 4. Here, the modes indicating the effective symbol length include mode 1 (effective symbol length 252 μs), mode 2 (effective symbol length 504 μs), and mode 3 (effective symbol length 1008 μs).

  Note that a period (effective period) in which the FFT unit 33 performs Fourier transform to extract data from the digital signal and has a time length of the effective symbol length Te is referred to as an FFT window. That is, the determination of the symbol synchronization point by the AFC / symbol synchronization unit 32 corresponds to specifying the position of the FFT window in each symbol (effective period determination means).

  In the determination of the symbol synchronization point, a point at which optimum reception with the least influence of the delayed wave and the like that arrives after delay is set as the synchronization point. As a method of determining such a synchronization point, a method of referring to signal correlation, a method of correcting a phase shift using a pilot signal, or the like is used.

  An FFT (Fast Fourier Transform) unit 33 performs a Fourier (time-frequency) transform on the digital signal sent from the AFC / symbol synchronization unit 32. Since the digital signal input to the FFT unit 33 is an OFDM signal, it has an inverse Fourier transformed waveform, that is, a waveform in which a plurality of carriers modulated in accordance with data values are superimposed. Then, the FFT unit 33 takes out digital signals of a plurality of carrier waves modulated in accordance with the data values from the superimposed waveforms by Fourier transform. Further, the FFT unit 33 rearranges the digital signals corresponding to the respective data values distributed to the respective carrier waves so as to be temporally aligned in the original arrangement order of the data, and the digital corresponding to the data before the OFDM signal formation. Play the signal. Then, the FFT unit 33 sends this digital signal to the frame synchronization unit 34.

  The frame synchronization unit 34 synchronizes the digital signal sent from the FFT unit 33 in units of frames. One frame is composed of 204 symbols, and as described later, one group of TMCC information is acquired from the signal of this one frame. The digital signal synchronized by the frame synchronization unit 34 is sent to the waveform equalization unit 37 and simultaneously sent to the detection unit 35.

  The waveform equalizer 37 performs waveform equalization on the digital signal synchronized by the frame synchronizer 34 based on the scattered pilot signal included in the digital signal. Then, after performing signal correction by waveform equalization, the digital signal corresponding to the data value is demodulated, and the demodulated digital signal is sent to the error correction unit 36. Further, the waveform equalization unit 37 derives a deviation from the specified value of the constellation of each carrier wave based on a scattered pilot signal or the like included in the digital signal subjected to waveform equalization (deviation derivation means). Then, information relating to the MER (Modulation Error Ratio) or CN ratio of the received signal is extracted from the deviation from the specified value of the derived constellation and sent to the control unit 4.

  On the other hand, the detection unit 35 extracts TMCC information included for each signal of one frame, and sends information related to the TMCC to the demodulation control unit 41 and the control unit 4. TMCC information includes carrier modulation schemes such as 64QAM, 16QAM, and QPSK, convolutional coding rates (1/2, 2/3, 3/4, 5/6, 7/8), guard interval length, and other transmission schemes. Such information is included. As the guard interval length, any one of 1/4, 1/8, 1/16 and 1/32 of the effective symbol is employed.

  The error correction unit 36 (error correction unit) includes deinterleave units 43, 44, 45, and 47 (deinterleave unit) that perform deinterleave processing on the digital signal from the waveform equalization unit 37, and error correction of the encoded digital signal. And decoding units 46 and 49 for decoding the digital signal, and an energy despreading unit 48.

  The deinterleaving unit performs frequency deinterleaving, time deinterleaving, bit deinterleaving, and byte deinterleaving corresponding to various interleaving processes performed on the transmission side, respectively, a frequency deinterleaving unit 43, and time deinterleaving. Section 44, bit deinterleave section 45, and byte deinterleave section 47. Then, the digital signal subjected to various interleaving processes is returned to the digital signal before the interleaving process by these deinterleaving processes.

  Here, a supplementary description will be given of the interleaving process on the transmission side and the deinterleaving process by the deinterleaving unit on the reception side. For example, time interleaving on the transmitting side and time deinterleaving on the receiving side for returning the data subjected to the time interleaving to the original are performed as follows. FIG. 7 is a schematic diagram illustrating an example of time interleaving and time deinterleaving. In FIG. 7, three signals Si before and after the interleaving and deinterleaving processing are shown. Each of these signals Si is composed of a plurality of symbols Sb that are continuous in time.

  The modulated OFDM signal Si composed of a plurality of carriers is rearranged as shown in FIG. 7 according to a predetermined order for each data corresponding to the length of the symbol Sb by time interleaving on the transmission side. It is assumed that when a signal corresponding to the rearranged data is transmitted, a continuous burst error 101 occurs in a part of the signal depending on the state of the transmission path.

  When the signal Si including the burst error 101 is received by the mobile phone 201, the data once rearranged in time by time interleaving is restored to the original order by time deinterleaving. At this time, the burst error 101 generated across a plurality of symbols in the transmission path is dispersed like the error 102 for each symbol by time deinterleaving.

  That is, as shown in FIG. 7, rearrangement is performed so that each symbol Sb moves to a position after the temporal position before time interleaving by time interleaving. In addition, signals included in carriers having different frequencies in each symbol Sb are included in different temporal positions in the rearranged signals. As described above, even when a burst error in which errors are concentrated in time occurs, the error is distributed after time deinterleaving on the demodulation side, so that error correction can be performed by decoding processing in the decoding unit.

  In byte interleaving on the transmission side, rearrangement of signals in units of bytes is performed so that data is dispersed in units of 204-byte RS encoding. In bit interleaving, signals are rearranged in bit units. Further, in frequency interleaving, symbols are rearranged between a plurality of carriers included in the OFDM signal Si. Then, the data is returned to the data before interleaving by byte deinterleaving, bit deinterleaving, and frequency deinterleaving on the receiving side.

There are a Viterbi decoding unit 46 and an RS decoding unit 49 as decoding units for decoding the digital signal sent from the waveform equalizing unit 37. The digital signal that has been subjected to Viterbi coding and RS coding on the transmission side is subjected to the digital signal before being encoded by the Viterbi decoding unit 46 and the RS decoding unit 49 after the error is dispersed by the deinterleaving process described above. By returning to, errors that occurred during transmission are corrected. In the present embodiment, “error correction is possible” refers to a case where the bit error rate after decoding is a predetermined value or less. For example, a case where the bit error rate after RS decoding is 1 × 10 ⁻¹¹ or less is a case where error correction by RS decoding and Viterbi decoding is possible.

  By the way, the reliability of each data of the data string input to the Viterbi decoding unit 46 is set based on the reception status such as the magnitude of the input signal, and the Viterbi decoding unit 46 is based on this reliability. It is configured to change the error correction performance. Since the Viterbi coding method is a method of performing coding from the history of preceding data, in the Viterbi decoding unit 46 that decodes the Viterbi-coded signal, the traceback length (the number of data to be referred back to the past). The longer the), the higher the error correction performance. Therefore, the Viterbi decoding unit 46 may be configured to change its error correction performance by changing the traceback length based on reliability.

  The energy despreading unit 48 returns the digital signal sent from the waveform equalizing unit 37 to the digital signal before being energy spread.

  The error correction unit 36 derives a bit error rate of the digital signal based on the number of corrected errors (error rate deriving unit), and sends the derived bit error rate to the control unit 4. This bit error rate may be a ratio of the number of bits corrected by Viterbi decoding and RS decoding to the number of bits of the signal immediately after the bit deinterleaving process is performed. Alternatively, it may be the ratio of the number of bits corrected by RS decoding to the number of bits of the signal immediately after the byte deinterleaving process is performed.

  The various deinterleaving, decoding, and energy despreading described above are performed in reverse order corresponding to the order of various interleaving, encoding, and energy spreading performed on the transmission side. That is, as shown in FIG. 6, frequency deinterleaving, time deinterleaving, bit deinterleaving, Viterbi decoding, byte deinterleaving, energy despreading, and RS decoding are performed in this order.

  Next, the demodulation control unit 41 will be described. The demodulation control unit 41 (operation control means) receives an instruction from the control unit 4 and controls the operation of a plurality of circuit components constituting each unit of the demodulation unit 40 such as the ADC unit 31 and the FFT unit 33 described above. . Here, the demodulation control unit 41 may be a component composed of a circuit specialized to perform its control function, or may be a program recorded in the ROM, including a general-purpose CPU, ROM, RAM, and the like. May be configured to perform its control function by being executed by the CPU.

  Next, the control unit 4 will be described. The control unit 4 includes a CPU, a ROM, a RAM, and the like, and is configured to perform various controls related to the operation of each unit of the tuner 2 and the demodulator 3 by causing the CPU to execute various programs recorded in the ROM. Has been. That is, the control unit 4 outputs a control signal to the tuner control unit 26 and the demodulation control unit 41 and controls the operation of the circuit components constituting the tuner 2 and the demodulator 3. For example, the control unit 4 uses the tuner control unit 26 and the demodulation control unit 41 to perform the RF amplifier unit 21, the mixer unit 22, the VCO / PLL unit 23, the filter unit 24, the IF amplifier unit 25, and the ADC of the demodulator 3. The power supplied to the circuit components constituting the unit 31 is reduced for a certain period, or the power supplied is made zero.

<Operation control of circuit components>
By the way, when the operation control of the circuit components as described above is performed by the tuner control unit 26 or the demodulation control unit 41, an error may occur in the signal Si. FIG. 8 is a timing chart showing the influence of the power control on the signal Si when the power supplied to a certain circuit component is controlled as an example of the operation control of the circuit component. In the following description, it is assumed that the signal reception state is stable, and errors other than errors generated by power control are always constant unless otherwise specified.

  In FIG. 8, a diagram 70 shows the power supplied to the circuit component to be controlled. A diagram 71 shows the amount of errors included in the signal Si. When the power supplied to the circuit component is reduced by a certain control power amount ΔP for a certain time T, an error 74a occurs in the signal Si due to this power reduction. In FIG. 8, it is assumed that an error 74a caused by power control is within one symbol 73 of symbols Sb included in signal Si.

  By the way, errors included in one symbol 73 of the signal Si are distributed by various deinterleaving processes. For example, as shown in FIG. 8, the error included in the symbol 73 is dispersed in the range of the time interleave length Li by the time deinterleave process. Therefore, the error 74a generated due to the power control by the control unit 4 becomes an error 74b dispersed in the time interleave length Li by the time deinterleave processing, as indicated by the one-dot chain line arrow in FIG.

  However, depending on the timing at which the power control is started, the length of time T during which the power control is performed, or the control power amount ΔP, the error 74a caused by the power control is dispersed by the time deinterleaving process. However, the distributed error 74 b may exceed a threshold that can be corrected by the error correction unit 36. In such a case, the error 74b cannot be completely corrected by the error correction unit 36, and a part of the error 74b remains in the signal Si, so that the reliability of finally acquired data is lowered.

  Therefore, the digital demodulator 1 according to the present embodiment performs operation control start timing, operation control control amount (supplied power, etc.) so that errors occurring in the signal Si are minimized by performing operation control of circuit components. The operation parameter change amount) and the control time can be appropriately determined.

<Determination of operation control start timing>
As shown in FIG. 9, the control unit 4 includes a start timing determination unit 80 (start timing determination means) that determines the start timing of the operation control of the circuit components.

  The start timing determination unit 80 first determines a symbol to be handled by a circuit component when the operation control of the circuit component is performed among a plurality of symbols connected in time.

  As shown in FIG. 8, the error 74a generated within the range of a certain symbol 73 reaches the signal Si over the range of the time interleave length Li after time deinterleaving. Therefore, for example, when controlling two or more circuit components (first circuit component and second circuit component), if errors caused by such multiple times of operation control are overlapped, the error is signal Si. There is a possibility that the error correction unit 36 cannot correct the error. Therefore, in order to make it easy for the error correction unit 36 to correct the error so that the ranges occupied by the errors generated by the plurality of operation controls do not overlap each other after the time deinterleaving process, the start timing determination unit 80 Symbols handled by the circuit components are determined at the time of the operation control so that the operation control is performed a plurality of times with a time interval equal to or longer than the time interleave length Li. In this configuration, the operation of the same circuit component is controlled a plurality of times with a certain time interval (when the first circuit component and the second circuit component are the same), or a plurality of two or more circuits. The present invention can be applied to any case where the operation of each component is controlled separately (when the first circuit component and the second circuit component are different).

  Next, the start timing determination unit 80 further determines at which timing operation control is to be started within the period of each symbol determined as described above. This will be described in detail below.

  As described above, the received signal Sr input to the tuner is an OFDM signal obtained by adding a guard interval to the main signal having an effective symbol length. As shown in FIG. 10, two symbols Sba and Sbb that are temporally connected have guard intervals 53a and 53b, and sub-guard intervals 54a and 54b each having the same signal portion as the guard intervals 53a and 53b. .

  Here, the symbol synchronization point 69 determined by the AFC / symbol synchronization unit 32 of the demodulator 3 and serving as the starting point of the Fourier transform by the FFT unit 33 is located within the guard intervals 53a and 53b. In the OFDM signal 50, the signal in the period 55 having a time length of the effective symbol length Te from the symbol synchronization point 69 is subjected to Fourier transform by the FFT unit 33, and a signal corresponding to the original data is extracted. It is. If the signal Sr input to the tuner 2 contains a small amount of noise, or if the change in signal state is small, such as when there is little change in the time even if noise is included, the symbol synchronization point 69. Are fixed at approximately the same position. On the other hand, when the state of the signal 50 changes frequently, such as when noise occurs irregularly, the position of the symbol synchronization point 69 changes. A signal in the period 55 having a time length from the symbol synchronization point 69 to the effective symbol length Te is called an FFT window.

  In FIG. 10, the period 65 located between the FFT windows 55 of the two symbols Sba and Sbb has the same time length as the subguard intervals 54a and 54b. The period 65 is an invalid period that is not used to acquire transmitted data. Therefore, when the operation control of the circuit components constituting the tuner 2 and the demodulator 3 is performed in or near the period 65, the data acquired after the FFT is less affected by the operation control ( Are less prone to errors). Therefore, the start timing determination unit 80 determines the start timing 75 of the operation control of the circuit components within a period including the sub guard interval 54a of the symbol Sba and the guard interval 53b of the symbol Sbb connected to the sub guard interval 54a. Here, the start timing determination unit 80 operates within the invalid period 65 that does not overlap with the FFT window 55 that is the valid period in order to further reduce the influence of the operation control of the circuit components on the data acquired after the FFT. It is preferable to determine the control start timing 75.

  Further, as shown in FIG. 10, the start timing 75 is determined within the sub-guard interval 54, and the control period of the operation control of the circuit components is set so as to cross the boundary between the sub-guard interval 54 and the guard interval 53. It is preferable. In this case, the control time for the operation control of the circuit components is lengthened, and the influence exerted on the data acquired after the FFT by this operation control is further reduced.

  A diagram 61 in FIG. 10 shows a change in the supplied power when the supplied power to the circuit component is controlled as an example of the operation control of the circuit component. Here, in the period 65 that does not overlap with the FFT window 55, the tuner control unit 26 and the demodulation control unit 41 reduce the power supplied to the circuit components constituting the tuner 2 and the demodulator 3. Alternatively, the power supplied to the circuit components is made zero. As a result, it is possible to reduce the error generated in the signal by the power control while reducing the power consumption of the digital demodulator 1.

  Further, as shown in a diagram 62 of FIG. 10, if the setting of the symbol synchronization point 69 (FFT window 55) is devised, a period 65 that does not overlap with the FFT window 55 can be set to a sub guard interval 54a of the symbol Sba at the maximum. It is possible to extend the entire period having a time length twice as long as the guard interval, which is composed of the guard interval 53b of the symbol Sbb. Then, by making the power control start timing 75 as close as possible to the rear end of the FFT window 55 of the preceding symbol Sb, the control time of the power control is further extended, and errors caused in the signal by the power control are suppressed to a small level. Is possible.

  By the way, when the change of the signal state is small and the position of the symbol synchronization point determined by the AFC / symbol synchronization unit 32 hardly changes, the start timing determination unit 80 is sent from the AFC / symbol synchronization unit 32. Based on the information related to the past symbol synchronization point, the operation control start timing is determined within a period 65 that does not overlap the FFT window 55.

  On the other hand, when the signal state changes greatly and the optimum symbol synchronization point changes frequently, the operation control start timing and the actual control timing are determined by determining the operation control timing based on the information related to the past symbol synchronization point. The symbol synchronization point is shifted. When such a timing shift occurs, operation control is performed at a timing at which the tuner 2 handles the FFT window 55, and an error in the signal Si increases due to the operation control. Therefore, as shown in FIG. 9, the control unit 4 includes a symbol synchronization extraction unit 81 that extracts a symbol synchronization point separately from the AFC / symbol synchronization unit 32 of the demodulator 3.

  The symbol synchronization extraction unit 81 receives the IF signal Si from the IF amplifier unit (see FIG. 4), and based on the IF signal Si, the influence of the delayed wave that arrives with delay with respect to the reception signal Sr is eliminated. A symbol synchronization point capable of optimal reception is extracted independently of the AFC / symbol synchronization unit 32 of the demodulator 3. Then, the start timing determination unit 80 selects the symbol synchronization point sent from the AFC / symbol synchronization unit 32 and the symbol synchronization point extracted by the symbol synchronization extraction unit 81 based on whether or not the signal state is stable. The operation control start timing is determined based on the information related to the selected symbol synchronization point.

  As described above, when the change in the signal state is large, the start timing determination unit 80 performs symbol synchronization instead of the information related to the past symbol synchronization point transmitted from the AFC / symbol synchronization unit 32 on the demodulator 3 side. Since the start timing is determined using the information related to the symbol synchronization point extracted by the extraction unit 81, a time lag is unlikely to occur between the symbol synchronization timing and the operation control timing.

  As a symbol synchronization extraction method, for example, a method of extracting symbol synchronization based on the correlation between the IF signal Si and a delayed signal obtained by delaying the IF signal Si can be employed. A specific configuration for that purpose will be described below.

  The symbol synchronization extraction unit 81 acquires mode information sent from the demodulator 3 and information related to the guard interval length included in the TMCC information when extracting the symbol synchronization point. This TMCC information is sent from the detection unit 35 of the demodulator 3 to the symbol synchronization extraction unit 81. As illustrated in FIG. 11, the symbol synchronization extraction unit 81 includes an input unit 90, a delay unit 91, a correlation calculation unit 92, and a synchronization information generation unit 93.

  The input unit 90 receives the IF signal Si sent from the IF amplifier unit 25, and further sends the IF signal Si to the delay unit 91 and the correlation calculation unit 92. The delay unit 91 (delay means) receives the mode information sent from the demodulator 3 in advance, and the delay unit 91 delays the time by the effective symbol length based on the mode information, while the input unit 90 The IF signal Si sent from is sequentially sent to the correlation calculation unit 92.

  Alternatively, effective symbol length information may be extracted from the mode information by the demodulator 3, and the effective symbol length information may be transmitted to the symbol synchronization extraction unit 81. In this case, the delay unit 91 delays the IF signal Si in terms of time by the effective symbol length based on the transmitted information.

  The correlation calculation unit 92 calculates a correlation value between the IF signal Si sent directly from the input unit 90 and the IF signal Si (delayed signal) sent after being delayed by the delay unit 91. Instead of the correlation value, a value calculated by a calculation method similar to correlation, such as adding two sent IF signals Si to obtain an absolute value, may be used. The synchronization information generation unit 93 derives a symbol synchronization point based on the correlation value calculated by the correlation calculation unit 92.

  The above-described correlation calculation by the correlation calculation unit 92 and symbol synchronization point extraction by the synchronization information generation unit 93 will be described in more detail with reference to FIG.

  FIG. 12A shows the correlation value of the signal 50 that is not affected by a delayed wave that arrives after being delayed. As described above, the correlation value is calculated between the signal 50 and the delayed signal delayed from the signal 50 by the effective symbol length. For example, in FIG. 12 (a), the correlation value at time t3 is calculated from the signal at time t3 and the signal at time t1 that is backed by the effective symbol length from time t3. That is, the correlation value at time t3 is calculated from the guard interval 53 and the sub guard interval 54 in the same symbol. Here, since the guard interval 53 and the sub guard interval 54 are the same signal, the correlation value at time t3 is a high value. On the other hand, the correlation value at time t4 is a low value because it is calculated from the signal at time t4 and the signal at time t2 in the previous symbol. Therefore, the temporal position of the subguard interval 54 can be derived from the correlation value calculated in this way.

  On the other hand, FIG. 12B shows a correlation value when there is a delayed wave 150 that arrives with a delay. In this case, the IF signal Si is a signal in which the transmitted original signal 50 and the delayed wave 150 are superimposed. In FIG. 12A in which there is no influence of the delayed wave, the correlation value in the guard interval 54 always showed a high value. However, in FIG. Because the signals belonging to the symbols overlap, a period 95 showing a partially low correlation value occurs in the subguard interval 54. In other words, in order to extract a signal in which the previous symbol does not overlap, a signal after time 169 that is later in time by the length of the period 95 from the front end of the guard interval 53 in the transmitted original signal. Extraction will be sufficient. Therefore, the symbol synchronization point becomes time 169, and the synchronization information generation unit 93 generates symbol synchronization information with the time 169 as the symbol synchronization point.

  As described above, when extracting the synchronization point based on the correlation value, it may be determined whether or not the correlation value exceeds a predetermined threshold value, and the symbol synchronization point may be extracted based on the determination result. Further, assuming that the received signal Sr is in a fading state, the correlation values before and after the effective symbol length may be calculated and the averaged correlation value may be employed. Further, when it is determined that the IF signal Si as a whole shows a low correlation value by a method such as evaluating the average of past correlation values, the signal state such as setting the threshold value of the correlation value low. The threshold value may be changed according to the above.

<Correctability determination and control amount and control time change>
As described above, the operation control of the circuit components by the tuner control unit 26 and the demodulation control unit 41 starts within a period (preferably, the invalid period 65 shown in FIG. 10) including the sub-guard interval and the guard interval connected thereto. As a result, the amount of error generated in the signal Si by the operation control is reduced. However, this error is not always suppressed to 0, and it depends to some extent on the control amount of operation control (that is, the amount of change of various parameters related to the operation of circuit components) and the control time (time at which the parameter is changed). Errors can occur.

  For example, in order to effectively reduce the power consumption of the digital demodulator 1, it is preferable to reduce the power supplied to the circuit components as much as possible at the same time and perform this power reduction control as long as possible. However, in FIG. 10, the end timing of the power control started within the invalid period 65 of a certain symbol is set to a period overlapping with the FFT window 55 of the symbol, and the power control of the circuit component is performed up to the FFT window 55. In some cases, data obtained by FFT is affected. That is, by performing this power control, the amount of errors that occur in the signal Si increases, and there is a possibility that accurate data cannot be acquired. In other words, it is preferable that the control amount and the control time of the power control are appropriately set within a range in which the error correction unit 36 can correct the amount of error generated in the signal Si by performing the power control.

  Therefore, the digital demodulator 1 according to the present embodiment determines whether or not an error included in the signal Si can be corrected by the error correction unit 36 by performing the operation control of the circuit components, and further determines the determination. Based on the result, the control amount and control time of the operation control are changed. The configuration will be described in detail below.

  As shown in FIG. 9, the control unit 4 includes an error estimation unit 82, a correctability determination unit 83, and a control change unit 84 in addition to the above-described start timing determination unit 80 and the like.

  The error estimation unit 82 (error estimation means) controls the operation of a circuit component by changing a parameter related to the operation of a circuit component by a predetermined amount that is also set during a preset control time. Assuming that the error has occurred, the virtual error amount (virtual error amount) that will occur in the signal Si is estimated, and the symbol where the error occurs is specified. The amount of this virtual error depends on the components related to the operation control, the control amount (parameter change amount) of the operation control and the control time, the carrier modulation method, the coding rate, and the like. Therefore, the error estimation unit 82 holds in advance a table indicating the correspondence relationship between these variables and the error amount, and based on this table and the TMCC information including the carrier modulation scheme transmitted from the detection unit 35, etc. Deriving the amount of error. Alternatively, the error estimation unit 82 may obtain the amount of virtual errors from the above-described variable and error amount function.

  The correctability determination unit 83 (correction determination unit) determines whether or not the error correction unit 36 can correct an error included in the signal Si by controlling the operation of the circuit components. Specifically, the correctability determination unit 83 first derives the error amount (virtual error amount) estimated by the error estimation unit 82 and the error correction unit 36 (error rate deriving unit, pre-control error deriving unit). From the bit error rate (pre-control error amount), the total amount of errors that are included in the signal Si when the operation control of the circuit components is performed is calculated.

  On the other hand, the correctability determination unit 83 holds the amount of errors that can be corrected by the error correction unit 36 as a threshold value. Then, by comparing the calculated total amount of errors with a threshold value, it is possible to easily determine whether or not errors can be corrected. That is, when the total amount of errors included in the signal Si is less than or equal to this threshold value, the correctability determination unit 83 determines an error that the signal Si includes when the operation control of the circuit component is performed. 36, it is determined that the correction can be made. On the other hand, when the total amount of errors included in the signal Si exceeds the above-described threshold value, the correctability determination unit 83 determines an error that the signal Si includes when the operation control of the circuit component is performed. In 36, it is determined that the correction cannot be made. As described above, in this embodiment, since the signal state is assumed to be relatively stable, the error rate sent from the error correction unit 36 is within a certain time range (for example, the time interleave length). The average value in Li) may be sufficient.

  The error estimation unit 82 may derive the amount of virtual noise generated by the operation control of the circuit component as the amount of virtual error. In this case, the correctability determination unit 83 derives the CN ratio of the signal Si before control from the information regarding the CN ratio sent from the waveform equalization unit 37 as the pre-control error amount (CN ratio deriving unit). Furthermore, the total amount of errors that are included in the signal Si when the operation control of the circuit components is performed from the virtual noise amount estimated by the error estimation unit 82 and the CN ratio of the signal Si before control. The CN ratio after control corresponding to is calculated. Then, whether or not error correction is possible is determined by comparing the CN ratio after the control with a predetermined threshold related to the CN ratio.

  Alternatively, the error estimation unit 82 may derive a virtual deviation from a constellation specified value generated by the operation control of the circuit component as the amount of virtual errors. In this case, the correctability determination unit 83 performs power control from this virtual constellation shift and the constellation shift before control derived by the waveform equalization unit 37 (shift derivation means). A constellation shift after control corresponding to the total amount of errors included in the signal Si is calculated. Then, whether or not error correction is possible is determined by comparing the constellation shift after the control with a predetermined threshold value regarding the constellation shift.

  Note that the threshold regarding the error amount held by the correctability determination unit 83 varies depending on the carrier modulation scheme and the coding rate of the convolutional code. For this reason, the correctability determination unit 83 holds a table indicating the correspondence relationship between the carrier modulation scheme and the various threshold values, and obtains an appropriate threshold value from such a table and TMCC information (threshold value derivation means). .

  When the correctability determination unit 83 determines that the error included in the received signal can be corrected by the error correction unit 36 when it is assumed that the operation control of the circuit component has been performed, the tuner control unit 26 and the demodulation control unit 41 change the parameters relating to the operation of the circuit components constituting the tuner 2 and the demodulator 3 by a preset control amount during the control time.

  The control change unit 84, when the correctability determination unit 83 determines that the error included in the received signal cannot be corrected by the error correction unit 36, at least the control amount of the operation control and the control time of the operation control One is changed so that the amount of error caused by this operation control is reduced. Here, the control change unit 84 can correct the error included in the signal Si by the error correction unit 36 until the determination result of the correctability determination unit 83 changes (that is, when it is assumed that the operation control is performed). Until it is determined that the control amount or the control time of the operation control is changed stepwise. Therefore, an error that is included in the signal Si due to the operation control of the circuit component is surely corrected by the error correction unit 36, and accurate data can be acquired.

  In the above description, as shown in FIG. 8, when an error that occurs due to the operation control of the circuit component is within the range of one symbol 73 among the plurality of symbols Sb included in the signal Si. However, depending on the length of control time for operation control, an error may occur over a plurality of consecutive symbols 73. For example, FIG. 13 shows a case where the control period of one operation control extends over two or more symbols 73a and 73b, and an error occurs in these two consecutive symbols 73a and 73b. In this case, since the error 74a generated in the two symbols 73a and 73b is distributed over the time interleave length Li, the error 74b generated in the two symbols 73a and 73b after the time deinterleaving. Are partially overlapped, as shown in the diagram 72. If the overlapped error does not exceed the threshold, correction by the error correction unit 36 is possible.

<Demodulator performance degradation control>
By the way, as shown in FIG. 13, when the control time T of the operation control finally set by the control changing unit 84 is longer than the effective symbol length of the symbol Sb, one or more symbols are almost completely In the case of being crushed, it becomes impossible to extract the data of the symbol. In this case, in the demodulator 40, it is wasteful to perform the same demodulation processing as that of a symbol having a normal signal state on a symbol that has been completely collapsed, because it consumes extra power. is there.

  Therefore, the demodulation control unit 41 (demodulation control means), when the control time finally determined by the control change unit 84 is longer than the effective symbol length included in the mode information sent from the AFC / symbol synchronization unit 32, The demodulator 3 as a whole is controlled by controlling the operation of each unit of the demodulator 40 when processing a symbol predicted to cause a virtual error by performing the operation control of the circuit components so that the performance thereof is degraded. Reduce the power consumption.

  The performance degradation control by the demodulation control unit 41 will be described more specifically. First, the demodulation control unit 41 reduces the resolution (number of bits) of the ADC unit 31 or sets the sampling frequency at the timing of processing a symbol predicted to generate a virtual error by the error estimation unit 82 described above. For example, the power supply is reduced so as to reduce the performance of the ADC unit 31 by reducing the size. Alternatively, the power supplied to the ADC unit 31 may be zero (the power is turned off).

  Further, the demodulation control unit 41 is in symbol units that are predicted to be corrupted due to an error with respect to at least one of the digital circuits such as the FFT unit 33 that processes the digital signal converted by the ADC unit 31. The processing of the signal Si is stopped by turning off the power.

  First, in the AFC / symbol synchronization unit 32, normal data is not input from the ADC unit 31, so the symbol synchronization processing is stopped. At this time, the previous state is maintained in order to prevent the previous and subsequent data from being adversely affected. For example, when the AFC / symbol synchronization unit 32 determines the symbol synchronization point with reference to the correlation of the signal, the autocorrelation calculation is stopped and the information related to the symbol synchronization point is held in the previous state. Further, the FFT processing in the FFT unit 33 is stopped.

By the way, when the FFT process is stopped, accurate symbol data cannot be extracted. Even when FFT processing is not stopped, accurate symbol data cannot be extracted by stopping processing other than FFT (for example, symbol synchronization). In this case, since the TMCC information relating to the symbol is incorrect, the detection processing (retrieving TMCC information) in the detection unit 35 is stopped at the symbol, and the TMCC of the symbol is based on the TMCC data relating to the symbol in the previous frame. Retain or reproduce information. Further, the waveform equalization unit 37 stops the waveform equalization process. Here, in order to reduce the influence of noise, when performing equalization processing by performing filtering processing or averaging processing using a scattered pilot signal in terms of time, the symbols before and after are adversely affected. In order to prevent this, the information of the symbol whose signal state has deteriorated is not used for such filtering processing and averaging processing.
Further, the frequency deinterleaving process in the frequency deinterleaving unit 43 is stopped.

  In this way, the demodulation control unit 41 stops the processing of the digital circuit from the AFC / symbol synchronization unit 32 to the frequency deinterleaving unit 43 on a symbol-by-symbol basis. Power consumption is reduced.

  Then, after the above performance degradation control is performed, when a symbol having a normal signal state (no error caused by the operation control of the circuit component is generated) is input, the demodulation control unit 41 supplies the ADC unit 31. The power is returned to the original state, and the digital circuit such as the FFT unit 33 is returned to the original state so that the processing for the signal Si is normally performed.

  By the way, when the demodulation control unit 41 performs power reduction control of the ADC unit 31 or control to stop the subsequent digital circuit processing, data is not output from the frequency deinterleave unit 43 to the time deinterleave unit 44. The time deinterleaving process cannot be normally performed. Therefore, in the present embodiment, as shown in FIG. 6, when the processing of the digital circuit is stopped in symbol units in the demodulator 40, a dummy signal in symbol units is sent to the time deinterleave unit 44 instead of the signal Si. A dummy signal generation unit 90 to be supplied is constructed. This dummy signal generation unit 90 receives a command from the demodulation control unit 41 and outputs a dummy signal to the time deinterleaving unit 44 instead of the symbol whose signal state has deteriorated. Specifically, when power control of the ADC unit 31 is performed, a dummy signal is output from the dummy signal generation unit 90 to the time deinterleaving unit 44 in accordance with a clock output from the ADC unit 31.

  Here, as described above, the reliability of each data of the data string input to the Viterbi decoding unit 46 of the error correction unit 36 is set based on the magnitude of the input signal, and the Viterbi decoding unit 46 Based on this reliability, error correction is performed and performance is changed. However, when the performance degradation control by the demodulation control unit 41 as described above is performed, an incorrect signal (dummy signal) is input to the Viterbi decoding unit 46 regardless of the set reliability. As a result, there is a possibility that the error correction performance in the Viterbi decoding unit 46 is lowered.

  Therefore, the dummy signal generation unit 90 sets the reliability of the dummy signal to the lowest. In this case, when a dummy signal is input, the Viterbi decoding unit 46 determines that the reliability of the input signal is the lowest and performs error correction based on a signal other than the dummy signal. Correction performance can be improved. Further, when a dummy signal is input, the Viterbi decoding unit 46 improves the error correction performance by increasing the traceback length (the number of data to be referred back to the past) at the time of decoding.

  Next, a series of controls including operation control of circuit components by the tuner control unit 26 and the demodulation control unit 41 will be described with reference to the flowchart of FIG. However, in FIG. 14, Sn (n = 1, 2, 3 ...) shows each step.

  First, the control unit 4 obtains TMCC information such as an effective symbol length mode and a received signal transmission method from the demodulator 3 (S1). Next, the start timing determination unit 80 determines a symbol to be handled by the circuit component when the operation control of the circuit component is performed, and the start timing of the operation control is linked to the sub guard interval of a certain symbol. It is determined within a period composed of a guard interval of another symbol (S2: start timing determination step).

  Then, when it is assumed that the error estimation unit 82 performs control for changing the parameter related to the operation of the circuit component by a predetermined control amount during the predetermined control period from the start timing determined in S2, an error is detected. A symbol that is expected to be generated is specified, and the amount of the virtual error is estimated (S3: error estimation step). Further, the signal Si is included in the signal Si based on the amount of virtual errors estimated by the error estimator 82 and the error rate or the like (amount of pre-control error) sent from the error corrector 36 by the correctability determination unit 83. Is calculated and compared with a predetermined threshold value, and it is determined whether or not this error can be corrected by the error correction unit 36 (S4: correction possibility determination step).

  When the correction possibility determination unit 83 determines that the error correction unit 36 can correct the error included in the signal Si (S4: Yes), the tuner control unit 26 or the demodulation control unit 41, the operation control of the circuit component is executed by changing the operation parameter of the circuit component by a predetermined control amount during the predetermined control time set in advance from the start timing determined in S2 (S5: Operation Control step).

  On the other hand, when the error correction unit 36 determines that the error included in the signal Si cannot be corrected (S4: No), the control change unit 84 At least one of the control amount (operation parameter change amount) and the control time is changed so that the amount of error caused by the operation control is reduced (S6: control change step). Here, the control change unit 84 until the error correction unit 36 determines that the error included in the signal Si when it is assumed that the operation control of the circuit component has been performed in the correction possibility determination unit 83. Changes at least one of the control amount and the control time (S3, S4, S6). When it is determined that the error included in the signal Si is correctable (S4: Yes), the tuner control unit 26 or the demodulation control unit 41 determines the control amount and control time finally determined. Then, the operation control of the circuit components is executed (S5).

  Here, when the control time of the operation control of the circuit component is longer than the effective symbol length and one or more symbols are almost completely destroyed (S7: Yes), the circuit constituting the demodulator 40 by the demodulator 41 The operation when the component processes the symbol is controlled so that its performance is reduced (S8). Specifically, the power supplied to the ADC unit 31 is reduced or the power is made zero. Further, processing in at least one of the plurality of digital circuits from the AFC / symbol synchronization unit 32 to the frequency deinterleaving unit 41 that processes the digital signal output from the ADC unit 31 is stopped. On the other hand, when the control time of the operation control is shorter than the effective symbol length (S7: No), the demodulation control unit 41 does not perform the performance deterioration control of the demodulation unit 40. However, even when the control time of the operation control is shorter than the effective symbol length, if the influence of the operation control on the signal Si is large and one or more symbols are crushed, the performance deterioration control by the demodulation control unit 41 is performed. I do.

  Then, the error finally included in the signal Si by performing the various controls described above is corrected in the error correction unit 36 after being dispersed by time deinterleaving processing or the like (S9: error correction). Step).

According to the digital demodulator 1 described above, the following effects can be obtained.
The circuit component operation control by the tuner control unit 26 or the demodulation control unit 41 is a period (preferably an effective period for acquiring data) that includes a guard interval of a certain symbol and a sub-guard interval of another symbol connected thereto. It starts in a period that does not overlap an FFT window. Therefore, errors occurring in the signal Si are reduced by controlling the operation of this circuit component. Furthermore, errors generated in the received signal due to the operation control of the circuit components are dispersed by various deinterleaving processes such as a time deinterleaving process, so that the error correction unit can easily correct the errors. Therefore, it is possible to obtain more accurate data by minimizing errors caused by the operation control of the circuit components constituting the tuner 2 and the demodulator 3.

Next, modified embodiments in which various modifications are made to the embodiment will be described. However, components having the same configuration as in the above embodiment are given the same reference numerals and description thereof is omitted as appropriate.
1] In the above embodiment, when it is determined that the error included in the signal Si cannot be corrected by the error correction unit 36, the control change unit 84 sets the control amount and the dynamic control time for the operation control to the error amount. However, when it is determined that the error included in the signal Si can be corrected by the error correction unit 36, the control amount and the control time are increased. You may be comprised so that it may change.

  For example, when the power supplied to the circuit component is controlled by the tuner control unit 26 or the demodulation control unit 41, while it is determined that the error caused by the control can be corrected, the power reduction amount and the control time are set. When it is determined that error correction is impossible, the power control is performed by adopting the power reduction amount and the control time when it is determined that correction is possible immediately before. In this case, the power reduction amount can be set as large as possible, or the control time can be set as long as possible within a range in which an error included in the received signal can be corrected.

  2] When it is determined by the correctability determination unit that an error included in the signal Si cannot be corrected by the error correction unit by controlling the operation of a certain circuit component, it is included in the signal Si. The operation of another circuit component may be controlled so that the amount of error is reduced. For example, when it is assumed that the power supplied to the VCO / PLL unit, which is a circuit component constituting the tuner 2, is controlled by the tuner control unit, if the error contained in the signal Si cannot be corrected, the power control In order to reduce the relative amount of the generated noise with respect to the signal Sr, control for increasing the amplification amount of the signal Sr in the RF amplifier unit is performed in advance.

  As shown in FIG. 15, the control unit 4A of this modified form includes a start timing determination unit 80, a symbol synchronization extraction unit 81, an error estimation unit 82, and a correctability determination unit 83, and further includes a control determination unit 85. Have

  First, the start timing determination unit 80 determines the start timing of the operation control of a certain circuit component A (third circuit component) constituting the tuner 2 and the demodulator 3. Further, the error estimation unit 82 estimates the amount of virtual error that will occur in the signal Si by the operation control of the circuit component A. Then, the correctability determination unit 83 calculates the total amount of errors to be included in the signal Si, and determines whether or not the total amount of errors can be corrected by the error correction unit 36.

  When the correctability determination unit 83 determines that the error included in the signal Si can be corrected, the operation control of the circuit component A is performed by the tuner control unit 26 and the demodulation control unit 41 as in the above embodiment. Done.

  When it is determined by the correctability determination unit 83 that the error included in the signal Si cannot be corrected, the control determination unit 85 determines that the error included in the signal Si is due to operation control. The circuit component B (fourth circuit component) different from the circuit component A is determined so that the amount of the circuit component A decreases, and the operation control start timing and control amount (change amount of the operation parameter) of the circuit component B are determined. ). Here, the control amount of the operation control of the circuit component B is appropriate so that the amount of error included in the signal Si is reduced to an amount that can be corrected by the error correction unit by performing the operation control of the circuit component B. Set to Further, the control determination unit 85 determines the start timing and the control amount of the control for returning the operation parameter of the circuit component B after the operation control of the circuit component A is completed.

  Here, the operation control start timing of the circuit component B is determined within a period that includes the sub guard interval and the guard interval and does not overlap with the FFT window, similar to the operation control start timing of the circuit component A. It is preferable.

  The operation control of the circuit component A and the circuit component B will be described with reference to the timing chart of FIG. In FIG. 16, a diagram 71 shows an error occurring in the signal Si before the time deinterleaving process. On the other hand, a diagram 172 shows an error in the signal Si after the time deinterleaving process.

  When it is determined that the error included in the signal Si cannot be corrected by the operation control of the circuit component A, the tuner control unit 26 or the demodulation control unit 41 precedes the operation control of the circuit component A by the circuit. The operation parameter of the component B is changed from the start timing T2 determined by the control determination unit 85 by the control amount determined by the control determination unit 85. Then, as shown in a diagram 172, errors included in the signal Si decrease over a period P2 having a length of the time interleave length Li.

  Next, the operation of the circuit component A is controlled in accordance with a preset control amount and control time from the start timing T1 determined by the start timing determination unit 80. As a result, an error 74a occurs in the signal Si. The error 74a is distributed over the period P1 having the length of the time interleave length Li by the time deinterleave processing. Here, since the amount of errors in the signal Si is reduced in advance by the operation control of the circuit component B, the error included in the signal Si is increased by the operation control of the circuit component A. The threshold value for determining whether correction is possible is not exceeded. Therefore, an error included in the signal Si is reliably corrected by the error correction unit 36.

  After the operation control of the circuit component A is performed, the operation parameter of the circuit component B is changed from the start timing T3 determined by the control determination unit 85 by the control amount determined by the control determination unit 85. Thus, the circuit component B is returned to the operating state before time T2. As a result, the error included in the signal Si increases to an error amount before time T2. Note that the error increased due to the change of the operation parameter at time T3 is also distributed over the period P3 of the time interleave length Li by the time deinterleave processing.

  In FIG. 16, T2 and T1, and T1 and T2, which are operation control start timings of the circuit component A and the circuit component B, are separated by a time interleave length Li or more, but an error included in the signal Si is detected. If the amount does not exceed the threshold, these start timings may be set such that the time interval between them is less than the time interleave length Li.

  Further, in this modified form, as shown in FIG. 15, the control unit 4A has a control determining unit 85 instead of the control changing unit 84 (see FIG. 9) of the above embodiment. The unit may include both the control change unit 84 and the control determination unit 85. That is, when it is determined that the error included in the signal Si cannot be corrected by performing the operation control of the circuit component A, the circuit is controlled by the control changing unit 84 so that the error is within the correctable range. The control amount of the component A may be changed, and the control determining unit 85 may determine the circuit component B to be controlled and its control amount.

  3] In the above embodiment, it is assumed that the state of the received signal is stable, but the present invention can also be applied to a case where the signal state is unstable. However, as described above, when the signal state is stable, the error rate or CN ratio averaged in units of time interleave length is used to determine the error when determining whether the correction is possible or not by the correctability determination unit 83. Although it may be calculated, when the signal state is unstable (for example, when an error other than the error due to the operation control of the circuit component greatly fluctuates), the error rate, MER or CN ratio averaged in smaller time units Etc. are preferably used. In this case, since the error is calculated at a shorter time interval, it is possible to reliably determine whether the error can be corrected even when the signal state is unstable and the error amount changes in a short time. Alternatively, as an error rate, MER, CN ratio, etc., an instantaneous value may be used instead of an average value in a certain time range.

  4] In the above embodiment, the control unit 4 is constructed outside the tuner 2 and the demodulator 3, but each unit having the function of the control unit 4 may be constructed inside the tuner 2 and the demodulator 3. . Or the control part 4 may be constructed | assembled by the host CPU which controls digital receivers, such as a mobile telephone provided with the digital demodulator 1 of embodiment mentioned above, and the program which functions this CPU. In addition, the tuner control unit 26 and the demodulation control unit 41 are not necessarily built inside the tuner 2 and the demodulator 3, and may be built outside the tuner 2 and the demodulator 3.

It is a figure which shows the mobile telephone which is an example of the digital receiver which concerns on embodiment of this invention. It is a figure which shows the structure of 1 symbol of an OFDM signal. It is a block diagram which shows schematic structure of a digital demodulation apparatus. It is a block diagram of a tuner. It is a block diagram of a demodulator. It is a block diagram of a demodulation part. It is explanatory drawing of time interleaving and time deinterleaving. It is a timing chart in case the operation control of a circuit component affects one symbol of a received signal. It is a block diagram of a control part. It is a timing chart of the power control of a circuit component. It is a block diagram of a symbol synchronous extraction part. It is explanatory drawing about the calculation of the correlation value of the signal at the time of symbol synchronous point extraction, (a) shows the case where a delay wave does not exist, (b) shows the case where a delay wave exists, respectively. It is a timing chart in case the operation control of a circuit component has influence over two continuous symbols of a received signal. It is a flowchart of a series of control including the operation control of a circuit component. It is a block diagram of a control part concerning a change form. It is a timing chart regarding operation control of two circuit components (circuit component A and circuit component B) concerning a change form.

Explanation of symbols

Sr, Si signal Sb Symbol 1 Digital demodulator 2 Tuner 3 Demodulator 21 IF amplifier unit 22 Mixer unit 23 VCO / PLL unit 24 Filter unit 25 RF amplifier unit 26 Tuner control unit 31 ADC unit 36 Error correction unit 37 Waveform equalization unit 41 Demodulation control unit 44 Time deinterleaving unit 53 Guard interval 54 Sub guard interval 55 FFT window 80 Start timing determination unit 82 Error estimation unit 83 Correctability determination unit 84 Control change unit 91 Delay unit 92 Correlation calculation unit 201 Mobile phone (digital reception) apparatus)

Claims (25)

A plurality of symbols that are the same signal as the sub guard interval consisting of one end of the main signal and include a guard interval added so as to be connected to the other end of the main signal, and further interleaving these symbols. A digital demodulator that demodulates a received signal that has been processed,
A tuner that performs channel selection processing on the received signal, and a demodulator that performs demodulation processing on a signal from the tuner;
An error correction unit that includes deinterleaving means for performing deinterleaving processing on the received signal that has been subjected to the interleaving process to disperse errors included in the received signal, and correcting errors distributed by the deinterleaving means; When,
Operation control means for controlling operation of at least one of a plurality of circuit components constituting the tuner and the demodulator;
A start timing determining means for determining a timing at which the operation control means starts operation control of the circuit component;
The start timing determination means determines the start timing of the operation control of the circuit component by the operation control means within a period composed of the guard interval of a certain symbol and the sub guard interval of another symbol connected to the guard interval. And
The operation control means is configured to control operations of the first circuit component and the second circuit component included in the plurality of circuit components,
The start timing determining means includes a start timing of the operation control of the first circuit component and a start timing of the operation control of the second circuit component, which are occupied by errors that are generated by the operation control, respectively. Are determined so as not to overlap each other after the deinterleaving process . The start timing determining means determines the start timing of the operation control of the circuit component by the operation control means in terms of the time between the guard interval of a certain symbol and the sub guard interval of another symbol connected to the guard interval. Decide within one of the earlier periods,
2. The operation control unit performs operation control of the circuit component so as to cross a boundary between the guard interval and the sub guard interval from a start timing determined by the start timing determination unit. The digital demodulator according to 1. The demodulator includes a valid period determining means for determining a valid period in which data is acquired from the symbol and whose time length is equal to the time length of the main signal,
3. The digital demodulator according to claim 1, wherein the start timing determination unit determines the start timing within an invalid period that does not overlap the valid period. The deinterleaving process is a time deinterleaving process that restores the sequence of the plurality of symbols rearranged in time by the time interleaving process;
The start timing determining means determines the start timing of the operation control of the first circuit component and the start timing of the operation control of the second circuit component, and the time interval between these two start timings is equal to or greater than the time interleave length. The digital demodulator according to claim 1, wherein the digital demodulator is determined to be Error estimation means for estimating the amount of virtual error that will occur in the received signal by performing operation control of the circuit component by the operation control means;
Whether or not the error correction means can correct an error that is included in the received signal by performing the operation control of the circuit component by the operation control means from the amount of the virtual error estimated by the error estimation means. Correctability determination means for determining whether or not
Digital demodulating apparatus according to any one of claims 1-4, characterized in that it comprises a. Comprising pre-control error deriving means for deriving an amount of pre-control error included in the received signal before operation control of the circuit component is performed by the operation control means;
The correction feasibility determination unit is configured to determine an error to be included in the received signal from the amount of the virtual error estimated by the error estimation unit and the amount of the pre-control error derived by the pre-control error deriving unit. 6. The digital demodulator according to claim 5 , wherein a quantity is derived. The correctability determination means includes threshold value derivation means for deriving a threshold value of an amount of error that will be included in the received signal by performing operation control of the circuit component.
The error correction unit determines that the error correction unit can correct the error when the amount of error included in the received signal is equal to or less than the threshold derived by the threshold deriving unit. 6. The digital demodulator according to 6 . 8. The digital demodulator according to claim 7 , wherein the threshold deriving unit derives the threshold based on at least one of a received signal modulation scheme and a coding rate. The control before error derivation means, any claim 6-8, characterized in that it has an error rate deriving means for deriving an error rate of the previous received signal operation control of the circuit component by the operation control means is performed A digital demodulator according to claim 1. The pre-control error deriving unit includes a deviation deriving unit for deriving a deviation from a constellation value of a received signal before the operation control unit performs the operation control of the circuit component. The digital demodulator according to any one of 6 to 8 . The control before error derivation means, any claim 6-8, characterized in that it has a CN ratio deriving means for deriving a CN ratio before the received signal operation control of the circuit component by the operation control means is performed A digital demodulator according to claim 1. The operation control means is configured to control operations of a third circuit component and a fourth circuit component included in the plurality of circuit components,
Further, the operation control means controls the operation of the fourth circuit component so that the amount of errors included in the received signal is reduced by controlling the operation of the third circuit component. digital demodulating apparatus according to any one of claims 5 to 11, characterized in that. 13. The digital demodulator according to claim 12 , wherein the operation control means performs operation control of the fourth circuit component prior to operation control of the third circuit component. When it is determined by the correctability determination means that the error correction means cannot correct an error that is included in the received signal by performing the operation control of the third circuit component by the operation control means. The digital demodulator according to claim 12 or 13 , wherein the operation control means controls the operation of the third circuit component and also controls the operation of the fourth circuit component. Whether or not the error correction means can correct an error included in the received signal by performing the operation control of the circuit component by the operation control means for a certain amount of time by the correction possibility determination means. after either has been determined, based on the determination result, to one of claims 5 to 14, characterized in that it comprises a control changing means for changing at least one of the operation control of the controlled variable and the control time The digital demodulator according to the description. Demodulation control means for controlling an operation at the time of processing a symbol in which an error occurs due to the operation control of at least one of a plurality of circuit components constituting the demodulator so that the performance thereof is degraded. 16. The digital demodulator according to claim 1, further comprising a digital demodulator. The start timing determining means includes
Delay means for delaying the received signal to generate a delayed signal;
16. The digital demodulator according to claim 1, further comprising correlation deriving means for deriving a correlation between the received signal and the delayed signal. The operation control means, at a timing determined by the start timing determining means, digital demodulating apparatus according to any one of claims 1 to 17, characterized in that for controlling the power supplied to the circuit components. 19. The digital demodulator according to claim 18 , wherein the operation control unit zeroes the power supplied to the circuit component at the timing determined by the start timing determination unit. The tuner includes an RF amplifier, a mixer, a filter, an IF amplifier, and a VCO / PLL.
The said operation control means controls the electric power supplied to the circuit component which comprises at least 1 of RF amplifier, a mixer, a filter, IF amplifier, and VCO * PLL, The Claim 18 or 19 characterized by the above-mentioned. Digital demodulator. The demodulator includes an ADC that converts an analog signal from the tuner into a digital signal;
It said operation control means, a digital demodulating apparatus according to any one of claims 18 to 20, wherein the controller controls the power supplied to the circuit components constituting the ADC. A digital demodulator according to any one of claims 1 to 21 is provided,
A digital reception device that performs reproduction processing of at least one of characters, images, sounds, and data based on a reception signal demodulated by the digital demodulation device. A plurality of symbols that are the same signal as the sub guard interval consisting of one end of the main signal and include a guard interval added so as to be connected to the other end of the main signal, and further interleaving these symbols. A control method of a digital demodulator comprising a tuner that performs channel selection processing on a received signal that has been processed, and a demodulator that performs demodulation processing on a signal from the tuner,
An error correction step for performing a deinterleaving process on the received signal that has been subjected to the interleaving process to disperse errors contained in the received signal and correcting the distributed errors;
An operation control step for controlling the operation of at least one of a plurality of circuit components constituting the tuner and the demodulator;
And a start timing determining step of determining a timing for starting the operation control of the circuit components in the operation control step,
In the start timing determining step, the start timing of the operation control of the circuit component in the operation control step is determined within a period including the guard interval of a certain symbol and the sub guard interval of another symbol connected to the guard interval. And
In the operation control step, each of the first circuit component and the second circuit component included in the plurality of circuit components is controlled,
In the start timing determination step, the start timing of the operation control of the first circuit component and the start timing of the operation control of the second circuit component are occupied by errors that are generated by the operation control, respectively. Are determined so as not to overlap each other after the deinterleaving process . A plurality of symbols that are the same signal as the sub guard interval consisting of one end of the main signal and include a guard interval added so as to be connected to the other end of the main signal, and further interleaving these symbols. A control program for a digital demodulator comprising a tuner that performs channel selection processing on a received signal that has been processed, and a demodulator that performs demodulation processing on the signal from the tuner,
An error correction step for performing a deinterleaving process on the received signal that has been subjected to the interleaving process to disperse errors contained in the received signal and correcting the distributed errors;
An operation control step for controlling the operation of at least one of a plurality of circuit components constituting the tuner and the demodulator;
And a start timing determining step of determining a timing for starting the operation control of the circuit components in the operation control step,
In the start timing determining step, the start timing of the operation control of the circuit component in the operation control step is determined within a period including the guard interval of a certain symbol and the sub guard interval of another symbol connected to the guard interval. And
In the operation control step, each of the first circuit component and the second circuit component included in the plurality of circuit components is controlled,
In the start timing determination step, the start timing of the operation control of the first circuit component and the start timing of the operation control of the second circuit component are occupied by errors that are generated by the operation control, respectively. Are determined so as not to overlap each other after the deinterleaving process . 25. A recording medium on which a control program for the digital demodulator according to claim 24 is recorded.

Images