JP2003062160A - Communication system between game machines - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication system between game machines which realizes the efficient utilization of a storage means so as to reduce scrapping of the storage means storing data for display even in occurrence of such a situation as scrapping a game machine. SOLUTION: The communication system between game machines is obtained by arranging a plurality of the game machines provided with display means for displaying identification information related with a game and providing a communication means capable of communicating data to the respective game machines to form a data communication network 31. The plurality of these game machines are divided to a master set H provided with a storage means 43 having data required for display at a display means stored thereon and slave sets T1 to Tn which are not provided with the storage means 43. The slave sets T1 to Tn receive data from the master set H via the data communication network 31 at need and displays identification information on the display means based on the data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication system between gaming machines in a gaming machine such as a pachinko machine or a slot machine whose gaming operation is controlled by a control means such as a microcomputer.

[0002]

2. Description of the Related Art In a gaming machine such as a pachinko machine or a slot machine, a CP as an arithmetic unit is used to control its operation.
Various control boards in which an electronic circuit composed of U, a RAM as a storage element, a ROM, and the like are arranged are provided inside.

In recent years, a game machine equipped with a display means such as a liquid crystal display device and performing various effects such as moving images has become mainstream, and image data and moving image data necessary for these effects are generally masked. It is stored in a read-only storage element called a ROM and is arranged on the control board of each gaming machine. Two to four mask ROMs are mounted for each game machine.

[0004]

However, since the data stored in the mask ROM is peculiar to the gaming machine, in a situation where a large number of gaming machines are unsold, the mask ROM is Like other parts, it could not be reused and was discarded.

It is an object of the present invention to enable efficient use of mask ROM so that even if a situation occurs in which the game machine is discarded, it is possible to efficiently use the mask ROM. It is to provide a system.

[0006]

According to the present invention, a plurality of gaming machines having a display means for displaying identification information related to a game are arranged, and each gaming machine is provided with a communication means capable of data communication to provide a data communication network. A communication system between gaming machines that forms
The plurality of gaming machines are divided into a parent machine having a storage means in which data necessary for display on the display means is stored, and a child machine having no storage means, and the child machines are provided with data as necessary. It is characterized in that data is received from the master unit via the communication network and the identification information is displayed on the display means based on the data.

A second aspect of the present invention is characterized in that a buffer RAM is connected to the communication means of the master unit.

A third aspect of the present invention is characterized in that the communication means and the storage means of the base unit are connected by a DMA bus.

According to a fourth aspect of the present invention, the communication means of the master unit and the data RAM for storing the data fetched from the storage unit when the display unit of the master unit displays are DMA.
It is characterized by connecting by bus.

A fifth aspect of the present invention is characterized in that a buffer RAM is connected to the communication means of the slave unit.

A sixth aspect of the present invention is that the communication means of the slave unit and the data RAM for storing the data necessary for executing the display on the display unit of the slave unit are connected by the DMA bus. Characterize.

A seventh aspect of the present invention is characterized in that the data stored in the storage means is moving image data.

According to an eighth aspect of the present invention, a data communication network is
It is characterized by being formed by Ethernet (registered trademark).

[0014]

According to the present invention, the slave unit is not provided with the storage means for storing the display data, and is configured to receive the data from the master unit and display the identification information as necessary. For example, even when a situation occurs in which the game machine is discarded, the storage means other than the parent machine does not have to be discarded, and the amount of waste of the storage means can be greatly reduced. For example, for the same gaming machine placed in the gaming hall, if one of the gaming machines is the parent machine and the others are the slave machines, the amount of waste of the storage means can be reduced to tens of thousands. . Further, since it is not necessary to mount the storage unit mounted on the master unit on the slave unit, the cost is reduced accordingly, and a large cost reduction is realized as a whole. In addition,
A typical example of the storage means is a read-only storage element (ROM), and a mask ROM is generally used as the ROM that stores display data on the display means.

According to the second aspect of the present invention, since the buffer RAM is connected to the communication means of the master unit, all the necessary data are stored in the buffer RAM all at once when transmitting data to the slave unit. By doing so, necessary data can be sequentially transferred to the child device. As a result, the waiting time required for data reception on the slave side can be reduced, and the data transfer time can be shortened.

According to the third aspect of the present invention, since the communication means and the storage means of the master unit are connected by the DMA (Direct Memory Access) bus, when a data acquisition request is issued from the slave unit side, The communication unit can acquire the data from the storage unit and transfer the data to the slave unit without using the CPU. As a result, the data transfer time can be shortened.

According to the fourth aspect of the present invention, in the case where the communication means and the storage means of the master unit are connected by the DMA bus, the display means of the master unit is used to execute the display. Data RA for storing the retrieved data
Since M and the communication means of the parent device are connected by the DMA bus, the data taken out from the storage means can be directly transferred to the data RAM from the communication means of the parent device without passing through the CPU. Can be shortened. As a result, the display control on the display unit of the parent device does not have to be hindered by the delay in data transfer.

According to the fifth aspect of the present invention, since the buffer RAM is connected to the communication means of the slave unit, the data transferred from the master unit is temporarily stored in this buffer RAM to transfer the data. It is not necessary to process the processed data and overflow the data.

According to the sixth aspect of the present invention, the communication means of the slave unit and the data RAM for storing the data necessary for displaying on the display means of the slave unit are connected by the DMA bus. Therefore, the data transferred from the base unit is
The above-mentioned data RA is transmitted from the communication means of the slave unit without going through
Since data can be directly transferred to M, the data transfer time can be shortened. As a result, the display control on the display unit does not have to be hindered by the delay in data transfer even on the slave unit side.

When the DMA bus is used, data can be exchanged without going through the CPU, so that there is an advantage that the processing being executed in the CPU is not disturbed.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment in which the present invention is applied to a so-called "pachi-slot machine" which is an example of a gaming machine will be described below. The gaming machines to which the present invention can be applied include a pachinko gaming machine and a slot machine.

FIG. 1 is a perspective view showing the appearance of the pachi-slot machine 1. This pachi-slot machine 1 uses coins as game media,
Although it is a gaming machine that plays games using medals or tokens, the following description will be made assuming that medals are used.

The pachi-slot machine 1 is composed of a cabinet 1a for accommodating a reel unit and the like, and a front door 1b provided on the cabinet 1a so as to be openable and closable. A panel display portion 2 as a substantially vertical surface is formed on the front surface of the front door 1b, and three vertically long rectangular display windows (left display window 4L, middle display window 4C, right display window 4 are formed in the center thereof.
R) is provided. The display windows 4L, 4C, 4R are provided with top lines 8b, center lines 8c and bottom lines 8d in the horizontal direction, and cross-down lines 8a and cross-up lines 8e in the diagonal direction as winning lines. These pay lines 8a to 8e are described below in 1-B.
ET switch 11, 2-BET switch 12, maximum BE
Operating the T switch 13 or the medal slot 2
By inserting medals into 2, 1 and 3 respectively
5 books are activated. Which winning line has been activated is indicated by lighting of BET lamps 9a, 9b, 9c, which will be described later.

Inside the cabinet 1a located inside the display windows 4L, 4C, 4R, there is provided a reel unit in which three reels (left reel 3L, middle reel 3C, right reel 3R) are rotatably constituted. ing. 3 reels 3
On the outer peripheral surfaces of L, 3C, 3R, a plurality of types of symbols (for example, "7", "BAR", "cherry", etc.) are drawn. Therefore, by rotating these reels 3L, 3C, 3R, the variable display of symbols can be observed through the display windows 4L, 4C, 4R. Reel 3L, 3C, 3R
The variable display of the symbols due to the rotation of is started by the operation of the start lever 6 by the player, and thereafter, by the operation of the stop buttons 7L, 7C, 7R by the player, the reels 3L, 3C, 3R corresponding to the operation timing are displayed. Stop control is performed. At this time, a predetermined prize is generated according to the symbol combination stopped in the display windows 4L, 4C, and 4R (specifically, the symbol combination on the activated pay line), and the winning mode thereof. The number of medals will be paid out according to.

On the left side of the left display window 4L, a 1-BET lamp 9a, a 2-BET lamp 9b and a maximum BET lamp 9 are provided.
c, a credit display unit 19 is provided. The 1-BET lamp 9a, the 2-BET lamp 9b, and the maximum BET lamp 9c are turned on according to the number of medals bet for playing one game (hereinafter referred to as the "BET number"). Here, one game ends when all reels stop or when the effect display on the liquid crystal display device 5 of the game ends. The 1-BET lamp 9a lights up when the BET number is "1" and one pay line is activated. The 2-BET lamp 9b is 3 when the BET number is "2".
Illuminates when the winning line of the book is activated. Maximum B
The ET lamp 9c lights up when the BET number is "3" and all (5) pay lines are activated. The credit display unit 19 has a display unit formed of 7-segment LEDs and displays the number of stored medals.

On the right side of the right display window 4R, the WIN lamp 1
7 and a payout display unit 18 are provided. WIN lamp 17
Is lit when BB or RB wins, BB or R
When B is internally elected, it lights up with a predetermined probability. The payout display unit 18 is formed of a 7-segment LED, and displays the number of paid-out medals when a winning is achieved.

Below the display windows 4L, 4C, 4R, a pedestal portion 10 having a horizontal plane is formed, and the pedestal portion 10 and the display window 4 are formed.
A liquid crystal display device 5 is provided between L, 4C and 4R. On the display screen 5a of the liquid crystal display device 5, effects by various images are displayed during the game. Various effects performed by the liquid crystal display device 5 are controlled by a symbol control circuit described later.

A medal slot 2 is provided on the right side of the liquid crystal display device 5.
2 is provided, and 1-BET is provided on the left side of the liquid crystal display device 5.
Switch 11, 2-BET switch 12, and maximum B
An ET switch 13 is provided. 1-BET switch 1
1 indicates that one of the credited medals is bet on the game by one push operation, and the 2-BET switch 12 indicates two of the credited medals by one push operation. Bet on the game, maximum BE
The T switch 13 bets the maximum number of medals that can be bet in one game. By operating these BET switches, as described above, the predetermined pay line is activated.

Between the credit display section 19 and the 1-BET switch 11 and the 2-BET switch 12, there are provided a cross button 26, an O button 27, and an X button 28 as operation buttons. These buttons are operated, for example, when selecting effect contents displayed on the display screen 5a.

A C / P switch 14 is provided on the left side of the front surface of the pedestal portion 10 for switching the credit / payout of medals acquired by the player by a push button operation. By switching the C / P switch 14, medals are paid out from the medal payout opening 15 in the lower front portion, and the paid-out medals are stored in the medal receiving portion 16. On the right side of the C / P switch 14, the start lever 6 for starting the variable display of the symbols in the display windows 4L, 4C, 4R is rotated within a predetermined angle range by rotating the reel by the player's operation. It is movably attached.

At the center of the front surface of the pedestal portion 10 and below the liquid crystal display device 5, three stop buttons (left stop button) are provided as stop means for stopping the rotation of the three reels 3L, 3C, 3R, respectively. 7L, a middle stop button 7C, a right stop button 7R) are provided so as to be operated by the player. Above the front door 1b, two speakers (left speaker 21L and right speaker 21R) are provided on the left and right, and between the two speakers 21L and 21R, a combination of winning symbols and the number of medals to be paid, etc. A payout table panel 23 for displaying is provided.

FIG. 2 shows a first embodiment of a communication system between gaming machines, which is constituted by installing a plurality of pachi-slot machines as described above. Each pachi-slot machine is provided with a communication interface as a communication means that enables bidirectional data communication with the outside, and the pachi-slot machines and the hall computer 30 form a data communication network (LAN) by Ethernet 31. The hall computer 30 is a management computer for collecting game data of each pachi-slot machine and centrally managing each pachi-slot machine.

Each pachi-slot machine internally has a main control circuit for controlling its main operation and an image control circuit for controlling effects in the liquid crystal display device 5. Here, this Figure 2
In the inter-gaming-machine communication system shown in FIG. 1, an image ROM 43 is provided in the image control circuit 42 for one pachi-slot machine, and an image RO is provided in the image control circuit 42 'for the other pachi-slot machines.
The M43 is not provided. Where image ROM
One pachi-slot machine provided with 43 in the image control circuit 42 is referred to as a "parent machine", and is indicated by "H" in the figure. Image ROM 43
The called multiple that is not provided with the image control circuit 42 'in the pachi-slot machine of the (n stand here) as "slave unit" in the figure T ₁ ~
Denote by T _n . The image ROM 43 is used for the liquid crystal display device 5.
This is a storage means for storing image data or moving image data necessary for display in, and a read-only storage element (memory) is used. In this embodiment, so-called "mask RO" in which data is previously burned in during manufacturing and rewriting is not possible.
"M" shall be used.

In the parent machine H having the image ROM 43 in the image control circuit 42, the main control circuit 4 is operated when the game is started.
A control signal (command) including information such as an internal winning combination transmitted from 1 is transmitted to the image control circuit 42, and based on the command, the liquid crystal display device 5 in the image control circuit 42.
The contents of the performance will be decided. The effect is image ROM4
Necessary image data is read out from 3 and the display is controlled.
Therefore, the image ROM 43 stores the image data necessary for the effect displayed on the liquid crystal display device 5.

On the other hand, the image ROM 43 is replaced by the image control circuit 4
In handset T ₁ through T _n which does not have in the 2 ', the image data necessary for rendering the content on the liquid crystal display device 5 as appropriate when necessary from the image ROM43 of the image control circuit 42 of the parent device H It is read and the effect is displayed. Specifically, the child device T ₁
Than through T _n image control circuit 42 ', the transmitted signal for requesting the image data necessary for rendering (hereinafter referred to as "image request command".) Via Ethernet 31 to the image control circuit 42 of the parent device H, the Upon receiving the image request command, the image control circuit 42 of the master H transfers the necessary image data to the image control circuit 42 ′ of the slave that is the command transmission source.

FIG. 3 shows a second embodiment of the inter-gaming machine communication system constructed by installing a plurality of pachi-slot machines. Also here, as in the embodiment shown in FIG. 2, each pachi-slot machine and the hall computer 30 are connected by the Ethernet 31, and the pachi-slot machine has one parent that includes the image control circuit 42 having the image ROM 43. Machine H and image ROM 43
A plurality of (n in this case) pachi-slot machines equipped with the image control circuit 42 ′ that does not include the slaves T _{1 to} T _n .

[0037] In the game machine communication system shown in FIG. 3, the image control circuit 42 'of the image control circuit 42 and sub-terminal _T 1 through T _n of the master unit H, respectively provided a buffer RAM 44. By providing the buffer RAM 44, when the parent device H receives the image request command from the child devices T _{1 to} T _n , all of the image data related to the request is stored in the buffer RAM 44 at once, and the child device Machine T ₁ ~
The necessary data can be transferred to T _{n in} order. As a result, the waiting time required for data reception on the slave side can be reduced, and the data transfer time can be shortened. In the image control circuit 42 'of the child device T ₁ through T _n, it can also be written to temporarily buffer RAM44 image data transferred from the master unit H, the image data from the buffer RAM44 optionally It is possible to read out and display the effect. That is, the buffer RA
M44 works effectively when the image data transferred by the image control circuit 42 'cannot be processed at one time.

FIG. 4 shows in more detail the circuit configurations of the master unit H and the slave unit T ₁ shown in FIG.

The image control circuit 42 of the parent device H includes a CPU 50 which is an arithmetic processing unit, a control ROM 51 which is a read-only storage element, and a work R which is a readable / writable storage element.
AM 52, a communication interface 5 that inputs data from the main control circuit 41 to the image control circuit 42 and outputs data from the image control circuit 42 to the liquid crystal display device 5.
3. Image LS for controlling image display on the liquid crystal display device 5
VDP (Video Display Processor) 54 as I,
An image ROM 43 that stores image data necessary for rendering, a buffer RAM 44, another child device or a hall computer 30.
A communication interface 55 that inputs and outputs data to and from
And D for controlling the input / output of data via the DMA bus
The MA controller 60 is provided.

The control ROM 51, work RAM 52, communication interface 53, and VDP 54 are the CPU 50.
And CPU bus. That is, each means connected by the CPU bus always exchanges data via the CPU 50. The CPU 50 collects a command from the main control circuit 41 based on a control program stored in the control ROM 51, and performs necessary processing according to the command (for example, determination of effect contents, display control in the liquid crystal display device 5). Etc.). The control ROM 51 stores a program for monitoring and collecting commands from the main control circuit 41 and a program for performing control according to the commands, and the work RAM 52 is a work area when various processes are executed by the CPU 50. Used as. VDP
Reference numeral 54 retrieves necessary image data from the image ROM 43 based on a command transmitted from the CPU 50 via the CPU bus, and controls the display of an image on the liquid crystal display device 5 via the communication interface 53.

The VDP 54 and the communication interface 55, and the buffer RAM 44 and the communication interface 55 are connected by a DMA bus via a DMA controller 60. According to this DMA bus connection, data can be exchanged between the communication interface 55 and the VDP 54 and the buffer RAM 44 without going through the CPU 50. That is, since it is possible to exchange image data with the outside without imposing a burden on the CPU 50, the processing being executed by the CPU 50 is not hindered. Moreover, since it is not accompanied by the processing of the CPU 50,
High-speed, large-capacity image data transfer is possible.

The buffer RAM 44 is used as a temporary storage area for the image data when the image data is transferred from the image ROM 43 to the other slaves T _{1 to} T _n . Specifically, when the VDP 54 receives an image request command from another child device T _{1 to} T _n , the VDP 54 retrieves all the requested image data from the image ROM 43, stores it in the buffer RAM 44 at once, and sequentially outputs the image data. To the other slaves T _{1 to} T _n that are the transmission source of the request command,
The image data is transferred via the Ethernet 31. That is, the image data taken out from the image ROM 43 is transferred via the buffer RAM 44 to the other slaves T _{1 to} T _n .

The image control circuit 42 of the slave unit _{T 1} 'is, CPU
50 ', control ROM 51', work RAM 52 ', data input from the main control circuit 41' to the image control circuit 42 ', and liquid crystal display device 5'from the image control circuit 42'.
A communication interface 53 'for outputting data to
Image LSI for controlling image display on liquid crystal display device 5 '
VDP 54 ', a data RAM 57' for storing image data necessary for rendering on the liquid crystal display device 5 ', and a master H
Buffer RAM 44 'for temporarily storing the image data transferred from the image ROM 43, the communication interface 55' for inputting / outputting data to / from other slaves or the hall computer 30, and the input of data via the DMA bus. A DMA controller 60 'that controls the output is provided. That is, the image control circuit 42 ′ of the child device T ₁ uses the image R
It is configured by the same circuit as the image control circuit 42 of the parent device H except that the OM 43 is replaced by the data RAM 57 '.

[0044] 'also in the control ROM 51' image control circuit 42 of the slave unit _{T 1,} a work RAM 52 ', the communication interface 53', and VDP54 'is, CPU 5
0'is connected to the CPU bus. The CPU 50 ′ is based on the control program stored in the control ROM 51 ′,
It collects commands from the main control circuit 41 'and performs necessary processing according to the commands. The control ROM 51 'stores a program for monitoring and collecting commands from the main control circuit 41' and a program for performing control according to the commands, and the work RAM 52 'executes various processes in the CPU 50'. When used as a work area. The VDP 54 'takes out necessary image data from the data RAM 57' based on the command from the CPU 50 'and controls the display of the image on the liquid crystal display device 5'via the communication interface 53'. The image data stored in the data RAM 57 'is the image data transferred from the image ROM 43 of the master H.
When the VDP 54 ′ receives a command to execute the effect display from the CPU 50 ′, the VDP 54 ′ transmits an image request command requesting an image necessary for the effect to the VDP 54 of the parent device H via the Ethernet 31 and the parent device H. Image ROM 43
Obtain more necessary image data. That is, the cordless handset T ₁
Then, without storing the image data, the image data is obtained from the parent device H as necessary, and the effect display is performed.

Further, the image control circuit 42 of the handset _{T 1} '
Also in VDP54 'and the communication interface 5
5 ', the buffer RAM 44', and the communication interface 55 'are connected by a DMA bus via a DMA controller 60', and image data can be exchanged with the outside without burdening the CPU 50 ', and at the same time, at high speed. It is possible to read a large amount of image data.

The buffer RAM 44 'stores the image R of the master H.
It is used as an area for temporarily storing the image data transferred from the OM 43 via the Ethernet 31. That is, when the transfer of the image data from the parent device H side is confirmed in the communication interface 55 ′, the image data is temporarily stored in the buffer RAM 44 ′. The image data stored in the buffer RAM 44 ′ is
The data is sequentially transferred to the data RAM 57 '. When the image data transferred from the parent device H is transmitted to the VDP 54 'at one time, the VDP 54' may not be able to process the image data and the image data may be congested. However, the image data once transferred to the buffer RAM 44 '. By storing the, the problem is solved and smooth data transfer becomes possible. Further, the image data stored in the buffer RAM 44 'can also be used as backup data when a trouble such as the loss of data in the data RAM 57' occurs. Also, as mentioned above,
The image data stored in the buffer RAM 44 'is converted to the data R
Instead of storing it in the AM 57 ', the image data may be directly read from the buffer RAM 44' and the display control of the liquid crystal display device 5'may be performed.

FIG. 5 shows still another example of the circuit configuration of the master H and the slave T ₁ .

The image control circuit 42 of the master H shown in FIG.
Then, the control ROM 51, the work RAM 52, the communication interface 53, and the VDP 54 are the CPU 50 and the D.
It is connected to the MA controller 60 via a CPU / DMA bus. The CPU / DMA bus is configured so that the CPU bus and the DMA bus can be switched as needed. For example, when functioning as a CPU bus, the CPU 50
Data is exchanged via the CPU, and when it functions as a DMA bus, the data is exchanged without going through the CPU 50. Further, the data RAM 57 connected to the VDP 54, the communication interface 55, and the image RO
The M43 and the communication interface 55 are connected by a DMA bus via the DMA controller 60.

In the case of the circuit configuration of the image control circuit 42 shown in FIG. 5, the VDP 54 is a C functioning as a CPU bus.
Based on the command transmitted from the CPU 50 via the PU / DMA bus, the image data required for image display control on the liquid crystal display device 5 is fetched from the image ROM 43. The image data is transferred to the VDP 54 via the data RAM 57 via the DMA bus. Further, according to the circuit configuration of the image control circuit 42 shown in FIG. 5, if necessary, C
PU / DMA bus function as DMA bus, CPU
It is also possible to transfer the image data fetched from the image ROM 43 to the VDP 54 via the work RAM 52 without passing through 50.

Further, since the image ROM 43 is connected to the communication interface 55 by the DMA bus, when the image request command is received from another child device T _{1 to} T _n , the image ROM 43 receives the image corresponding to the request. The data is sequentially transmitted to the other slaves T _{1 to} T that are the transmission sources of the image request commands.
_n is transferred via the Ethernet 31.

The image control circuit 42 of the slave unit _{T 1} shown in FIG. 5 '
Then, the control ROM 51 ', the work RAM 52', the communication interface 53 ', and the VDP 54' are similar to the CPU 50 'and D in the same manner as the image control circuit 42 of the parent device H.
It is connected to the MA controller 60 'by a CPU / DMA bus. Also, the data RAM 5 connected to the VDP 54 '
7 ', communication interface 55', and buffer RA
The M44 'and the communication interface 55' are connected by the DMA bus via the DMA controller 60 '.

In the case of the circuit configuration of the image control circuit 42 'shown in FIG. 5, the VDP 54' has a liquid crystal display device 5'based on a command transmitted from the CPU 50 'via the CPU / DMA bus functioning as a CPU bus. The image data necessary for controlling the display of the image in (4) is taken out from the buffer RAM 44 '. The image data is transferred to the VDP 54 'via the data RAM 57' via the DMA bus. The image data stored in the buffer RAM 44 'is VDP5
4 ', which is transferred from the image ROM 43 of the parent device H via the Ethernet 31 in response to the request from 4'. That is, the buffer RAM 44 'is the communication interface 5
When the transfer of the image data from the parent device H side is confirmed in 5 ', the image data is temporarily stored and then sequentially transferred to the data RAM 57'. Further, according to the circuit configuration of the image control circuit 42 'shown in FIG. 5, the CPU / DMA bus is made to function as a DMA bus as necessary, and the buffer is provided not via the CPU 50' but via the work RAM 52 '. The image data fetched from the RAM 44 'can also be transferred to the VDP 54'.

Also, without going through the buffer RAM 44 ',
The image data transferred from the image ROM 43 of the parent device H is
V via data RAM 57 'or work RAM 52'
It may be transferred to the DP 54 '.

FIG. 6 shows still another embodiment of the communication system between gaming machines in which the parent machine H and the child machines T _{1 to} T _n are connected by the Ethernet 31. In the example shown in FIG. 6, only one master H is provided with an image control circuit 42 including a control ROM 51 in which a control program for effect display is stored and an image ROM 43 in which image data necessary for effect is stored.
In the other plural (n in this case) slave units T _{1 to} T _n , the main control circuit 4 is provided without providing the image control circuit as described above.
This is the case when it is configured with only 1 '. In this case, the child device T ₁ ~
The effect display in T _n is performed by reading the control program and image data required for effect display from the master H.

Specifically, when the game is started in the child machines T _{1 to} T _n which are not equipped with the image control circuit, the image of the parent machine H is displayed from the main control circuit 41 ′ of the child machines T _{1 to} T _n. A command including information such as an internal winning combination is transmitted to the control circuit 42 via the Ethernet 31. And the master H
In the image control circuit 42, the control program for determining the effect contents in the slaves T _{1 to} T _n that is the transmission source of the command and executing the effect is stored in the control ROM 51 as image data necessary for the effect. From the image ROM 43 via the Ethernet 31, the child devices T ₁ to
Transferred to T _n . In the handset T ₁ through T _n, on the basis of a control program and image data transferred from the master unit H, 'in a liquid crystal display device 5' main control circuit 41 display control is performed.

In the above embodiment, Ethernet is used as the communication system between the gaming machines, but the invention is not limited to this.
Other communication methods may be used. Further, the configuration may be made up of only the master H and the slaves T _{1 to} T _n , excluding the hall computer 30 described above.

[Brief description of drawings]

FIG. 1 is a perspective view showing an appearance of a gaming machine to which the present invention is applied.

FIG. 2 is a block diagram showing a first embodiment of a communication system between gaming machines.

FIG. 3 is a block diagram showing a second embodiment of the communication system between gaming machines.

FIG. 4 is a block diagram showing a detailed circuit configuration of a master unit and a slave unit.

FIG. 5 is a block diagram showing another example of detailed circuit configurations of a master unit and a slave unit.

FIG. 6 is a block diagram showing yet another embodiment of the communication system between gaming machines.

[Explanation of symbols]

1 ... pachi-slot machine, 1a ... cabinet, 1b ... front door, 2 ... panel display, 3L ... left reel, 3C ... center reel, 3R ... right reel, 4L ... left display window, 4C ... center display window, 4R ... right Display window, 5 ... Liquid crystal display device, 5a ... Display screen, 6 ... Start lever, 7L ... Left stop button, 7C ...
Middle stop button, 7R ... right stop button, 8a ... cross down line, 8b ... top line, 8c ... center line, 8d ... bottom line, 8e ... cross up line,
9a ... 1-BET lamp, 9b ... 2-BET lamp, 9
c ... maximum BET lamp, 10 ... pedestal, 11 ... 1-BE
T switch, 12 ... 2-BET switch, 13 ... Maximum B
ET switch, 14 ... C / P switch, 15 ... medal payout port, 16 ... medal receiving section, 17 ... WIN lamp, 18
... Payout display part, 19 ... Credit display part, 21L ... Left speaker, 21R ... Right speaker, 22 ... Medal slot, 2
3 ... Payout table panel, 26 ... Cross button, 27 ... ○ button, 28 ... X button, 31 ... Ethernet.

Claims (8)

[Claims] 1. A communication system between gaming machines in which a plurality of gaming machines having a display means for displaying identification information related to a game are arranged, and each gaming machine is provided with a communication means capable of data communication to form a data communication network. The plurality of gaming machines are divided into a parent machine having a storage means in which data necessary for display on the display means is stored, and a child machine not having the storage means, Machine is configured to receive data from the master machine via the data communication network as necessary and display the identification information on the display means based on the data. system. 2. The inter-gaming machine communication system according to claim 1, wherein a buffer RAM is connected to the communication means of the parent machine. 3. The communication system between gaming machines according to claim 1 or 2, wherein the communication means of the master machine and the storage means are D.
A communication system between gaming machines characterized by being connected by an MA bus. 4. The inter-gaming-machine communication system according to claim 3, further comprising: a communication means of the master machine, and a data RAM for storing data taken out from the storage means when the display means of the master machine displays. Are connected by a DMA bus, a communication system between gaming machines. 5. The inter-gaming machine communication system according to any one of claims 1 to 4, wherein a buffer RAM is connected to the communication means of the slave machine. 6. The inter-gaming-machine communication system according to any one of claims 1 to 5, wherein data for storing data necessary for executing display on the communication means of the child machine and the display means of the child machine. A communication system between gaming machines, characterized in that the RAM and the RAM are connected by a DMA bus. 7. The inter-gaming machine communication system according to any one of claims 1 to 6, wherein the data stored in the storage means is moving image data. 8. The communication system between gaming machines according to claim 1, wherein the data communication network is formed by Ethernet (registered trademark).