JP2003060988A - Image information changeover device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image information changeover device that can stably and surely switch image information, without making the configuration complicated. SOLUTION: The image information changeover device is configured to comprise a plurality of buffers that individually receive a plurality of image information items, a selection means that selects single image information externally designated among the image information items received via the buffers, a mutual synchronization means that makes frequency composite in parallel, in response to a plurality of synchronization signals individually synchronous with a plurality of the image information items and generates in parallel a plurality of sub synchronization signals in synchronism with the synchronization signal, corresponding to the single image information externally designated among a plurality of the synchronization signals, and a control means that conducts prescribed frequency composite, in response to the single sub synchronization signal corresponding to the single image information externally designated, among a plurality of the sub synchronization signals, to determine the time, when reading of a plurality of the buffers is made in parallel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image information switching device for selecting a single image information designated from the outside out of a plurality of image information given in parallel asynchronously as a target of predetermined processing.

[0002]

2. Description of the Related Art In recent years, in the field of broadcasting, it is possible to provide multimedia transmission, real-time cooperation with viewers, and other services by applying highly advanced digital transmission technology and information processing technology, and Research and development are underway on various high-value broadcasting formats. Conventionally, for example, the exchange of programs and materials (hereinafter, both are simply referred to as “materials”) exchanged between broadcasting stations via a communication network is performed with materials supplied via a communication line.
This has been realized by equipping each broadcasting station with a device for selecting a desired material to be transmitted or edited among the materials obtained in advance.

[0003]

By the way, in the process of selecting the desired material described above, in general, even though the images of the individual materials are given as the video signals generated asynchronously with each other, different video signals are generated. It is not allowed that the speed changes each time is selected or that video frames are dropped or overlapped. Therefore, for example, the device that realizes the above-described material transmission and relay must constantly maintain synchronization with a common synchronization signal.

Conventionally, if these devices do not have the function of synchronizing with the common synchronizing signal described above,
Due to the difference in speed of individual video signals in the process of transferring the selected video signal to the clock signal of a predetermined speed in the front stage or inside of each device and in the process of changing the video signal. "Video synchronization device" that appropriately performs "replenishment of shortage" and "disposal of excess" of video information
Was provided.

However, the disturbance of the video signal caused by such "replenishment of shortage" and "disposal of excess" is
It does not match the high quality that is strictly required for image transmission, and especially in a system where image information is transmitted based on a digital transmission method, it takes a long time to establish synchronization after the loss of important information such as a synchronization word. Often unacceptable because it could cost.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image information switching device which can stably and reliably achieve switching of high quality image information to be selected without complicating the structure.

[0007]

FIG. 1 is a block diagram of the first principle of the present invention. In the invention according to claim 1, the mutual synchronization means 13 performs frequency synthesis in parallel according to a plurality of synchronization signals individually synchronized with a plurality of image information, and from among the plurality of synchronization signals, from the outside. A plurality of sub-sync signals synchronized with the sync signal corresponding to the specified single image information are generated in parallel. The control means 14 performs a predetermined frequency synthesis in accordance with a single sub-sync signal corresponding to the above-mentioned single image information designated from the outside among the plurality of sub-sync signals thus generated. , Multiple buffers 11-1
Determines when ~ 11-N reads should occur in parallel. The selecting means 12 selects a single image information designated from the outside among the image information read in parallel from the plurality of buffers 11-1 to 11-N in this way.

That is, even if the single image information designated from the outside and selected by the selecting means 12 is asynchronously changed to the above-mentioned plurality of image information at any time, the plurality of buffers 11 are provided. The image information accumulated prior to -1 to 11-N is sequentially read at a common phase and speed. Therefore, the quality of the image indicated by the single image information selected by the selection unit 12 is stable without synchronization being established in advance between the individual devices that output the plurality of image information in parallel. Maintained high.

FIG. 2 is a block diagram of the second principle of the present invention. In the invention according to claim 2, the area management means 15
Performs frame synchronization with individual images represented by a plurality of image information, and performs area management related to writing and reading of the plurality of buffers 11-1 to 11-N for each frame of these images. The selection means 12 includes a plurality of buffers 11-1.
From the image information given through 11-N, a single image information designated from the outside is selected.

That is, the single image information designated from the outside and to be selected by the selecting means 12 is changed asynchronously with the above-mentioned plurality of image information, and the speed and phase of these plurality of image information are different. , Or even if it fluctuates, the single video information can be switched in frame units with high accuracy. Therefore, the selection means 12
The quality of the single image information transmitted to the subsequent stage is stably maintained high.

According to a third aspect of the invention, in the image information switching device according to the second aspect, the control means 16 is
Of the plurality of buffers 11-1 to 11-N, in synchronization with the reading of image information from a specific buffer corresponding to a single image information designated from the outside, writing to a buffer other than the specific buffer is performed. Determines when the read and should occur.

That is, the selection means 12 is provided with the image information read from the plurality of buffers 11-1 to 11-N in parallel for each frame of the image indicated by the plurality of image information, and is externally supplied. Even if the specified single image information is changed at a time other than such a frame boundary, this single image information can be selected promptly without any change in the phase or cycle for each frame. Selected by means 12.

Therefore, the selecting means 12 can select desired image information designated from the outside within a shorter time than the frame period, and the responsiveness can be improved without significantly degrading the image quality. . According to a fourth aspect of the invention, in the image information switching device according to any one of the first to third aspects, the monitoring means 17 is designated among the plurality of buffers 11-1 to 11-N. The information amount of the image information recorded in the specific buffer corresponding to the single image information is monitored. The control means 14, 16 compare the amount of information thus monitored with a predetermined threshold value,
The frequency of reading is set to be high over a period in which the former exceeds the latter.

That is, a plurality of buffers 11-1 to 11-N
Among these, the information amount of the image information accumulated in the buffer corresponding to the single image information designated from the outside is maintained below the above-mentioned threshold value. Therefore, the responsiveness and the real-time property are stably kept high as compared with the case where no pawl is set for such an amount of information.

According to a fifth aspect of the invention, the storage means comprises:
A plurality of pieces of image information are written and stored by clock signals having different frequencies. The frequency dividing means performs counting based on each of these clock signals to output a plurality of frequency-divided clock signals obtained by frequency-dividing each of the clock signals. The selecting means initializes each count of the frequency dividing means by selecting any one of these divided clock signals and supplying it to the frequency dividing means. The phase-locked oscillating means generates a signal phase-synchronized with the frequency-divided clock signal thus selected, and supplies it as a common reading clock for a plurality of image information from the storage means.

That is, even when these image information are given to the storage means asynchronously with each other, the plurality of image information accumulated prior to the storage means are sequentially read out at a common phase and speed. Therefore, the quality of the image indicated by the individual image information is stably maintained high without synchronization being established in advance between the individual devices that output the plurality of image information in parallel.

In the first invention relating to the invention described in claims 1 to 5, the preprocessing means 18 is individually provided through all or part of the plurality of buffers 11-1 to 11-N. Match all or part of the format, word length, and speed of the image information to be delivered with the corresponding buffer. That is, a plurality of pieces of image information are stored in a plurality of buffers 11-1 to 11-11.
The invention described in any one of claims 1 to 5 can be applied even when given in a format, word length, speed, or the like that is not directly stored in -N.

Therefore, flexible adaptability to various devices and systems is ensured. Claims 1 to 5
In the second invention related to the invention described in 1), the post-processing means 19 includes all or a part of the format, word length and speed of the single image information selected by the selection means 12, and the selection means 12 thereof. Match with the circuit or transmission line to be arranged in the subsequent stage.

That is, even if the format, word length, speed, etc. of the single image information selected by the selecting means 12 do not match the circuit or transmission line arranged after the selecting means 12, The invention described in any one of claims 1 to 5 can be applied. Therefore, flexible adaptability to various devices and systems is secured. In the invention as a subordinate concept of the invention described in claim 4, in the image information switching device according to claim 4, the control means 14 includes the selection means 1
The reading frequency is set to a value less than or equal to the maximum frequency at which the second stage can respond.

That is, a plurality of buffers 11-1 to 11-N
Of the above, the information amount of the image information accumulated in the buffer corresponding to the single image information specified from the outside quickly converges to the above-mentioned threshold value or less while satisfying the condition that the latter stage can respond. And is maintained. Therefore, the reliability and performance are stably maintained high as compared with the case where no pawl is set with respect to the frequency of reading in which the amount of image information accumulated in these buffers 11-1 to 11-N is reduced. .

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 3 is a diagram showing a first embodiment of the present invention. In the figure, the memory 31-
Video signals A and B are input to the write data inputs of A and 31-B, respectively. The read data outputs of the memories 31-A and 31-B are respectively connected to the corresponding inputs of the video selection unit 32, and the video signal is obtained at the output of the video selection unit 32. A selection signal output by the switching control unit 33 is input to the control input of the video selection unit 32, and clocks individually synchronized with the video signals A and B are input to the write clock inputs of the memories 31-A and 31-B, respectively. Signal A, B
Is entered. These clock signals A and B are connected to the corresponding inputs of the memory control unit 34, and the memory control unit 34 gives the write control signal A and the read control signal A to the memory 31-A and writes them to the memory 31-B. A control signal B and a read control signal B are given. The clock signals A and B and the selection signal described above are supplied to the clock adjusting unit 40.
Output to the memory 3
Connected to the read clock inputs of 1-A and 31-B.

The clock adjusting section 40 is composed of the following elements. .Frequency divider 4 to which clock signals A and B are input respectively
1-A, 41-B-Switch 42 having two inputs respectively connected to the outputs of the frequency dividers 41-A, 41-B and a control input to which the selection signal described above is inputted- PLL section 43 connected in cascade to the output and arranged as the final stage. The first input directly connected to the output of frequency divider 41-B and the second input directly connected to the output of frequency divider 41-A. In addition to the above, a switch 44 having a control input to which the selection signal described above is input and having an output connected to the load terminal of the frequency divider 41-A.
-A ・ The above-mentioned selection signal is input together with the first input directly connected to the output of the frequency divider 41-A and the second input directly connected to the output of the frequency divider 41-B. A switch 44 having a control input and an output connected to the load terminal of the frequency divider 41-B.
-B In addition, the circuit configured by the frequency dividers 41-A and 41-B, the switch 42, and the switches 44-A and 44-B is referred to as a "clock selection unit" for simplicity and The reference numeral “45” is given and shown.

FIG. 4 is an operation time chart of the first embodiment of the present invention. Regarding the frequencies (cycles) of the clock signals A and B, both nominal values are generally set to the same value, but in the following, in order to clearly show the operation of this embodiment described later, FIG. Indicates the difference between them as a significantly different value. The operation of the first embodiment of the present invention will be described below with reference to FIGS. 3 and 4.

First, in the following, for items common to both the subscripts "A" and "B" added to the code or signal name, the subscript "C" indicating that is applied, and Of the subscripts “A” and “B”, subscripts that do not correspond to the subscript “C” will be described by applying the lowercase subscript “c”. The memory control unit 34 determines the clock signal C based on the cycle of the image signal C and the word length of the memory 31-C, the timing, and the frequency division ratio.
By dividing the frequency, the write control signal C indicating the time at which the image information should be written into the memory 31-C for each predetermined word, and the image information previously written in the memory 31-C. A read control signal C indicating a time point to be read is generated in parallel.

The write control signal C and the read control signal C will be described below for the sake of simplicity, as a result of the above-mentioned frequency division, which is cyclically updated and is a memory 31 to be the target of writing and reading. Suppose that the address of the storage area of -C is included.
The memory 31-C sequentially stores the image signal C at a time point uniquely determined based on both the write control signal C thus generated and the clock signal C described above.

Further, the switching control unit 33 includes a memory 31.
-Given as a sequence of words read from A, 31-B 2
A selection signal indicating one of the two image signals to be transmitted to the subsequent stage via the video selection unit 32 as a logical value is given to the video selection unit 32 and the clock adjustment unit 40. In the clock adjustment unit 40, the frequency divider 41-C is given a predetermined frequency division ratio (here, for simplicity, it is assumed that it is “6”) in advance, and the clock signal C is generated at the frequency division ratio. The frequency-divided signal C having a pulse width equal to the cycle of the clock signal C is generated by dividing the frequency.

In the switches 44-C and 44-c, for example, the above-mentioned selection signal is the video signal C (or the clock signal C).
In the case corresponding to, the frequency-divided signal C generated by the frequency divider 41-C is applied to the load terminals of the frequency divider 41-C and the frequency divider 41-c. In the frequency dividers 41-C and 41-c, the above-mentioned frequency division ratio is preset again at the time of the trailing edge of the frequency division signal C (FIG. 4 (1)), and it is performed in advance. The result of the frequency division is invalidated.

That is, the clock signal C corresponding to the logical value of the selection signal is divided by the frequency divider 41-C at a predetermined frequency division ratio, and is thus converted into the frequency division signal C (see FIG. )).
The switch 42 supplies the frequency division signal C corresponding to the logical value of the selection signal among the frequency division signals C and c generated by the frequency dividers 41-C and 41-c to the PLL unit 43. The PLL unit 43 is
A read clock signal C is generated which is synchronized with the frequency-divided signal C and which indicates a cycle and a time point at which the word string accumulated in the memory 31-C should be read. -Give to B in parallel.

Therefore, the sequence of words previously stored in the memory 31-C is sequentially read at a cycle and a time point uniquely determined according to the read clock signal C and the read control signal C described above. It is output and transmitted as a video signal to the circuit in the subsequent stage via the video selection unit 32. Further, the frequency divider 41-c included in the clock adjusting unit 40 is at the time of the trailing edge of the frequency division signal C given by the frequency divider 41-C via the switch 44-c (FIG. 4 (3)). The above-mentioned division ratio is newly set at.

That is, even if the frequencies of the clock signals A and B are different or both are generated asynchronously with each other, the frequency division signal obtained by frequency division of the clock c by the frequency divider 41-c. The phase difference between c and the divided signal C is kept at a small value without being integrated. As described above, according to this embodiment, the phases of the divided signals A and B to be input to the PLL unit 43 via the switch 42 are updated at any time when the logical value of the selection signal provided by the switching control unit 33 is changed. Even if it does, it stays almost constant without a significant jump.

Therefore, the output of the image selection unit 32 is
Regardless of when the logical value of the selection signal is updated, a desired video signal can be obtained without causing disturbance such as loss or duplication. FIG. 5 is a diagram showing a second embodiment of the present invention. In the present embodiment, a switching control unit 33a is provided instead of the switching control unit 33, and a memory control unit 50 described below is provided instead of the memory control unit 34. One output of the switching control unit 33a is connected to the control input of the video selection unit 32, and the other output of the switching control unit 33a is connected to the corresponding inputs of the memory control unit 50 and the clock adjustment unit 40. The corresponding outputs of the memory control unit 50 are connected to the two inputs of the switching control unit 33a.

The memory control unit 50 is composed of the following elements. -Frame detection section 51-A to which video signal A and clock signal A are input-Frame detection section 51-B to which video signal B and clock signal B are input-Cascade connection to frame detection section 51-A and switching A control signal generation unit that receives the selection signal described above by the control unit 33a, has an output connected to one input of the switching control unit 33a, and further outputs the write control signal A and the read control signal A. 52-A: The frame detection section 51-B is connected in cascade, and the switching control section 33a supplies the above-mentioned selection signal and has an output connected to the other input of the switching control section 33a. , A control signal generator 52-B which outputs a write control signal B and a read control signal B. FIG. 6 shows an operation timing chart of the second embodiment of the present invention. It is.

The operation of the second embodiment of the present invention will be described below with reference to FIGS. 5 and 6. Switching control unit 33
The selection signal with the updated logical value is supplied to the memory control unit 50 and the clock adjustment unit 40 prior to the video selection unit 32. The switching control unit 33a provides a selection signal of a new logical value to the video selection unit 32 by linking with the memory control unit 50 based on a procedure described later.

In the memory controller 50, the frame detector 5
1-C analyzes the video signal C based on the format of the video signal C while maintaining the synchronization with the clock signal C, so that the start point of the frame indicated by this video signal (see FIG. 6).
(1)) is detected. The control signal generation unit 52-C, at the end time of each frame in which the starting point is detected by the frame detection unit 51-C, in the period in which the video signal corresponding to the logical value of the selection signal described above corresponds to the video signal C. (Here, for simplification, it is assumed that it is indicated by the read address of the memory 31-C.) Is identified (FIG. 6 (2)), and the same processing as in the above-described first embodiment is performed. Thereby generate the write control signal C and the read control signal (including the read address of the memory 31-C).

Further, during such a period, the control signal generator 52-c causes the start point of each frame detected by the frame detector 51-c (here, for simplification, the memory 3
Assume that the read address is 1-c. ) Is identified (FIG. 6 (3)), and the same processing as in the above-described first embodiment is performed to sequentially generate only the write control signal c.

Further, when the logical value of the selection signal given by the switching control unit 33 changes (FIG. 6 (5)),
The control signal generation unit 52-C continuously outputs the write control signal C and the read control signal C successively until the end of the frame described above is identified first (FIG. 6 (6)). The time point is notified to the control signal generation unit 52-c and the switching control unit 53.

The switching control section 53 sends a selection signal of a new logical value to the video selection section 3 at the time when such notification is identified.
2 (Fig. 6 (7)). The control signal generation unit 52-c acquires the read address corresponding to the beginning of the “latest frame in which the above-mentioned starting point is identified at such a time point”, and continues generation of the write control signal c, A read control signal c including the read addresses subsequent to the read address is generated (FIG. 6 (8)).

That is, even if the selection signals are updated asynchronously with the image signals A and B, the image selection section 32 is irrespective of the difference or fluctuation in the speed or phase of the image signals A and B. In the subsequent stage, the video signal is switched and given in frame units. FIG. 7 is a diagram showing a third embodiment of the present invention.

In this embodiment, the memory control unit 50 is replaced with a memory control unit 51a described below. The memory control unit 50a includes the following elements. -Frame detection section 51-A to which video signal A and clock signal A are input-Frame detection section 51-B to which video signal B and clock signal B are input-Cascade connection to frame detection section 51-A and switching A selection signal is given by the control unit 33a, and
The switching control unit 33a has an output connected to one input of the switching control unit 33a, and further outputs a write control signal A and a read control signal A. The control signal generation unit 53-A and the frame detection unit 51-B are connected in cascade. And is directly connected to the above-mentioned control signal generation unit 53-A via a bidirectional line,
A control signal generation unit 53 that outputs a write control signal B and a read control signal B while being provided with a selection signal by the switching control unit 33a and having an output connected to the other input of the switching control unit 33a. -B FIG. 8 is an operation time chart of the third embodiment of the present invention.

The operation of the third embodiment of the present invention will be described below with reference to FIGS. 7 and 8. Control signal generator 53
-C is read during the period in which the video signal C (clock signal C) corresponds to the logical value of the selection signal C, similarly to the control signal generation unit 52-C provided in the second embodiment described above. The control signal C is generated, and the phase of the read control signal C (here, for simplification, it is assumed to indicate the "rise time") is sequentially notified to the control signal generation unit 53-c.

The control signal generator 53-c generates the read control signal c regardless of whether the video signal c (clock signal c) corresponds to the logical value of the selection signal c. The procedure of the process performed by the control signal generation unit 53-c to generate such a read control signal c will be described with reference to the control signal generation unit 52-c provided in the second embodiment described above. Since the procedure is the same as the procedure of the processing performed, the description thereof is omitted here.

That is, according to this embodiment, the two inputs of the video selection unit 32 are simultaneously input to the memories 31-A and 31 in units of image frames indicated by the image signals A and B.
-The sequence of words read from B is given in parallel. Therefore, even when the logical value of the selection signal is updated at a time other than such a frame boundary time (FIG. 8 (1)), the cycle or phase in frame units does not change at all and the prompt Video signal switching is achieved (Fig. 8 (2),
(3)).

In this embodiment, at the time when the logical value of the selection signal given to the video selection unit 32 is updated, the switching control unit 33a and the control signal generation unit 53 are the same as in the second embodiment described above. -A and 53-B are decided in cooperation with each other. However, the present invention is not limited to such a configuration, and for example, the phase difference between the read control signals A and B generated in parallel under the cooperation of the control signal generation units 53-A and 53-B is allowed. If the value is kept small enough to be maintained, the switching control unit 33 shown in FIG.
It may be provided instead of 3a.

FIG. 9 is a diagram showing a fourth embodiment of the present invention. In this embodiment, a memory control unit 60 is provided in place of the memory control unit 50a, and a PLL unit 70 is provided in place of the PLL unit 43. The clock selection unit 4
The details of the configuration of No. 5 are the same as the configurations of the clock selection unit 45 provided in the above-described first to third embodiments, and are not the features of this embodiment, and therefore are not shown here. .

The memory control unit 60 is composed of the following elements. A frame detection unit 51-A to which the video signal A and the clock signal A are input. A frame detection unit 51-B to which the video signal B and the clock signal B are input. A control signal generation unit 61-A that outputs the write control signal A and the read control signal A while being supplied with the above-mentioned selection signal and having an output connected to one input of the switching control unit 33a. Is connected in series to the section 51-B and is directly connected to the above-mentioned control signal generation section 53-A via a bidirectional line,
A control signal generation unit 61-B that outputs the write control signal B and the read control signal B while having the output connected to the other input of the switching control unit 33a while being supplied with the selection signal described above. The information amount detection unit 6 directly connected to the monitor terminals of the control signal generation units 61-A and 61-B and to which the selection signal described above is input.
The feature of the configuration of the 2 PLL unit 70 is that the following elements are provided.

Switching unit 71 inserted in a predetermined portion of the phase locked loop (here, for simplification, it is processed as “interstage between the phase comparator and the voltage controlled oscillator”). In addition to the first input given the selection signal and the second input connected to the output of the information amount detection unit 62,
A predetermined upper limit value has a third input given in advance, and among the three inputs of the switching unit 71 described above, an input different from the input that is the output of the phase comparator described above,
Information Quantity Verification Unit 72 Having Two Outputs Connected to Selective Inputs FIG. 10 is an operation time chart of the fourth embodiment of the present invention.

The operation of the fourth embodiment of the present invention will be described below with reference to FIGS. 9 and 10. Control signal generator 6
1-A and 61-B are control signal generators 52-A and 52-B included in the second embodiment, control signal generators 53-A included in the third embodiment, Write control signals A and B and read control signals A and B are generated in the same manner as any of 53-B.

The control signal generator 61-C obtains the difference between the read address included in the latest read control signal C and the write address included in the latest write control signal C, for example, to obtain the memory 31-C. The number of words accumulated in (hereinafter, simply referred to as “accumulated information amount C”) is calculated,
The accumulated information C is given to the information amount detector 62. In this way, the information amount detection unit 62 is controlled by the control signal generation units 61-A, 6-A, 6-A.
Of the stored information amounts A and B given in parallel by 1-B, one of the stored information amounts (hereinafter referred to as “monitored information amount”) corresponding to the above-described selection signal is selected.

In the clock adjusting unit 70, the information amount verification unit 7
2 is applied to the voltage-controlled oscillator (not shown) described above because a read clock signal having a frequency higher than the nominal value of the frequency of the read clock signal to be provided to the memories 31-A and 31-B is generated. A control voltage to be performed (hereinafter referred to as “temporary control voltage U”) is given in advance, and the provisional control voltage U is given to the corresponding input of the switching unit 71.

Further, the information amount verification unit 72 compares such monitored information amount with the above-mentioned upper limit value, and only in the period (FIG. 10 (1)) in which the former exceeds the latter (FIG. 10 (1)). It requires disconnection of the synchronous loop and application of the above-mentioned provisional control voltage U to a voltage controlled oscillator (not shown). That is, during a period in which the monitored information amount exceeds the upper limit value, the word of the monitored information amount is accumulated in the memory (memory 31-
The frequency of the read clock signal given to either A or 31-B) is set to a value larger than the above-mentioned nominal value (FIG. 10 (2)).

As described above, according to this embodiment, the memory 3
The number of words stored in 1-A, 31-B is kept small. Therefore, in the device or the image transmission system provided with the image information switching device according to the present embodiment, the propagation delay time and the transmission delay time are surely shortened and stably kept at a small value.

In this embodiment, the phase-locked loop described above is disconnected and the provisional control voltage U for the voltage controlled oscillator is set.
Is applied only during a period in which the monitored information amount exceeds the above-mentioned upper limit value. However, the present invention is not limited to such a configuration. For example, a lower limit value and a provisional control voltage L smaller than the above-described upper limit value and the provisional control voltage U are given in advance, and the monitored information amount has the lower limit value. When the voltage falls, the provisional control voltage L instead of the provisional control voltage U may be applied to the voltage controlled oscillator to maintain the value of the monitored information amount at the lower limit value or the upper limit value.

Further, in the present embodiment, when the monitored information amount is switched in accordance with the above-mentioned selection signal, the magnitude relationship between the monitored information amount and the above-mentioned upper limit value or addition / subtraction value is determined, The provisional control voltage U or the provisional control voltage L is applied to the voltage controlled oscillator according to the result. However, in the present invention, the above-mentioned determination is performed regardless of the video signal indicated by such a selection signal and the setting of the control voltage for the voltage-controlled oscillator according to the result of the determination is appropriately performed, thereby It is also possible to flexibly adapt to the speed of both or one of the signals A and B and the fluctuation of the substantial amount of information.

Further, as prior arts related to the present invention, for example, "Video synchronization switching device" disclosed in Japanese Patent Laid-Open No. 10-200884 and Japanese Patent Laid-Open No. 11-33163.
There is a "synchronous control circuit" published in Japanese Patent No. 8 publication. However, the present invention is different from those of the prior art in that the basic configuration is different, and under the configuration described above, "the error of the video information that could occur at the time of switching in the conventional example is avoided, and the video information is The speed, phase, and other continuity of "is ensured".

Further, the present embodiment is configured by making the above-described modifications to the configurations of the above-mentioned second to third embodiments. However, the present embodiment is not limited to such a configuration, and as long as the error in the phase of the image signal that is switched according to the update of the logical value of the selection signal is a small value that is acceptable, for example, the first It may be configured by making the above-described changes to the configuration of the embodiment.

Further, in the present embodiment, the method of obtaining the values of the provisional control voltages U and L is not shown. However, the values of the provisional control voltages U and L are set to, for example, the image selection unit 3
As long as the frequency of the read clock signal is set to a value that matches the configuration and characteristics of the circuit or transmission line arranged in the second stage (speed at which the circuit can respond, upper limit of transmission speed suitable for the transmission line, etc.) , And may be set to any value.

In each of the above-mentioned embodiments, the image signals A and B are both given as digital signals. However, the present invention is not limited to such a configuration. For example, as shown by the dotted line in FIG. 11, a digital image signal is generated from an analog signal and a clock signal synchronized with the digital image signal is generated in parallel. By arranging the A / D converter to be generated in the first stage, either or both of the image signals A and B may be applied to a device or an analog image transmission system to which an analog signal is given.

Furthermore, in each of the above-mentioned embodiments, the image selection section 3 is read by the memories 31-A and 31-B.
The word lengths and formats of the words selected by 2 are consistent with the form of processing to be performed on these words. However, the present invention is not limited to such a configuration, and, for example, when the speed, the format, etc. do not match the above-described processing mode, as shown by the one-dot chain line or two-dot chain line in FIGS.
The following elements may be provided to achieve that match.

A / D converter or serial-parallel converter arranged in the first stage D / A converter or parallel-serial converter arranged in the last stage Also, in each of the above-described embodiments, the video signal A , B are all generated based on the raster scan method. However, any scanning method should be applied to the generation of such video information.

Further, in each of the above-described embodiments, the image information switching device for selecting either one of the two image signals A and B is configured. However, the present invention is not limited to such an image information switching device, and for example, 3
The same can be applied to the image information switching device that selects any one of the two or more image signals.

Further, in each of the above-described embodiments, the frequency division signal to be given to the PLL units 43 and 70 is the frequency divider 41-A,
41-B directly generated by one of the
The units 43 and 70 perform the indirect frequency synthesis through the phase locked loop to read the read clock signals A and B.
Is being generated. However, the clock adjustment unit 40 is not limited to such a configuration, and as long as the frequency-divided signals A and B and the read clock signals A and B described above are generated reliably,
For example, it may be configured as any circuit that performs frequency synthesis under an appropriate combination of multiplication, division, mixing, and filtering (all or part of which may be achieved as digital signal processing).

Further, in each of the above-mentioned embodiments, the clock signal C and the read clock signal C are given to the memory 31-C. However, the present invention is not limited to such a configuration, and for example, the memory 31-C may be the write control signal C.
If the writing can be performed in synchronization with only the read control signal C and the reading can be performed in synchronization with only the read control signal C,
The write control signal C and the read control signal C may be generated as signals synchronized with the clock signal C and the read clock signal C described above, respectively.

In each of the above-mentioned embodiments, the memories 31-A and 31-B in which writing and reading are performed asynchronously and which can be randomly accessed, and these memories 3 are used.
Buffering of video signals A and B provided in parallel under the cooperation with the memory control units 34, 50, 50a, and 60 that lead the writing and reading of 1-A and 31-B is performed. There is.

However, the present invention is not limited to such a configuration, and if writing and reading based on the first-in-first-out method are possible, for example, any storage device such as a FIFO is applied. Good. Furthermore, the present invention is not limited to the above-described embodiments, and various embodiments can be made within the scope of the present invention, and some or all of the constituent elements may be improved. Good.

Hereinafter, the configurations of the invention disclosed in the above-described embodiments will be organized hierarchically and multi-facetedly, and will be listed sequentially as additional items. (Supplementary Note 1) Out of the plurality of buffers 11-1 to 11-N used for individually delivering a plurality of image information and the image information given via the plurality of buffers 11-1 to 11-N, Selector 1 for selecting a single image information specified from
2 and frequency synthesizing in parallel according to a plurality of synchronizing signals individually synchronized with the plurality of image information, and corresponding to a single image information designated from the outside among the plurality of synchronizing signals. Mutual synchronization means 13 for generating a plurality of sub-synchronization signals in parallel with each other, and a single image designated from the outside of the plurality of sub-synchronization signals generated by the mutual synchronization means 13. Control means 14 for performing a predetermined frequency synthesis according to a single sub-synchronization signal corresponding to information, and determining a time point at which the reading of the plurality of buffers 11-1 to 11n should be performed in parallel. An image information switching device characterized by:

(Supplementary Note 2) Frame synchronization is performed between the plurality of buffers 11-1 to 11-N used for individually delivering a plurality of image information and the individual images indicated by the plurality of image information, and Area management means 15 for performing area management related to writing and reading of the plurality of buffers 11-1 to 11-N for each frame of the image, and the plurality of buffers 11-1 to 11-N. Selection means 12 for selecting a single image information designated from the outside of the image information
And an image information switching device.

(Supplementary Note 3) In the image information switching device according to Supplementary Note 2, the plurality of buffers 11-1 to 11-N are provided.
Of the above, in synchronization with the reading of the image information from a specific buffer corresponding to the single image information specified from the outside, the time point at which writing to and reading from a buffer other than the specific buffer are to be determined. An image information switching device, comprising:

(Supplementary Note 4) In the image information switching device according to any one of Supplementary Notes 1 to 3, among the plurality of buffers 11-1 to 11-N, the designated single image information is stored. The monitoring means 17 for monitoring the information amount of the image information recorded in the corresponding specific buffer is provided, and the control means 14, 16 compare the information amount monitored by the monitoring means 17 with a predetermined threshold value. The image information switching device is characterized in that the former sets the reading frequency higher during a period exceeding the latter.

(Supplementary Note 5) In the image information switching device according to Supplementary Note 4, the control means 14 sets the reading frequency to a value less than or equal to the maximum frequency at which the latter stage of the selecting means 12 can respond. A characteristic image information switching device.

(Supplementary Note 6) In the image information switching device according to any one of Supplementary Notes 1 to 5, it should be individually delivered via all or part of the plurality of buffers 11-1 to 11-N. An image information switching device comprising a preprocessing means 18 for matching all or part of the format, word length, and speed of image information with a corresponding buffer.

(Supplementary Note 7) In the image switching apparatus according to any one of Supplementary Notes 1 to 6, the format, word length, and length of the single image information selected by the selecting means 12 are selected.
An image information switching device comprising a post-processing means 19 for matching all or a part of the speed and a circuit or transmission line to be arranged at a stage subsequent to the selection means 12.

(Supplementary Note 8) Each of the clock signals is divided by performing counting based on each of the storage means for writing and storing a plurality of image information with clock signals of different frequencies and each of the clock signals. Dividing means for outputting a plurality of divided clock signals, and selecting means for initializing each count of the dividing means by selecting any one of the divided clock signals and giving it to the dividing means. And a phase-locked oscillating means for generating a signal that is phase-synchronized with the selected divided clock signal and giving it as a common read clock for the plurality of image information from the storage means. A characteristic image information switching device.

[0073]

As described above, according to the invention described in claim 1 and the invention described in claim 5, the quality of each image shown by a plurality of image information is output in parallel. It is maintained stable and high without pre-established synchronization between individual devices. According to the second aspect of the invention, the quality of the single image information transmitted to the subsequent stage of the selecting means is stably maintained high. Further, according to the invention described in claim 3, the selecting means can select desired image information designated from the outside within a shorter time than the frame period, and the responsiveness is not significantly deteriorated. Is improved.

Further, according to the invention described in claim 4, in the case where no stopping is set for the information amount of the image information accumulated in the buffer corresponding to the single image information designated from the outside among the plurality of buffers. Compared with, the responsiveness and real-time property are stably maintained high. Further, in the first and second inventions related to the inventions according to the first to fifth aspects, flexible adaptability to various devices and systems is secured.

Further, in the invention of the subordinate concept of the invention described in claim 4, as compared with the case where no pawl is set in regard to the frequency of reading in which the information amount of the image information accumulated in the plurality of buffers is reduced, the reliability is improved. The sex and performance are stably kept high. Therefore, in the devices and systems to which these inventions are applied, a desired number of various image information can be stably and inexpensively selected as a target of a predetermined process without lowering the overall reliability and performance. .

[Brief description of drawings]

FIG. 1 is a first principle block diagram of the present invention.

FIG. 2 is a second principle block diagram of the present invention.

FIG. 3 is a diagram showing a first embodiment of the present invention.

FIG. 4 is an operation time chart of the first embodiment of the present invention.

FIG. 5 is a diagram showing a second embodiment of the present invention.

FIG. 6 is an operation time chart of the second embodiment of the present invention.

FIG. 7 is a diagram showing a third embodiment of the present invention.

FIG. 8 is an operation time chart of the third embodiment of the present invention.

FIG. 9 is a diagram showing a fourth embodiment of the present invention.

FIG. 10 is an operation time chart of the fourth embodiment of the present invention.

FIG. 11 is a diagram (1) showing another configuration example of each of the above-described embodiments.
Is.

FIG. 12 is a diagram showing another configuration example of each of the above-described embodiments (2)
Is.

[Explanation of symbols]

11 buffers 12 Selection means 13 Mutual synchronization means 14, 16 Control means 15 Area management means 17 Monitoring means 18 Pretreatment means 19 Post-processing means 31 memory 32 video selection section 33, 33a Switching control unit 34, 50, 50a, 60 Memory controller 40 Clock adjuster 41 frequency divider 42,44 switch 43,70 PLL section 45 Clock selection section 51 frame detector 52, 53, 61 control signal generator 62 Information amount detector 71 Switching unit 72 Information amount verification department

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroshi Otsuru             3-22-8, Hakata Station, Hakata-ku, Fukuoka City, Fukuoka Prefecture             Issue Fujitsu Kyushu Digital Technology Co., Ltd.             Inside the company (72) Inventor Yuji Nomura             3-22-8, Hakata Station, Hakata-ku, Fukuoka City, Fukuoka Prefecture             Issue Fujitsu Kyushu Digital Technology Co., Ltd.             Inside the company (72) Inventor Iwahashizume             3-22-8, Hakata Station, Hakata-ku, Fukuoka City, Fukuoka Prefecture             Issue Fujitsu Kyushu Digital Technology Co., Ltd.             Inside the company F-term (reference) 5C020 AA11 AA12 AA14                 5C023 AA21 BA15 CA01 DA01                 5C082 AA02 BA12 BA41 BB03 BC03                       BC16 BC19 CB03 DA76 MM06                       MM09 MM10

Claims (5)

[Claims] 1. A plurality of buffers provided for individually delivering a plurality of image information, and image information provided via the plurality of buffers,
Selection means for selecting a single image information specified from the outside, frequency synthesis is performed in parallel in accordance with a plurality of synchronization signals individually synchronized with the plurality of image information, and among these plurality of synchronization signals A mutual synchronization unit that generates a plurality of sub-synchronization signals in synchronization with a synchronization signal corresponding to a single image information designated from the outside, and a plurality of sub-synchronization signals generated by the mutual synchronization unit. Among them, a predetermined frequency synthesis is performed according to a single sub-sync signal corresponding to a single image information designated from the outside,
An image information switching device, comprising: a control unit that determines a time point at which the reading of the plurality of buffers should be performed in parallel. 2. A plurality of buffers used for individually delivering a plurality of image information and frame synchronization with the individual images indicated by the plurality of image information, and the plurality of buffers are provided for each frame of these images. Area management means for performing area management relating to writing and reading of a buffer, and image information given via the plurality of buffers,
An image information switching device comprising: a selection unit for selecting a single image information designated from the outside. 3. The image information switching device according to claim 2, wherein in synchronization with reading of image information from a specific buffer corresponding to the single image information designated from the outside of the plurality of buffers. And an image information switching device, comprising control means for determining a time point at which writing to and reading from a buffer other than the specific buffer should be performed. 4. The image information switching device according to claim 1, wherein the image information is recorded in a specific buffer corresponding to the designated single image information among the plurality of buffers. Monitoring means for monitoring the information amount of the image information being displayed, the control means compares the information amount monitored by the monitoring means with a predetermined threshold value, and the former is read over a period exceeding the latter. An image information switching device, characterized in that the frequency of setting is set high. 5. A storage unit for writing and storing a plurality of image information with clock signals having different frequencies, and a plurality of storage units for dividing each of the clock signals by counting based on each of the clock signals. Dividing means for outputting the divided clock signal, and selecting means for initializing each count of the dividing means by selecting any one of the divided clock signals and giving it to the dividing means, Phase-locked oscillating means for generating a signal phase-synchronized with the frequency-divided clock signal being selected and giving it as a common read clock for the plurality of image information from the storage means. Image information switching device.