JPH0759054A - Video signal converter - Google Patents

Abstract

PURPOSE:To prevent a white/read operation from outrunning wind being outrun by setting a field or a frame frequency of a video signal of a 2nd video signal system so as to have a predetermined synchronization relation with that of a 1st video signal system. CONSTITUTION:A write clock Wck phase-locked to a horizontal synchronizing signal Hin and having a frequency of a multiple of (m) is outputted from a VCO 26 of a PLL circuit and an input video signal is converted at an A/D converter 21 based on the clock Wck. A frame memory controller 35 controls write of a digitized input video signal to a frame memory 31 based on a clock Hw outputted from a frequency divider 27 of the PLL circuit and a frame pulse Fw outputted from a frame pulse generator 28. A write address counter of the controller 35 is reset for each frame by the pulse Fw. RGB video data written in the memory 31 are sequentially read by other TV under the control of the controller 35.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal converter for enabling the use of video signals between systems of different systems, for example, between different television systems or between television systems and computer image signal systems. The present invention relates to a video signal conversion device that enables conversion of a video signal between the two.

[0002]

2. Description of the Related Art As is well known, the NTSC system is adopted in television broadcasting in Japan and the United States, and the PAL system or SECAM system is adopted in Europe. On the other hand, computer devices are currently displaying images on the display by their own TV system. It should be noted that the term “TV system” as used herein includes both a television video signal system and a computer image signal system (the same applies hereinafter).

It has been impossible in the past to display video signals of different systems on the same display, but recently, a special display corresponding to a plurality of scanning systems has been put on the market, and the same display is available. With multiple TVs
The system image display is possible.

On the other hand, various devices for converting one TV system into another TV system have been devised. By using such a system conversion device, for example, a video signal of a computer can be transmitted to NTS.
Converted to C format video signal and split-screen display on the same display as other NTSC format video, or conversely, N
It is possible to easily display a TSC video signal together with a computer video signal on a screen.

A conventional TV system conversion apparatus will be described with reference to FIGS. 3 and 4.

In FIG. 3, input video signals (Rin, G
in, Bin) are converted into digital signals by the A / D converter 21 and written into a predetermined address of the frame memory 31 based on the field or the frame frequency. R, G, and B are red,
The three primary colors of green and blue are shown (same below).

The video data written in the frame memory 31 is sequentially read out in synchronization with the field or frame frequency of another TV system. At this time, when the video data is insufficient, the data interpolator 41 replenishes the insufficient portion by appropriate approximate interpolation, and conversely, when it is excessive, the video data is appropriately thinned. The image data thus obtained is D /
The video signal (Rout, Gout, Bou) of the desired TV system is converted into an analog signal by the A converter 61.
is output as t).

An example of a circuit for performing such control is shown in FIG. In the figure, a phase locked loop (PLL) circuit composed of a phase comparator 25, a voltage controlled oscillator 26, and a frequency divider 27 receives a horizontal sync signal Hin and generates write clocks Wck and Hw. Further, the frame pulse generator 28 inputs the horizontal synchronizing signal Hin and the vertical synchronizing signal Vin and generates a frame pulse Fw. The frame memory controller 35 controls the writing of the frame memory 31 in accordance with these clock pulses.

The video data written in the frame memory 31 is read by different TV systems. First, different TVs based on a fixed reference clock from the reference oscillator 54.
Read clocks Rck, Hr, and Fr according to the method
Are generated respectively, and the frame memory controller 35 controls the reading of the frame memory 31 according to them. The horizontal synchronizing signal Hout and the vertical synchronizing signal Vout of different TV systems are generated by the output synchronizing signal generator 45 according to the same read clock.

An example of such a TV system conversion device is disclosed in Japanese Patent Application Laid-Open No. 59-104866. The conversion device described in this publication performs conversion between two types of TV systems whose vertical scanning frequencies are slightly different from each other through a memory device capable of writing and reading independently of each other. At that time, in order to prevent the movement of the screen from becoming discontinuous, it is necessary to delete or insert the screen corresponding to the difference in vertical scanning frequency between the two types of TV systems within the range of the memory capacity of the memory device. It is controlled to be performed when the correlation value between adjacent frames or fields is out of the predetermined range. Further, this prevents the phenomenon of passing / passing between the write and read addresses of the memory device in the portion that impairs the continuity of images.

Another conventional example is Japanese Patent Laid-Open No. 1-19.
There is a conversion device described in Japanese Patent No. 4782. this is,
An input video signal of m fields is digitized and written in a memory, interpolation of scanning lines and addition of a pseudo vertical synchronizing signal are performed to obtain another video signal of n fields.
When a screen is inserted / deleted in the memory output data,
Since a difference between even / odd fields occurs and a screen shift occurs in the vertical direction, data is interpolated and generated, and a vertical synchronization signal having a period of 1 / n is added to this.

[0012]

However, in the TV system converter disclosed in the above publication, whether the frame or field frequencies of the input TV system and the output TV system are close to each other in a fixed relationship. Or, it cannot respond unless it is synchronized.

Also, in the other TV system converters, unless the frame or field frequencies on the input side and the output side are synchronized with each other in a fixed relationship, the write and read operations on the digital memory are temporal. Overtaking / overtaking will occur. The frequency of occurrence of this phenomenon is related to the difference in the frame or field frequency between before and after conversion of the TV system, and when the frame or field frequency before conversion is higher than that after conversion, the thinning of the frame or field image is reversed. If the frame or field frequency before conversion is lower than that after conversion, duplication of frame or field images will occur.

For example, in writing and reading of the memory,
Approximately 1 if there is a 0.1% frame frequency difference
An overtaking / overtaking phenomenon occurs on the frame memory once every 000 frames. This phenomenon has been a cause of deteriorating the image quality because the flow of a series of operations is disturbed for a moment, especially in the case of a moving image.

Therefore, according to the present invention, even if the frame frequency or the field frequency is not in a fixed synchronous relationship between the input side TV system and the output side TV system, temporal overtaking / overtaking in the writing and reading operations for the image memory is performed. An object of the present invention is to provide a video signal system converter capable of preventing a phenomenon and preventing deterioration of video quality.

[0016]

A video signal conversion apparatus according to the present invention writes a video signal in a digital memory by a first video signal system and reads it by a second video signal system, so that a video signal between different video signal systems can be obtained. A device for converting a signal, which generates a write control clock signal synchronized with a horizontal synchronizing signal of the first video signal system, writes the video signal in a digital memory, and synchronizes with a vertical synchronizing signal of the first video signal system. Then, a read control clock signal substantially according to the second video signal system is generated to read the video signal from the digital memory.

[0017]

When the field or frame frequency of the second video signal system does not need to be strictly defined and can be allowed within a certain range, the field or frame frequency of the video signal of the second video signal system is set to the first By setting the field or frame frequency of the video signal system so as to have a constant synchronization relationship with the field or frame frequency, it is possible to prevent an overtaking / overtaking phenomenon of write and read operations on the digital memory.

Generally, when the video signal after the TV format conversion is independently displayed on the monitor or recorded,
It is not necessary to strictly specify the frame frequency, and it is specified that the frame frequency can be used within a certain range. Therefore, under this condition, even if the field or frame frequency having a certain synchronization relationship with the vertical synchronizing signal of the first video signal system is set to the reference field or frame frequency of the second video signal system, the operation is not possible. No hindrance will occur. Therefore, by performing the conversion of the TV system while maintaining such a synchronous relationship, it is possible to prevent the temporal overtaking / overtaking phenomenon in the writing and reading operations of the video signal on the digital memory. As a result, it is possible to reproduce a moving image in which continuity on the time axis is maintained within a possible range.

[0019]

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a partial block diagram showing an embodiment of a TV system converter according to the present invention. However, in FIG. 1, the circuit of the video signal system shown in FIG. 3 is omitted in order to avoid complication of the drawing. In the following description, please refer to FIG. 1 and FIG. 3 in combination.

Input video signal (Rin, Gin, Bin)
3 are converted into digital signals by the A / D converter 21 and written into a predetermined address of the frame memory 31, as shown in FIG. The video data written in the frame memory 31 is sequentially read out according to another TV system. At this time, if the video data is insufficient, the data interpolator 41 supplements the insufficient portion with appropriate approximate interpolation, and conversely excessively. In that case, the video data is appropriately thinned. The video data obtained in this way is D / A converter 61.
Is converted into an analog signal and a desired TV system video signal (Rout, Gout, Bout) is obtained.

The frame memory 31 is controlled for writing and reading by the frame memory controller 35 shown in FIG. The write control is performed by the write clock Wc
k, a clock Hw obtained by dividing Wck by a dividing ratio m, and a frame pulse Fw. The read control is performed according to the read clock Rck, the clock Hr obtained by dividing the Rck by the division ratio p, and the clock Fr obtained by further dividing the Hr by the division ratio q.

The write clocks Wck and Hw are phase comparators 2 for inputting the horizontal synchronizing signal Hin as a reference signal.
5, a voltage controlled oscillator (VCO) 26, and a frequency divider 27 having a frequency division ratio m. Here, the VCO 26 generates a clock in which the frequency of the horizontal synchronizing signal Hin is multiplied by m. Therefore, the write clock Wck which is the output of the VCO 26 is phase-locked with the horizontal synchronizing signal Hin integrated with the input video signal, and its frequency is multiplied by m. Further, the clock Hw is phase-synchronized with the horizontal synchronizing signal Hin and has the same frequency as Hin.
The frame pulse Fw is a frame pulse generator 28 that takes a logical product of the horizontal synchronizing signal Hin and the vertical synchronizing signal Vin.
And is used as a frame reference of the input video signal. The frequency division ratio m of the frequency divider 27 is determined by the number of effective pixels included in one line of the input video signal and the T after conversion.
The number of effective pixels in the V method is set to be equal.

Read clocks Rck, Hr, and Fr
Is a frequency divider 51 having a variable frequency division ratio a for inputting the vertical synchronization signal Vin, a phase comparator 52 for inputting the output of the frequency divider 51 as a reference signal, a VCO 53, a frequency divider 56 for frequency division ratio p, and a frequency divider 56. It is generated by a PLL circuit including a frequency divider 57 having a frequency division ratio q and a frequency divider 58 having a variable frequency division ratio b. This PL
The L circuit has a frequency synthesizer configuration capable of changing the output frequency by the variable frequency division ratios a and b.

Here, the clock pulse Hr is the output TV
The method corresponds to horizontal synchronization, and the clock pulse Fr also corresponds to vertical synchronization. That is, the division ratio p is set to a value equal to the number of pixels included in one line of the TV system after conversion,
The frequency division ratio q is set to a value equal to the number of scanning lines in one frame of the TV system after conversion.

The variable frequency division ratios a and b of the frequency divider 51 and the frequency divider 58 are set by the frequency division ratio setting outputs 107 and 108 output from the frequency detector 59. The frequency division ratios a and b are set according to the field frequency of the input video signal and the frame frequency of the output video signal, as described later. However, the comparison frequency of the phase comparator 52 is set to be as high as possible in order to speed up and stabilize the PLL circuit.

The frequency detector 59 has a fixed reference clock 105 from the reference clock generator 54 and a vertical synchronizing signal Vi.
n is input, and the field frequency of the input video signal is detected with the fixed reference clock 105 as a reference. If the field frequency is within a preset range as described later, the selector 55 causes the selector 55 to output the VCO.
The clock output from 53 is selected, and the PLL described above is selected.
Read control is performed in synchronization with the vertical synchronizing signal Vin by forming a circuit. On the other hand, if the input field frequency is outside the above range, the selector 55 causes the reference clock generator 54 to
The fixed reference clock of is selected, and the same asynchronous read control as the conventional one is performed. Details of the frequency detector 59 will be described later (FIG. 2).

By inputting the read clocks Rck, Hr, and Fr generated in this way, the frame memory controller 35 controls the read operation, and the output sync signal generator 45 outputs the converted horizontal sync signal of the TV system. It outputs Hout and the vertical synchronization signal Vout.

FIG. 2 shows the frequency detector 5 in this embodiment.
It is a block diagram which shows the structure of 9. In the figure, the fixed reference clock 105 from the reference clock generator 54 is input to the frequency counter 101 and counted. The vertical synchronizing signal Vin is input to the reset pulse generator 104, and the reset pulse generated here causes the frequency counter 10 to operate.
1 is reset. The data stored in the read-only memory (ROM) 102 is accessed according to the count value of the frequency counter 101, and the data is stored in the data latch 103.
Is output to.

The ROM 102 stores in advance the data to be accessed when it is within the set field frequency range and the data to be accessed when it is outside the field frequency range. When the data is within the set field frequency range, the data is the judgment data indicating that the field frequency of the vertical synchronizing signal Vin matches the set range, and the output clock frequency (Rck, H) at that time.
r, Fr) and the data for setting the frequency division ratios a and b of the frequency dividers 51 and 58 respectively so as to be as close as possible to the optimum value.

Access to the ROM 102 is performed by the counter 101.
It is performed by the count value of. Fixed reference clock frequency 1
The period of 05 is Tr, and the count value of the frequency counter 101 is N.
v and the reset pulse width is Ts, the vertical synchronization signal V
The field period Tv of in is Tv = Tr × Nv + Ts
It can be expressed as. Since Tr and Ts are fixed values, it can be seen that the field frequency of the vertical synchronization signal Vin corresponds to the counter count value Nv. Therefore,
By using the counter count value Nv as the address of the ROM 102, it is possible to access data according to the field frequency of the vertical synchronization signal Vin.

The data output from the ROM 102 is latched by the data latch 103, and the frequency match determination output 10
6 to the selector 55, the frequency division ratio a setting output 107 to the frequency divider 51, the frequency division ratio b setting output 108 to the frequency division ratio 58,
It is output respectively. The latch clock of the data latch 103 uses the output of the reset pulse generator 104 and latches the state immediately before the frequency counter 101 is reset.

Next, the write and read operations of this embodiment will be described.

A write clock Wck having a frequency m times that is phase-synchronized with the write horizontal synchronizing signal Hin to the frame memory 31 is output from the VCO 26 of the PLL circuit, and the A / D converter 21 uses the clock Wck to digitally input the input video signal. The conversion is done. The frame memory controller 35 controls writing of the digitized input video signal to the frame memory 31 according to the clock Hw output from the frequency divider 27 of the PLL circuit and the frame pulse Fw output from the frame pulse generator 28. I do. The frame pulse Fw resets the write address counter of the frame memory controller 35 for each frame.

Readout from the frame memory 31 The RGB video data written in the frame memory 31 is controlled by the frame memory controller 35, and the RGB video data is transferred to another TV.
It is sequentially read by the method.

In such a read operation, first, the vertical synchronizing signal Vin of the input video signal is input and the frequency detector 59 detects the field frequency. For example, if the field frequency of the input video signal is f1 and the optimum frame frequency for the TV system video signal on the output side is f2, the frequency detector 59 that has detected the field frequency f1.
Uses R corresponding to the counter count value as an address.
Access the data of the OM 102.

If the field frequency f1 is within the set field frequency range, the sum decision output 106 is the selector 55.
Further, the frequency division ratio setting outputs 107 and 108 are output to the frequency dividers 51 and 58, respectively, and the frequency division ratios a and b are set so that the PLL circuit generates a clock frequency as close as possible to the optimum frame frequency f2. It V at this time
The read clock Rck output from the CO 53 and the clock Hr output from the frequency dividers 56 and 57, respectively.
And Fr are the vertical synchronization signal V by this PLL circuit.
It is a clock that is phase-locked to in. Therefore, the output side T
The frame clock Fr corresponding to the V system vertical synchronization signal Vout is generated by the PLL circuit at the field frequency f1.
And has a frequency f1 × a / b equal to or closest to the optimum frame frequency f2.

The data stored in the ROM 102 includes the optimum frame frequency f2 and the generated frame frequency f1 ×.
Dividing ratio a so that the difference with a / b is within the allowable range
And b are set. For example, when the field frequency f1 of the input video signal is 59.94 Hz and the frame frequency f2 of the output video signal is 60 Hz, the frequency division ratios a and b of the frequency dividers 51 and 58 are both a = b = 1. Is set. Also, the field frequency f1 of the input video signal
Is 50 Hz and the frame frequency f2 of the output video signal is 60
In the case of Hz, the frequency division ratio a = 5 and the frequency division ratio b = 6 are set.

As a result, when the field frequency of the input video signal is within the optimum field frequency range for system conversion, the write address and the read address of the frame memory 31 operate in a synchronous relationship, and the frame memory operates. The temporal overtaking / overtaking phenomenon of 31 is prevented.

If the field frequency f1 is out of the set field frequency range, the selector 55 selects the fixed reference clock from the reference clock generator 54, and the asynchronous read control similar to the conventional one is performed.

In this way, the frame memory controller 3
The RGB video data read by the synchronous read control 5 is output to the data interpolator 41. The data interpolator 41 uses the memory 3 according to the conversion processing of the TV system.
Data interpolation is performed by calculating the read data of No. 1 with data having a certain time difference. This is used particularly when data is approximately generated between scanning lines. The output of the data interpolator 41 is converted into an analog video signal by the D / A converter 61, and the desired TV system video signal (Rou
t, Gout, Bout).

[0042]

As described above in detail, in the video signal system converter according to the present invention, when the field or frame frequency of the input video signal is within a predetermined range of the optimum field or frame frequency after system conversion. Since the read address and the write address of the frame memory operate on the basis of a synchronous relationship, it is possible to prevent the temporal memory overtaking / overtaking phenomenon from occurring. In particular, in the case of a moving image, it is possible to prevent a phenomenon that the flow of operation is disturbed for a moment, which has been a problem in the past, and greatly contributes to improvement of image quality.

[Brief description of drawings]

FIG. 1 is a block diagram showing a control system circuit of an embodiment of a TV system converter according to the present invention.

FIG. 2 is a block diagram showing a configuration of a frequency detector 59 in this embodiment.

FIG. 3 is a block diagram showing an example of a video signal system circuit of the TV system conversion device.

FIG. 4 is a block diagram showing a control system circuit of a conventional TV system converter.

[Explanation of symbols]

 21 A / D converter 25 Phase comparator 26 Voltage controlled oscillator 27 Frequency divider 28 Frame pulse generator 31 Frame memory 35 Frame memory control circuit 41 Data interpolator 45 Output synchronization generator 51 Frequency divider 52 Phase comparator 53 Voltage Control oscillator 54 Fixed reference clock generator 55 Clock selector 56 Frequency divider 57 Frequency divider 58 Frequency divider 59 Frequency detector 61 D / A converter 101 Frequency counter 102 Read-only memory 103 Data latch 104 Reset pulse generator 105 Fixed Reference clock pulse 106 Match determination output 107 Frequency division ratio a setting output of frequency divider 51 108 Frequency division ratio b setting output of frequency divider 58

Claims (7)

[Claims] 1. A device for converting a video signal between different video signal systems by writing the video signal in a digital memory in the first video signal system and reading it in the second video signal system, wherein the first video signal system is used. Write control clock generating means for generating a write control clock signal in synchronization with the horizontal synchronization signal, and a read control clock in synchronization with the vertical synchronization signal of the first video signal system and substantially according to the second video signal system. Read control clock generating means for generating a signal, the video signal is written to the digital memory according to a first video signal system based on the write control clock signal, and the video is output from the digital memory based on the read control clock signal Memory system for performing writing and reading control for reading signals according to the second video signal system A video signal conversion device comprising: a control means. 2. The write control clock generation means generates a write clock signal having an integer multiple frequency in synchronization with the horizontal synchronization signal and a horizontal reference clock signal having the same frequency as the horizontal synchronization signal. 2. A video signal conversion device according to claim 1, further comprising: a phase-locked loop circuit for use with the logic circuit, and a logic circuit that generates a vertical reference clock signal by taking a logical product of the horizontal synchronization signal and the vertical synchronization signal. . 3. The read control clock generation means,
It is characterized by comprising a read phase-locked loop circuit which is synchronized with the vertical synchronizing signal and which generates a horizontal reference clock signal, a vertical reference clock signal and a read clock signal substantially according to the second video signal system. The video signal conversion device according to claim 1. 4. A device for converting a video signal between different video signal systems by writing the video signal in a digital memory in the first video signal system and reading it in the second video signal system, wherein the first video signal system is used. Write control clock generating means for generating a write control clock signal in synchronization with the horizontal synchronizing signal, and a read control clock signal in synchronization with the vertical synchronizing signal of the first video signal system, and by the frequency control signal. A read control clock generating means capable of changing the frequency of the read control clock signal, and a read control clock in which the frequency of the read control clock signal is in accordance with a second video signal system based on the frequency of the vertical synchronization signal. The frequency control signal that is closest to the frequency is the read control clock. Frequency control means for outputting to the generating means; writing the video signal in the digital memory according to a first video signal system based on the write control clock signal; and outputting the video signal from the digital memory based on the read control clock signal A video signal conversion device comprising: a memory control unit for performing writing and reading control for reading according to the second video signal system. 5. The frequency control means inputs a counter for detecting the frequency of the vertical synchronizing signal as a count value, and inputs the count value as an address, and the count value is a second value.
The frequency control signal is output so that the frequency of the read control clock signal is closest to the read control clock frequency according to the second video signal system according to the address within the range that enables the video signal system 5. The video signal conversion device according to claim 4, further comprising: 6. The read control clock generation means has a phase locked loop circuit for generating the read control clock signal composed of a horizontal reference clock signal synchronized with the vertical synchronization signal, a vertical reference clock signal, and a read clock signal. 5. The video signal converter according to claim 4, wherein the video signal converter comprises a frequency synthesizer capable of changing the frequency of the read control clock signal by changing the frequency division ratio by the frequency control signal. 7. A device for converting a video signal between different video signal systems by writing the video signal in a digital memory in the first video signal system and reading it in the second video signal system, wherein the first video signal system is used. Write control clock generation means for generating a write control clock signal in synchronization with the horizontal synchronization signal, and a first read control clock signal in synchronization with the vertical synchronization signal of the first video signal system, and the frequency. A variable frequency clock generation means capable of changing the frequency of the first read control clock signal by a control signal, and a second read control clock signal not synchronized with the vertical synchronizing signal of the first video signal system. Fixed frequency clock generating means, and a frequency range of the vertical synchronizing signal enabling the second video signal system. If so, the first read control clock signal is selected, and if it is out of the range that enables the second video signal system, the second read control clock signal is selected, and the first read control clock signal is selected. When the read control clock signal is selected, the frequency control signal is generated so that the frequency of the first read control clock signal becomes closest to the read control clock frequency according to the second video signal system. Frequency control means for outputting to said means, said video signal is written to said digital memory according to a first video signal system based on said write control clock signal, and said digital memory is written from said digital memory based on said selected read control clock signal. Write and read control to read the video signal according to the second video signal system Video signal converting device comprising a memory control unit, in that it consists of.