JPH11187396A - Image decoding method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent disturbance on a display screen caused by switching of master systems when the images of plural streams are simultaneously decoded and composited and then shown on a single display screen. SOLUTION: A demultiplexer 101 separates the image data on every channel from the PCR(program clock reference) value from a multiplex bit stream. These separated image data are stored in the input buffers 107 to 110. A master selection part consisting of a PCR selector 120 and an STC(standard time clock) selector 121 selects a master system. The selected master STC, a comparator 123, a low-pass filter 124 and a VCO(voltage controlled oscillator) 125 form a PLL(phase-locked loop). Then the VCO 125 reproduces a system clock, and a synchronous signal generation part 126 generates a decoding start signal and a display synchronous signal based on the system clock. The reference time information on channels are obtained from the STC counters 103 to 106. The decoding control parts 111 to 114 wake the decoders 15 to 118 start decoding based on the decoding start signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image decoding method and apparatus for decoding a plurality of encoded image signals at the same time.

[0002]

2. Description of the Related Art In recent years, digital satellite broadcasting via broadcasting satellites and communication satellites has been started to solve the shortage of the number of channels of analog terrestrial television broadcasting and to develop a new multi-channel service. There is also a trend toward digitalization in cable television (CATV) and terrestrial broadcasting using a coaxial cable or an optical fiber cable as a communication path.

[0003] In digital broadcasting, since a digitized image signal or audio signal is compressed with high efficiency by using a compression technique such as MPEG or AC-3, compared to the conventional analog broadcasting, the digital broadcasting has 6 times the same bandwidth. Up to eight times the number of channels can be secured, and various services can be provided.

In order to receive such a digital TV broadcast, in order to make it easy for a viewer to select a channel, images of a plurality of channels are simultaneously decoded, and one TV screen is divided into a plurality of small areas. A multi-screen display function for simultaneously displaying the decoded image of each channel in each of the small areas is provided.

[0005] That is, consider a case where an MPEG transport stream in which TV signals of a plurality of channels are coded and multiplexed is received, and the respective channels are simultaneously decoded and synthesized to be multi-window displayed on one display screen. In this case, as shown in the block diagram of FIG. 4, the transport stream is demultiplexed (DEMU).
X) 101 to separate each TV channel, and input buffers 201 to 2 for each stream.
Enter in 04. Then, the image data streams are independently decoded by the decoders 115 to 118, and the decoded images are stored in the output buffers 205 to 208.

Then, as shown in the timing chart of FIG. 5, image data of each channel is decoded according to decoding start information included in the image data stream of each channel. Also, a master image is selected from the image data streams to be decoded,
An output buffer 205 using a synchronization signal reproduced from data used when displaying image data serving as a master.
２０８208 to read out the decoded images stored in
19, the images are combined and displayed on one screen.

[0007]

However, in the above-mentioned conventional example, an output buffer memory for holding the decoded image for synchronizing the decoded image is required.

Further, since the horizontal and vertical synchronizing signals of the display system are used for the master image, these synchronizing signals are also switched each time the master is switched as shown in FIG. , The display screen is disturbed when the master is switched.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide an image decoding method and apparatus which prevent a display screen from being disturbed when a master image is switched from a plurality of simultaneously displayed images.

Another object of the present invention is to provide an image decoding method and apparatus capable of eliminating an output buffer memory for image synthesis and reducing the amount of hardware of the image decoding apparatus.

[0011]

In order to achieve the above object, the present invention provides a method for inputting a bit stream containing coded image data, and setting a reference time and a system based on reference time information contained in the bit stream. In a decoding method for reproducing a clock and decoding the image data,
A first step of inputting a multiplexed bit stream in which a plurality of the bit streams are multiplexed and separating one or more bit streams including image data to be decoded from the multiplexed bit stream; A second step of selecting one bit stream including image data to be a master stream, and a reference time used when decoding a master image based on reference time information included in the master stream. A third step of reproducing a system clock, and decoding the separated image using the reference time information included in the bit stream including the image data to be decoded and the reproduced system clock. A fourth step of reproducing a reference time to be used; A fifth step of generating a decoding start signal by using the second step, and a fifth step of storing image data included in the separated bit stream in an input buffer in parallel with the processing of the second to fifth steps. And a seventh step of starting decoding of the image data stored in the input buffer in accordance with the decoding start signal.

According to the present invention, a bit stream containing coded image data is input, a reference time and a system clock are reproduced based on reference time information contained in the bit stream, and the image data is decoded. A multiplexed bit stream in which a plurality of the bit streams are multiplexed, and separating means for separating one or more bit streams including image data to be decoded from the multiplexed bit stream; Means for selecting one bit stream including image data to be a master from a coded bit stream as a master stream, and one or more input buffers for accumulating image data included in the bit stream for each of the separated bit streams Based on the reference time information contained in the master stream. A clock reproduction means for reproducing a reference time and a system clock used when decoding a master image, reference time information contained in a bit stream containing the image data to be decoded, and the reproduced system clock. Reference time reproducing means for reproducing a reference time used when decoding the separated image, and a decoding start signal common to each of the separated bit streams using the reproduced system clock. An image decoding apparatus comprising: a decoding start signal generating unit for generating a decoding start signal; and one or more decoding units for starting decoding of image data stored in the input buffer based on the decoding start signal. It is.

In the present invention, the decoding start signal may be a signal synchronized with a display synchronization signal that does not depend on decoding start time information included in a master image signal.

In the present invention, the capacity secured as the input buffer is larger than the data amount required when starting decoding based on the decoding start time information included in the data. It is necessary to increase the number of data more than the maximum amount of data input for one frame time of data.

(Operation) According to the present invention having the above structure,
One or more bit streams to be decoded that are separated from a multiplexed bit stream obtained by multiplexing a bit stream including encoded image data are respectively stored in an input buffer, and a common decoding start signal common to each bit stream is used. Since each decoder corresponding to each input buffer decodes the image data, the timing of the images output from each decoder coincides, and the output buffer waiting for synthesizing a plurality of images on one display screen is provided. It becomes unnecessary and can be directly synthesized by the synthesizing unit.

Further, even if the stream including the image data serving as the master is switched, the phase of the synchronization signal is not disturbed.
Disturbance of the display image at the time of switching the master can be prevented.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings. In the present embodiment, MPEG
4 (hereinafter referred to as ch1 to ch4)
A description will be given of an example in which a multiplexed transport stream is input, and all these image signals are decoded and output.

FIG. 1 is a block diagram showing the configuration of an embodiment of an image decoding apparatus according to the present invention. In FIG.
The image decoding apparatus includes a demultiplexer (hereinafter, abbreviated as DEMUX) 101 serving as a separating unit that separates an encoded image data stream from a transport stream;
A PCR extraction unit 102 that is included in the EMUX 101 and separates and extracts a PCR (program, clock, and reference value) that is reference time information of each channel, and an STC counter 103 that reproduces the reference time of each channel using each PCR
１０６106, a PCR selector 120 and a STC which are master selection means for selecting a master PCR and STC counter from the four-channel PCR and STC counters.
A selector 121, input buffers 107 to 110 for storing image data bit streams for each channel separated by the DEMUX 101, and a comparator 12 for comparing the value of the PCR selected as the master with the value of the STC counter.
3, a low pass filter (LPF) 124, and a voltage controlled oscillator (VCO) 125 for generating a system clock
A synchronizing signal generator 126 for generating a display synchronizing signal and a decoding start signal common to each channel based on a system clock, and an encoded image stored in each of the input buffers 107 to 110 in response to the decoding start signal Decoding control units 111 to 114 for starting decoding of data, and decoders 115 to 118 for starting decoding of coded image data of each channel under the control of decoding control units 111 to 114.
And a synthesizing unit 119 for synthesizing the decoding results of the four channels.
And

Note that an STC counter, a comparator 123, and an LP, which are masters selected by the STC selector 121, are used.
The F124 and the VCO 125 form a PLL (Phase Lock Loop), which is a system clock recovery means, and a reference time used when decoding a master image from the selected STC counter. The system clock to be used is obtained.

FIG. 2 is a block diagram showing the internal configuration of the decoder 115. 4 of the decoders 115 to 118 in FIG.
Since the two decoders are equal to each other and are similar to the conventional MPEG decoder, the decoder 115 is shown as an example. FIG.
, The decoder 115 includes a variable-length decoding unit 141, an inverse quantization unit 142, an inverse DCT unit 143, and a motion compensation unit 14.
4, a decode memory 146, and an output filter unit 145. The coded image data stored in the input buffer 107 of FIG. 1 is input to the variable length coding unit 141.
The decoding control from the decoding control unit 111 is received by the entire decoder 115.

Next, the operation of the image decoding apparatus shown in FIG. 1 will be described. The input transport stream is DEM
The UX 101 separates the data into coded image data streams of four channels based on the packet identification information (PID) in the transport stream, and stores the coded image data streams in input buffers 107 to 110 provided for each channel. It is decoded at 115-118.

Here, it is assumed that the image signal of ch1 is decoded using the STC counter 103 as a reference time and the decoder 115. Similarly, the image signal of ch2 is S
Using the TC counter 104 as a reference time, decoding is performed using the decoder 116, and the image signal of ch3 is decoded by the STC counter 105.
Is used as a reference time, decoding is performed using the decoder 117, ch4
It is assumed that the STC counter 106 is used as a reference time and the decoder 118 decodes the image signal.

In addition, P from the input bit stream
The PCR for each channel is extracted using the CR extraction unit 102 and sent to the STC counters 103 to 106.

First, the operation of reproducing the system clock and the reference time (STC) when the master stream is set to ch1 will be described. The PCR information included in the ch1 stream is extracted from the bit stream input to the DEMUX 101 using the PCR extraction unit 102, and the PCR value is sent to the STC counter 103. STC counter 103
Receives the stream of ch1 and receives the first PCR, loads this value into the counter, and operates each of the STC counters 103 to 106 using the system clock output from the VCO 125.

Next, the P1 of ch1 is again
When the CR is extracted, the PCR value of the extracted ch1 and the STC counter 10 are extracted via the PCR selector 120 and the STC selector 121 as the master stream selecting means.
The STC count value of ch1 counted at 3 is the P value composed of the comparator 123, LPF 124, and VCO 125.
LL, and the system clock locked to the ch1 stream is reproduced. Hereinafter, similarly, a stable system clock is continuously reproduced by reflecting the difference value in the PLL.

Here, the operation when the master stream is changed to another channel is to load the PCR value detected immediately after changing the master stream into the STC counter and set the difference value immediately after the change to 0. Thus, a sudden frequency change of the system clock can be avoided.

On the other hand, with respect to the streams of ch2, ch3 and ch4 which are slave streams other than the master stream, the PCR extracting section 102 extracts the PCR information contained in each slave stream, and the STC counter 104 corresponding to each channel. , 105, and 106. Each of the STC counters 104 to 106 loads the transmitted PCR value into its own counter, and
The counter operates using the system clock locked to the master stream output from the counter 25. That is, the STC counter assigned to the slave stream performs a counting operation while rewriting the value of the STC counter to the extracted PCR value every time a PCR is extracted.

Next, the operation of generating a decoding start signal from a system clock synchronized with the master stream will be described.
The system clock output from the VCO 125 is sent to the synchronization signal generator 126, and the system clock is frequency-divided by a counter, a frequency divider, etc., so that a decoding start signal,
Generate vertical and horizontal display synchronization signals.

Normally, the decoding start signal should be controlled so as to coincide with the decoding start time information (DTS) included in the master stream.
, And a decoding start signal is generated using a system clock at a phase at which the display system is uniquely determined.

Therefore, even when the master stream is changed from ch1 to ch2 as shown in FIG. 3, the decoding start signal is always generated at a constant phase regardless of the phase of the decoding start information included in each channel. Further, the cycle of the decoding start signal is made to match the frame rate of the master stream.
That is, if the master stream is changed, it goes without saying that the period of the decoding start signal is also changed to the frame rate of the changed master stream.

Next, the decoding start operation in each decoder will be described. When a decoding start signal common to each channel generated by the method described above is input to the decoding control units 111 to 114, at this timing, the values of the respective STC counters 103 to 106 and the value of the DTS in the stream are set. Compare.

As a result of the comparison, if the value of DTS is smaller than the value of the STC counter, the corresponding decoder is started to decode the current frame at the timing of the decoding start signal. Here, the value of DTS is 1 more than the value of STC counter.
If the value is smaller than the value of the frame, the decoding is skipped to a frame in which the value of the DTS is larger than the value of the STC counter.

If the value of DTS is larger, the decoding operation is stopped until the next decoding start signal is input. Also,
If the frame data does not include the DTS, the frame is decoded at the timing of the input decoding start signal in the same manner as when the value of the DTS is determined to be smaller than the value of the STC counter. Let it start.

Here, in order to start the data of each channel at a decoding start time different from the original decoding start time information (DTS) (see FIG. 3), the decoders 115 to 118 of each channel need to have the original DTS time. Therefore, since the decoding start time is delayed by a maximum of one frame time of the master image data, one frame of the master image data becomes larger than the input buffer amount required to start decoding in the original DTS time. It is necessary to have input buffers 107 to 110 each of which is larger than the maximum amount of data input in time.

The image data of a plurality of channels whose decoding has been started at the same timing in this way does not have an output buffer for synchronizing the outputs of the respective decoders 115 to 118, for example, via the synthesizing unit 119. Can be combined and output on one screen.

Further, the vertical / horizontal synchronization signal for display is generated by the synchronization signal generation section based on the system clock irrespective of the decoding start time information included in the master coded image data stream. Even if the master is switched, the phase of the synchronization signal of the display system is not affected, so that the screen is not disturbed when the master is switched.

[0037]

As described above, according to the present invention, a plurality of image data are simultaneously decoded by generating a common decoding start signal for each of the encoded image data using the system clock reproduced from the master stream. During the multi-window display, the phase of the synchronization signal is not disturbed even if the channel selected as the master stream is switched, so that the display screen is not disturbed.

Further, according to the present invention, of the input buffer and the output buffer provided in the conventional decoding device, an output buffer for adjusting the time of an output image is not required.
The buffer capacity can be reduced even in the sum of the capacity of the input buffer and the output buffer, and the amount of hardware of the decoding device can be reduced, and its size, reliability and power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a decoding device according to an embodiment of the present invention.

FIG. 2 is a detailed block diagram illustrating a configuration of a decoder used in the embodiment.

FIG. 3 is a decoding timing chart for explaining the operation of the embodiment;

FIG. 4 is a block diagram illustrating a configuration of a conventional decoding device.

FIG. 5 is a decoding timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

101: demultiplexer, 102: PCR extraction unit, 1
03, 104, 105, 106 ... STC counter, 10
7, 108, 109, 110 ... input buffer, 111,
112, 113, 114... Decoding control unit, 115, 11
6, 117, 118 ... decoder, 119 ... synthesis unit, 120
... PCR selector, 121 ... STC selector, 123 ...
Comparator, 124 LPF, 125 VCO, 126 Synchronous signal generator.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04N 7/08 H04N 5/073 Z 7/081 7/08 Z // H04N 5/073

Claims (6)

[Claims] 1. A decoding device for receiving a bit stream including encoded image data, reproducing a reference time and a system clock based on reference time information included in the bit stream, and decoding the image data. A method comprising: inputting a multiplexed bit stream in which a plurality of the bit streams are multiplexed; and separating one or more bit streams containing image data to be decoded from the multiplexed bit stream; A bit stream including image data to be a master from a stream is defined as 1 as a master stream.
A second step of selecting one, a third step of reproducing a reference time and a system clock used when decoding a master image based on the reference time information included in the master stream, Using the reference time information included in the bit stream including the decoded image data to be decoded and the reproduced system clock to reproduce a reference time used when decoding the separated image. A fifth step of generating a decoding start signal using the reproduced system clock; and image data included in the separated bit stream in parallel with the processing of the second to fifth steps. A sixth step of storing image data stored in the input buffer according to the decoding start signal. Picture decoding method is characterized in that and a seventh step of initiating a. 2. The image decoding apparatus according to claim 1, wherein the decoding start signal is a signal synchronized with a display synchronization signal that does not depend on decoding start time information included in a master image signal. Method. 3. The capacity secured as the input buffer is one frame of image data serving as a master, which is larger than the data amount required when starting decoding based on decoding start time information included in the data. 3. The image decoding method according to claim 1, wherein the number of data is greater than or equal to a maximum data amount input in time. 4. A decoding device which receives a bit stream including encoded image data, reproduces a reference time and a system clock based on reference time information included in the bit stream, and decodes the image data. An apparatus, comprising: a multiplexed bit stream in which a plurality of the bit streams are multiplexed; and a separating unit configured to separate one or more bit streams including image data to be decoded from the multiplexed bit stream; A bit stream containing image data to be a master from
Selecting means for selecting one, one or more input buffers for accumulating image data included in the bit stream for each of the separated bit streams, and a master based on reference time information included in the master stream. A clock reproducing unit that reproduces a reference time and a system clock used when decoding an image, and reference time information included in a bit stream that includes the image data to be decoded and the reproduced system clock, Reference time reproducing means for reproducing a reference time used for decoding the separated image; and decoding for generating a decoding start signal common to each of the separated bit streams using the reproduced system clock. Start signal generation means; and decoding of image data stored in the input buffer by the decoding start signal. Image decoding apparatus characterized by comprising a, and one or more decoding means to start. 5. The decoding start signal generated by the decoding start signal generating means is a signal synchronized with a display synchronization signal that does not depend on decoding start time information included in a master image signal. The image decoding apparatus according to claim 4, wherein 6. The capacity of the input buffer for one frame time of master image data is larger than the capacity required when decoding is started based on decoding start time information included in data. More than the maximum amount of data
The image decoding apparatus according to claim 4 or 5, wherein the number is large.