JP2006191538A - Compressed stream decoding instrument and compressed stream decoding method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make it possible that, in compressed stream decoding instrument capable of outputting two or more video images after decoding two or more compressed video image streams, the display picture disorder is prevented in both case of outputting two or more different images, and outputting two or more same images. <P>SOLUTION: A compressed stream decoding instrument 10 has compressed image stream processors 11 and 12. The compressed image stream processor 11 decodes TS1 using the clock CLK1 derived from PCR attached to TS1, and outputs the data decoded using CLK1 timing. The compressed image stream processor 12 performs selectively one processing which uses the clock CLK2 derived from PCR attached to TS2 for decoding/outputting TS2, and another processing which outputs the data decoded by the compressed image stream processor 11 using CLK1 timing. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a compressed stream decoding apparatus that decodes a plurality of code-compressed video streams, and more particularly to a compressed stream decoding apparatus and a decoding method capable of decoding a plurality of compressed video streams and outputting a plurality of videos. .

  In digital broadcasting services such as BS digital broadcasting, CS digital broadcasting, and terrestrial digital broadcasting, the MPEG-2 transport stream method is used. The MPEG-2 transport stream can take a configuration in which a plurality of programs are multiplexed in one transport stream.

  An apparatus that separates programs included in a plurality of MPEG-2 transport streams and decodes a plurality of compressed video streams included in the plurality of programs has been conventionally proposed (see, for example, Patent Document 1). According to these apparatuses, for example, a digital broadcast service is received and a single program (program) is viewed, and the same or different program is recorded, or the display screen is divided into a plurality of programs. Can be simultaneously displayed in each divided area.

  FIG. 7 shows a configuration of a conventional compressed stream decoding apparatus capable of decoding a plurality of compressed video streams included in a plurality of programs as described above. The compressed stream decoding apparatus 70 receives the two transport streams TS1 and TS2, decodes the compressed video stream in one program separated from TS1, and outputs the output image 1 from the display output unit 112. Similarly, the compressed video stream in one program separated from TS2 is decoded and output image 2 is output from display output unit 132.

In addition, the compressed stream decoding device 70 is a reference extracted from TS1 by a PLL (Phase Locked Loop) circuit formed by a comparator 104, a low-pass filter (LPF) 105, a voltage control oscillator (VCO) 106, and an STC counter 103. A system clock CLK1 synchronized with PCR (Program Clock Reference) which is time information is generated. The generated system clock CLK1 is used not only when determining the decoding timing and image output timing of the program separated from TS2, but also TS1.
JP-A-11-187396 Japanese Patent No. 3356078

  In the compressed stream decoding apparatus 70, if TS1 and TS2 are different transport streams, the bit rates for encoding both are usually not the same. For example, STC (System Time Clock), which is a reference clock for encoding and decoding in the MPEG-2 standard, allows an error of ± 1350 Hz with respect to a reference frequency of 27 MHz. In some cases, the STC at the time of operation differs within the allowable error range.

  In the conventional compressed stream decoding apparatus 70 of FIG. 7, the first compressed video stream processing unit 71 uses the clock CLK1 obtained by performing clock recovery from the transport stream TS1, and the second compressed video stream processing unit 72 uses the transport stream TS2. Also used when decrypting. For this reason, the STC for decoding the transport stream TS2 is different from the STC for encoding it. In such a situation, in the second compressed stream processing unit 72, the bit rate at which the video data of the program separated by the DEMUX 121 is stored in the input buffer 127, and the bit rate at which the decoder 128 decodes the video data in the input buffer 127. This causes a difference in overflow and underflow of the input buffer 127, resulting in the output image 2 being repeated or skipped.

  As described above, the conventional compressed stream decoding apparatus has a problem in that when a plurality of compressed video streams are decoded and a plurality of video outputs are output, the display image is disturbed due to skip / repeat or the like.

  The present invention has been made in consideration of the above-mentioned problems, and the problem to be solved by the present invention is to provide a compressed stream decoding apparatus capable of decoding a plurality of compressed video streams and outputting a plurality of video images. It is to prevent the display image from being disturbed by skip / repeat when outputting a plurality of different videos, and also to prevent the display image from being disturbed when a plurality of the same videos are output.

  The compressed stream decoding apparatus according to the present invention decodes the input first compressed video stream based on the first reference time information given to the first compressed video stream, and the decoded video data The first video data processing unit that outputs based on the first reference time information, and the input second compressed video stream are converted into second reference time information given to the second compressed video stream. And decoding the video data based on the second reference time information, or decoding the video data decoded by the first video data processing unit based on the first reference time information. And a second video data processing unit that performs processing to determine whether to output the compressed stream.

  With such a configuration, in a compressed stream decoding apparatus capable of decoding a plurality of compressed video streams and outputting a plurality of videos, when outputting a plurality of different videos, a reference time given to each compressed video stream Since decoding and output can be performed based on the information (PCR), it is possible to prevent display image disturbance such as skip / repeat. Furthermore, even when a plurality of the same videos are output, a plurality of the same images are displayed based on the display synchronization signal generated using the reference time information (PCR) given to the compressed video stream including the output video. Since the image is output, it is possible to prevent the display image from being disturbed.

  The second video data processing unit includes a selector for selecting either the video data decoded by the first video data processing unit or the video data decoded by the second video data processing unit. It is desirable to provide. When the selector selects the video data decoded by the first video data processing unit, one of the circuits constituting the second video data processing unit is processed until the second compressed video stream is input to the selector. Since all or part of the circuit can be stopped, the power consumption for the circuit that stops the operation can be reduced.

  Further, another compressed stream decoding apparatus according to the present invention decodes an input first compressed video stream based on first reference time information given to the first compressed video stream. A decoder, a first output buffer for storing the decoded video data output by the first decoder, the video data stored in the first output buffer, and the first reference time information. The first display output device that outputs in synchronization with the display synchronization signal generated by using the second compressed video stream that is input to the second reference time information given to the second compressed video stream A second decoder for decoding based on the second decoder, a second output buffer for storing the decoded video data output from the second decoder, and the video data stored in the first output buffer or the first 2 output buffs Any of the stored image data and select the one in which and a second display output unit for outputting video data selected. Further, when the second display output device outputs the video data stored in the first output buffer, the output is performed in synchronization with the display synchronization signal generated using the first reference time information. When the second display output unit outputs the video data stored in the second output buffer, the second display output unit outputs the video data in synchronization with the display synchronization signal generated using the second reference time information. It is characterized by.

  Further, the compressed stream decoding method according to the present invention decodes the input first compressed video stream based on the first reference time information given to the first compressed video stream, and the decoded video The first display output device stores data in a first output buffer, and synchronizes video data stored in the first output buffer with a display synchronization signal generated using the first reference time information. And the input second compressed video stream is decoded based on the second reference time information given to the second compressed video stream, and the decoded video data is stored in the second output buffer. And selecting either the video data stored in the first output buffer or the video data stored in the second output buffer, and outputting the selected video data from the second display output device. It is intended. Further, when the video data stored in the first output buffer is output from the second display output device, the video data is output in synchronization with the display synchronization signal generated using the first reference time information. When the video data stored in the second output buffer is output from the second display output device, the video data is output in synchronization with the display synchronization signal generated using the second reference time information. It is characterized by.

  When a plurality of different videos are output in a compressed stream decoding apparatus capable of decoding a plurality of compressed video streams and outputting a plurality of videos by such a configuration or method, a standard according to each compressed video stream is used. Since decoding and output can be performed using a clock, it is possible to prevent display image disturbance such as skip / repeat. Furthermore, even when a plurality of the same videos are output, all displays that output the same image using a reference clock in accordance with the compressed video stream that includes the output video and a display synchronization signal generated from the reference clock. Since the output operation of the output device is performed, it is possible to prevent the display image from being disturbed.

  Furthermore, another compressed stream decoding apparatus according to the present invention decodes an input first compressed video stream and second compressed video stream by time division processing, and outputs decoded video data. If the frame frequency of the first compressed video stream and the second compressed video stream are different, the decoding start of the picture included in one compressed video stream having a lower frame frequency is started. The decoding start time is adjusted so as to be delayed until after decoding of a picture included in the compressed video stream.

  With such a configuration, when two compressed video streams having different frame frequencies are decoded by time division processing, it is possible to display both compressed video streams without causing a delay. Therefore, it is possible to prevent the display image from being disturbed due to the decoding delay.

  According to the present invention, in a compressed stream decoding apparatus capable of decoding a plurality of compressed video streams and outputting a plurality of videos, it is possible to prevent disturbance of a display image when a plurality of different videos are output. It is also possible to prevent display image disturbance when a plurality of videos are output. Further, when a plurality of the same videos are output, the operation of at least a part of the circuit included in the compressed stream decoding device can be stopped, so that power consumption can be reduced.

Embodiment 1 of the Invention
The configuration and operation of the compressed stream decoding apparatus 10 according to the present embodiment will be described with reference to FIG. The compressed stream decoding apparatus 10 decodes the compressed video stream multiplexed on the MPEG-2 transport stream. First, the first compressed video stream processing unit 11 that decodes the compressed video stream multiplexed on the transport stream TS1 and outputs the output image 1 will be described.

  The DEMUX 101 separates one program with reference to PID (packet identification information) from TS1 in which one or more programs are multiplexed, and stores the compressed video data in the separated program in the input buffer 107 . The input buffer 107 is a memory that stores the compressed video data separated by the DEMUX 101. Note that the capacity of the input buffer 107 is defined in the MPEG-2 standard according to the type of compressed video data included in the transport stream 1 (specifically, the profile and level defined in the MPEG-2 standard). What is necessary is just to provide the capacity | capacitance more than Video_Buffer amount.

  When the display start signal 1 is input from the synchronization signal generation unit 111, the control unit 110 acquires the value of the STC counter 103, and the DTS (Decoding Time Stamp) value smaller than the acquired STC value is assigned to the picture. The decoder 108 is instructed to perform decoding.

  The decoder 108 acquires and decodes a picture to which a DTS value smaller than the STC value acquired by the control unit 110 is given from the input buffer 107, and stores the decoded video data (picture) in the output buffer 109.

  The output buffer 109 is a memory that stores a plurality of decoded video data (pictures). The reason for storing a plurality of pictures is that the pictures that make up the MPEG-2 compressed video stream include B pictures that have undergone inter-picture predictive coding using two past and future pictures. This is because the decoding order indicated by the DTS value and the reproduction order indicated by PTS (Presentation Time Stamp) may be different, and it is necessary to store the previously decoded pictures until the reproduction order arrives. Specifically, for example, as shown in Patent Document 2, it may be configured by four frame memories so that four pictures can be stored.

  The synchronization signal generation unit 111 generates the output clock 1 by multiplying or dividing the system clock CLK1 synchronized with the STC of the program to be decoded. The output clock 1 indicates the output timing for each pixel of the output image, and is a so-called dot clock. For example, when the output image is an HDTV video signal (1080i), a dot clock of 74.25 / 1.001 MHz is generated, and when the output image is an NTSC video signal (480i), a dot clock of 13.5 MHz or the like is generated. Further, the synchronization signal generator 111 includes a counter that counts the output timing of each pixel of the output image in synchronization with the output clock 1, and the counter value is a frame (picture) delimiter and a scanning line (line). When the value corresponds to the break, the display start signal 1 and the display synchronization signal 1 are generated. Here, the display start signal 1 is a signal for notifying the control unit 110 of the display start timing in units of pictures, that is, the release of the frame memory in which the previous display picture of the output buffer 109 is stored. And a signal for notifying the decoding start timing of the current picture. The control unit 110 acquires the STC value at the timing indicated by the display start signal 1 and instructs the decoder 108 to start decoding. On the other hand, the display synchronization signal 1 is a signal for notifying the vertical scanning period and the horizontal scanning period. Specifically, the display synchronization signal 1 is a vertical synchronization signal (Vsync) indicating the timing of the vertical blanking by the waveform change in units of the vertical scanning period. This is a horizontal synchronization signal (Hsync) indicating the timing of horizontal retrace according to the waveform change in units of scanning periods.

  The display output unit 112 acquires the decoded video data from the output buffer 109 based on the display start signal 1 received from the synchronization signal generator 111, and outputs it based on the output clock 1 and the display synchronization signal 1. An output destination of the display output device 112 is a display device such as a display for displaying video data, a hard disk drive for recording video data, a recording device such as a DVD drive, or the like. Depending on the output destination device, the output of the display output device 112 may be output as a digital video signal or may be output as an analog video signal such as an NTSC signal.

  Next, an operation for generating a 27 MHz system clock corresponding to STC, which is the MPEG-2 reference time, will be described. The PCR extraction unit 102 separates the PCR value corresponding to the compressed video stream separated in the DEMUX 101 from the TS 1, and outputs it to the STC counter 103 and the comparator 104. The PCR is a time stamp generated at the STC frequency (27 MHz), and indicates the STC on the transmission side that has encoded the compressed video stream.

  The STC counter 103 receives the PCR value from the PCR extraction unit 102, sets the counter value to the received PCR value, and counts up according to the system clock CLK1 output from the VCO 103.

  The comparator 104 that compares the PCR value with the value of the STC counter 103, the low-pass filter (LPF) 105, the voltage control oscillator (VCO) 106 that generates the system clock, and the STC counter 103 form a PLL (Phase Locked Loop) circuit. is doing. In the comparator 104, a difference between the PCR value and the value of the STC counter 103 counted in synchronization with the output of the VCO 106 is detected and reflected in the output of the VCO 106. Since the PCR value is a counter value indicating the STC that is the reference time used when encoding on the transmission side of the compressed video stream, the compressed video stream is transmitted by reproducing the clock with reference to the PCR value. A system clock synchronized with the STC on the side can be output.

  Next, the second compressed video stream processing unit 12 that decodes the compressed video stream multiplexed on the transport stream TS2 and outputs the output image 2 will be described. A DEMUX 121, a PCR extraction unit 122, an STC counter 123, a comparator 124, an LPF 125, a VCO 126, an input buffer 127, and a decoding unit that are provided to separate and decode the program multiplexed in the transport stream TS2 and output the output image 2 128, output buffer 129, control unit 130, synchronization signal generation unit 131, and display output unit 132 are equivalent to the components of the first compressed video stream processing unit 11, corresponding to the functions of DEMUX 101 to display output unit 112, respectively. It has the function of. A portion having a function different from the components of the first compressed video stream processing unit 11 described above will be described below.

  The selector 133 is a selector for selecting the image data output from the display output device 132 from either the data stored in the output buffer 109 or the data stored in the output buffer 129. The selector 134 is a selector for selecting a system clock serving as a reference when the synchronization signal generating unit 131 generates the output clock 2 or the like from either CLK1 or CLK2. CLK1 is a clock generated so as to be synchronized with the PCR of the compressed data stream separated by the DEMUX 101 of the first compressed video stream processing unit 11, and CLK2 is separated by the DEMUX 121 of the second compressed video stream processing unit 12. A system clock generated to synchronize with the PCR of the program.

  The output switching instruction unit 135 receives a signal instructing switching of the output image of the display output device from an external CPU or the like, and outputs a display output to the synchronization signal generation unit 131, the selector 133, and the selector 134 according to the signal. An output switching signal S1 for switching the output image 2 of the device 132 is output.

  Subsequently, an operation of switching the output image of the display output device 132 in the compressed stream decoding apparatus 10 according to the present embodiment will be described. First, an operation at the time of multi-stream decoding is performed in which the transport streams TS1 and TS2 are input to the compressed stream decoding apparatus 10 and separate output images corresponding to the transport streams TS1 and TS2 are output to the display output unit 112 and the display output unit 132. Will be explained. In this case, the synchronization signal generation unit 111 of the first compressed video stream processing unit 11 generates the output clock 1, the display synchronization signal 1, and the display start signal 1 based on the system clock CLK1 output from the VCO 106, and the second The synchronization signal generation unit 131 of the compressed video stream processing unit 12 generates the output clock 2, the display synchronization signal 2, and the display start signal 2 based on the system clock CLK2 output from the VCO 126.

  Accordingly, the first compressed video stream processing unit 11 can perform decoding and image output according to the system clock CLK1 synchronized with the STC when the compressed video stream separated from the transport stream TS1 is encoded. On the other hand, the second compressed video stream processing unit 12 can perform decoding and image output according to the system clock CLK2 synchronized with the STC when the compressed video stream separated from the transport stream TS2 is encoded. In this way, the first compressed video stream processing unit 11 and the second compressed video stream processing unit 12 perform the decoding and image output operation independently using the system clock that is appropriately reproduced, and therefore skip to the output image. / No repeat is generated.

  Next, one transport stream TS1 is input from a state where the compressed video stream is decoded and output from the plurality of transport streams TS1 and TS2, and the same output image is output to the display output unit 112 and the display output unit 132. The operation for switching to the state will be described.

  When the output switching instruction unit 135 receives a signal instructing switching of the output image of the display output device from an external CPU or the like, the output switching instruction unit 135 outputs a display output to the synchronization signal generation unit 131, the selector 133, and the selector 134 according to the signal. An output switching signal S1 for switching the output image 2 of the device 132 is output. The selector 134 that has received the output switching signal S1 selects the clock CLK1 output from the VCO 106 and outputs it to the STC counter 123, the synchronization signal generator 131, and the display output device 132. The synchronization signal generator 131 that has received the output switching signal S1 acquires the counter value of the synchronization signal generator 111 and updates its own counter value. Thus, the system clock input to the synchronization signal generation unit 111 and the synchronization signal generation unit 131, the display synchronization signal 1 generated by the synchronization signal generation unit 111, and the display synchronization signal 2 generated by the synchronization signal generation unit 131 can be synchronized. it can. Further, the data stored in the output buffer 109 is output as an output image to the display output device 132 via the selector 133 that has received the output switching signal S1.

  FIG. 2 shows a timing chart when changing from the multiple stream output state to the same stream output state. In the multi-stream output state, the synchronization signal generation unit 111 and the synchronization signal generation unit 131 count the internal counter based on the different reference clocks CLK1 or CLK2, and generate the display synchronization signal and the output clock. The signal generated by the unit 111 and the signal generated by the synchronization signal generation unit 131 are not synchronized with each other. As a result, overflow and underflow of the input buffers 107 and 108 do not occur, and display image disturbance such as skip / repeat can be prevented.

  On the other hand, when switching to the same stream output state, the selector 134 selects CLK1 according to the output switching signal S1, and the synchronization signal generator 131 acquires the counter value of the synchronization signal generator 111. Thereby, after receiving the output switching signal, the output clock 2 and the display synchronization signal 2 generated by the synchronization signal generation unit 131 are synchronized with the output clock 1 and the display synchronization signal 1 generated by the synchronization signal generation unit 111.

  Here, a problem that occurs when the display synchronization signal 1 generated by the synchronization signal generation unit 111 and the display synchronization signal 2 generated by the synchronization signal generation unit 131 do not match in the same stream output state will be described with reference to FIG. explain. FIG. 3A shows the decoding timing in the decoder 108 and the output timing of the picture decoded by the decoder 108 in the display output units 112 and 132, where I1 is an I picture, P1 and P2 are P pictures B1 to B3 represent B pictures. If the display synchronization signal 1 generated by the synchronization signal generation unit 111 and the display synchronization signal 2 generated by the synchronization signal generation unit 131 do not match, the operation clocks of the display output unit 112 and the display output unit 132 are not synchronized. A difference (Δt shown in FIG. 3A) occurs between the output timing of the output device 112 and the output timing of the display output device 132.

  On the other hand, FIG. 3B shows the write / read timing for the output buffer 109 when decoding and image output are performed at the timing of FIG. In the figure, # 0 to # 3 represent frame memory numbers when the output buffer 109 is configured with four frame memories so that four pictures can be stored. The writing by the decoder 108 should be performed on the frame memory that has been read by the display output units 112 and 132. Since the decoder 108 and the display output unit 112 access the output buffer 109 based on the same display start signal 1 generated by the synchronization signal generation unit 111, for example, the display output unit 112 performs reading at time t4. The writing process by the decoder 108 and the reading process by the display output unit 112 do not compete with each other such that the decoder 108 writes to the frame memory # 2 at time t5. This is because both writing and reading to the output buffer 109 by the decoder 108 and the display output unit 112 are performed in a frame period for each picture, and the start timing of writing or reading is synchronized. With this configuration, the frame memory utilization efficiency can be improved, and the number of frame memories provided in the output buffer 109 can be reduced as much as possible.

  However, the decoder 108 and the display output unit 132 access the output buffer 109 based on the separate display start signals 1 or 2 generated by the synchronization signal generation unit 111 or the synchronization signal generation unit 131. Therefore, the start timing of writing or reading to the output buffer 109 by the decoder 108 and the display output unit 132 is not synchronized. For this reason, as shown in FIG. 3B, if the start timing of writing or reading with respect to the output buffer 109 of the decoder 108 and the display output device 132 is shifted by Δt, for example, at time t5, the decoder 108 When writing to # 2, reading from the frame memory # 2 of the display output device 132 is not completed, and the writing processing by the decoder 108 and the reading processing by the display output device 132 compete.

  Thus, when a conflict between writing and reading with respect to the output buffer 109 occurs, the image data that should be output is lost, and an incorrect image is output, causing the output image of the display output device 132 to be disturbed. It becomes.

  In the same stream output state, the compressed stream decoding apparatus 10 according to the present embodiment is based on a common system clock CLK1 according to the PCR of the compressed video stream separated from the transport stream TS1, and the synchronization signal generator 111 and 131 generates display synchronization signals 1 and 2. Further, the synchronization signal generation unit 131 acquires the counter value output from the synchronization signal generation unit 111 and updates its own counter value. Thereby, it is possible to synchronize to the phase of the display synchronization signals 1 and 2, specifically, the output period of the vertical synchronization signal (Vsync) and the horizontal synchronization signal (Hsync) and the phase of the display start signals 1 and 2.

  With such a configuration and operation, the compressed stream decoding apparatus 10 according to the present embodiment can match the timing at which the display output unit 132 accesses the output buffer 109 with the access timing of the display output unit 112. Further, since the frame period determined by the output period of the vertical synchronization signal (Vsync) and the horizontal synchronization signal (Hsync) also coincides, the end timing of reading or writing to the output buffer 109 is also synchronized. For this reason, the contention of the output buffer 109 as described above does not occur, and a plurality of identical videos can be output without causing disturbance of the display image. FIG. 3C shows a state in which the read phase of the display output unit 132 is synchronized with the write timing phase of the decoder 108 and the read timing phase of the display output unit 108.

  Note that the compressed stream decoding apparatus 10 according to the present embodiment switches the system clock input to the synchronization signal generation unit 131 to CLK1, and takes the counter value of the synchronization signal generation unit 111 into the synchronization signal generation unit 131. The display synchronization signal 2 and the output clock 2 for the display output device 132 are synchronized with the display synchronization signal 1 and the output clock 1 for the display output device 112. However, in order to obtain the effect of the present invention, in short, the display output unit 112 and the display output unit 132 may operate according to the same display synchronization signal and output clock. Therefore, for example, when a plurality of the same streams are output, the display output unit 132 may be configured to operate with the display synchronization signal 1 and the output clock 1 output from the synchronization signal generator 111.

  Furthermore, the compressed stream decoding apparatus 10 can stop the operations of the lower DEMUX 121, the input buffer 127, the decoder 128, the output buffer 129, and the like when the same image data is output from the display output units 112 and 132. Therefore, there is an advantage that power consumption can be reduced.

Embodiment 2 of the Invention
The configuration and operation of the compressed stream decoding apparatus 20 according to this embodiment will be described with reference to FIG. The compressed stream decoding apparatus 10 according to the first embodiment of the invention is configured to select the outputs of the VCO 106 and the VCO 126 by the selector 134, whereas the compressed stream decoding apparatus 20 includes the PCR value and STC input to the comparator 124. By selecting the counter value by the selectors 201 and 202, the system clocks of the synchronization signal generator 111 and the synchronization signal generator 131 are synchronized when the same stream is output. Since the other configuration is the same as that of the compressed stream decoding apparatus 10 according to the first embodiment of the invention shown in FIG. 1, the same symbols are given and the detailed description is omitted.

  When the same stream is output in the compressed stream decoding apparatus 20, the selectors 201 and 202 are operated according to the output switching signal S1, and the PCR value extracted by the PCR extracting unit 102 and the STC value output from the STC counter 103 are compared. To the device 124. As a result, CLK2 output from the VCO 126 is reproduced based on the same PCR value and STC value as CLK1 output from the VCO 106, and thus both clocks are substantially synchronized. However, both clocks are not perfectly synchronized and contain different jitter depending on the characteristics of the LPF and VCO. As described above, when the system clocks CLK1 and CLK2 are not perfectly synchronized due to the influence of jitter, there are the following problems.

  In the same stream display state in which the display output unit 112 and the display output unit 132 output the same video, the phase of the display synchronization signal 2 generated by the synchronization signal generation unit 131 is synchronized as shown in the first embodiment of the invention. When attempting to completely synchronize with the phase of the display synchronization signal 1 generated by the signal generator 111, the phase may be shifted due to the influence of clock jitter. When such an unexpected phase shift occurs, contention between the writing of the decoder 109 and the reading of the display output unit 132 with respect to the output buffer 109 becomes a serious contention such that an erroneous image output or an image cannot be output. there is a possibility. Such an unexpected phase shift can also occur in the compressed stream decoding apparatus 10 shown in the first embodiment of the invention. For example, when the display synchronization signal 2 and the display start signal 2 generated by the synchronization signal generation unit 131 include a jitter component, or when the synchronization signal generation unit 131 acquires a counter value from the synchronization signal generation unit 111 The case where a time difference arises etc. can be considered.

  Therefore, the display synchronization signal 2 of the synchronization signal generator 131 is not completely synchronized with the display synchronization signal 1 of the synchronization signal generator 111, but is synchronized by providing an offset based on the clock jitter of CLK1 and CLK2. Is desirable. If CLK1 and CLK2 are not completely synchronized, the above-described contention of the output buffer 109 may occur. For example, writing by the decoder 108 is performed from the beginning of the frame memory after the display output unit 132 has read. If this is the case, reading and writing of the frame memory can be performed without causing competition in pixel units. Therefore, even if a deviation occurs between the display synchronization signal 1 and the display synchronization signal 2 due to clock jitter, an offset is provided in the display synchronization signal 2 to synchronize with the display synchronization signal 1 so that no competition occurs in units of pixels. You can do that.

  Specifically, when the synchronization signal generator 131 acquires the counter value output from the synchronization signal generator 111 and updates its own counter value, the counter value of the synchronization signal generator 111 is counted up. The counter value is updated by providing a predetermined difference in the phase for counting up its own counter value with respect to the phase. It should be noted that the phase difference at this time may be determined so that the above-described serious competition of writing / reading of the output buffer 109 does not occur even if the phase difference fluctuates due to clock jitter. FIG. 3D shows a state in which the read phase of the display output unit 132 is synchronized by providing an offset Δoff to the write timing phase of the decoder 108 and the read timing phase of the display output unit 108.

  In the compressed stream decoding apparatus 10 according to the first embodiment of the present invention, the clock signal input to the synchronization signal generating unit 131 at the time of output switching is switched discontinuously from CLK2 to CLK1. On the other hand, in the compressed stream decoding apparatus 20, since the synchronization signal generation unit 131 always receives the clock generated by the VCO 126, the clock signal input to the synchronization signal generation unit 131 is continuously input even when the output is switched. Can be switched automatically.

Embodiment 3 of the Invention
The configuration and operation of the compressed stream decoding apparatus 30 according to this embodiment will be described with reference to FIG. The compressed stream decoding device 30 shares the decoders 108 and 128 included in the compressed stream decoding device 10 according to the first embodiment of the invention, and a decoder 301 capable of decoding two video streams by time division processing; A feature is that a control unit 302 is provided to instruct the decoder 301 of the decoding timing. Since the other configuration is the same as that of the compressed stream decoding apparatus 10 according to the first embodiment of the invention shown in FIG. 1, the same symbols are given and the detailed description is omitted.

  Even with such a configuration, the input image of the selector 133 and the selector 134 is switched according to the output switching signal S1, and the counter value of the synchronization signal generator 131 is set, so that the output image of the display output device 132 is disturbed. The output image can be switched without any change.

  However, when decoding processing by time division is performed by one decoder 301, there is a problem that the decoding processing of the other compressed video stream is delayed due to waiting for the decoding processing of one compressed video stream, and the display image is disturbed. . This problem will be described with reference to FIG.

  FIG. 6A shows the timing when one of the compressed video streams has a frame frequency of 30 Hz and the other compressed video stream has a frame frequency of 60 Hz, and outputs these after performing decoding processing by time division. FIG. Note that one frame time of a compressed video stream having a frame frequency of 30 Hz is 1/30 seconds, and one frame time of a compressed video stream having a frame frequency of 60 Hz is 1/60 seconds. Here, as shown in the figure, it is assumed that the display synchronization signal (Vsync) of the 30 Hz video stream and the 60 Hz video stream is shifted by Δt. In addition, each picture is decoded within one frame time indicated by the interval of the display synchronization signal, and the picture after decoding reaches the display timing in the next frame after the decoded frame.

  As shown in FIG. 6A, when decoding of a picture P10 with a frame frequency of 30 Hz that has been preceded by decoding timing is started, a picture P20 with a frame frequency of 60 Hz that has come after decoding is then decoded by the preceding picture P10. The decoding start time is delayed until the process ends. As a result, the display timing of the picture P20 is also delayed, which causes the display image to be disturbed.

  In this way, the problem that the display image is disturbed due to the decoding processing delay of the compressed video stream occurs when two compressed video streams having different frame frequencies are decoded in synchronization with the reference clock extracted from each compressed video stream. This is a problem that occurs when two compressed video streams are decoded by a single decoder in a time-sharing process. In other words, this is a problem that occurs when a multi-stream display is performed regardless of whether or not the multi-stream display state and the single-stream display state are switched.

  Therefore, in order to avoid the above problem, in the compressed stream decoding apparatus 30 according to the present embodiment, the control unit 302 appropriately adjusts the decoding order and timing of the pictures decoded by the decoding unit 301. Specifically, when the decoding start time of the picture P10 with the frame frequency of 30 Hz comes, the decoding is not started immediately, and the picture P20 with the frame frequency of 60 Hz is decoded first, and then the picture P10 is decoded. Mediate. For example, as shown in FIG. 6, when the decoding time of a picture with a frame frequency of 60 Hz and a picture with a frame frequency of 30 Hz are both within ½ of one frame period, the decoding start time of the picture P10 with a frame frequency of 30 Hz is set to the frame The decoding process of the picture P20 having the frame frequency of 60 Hz may be started first by delaying the display synchronization signal (Vsync) of the stream having the frequency of 60 Hz to the middle. By delaying the decoding start of the picture P10 with the frame frequency of 30 Hz to the middle of the display synchronization signal (Vsync) of the stream with the frame frequency of 60 Hz, which is the difference Δt between the display synchronization signal (Vsync) of the 30 Hz video stream and the 60 Hz video stream. Even with such a value, the picture P20 having a frame frequency of 60 Hz can be decoded first.

  By performing arbitration in this way, two frames (for example, P20 and P21 in FIG. 6B) with a frame frequency of 60 Hz and a frame within two frame times (1/30 seconds) of a compressed video stream with a frame frequency of 60 Hz One picture having a frequency of 30 Hz (for example, P10 in FIG. 6B) can be decoded. Furthermore, since decoding of one picture with a frame frequency of 30 Hz (for example, P10 in FIG. 6B) is completed within one frame time (1/30 second) of a compressed video stream with a frame frequency of 30 Hz, the frame frequencies of 30 Hz and 60 Hz The two compressed video streams can be displayed without delay.

  In this way, by adjusting the decoding start time so as to delay the decoding start of a picture included in one compressed video stream with a low frame frequency until after decoding the other compressed video stream with a high frame frequency, Even when two different compressed video streams are decoded, it is possible to display both compressed video streams without causing a delay. Therefore, it is possible to prevent the display image from being disturbed due to the decoding delay as shown in FIG.

  Here, the above-described arbitration of the decoding start time may be performed by the control unit 302 using the display start signal 1 and the display start signal 2 input from the synchronization signal generation units 111 and 131. This is because the display start signal 1 and the display start signal 2 are signals for instructing the decoding start timing in units of pictures and reflect the vertical synchronization signal (Vsync) of the video data to be decoded.

  In Embodiments 1 to 3 of the invention described above, the configuration in which output of image data decoded from two transport streams is switched is shown for the sake of simplicity. However, decoding is performed from three or more transport streams. The present invention can also be applied when selecting output of the image data.

It is a block diagram of the compressed video stream decoding apparatus 10 concerning Embodiment 1 of invention. FIG. 10 is a timing chart for explaining the operation of the compressed video stream decoding apparatus 10. FIG. 10 is a timing chart for explaining operations of the compressed video stream decoding device 10 and the compressed video stream decoding device 20. It is a block diagram of the compressed video stream decoding apparatus 20 concerning Embodiment 2 of invention. It is a block diagram of the compressed video stream decoding apparatus 30 concerning Embodiment 3 of invention. 6 is a timing chart for explaining the operation of the compressed video stream decoding device 30. FIG. It is a block diagram of the conventional compressed video stream decoding apparatus 70.

Explanation of symbols

10, 20, 30 Compressed stream decoding device 11, 21 First compressed video stream processing unit 12, 22 Second compressed video stream processing unit 102, 122 PCR extraction unit 103, 123 STC counter 104, 124 Comparators 105, 125 Low pass filter (LPF)
106, 126 Voltage controlled oscillator (VCO)
108, 128, 301 Decoder 109, 129 Output buffer 111, 131 Sync signal generator 112, 132 Display output unit 135 Output switching instruction unit S1 Output switching signal

Claims (23)

The input first compressed video stream is decoded based on the first reference time information given to the first compressed video stream, and the decoded video data is based on the first reference time information. A first video data processing unit to output;
The input second compressed video stream is decoded based on the second reference time information given to the second compressed video stream, and the decoded video data is decoded based on the second reference time information. A second video data processing unit that selectively executes a process of outputting and a process of outputting the video data decoded by the first video data processing unit based on the first reference time information; Compressed stream decoding device. The first video data processing unit outputs video data obtained by decoding the first compressed video stream in synchronization with a display synchronization signal generated using the first reference time information,
When the second video data processing unit outputs video data obtained by decoding the second compressed video stream, the second video data processing unit outputs the video data in synchronization with the display synchronization signal generated using the second reference time information, 2. The compressed stream according to claim 1, wherein when the video data decoded by the first video data processing unit is output, the compressed stream is output in synchronization with a display synchronization signal generated using the first reference time information. Decoding device.   The second video data processing unit includes a selector that selects either the video data decoded by the first video data processing unit or the video data decoded by the second video data processing unit. The compressed stream decoding apparatus according to 1.   When the selector selects the video data decoded by the first video data processing unit, the second video data processing for performing a process from decoding the second compressed video stream to inputting to the selector The compressed stream decoding apparatus according to claim 3, wherein the operation of a part or all of the circuits included in the unit is stopped. The second video data processing unit includes a selector that selects the first reference time information or the second reference time information,
When outputting the video data obtained by decoding the second compressed video stream, the second video data processing unit generates a display synchronization signal generated using the second reference time information input via the selector. When the video data obtained by decoding the second compressed video stream is output in synchronization with the video data decoded by the first video data processing unit, the first data input via the selector is output. The compressed stream decoding device according to claim 1, wherein the video data decoded by the first video data processing unit is output in synchronization with a display synchronization signal generated based on one reference time information.   When the second video data processing unit outputs the video data decoded by the first video data processing unit, a display synchronization signal when the second video data processing unit outputs the video data, The compressed stream decoding apparatus according to claim 2, wherein the first video data processing unit synchronizes with a display synchronization signal when video data is output. A first decoder that decodes an input first compressed video stream based on first reference time information given to the first compressed video stream;
A first output buffer for storing decoded video data output by the first decoder;
A first display output device that outputs video data stored in the first output buffer in synchronization with a display synchronization signal generated using the first reference time information;
A second decoder that decodes the input second compressed video stream based on the second reference time information given to the second compressed video stream;
A second output buffer for storing the decoded video data output by the second decoder;
A second display output unit that selects either video data stored in the first output buffer or video data stored in the second output buffer and outputs the selected video data;
When the second display output device outputs the video data stored in the first output buffer, output is performed in synchronization with the display synchronization signal generated using the first reference time information,
When the second display output unit outputs the video data stored in the second output buffer, the compressed stream is output in synchronization with the display synchronization signal generated using the second reference time information. Decoding device.   When the video data stored in the first output buffer is output from the second display output unit, the display synchronization signal for the second display output unit is changed to the display synchronization signal for the first display output unit. The compressed stream decoding apparatus according to claim 7, wherein synchronization is performed.   When the video data stored in the first output buffer is output from the second display output unit, the display synchronization signal for the second display output unit is changed to the display synchronization signal for the first display output unit. The compressed stream decoding apparatus according to claim 7, wherein an offset is added for synchronization.   10. The offset is determined so that there is no contention between writing of video data to the first output buffer by the first decoder and reading of video data by the second display output unit. The compressed stream decoding device according to 1.   The writing of new video data to the first output buffer by the first decoder is the first output after the video data has been read by the first display output unit and the second display output unit. The compressed stream decoding apparatus according to claim 7, wherein the compressed stream decoding apparatus performs the storage area of the buffer. A first decoder that inputs a first compressed video stream, decodes the first compressed video stream, and outputs decoded video data;
A first clock generator for generating a reference clock for decoding the first compressed video stream based on the reference time information given to the first compressed video stream;
A first output buffer for storing decoded video data output by the first decoder;
A first display output unit that outputs video data stored in the first output buffer based on a display synchronization signal generated from a reference clock generated by the first clock generation unit;
A second decoder for inputting a second compressed video stream, decoding the second compressed video stream, and outputting decoded video data;
A second clock generator for generating a reference clock based on the reference time information given to the first compressed video stream or the reference time information given to the second compressed video stream;
A second output buffer for storing the decoded video data output by the second decoder;
A second display output unit that selects either video data stored in the first output buffer or video data stored in the second output buffer and outputs the selected video data;
When the second display output device outputs the video data stored in the first output buffer, the second clock generation unit is based on reference time information given to the first compressed video stream. Output video data based on the reference clock generated by
When the second display output unit outputs the video data stored in the second output buffer, the second clock generation unit is based on reference time information given to the second compressed video stream. Is a compressed stream decoding apparatus that decodes the second compressed video stream in the second decoder based on a reference clock generated by the second display output unit and outputs video data in the second display output unit. A first synchronization signal generation unit that generates a display synchronization signal when the first display output unit performs image output from a reference clock generated by the first clock generation unit;
A second synchronization signal generation unit that generates a display synchronization signal when the second display output unit performs image output from a reference clock generated by the second clock generation unit;
When the video data stored in the first output buffer is output to the second display output unit, the display synchronization signal generated by the second synchronization signal generation unit is output from the first synchronization signal generation unit. 13. The compressed stream decoding apparatus according to claim 12, wherein the display synchronization signal to be generated is synchronized by adding an offset.   14. The offset is determined so that contention between writing of video data to the first output buffer by the first decoder and reading of video data by the second display output device does not occur. The compressed stream decoding device according to 1. A compressed stream decoding device that decodes an input first compressed video stream and a second compressed video stream by time division processing and outputs decoded video data,
When the frame frequency of the first compressed video stream is different from that of the second compressed video stream, the decoding start of a picture included in one compressed video stream having a lower frame frequency is changed to the other compressed video stream having a higher frame frequency. A compressed stream decoding apparatus that adjusts a decoding start time so as to delay until after decoding of included pictures. A decoder that inputs a first compressed video stream and a second compressed video stream, decodes the first compressed video stream and the second compressed video stream by time division processing, and outputs decoded video data; ,
A first output buffer for storing video data obtained by decoding the first compressed video stream output by the decoder;
A first display output device for outputting the video data stored in the first output buffer in synchronization with a display synchronization signal generated based on reference time information given to the first compressed video stream; ,
A second output buffer for storing video data obtained by decoding the second compressed video stream output by the decoder;
A second display output unit that selects either video data stored in the first output buffer or video data stored in the second output buffer and outputs the selected video data;
When the second display output device outputs the video data stored in the first output buffer, output is performed in synchronization with the display synchronization signal generated using the first reference time information,
When the second display output unit outputs the video data stored in the second output buffer, the compressed stream is output in synchronization with the display synchronization signal generated using the second reference time information. Decoding device.   When the frame frequency of the first compressed video stream and the frame frequency of the second compressed video stream are different, the decoding start time in the decoder of the picture included in one compressed video stream having a smaller frame frequency is The compressed stream decoding apparatus according to claim 16, wherein the decoding start time is adjusted so as to be delayed until after decoding of a picture included in the other compressed video stream having a higher frame frequency. The input first compressed video stream is decoded based on the first reference time information given to the first compressed video stream, and the decoded video data is stored in the first output buffer,
The video data stored in the first output buffer is output from the first display output device in synchronization with the display synchronization signal generated using the first reference time information,
The input second compressed video stream is decoded based on the second reference time information given to the second compressed video stream, and the decoded video data is stored in the second output buffer,
A compressed stream decoding method for selecting either video data stored in the first output buffer or video data stored in the second output buffer, and outputting the selected video data from a second display output device And
When the video data stored in the first output buffer is output from the second display output device, output is performed in synchronization with the display synchronization signal generated using the first reference time information,
When the video data stored in the second output buffer is output from the second display output device, the video data is output in synchronization with a display synchronization signal generated using the second reference time information. A feature of a compressed stream decoding method.   When the video data stored in the first output buffer is output from the second display output unit, the display synchronization signal for the second display output unit is changed to the display synchronization signal for the first display output unit. 19. The compressed stream decoding method according to claim 18, wherein synchronization is performed.   When the video data stored in the first output buffer is output from the second display output unit, the display synchronization signal for the second display output unit is changed to the display synchronization signal for the first display output unit. 19. The compressed stream decoding method according to claim 18, further comprising synchronizing by adding an offset.   21. The compressed stream decoding method according to claim 20, wherein the offset is determined so as not to cause a conflict between writing of video data to the first output buffer and reading of video data by the second display output device. .   The writing of new video data to the first output buffer is performed on the storage area of the first output buffer in which the video data has been read by the first display output unit and the second display output unit. The compressed stream decoding method according to any one of claims 19 to 21 to be performed. A compressed stream decoding method for decoding input first compressed video stream and second compressed video stream by time division processing and outputting decoded video data,
When the frame frequency of the first compressed video stream is different from that of the second compressed video stream, the decoding start of a picture included in one compressed video stream having a lower frame frequency is changed to the other compressed video stream having a higher frame frequency. A compressed stream decoding method in which a decoding start time is adjusted so as to be delayed until after decoding of included pictures.

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